TW200915319A - Memory cell structures, memory arrays, memory devices, memory controllers, and memory systems, and methods of manufacturing and operating the same - Google Patents

Memory cell structures, memory arrays, memory devices, memory controllers, and memory systems, and methods of manufacturing and operating the same Download PDF

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Publication number
TW200915319A
TW200915319A TW097127540A TW97127540A TW200915319A TW 200915319 A TW200915319 A TW 200915319A TW 097127540 A TW097127540 A TW 097127540A TW 97127540 A TW97127540 A TW 97127540A TW 200915319 A TW200915319 A TW 200915319A
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Taiwan
Prior art keywords
floating body
memory
node
line
voltage
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TW097127540A
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Chinese (zh)
Inventor
Ki-Whan Song
Nam-Kyun Tak
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Samsung Electronics Co Ltd
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Priority claimed from US12/171,406 external-priority patent/US7969808B2/en
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of TW200915319A publication Critical patent/TW200915319A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)

Abstract

Example embodiments are directed to memory cell structures, memory arrays, memory devices, memory controllers, and memory systems using bipolar junction transistor (BJT) operation.

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200915319 九、發明說明： 【發明所屬之技術領域】 本么月係關於5己憶體單元結構、記憶體陣列、記憶體裝 置°己隐體控制态，及記憶體系統’及其製造及操作方 法。 【先前技術】 諸如DRAM之習知記憶體可包括-個電晶體及-個電容 器。然而’歸因於電容器，詳言之，歸因於電容器之尺 寸，存在對習知記憶體之可縮放性的限制。結果，開發出 包括-個電晶體（1T)及無電容器之記憶體作為一記憶體單 元’其被稱作”無電容器（capacit〇r_less)”記憶體。在下文 中被稱作驾知無電容器DRAM之無電容器丨T DRAM可包括 電浮動式主體。 一般而S ，習知無電容器記憶體利用絕緣體上矽（SC)I) 晶圓且藉由在浮體（floating body)中累積大多數載流子（電 洞或電子）或藉由自浮體發射大多數载流子來識別控制浮 體電壓之資料。當大多數載流子累積於浮體中時，此狀態 通常由資料"1”表示。相反，當自浮體排出大多數載流子 時’此狀態通常被稱作資料"〇”狀態。 存在用於習知無電容器記憶體裝置之兩種類型之操作。 第一類型為使用MOS操作之特徵且第二類型為使用BJT操 作之特徵。大體而言’使用BJT操作之特徵已被引入且其 可具有高於MOS操作之速度及/或優於M〇s操作之保存性 質。 133200.doc 200915319 【發明内容】 實例實施例係針對記憶體單元結構、記憶體陣歹…己憶 體裝置、記憶體控制器及記憶體系統，及其製造及操作； 法。實例實施例係針對使用BJT操作之記憶體單元处構 記憶體陣列、記憶體褒置、記憶體控制器及記憶體系統。 實例實施例係針對記憶體裝置，其包括—記憶體陣列， 該記憶體陣列進一步包括複數個記憶體單元，每一己憶體 單元包括-浮體電晶體’該浮體電晶體具有分別連接：至 少-位元線、纟少-源極線及至少—字線之[節點、第 -節點及閘極節點；及-控制單元，#用於藉由選擇該至 少-源極線及該至少-位元線中之—者回應於_再新指令 來執行-再新操作’其中若將第—f料儲存於連接至㈣ 2之記憶體單元處’則由雙極接面操作引發的—第一電流 流動。 ^實例實施例係針對記憶體裝置，其包括記憶體陣列，該 s己憶體陣列進-步包括複數個記憶體單元，每_記憶體單 =包括-浮體電晶體’該浮體電晶體具有分別連接至至少 一位元線、至少-源極線及至少—字線之第—節點、第二 節點及閘極節，點；及一控制單元，其用於根據資料資訊將 一位元線寫人電壓施加至該至少—位元線，接著將一源極 線寫入電壓施加至該1 $小_ -J-*C List . 主π主乂源極線，且接著將一字線寫入 電壓施加至該至少一字線來執行一寫入操作。 實例實施例係針對記憶體單元結構，其包括絕緣體上石夕 結構，該絕緣體上矽結構進一步包括一基板、一絕緣體及 133200.doc 200915319 一矽層，該矽層包枯 體區域，及-位於第二質之第—節點及第二節點、浮 之間的緩衝區4點以二節點中的—者與該浮體 嗜哞髀夕一中該緩衝區域具有低於該鄰近節點或 »亥汙體之雜質濃度且 -φ ^ ^ τ δ玄緩衝&域覆蓋第一節點及第二 構…者的整個邊界;及-位於碎層上之閘極結 社構1 例係針對記憶體單元結構，其包括絕緣體上石夕 作Ά °構進一步包括一基板、一絕緣體及 日’ 6亥矽層包括摻雜雜質之第-節點及第二節點、位 、笛間的具有一浮體長度之浮體區域，及一位於第一節點 。第二節點中之-者與該浮體之間的緩衝區域，其中該緩 衝區域具有低於該鄰近節點或該浮體之雜質濃度；及-位 夕層上具有一閘極長度之閘極結構，《中該浮體長度 大於該閘極長度。 實例實施例係針對記憶體單元結構，其包括絕緣體上矽 結構，該絕緣體上石夕結構進一步包括一基板、一絕緣體及 一矽層，該矽層包括摻雜雜質之發射極/源極及集極/汲 極 浮體區域及一位於發射極/源極與該浮體之間的輔 助浮體區域，纟中該辅助浮體區域具有低於該浮體之雜質 濃度；及一位於該矽層上之閘極結構。 實例實施例係針對記憶體單元結構，其包括一絕緣體上 矽結構，該絕緣體上矽結構進一步包括一基板、一絕緣體 及一矽層，該矽層包括摻雜雜質之第一節點及第二節點、 一浮體區域及一鄰近該浮體區域之延伸浮體區域；及一位 133200.doc 200915319 於石夕層上的閘極結構。 實例實施例係針對記憶體單元結構，其包括位於一基板 f之絕緣層、位於該絕緣層上且包括m 一第二 即.’沾及汗體區域之矽圖案’及一圍繞該浮體區域的閘 極’其中閘極之長度小於浮體區域且其中對於一給定電壓 “至該閘極之情況，施加至該第—節點及該第二節點之 電壓之間的電壓差誘發一雙極接面操作。 ㈣實_係針對記憶體單元結構，其包括位於一基板 上之絕緣層；—位於該絕緣層上之矽圖案，其包括一第一 節點、-第二節點及一浮體區域；—位於該浮體區域上的 延伸子體區域；及一圍繞該浮體區域及該延伸浮體區域之 閘極結構。 /例實施例係、針對用於控制包括複數個無電容心憶體 早元之記憶體裝置之方法，該方法包括提供用於識別一區 及—部分再新操作中的—者之模騎存器設定 )"，及提供—用於該再新操作之再新指令。 實例實施例係針對包括一暫存器之記憶體控制器，該暫 二予器儲存用於選擇區塊再新及部分再新中之—者的刪指 令0 ==例係針對無電容器記憶體裝置，其包括儲存用 於選擇區塊再新及部分再新中之—者之資訊的暫存Ρ 矽結構，該絕緣體上矽結構包括一基板 層，該矽層包括一第一節點及一第二節點 實例實施例係針對記憶體單元結構，其包括'絕緣體上 緣體及^一石夕 浮體區域， 133200.doc 200915319 及一位於該浮體區域上之閘極，复 ^ "中閘極的長度小於該浮 壓加至該閘極的情況， 接面操作。 電屋之間的差誘發雙極 例係針對記憶體裝置，其包括一記憶， 包括複數個記憶體單元，每-記憶體單元包 _ : ㈤體’該浮體f晶體具有分料接至至少一位 7L線、至少—源極線及至少一 ^ 及閑極；及一控制單元，盆用❹=一郎點、第二節點 /、用於藉由選擇至少一源極線t :者^不選擇至少—字線中之任—者來執行一讀取 二’虚中若將第一資料儲存於連接至所選源極線的記憶 體早^處，則由雙極接面操作引發之第一電流 【實施方式】 將多看伴圖式更詳細描述實例實施例。 本文中揭示詳細實例實施例。然而，出於描述實例實施 例之目的’本文中所揭示之特定結構及/或功能細節僅為 代表性的。然而，本發明 解…… 許多替代形式且不應被 解釋為僅限於本文中所陳述的實例實施例。 應理解，當將—組件稱作”在（另一組件）上”、”連接至" 或％接至”另_組件時’其可直接在另—組件上、連接至 :轉接，另一組件，或可存在介入組件。與之相比，當將 一組件稱作”直接在（另—組件）上"、"直接連接至”或”直接 耦接至”另一組件時，不存在介入組件。如本文中所用 術語”及/或”包括相關列出項中之-或多者中之任-者及所 133200.doc -10- 200915319 有組合。 應理解，儘管可在太古 在本文中使用術語第一、 等來描述各種元件、弟一弟二專 元件、組件、區域、層I,! 或部分，但此等 flJ 及/或部分不應受此等術語的限 制此荨術81僅用以區分一個异丛L, 八盥另-、，'且件、區域、層或部 刀與另'一凡件、組株、r? 0 « … °°s 、層或部分。因此，可將下文 所論述之第一元件、纟件 彼k队 、 ，，·件Q域、層或部分稱為第二元 件、組件、區域、層或邱八 層次°卩刀而不背離實例實施例之教示。 為了描述之間單性，可尤士 如 •在…下方”、"在...之下 W生了在本文中使用空間相對術語（諸 ，"士 ~1'~ —II ' α 下部"、"在…之上”、"上 部”及其類似物）來描述如圖式中 Μ叭甲所說明之一個組件或特徵 與另一(或多個)組件或特徵的關係。應理解，該等空間相 關術語意欲涵蓋裝置在估用φ + 在使时场料之除Β巾所描繪之 方位以外的不同方位。 本文中所使用之術語僅出於描述特定實例實施例之目的 且並不意欲具有限制性。如本文中所用，單數形式"一"及 •’該’’意欲亦包括複數形式’除非上下文中另外明確規定。 應進一步理解，當在此說明書中使用時，術語"包含”規^ 所陳述之特徵、整數、步驟、操作、元件及/或組件二 在’但並不排除-或多個其他特徵、整數、步驟、操作、 元件及/或組件之存在或添加。 除非另外定義’否則本文中所使用之所有術語(包 術術語及科學術語）具有與一般熟習實例實施例所屬之 術的技術者通常所理解之意義相同的意義。應進一步瞭解 133200.doc 11 - 200915319 術語（諸如常用詞典中所定義之彼等術語）應被解釋為具有 與其在相關技術背景中之含義一致的含義且不應以理想化 或過度形式化之意義來解釋，除非本文中明確地如此定 義。 現將參考隨附圖式中所說明之實例實施例，其中類似參 考數字始終指代類似組件。實例實施例不應被解釋為限於 此等圖式中所說明之區域之特定形狀，而應包括，例如， 由製造導致的形狀之偏差。舉例而言，圖示為矩形之植入 區域通常將在其邊緣處具有圓形或彎曲特徵及/或植入濃 度梯度而非自植入區域至未植入區域之二元變化。同樣， 藉由植入所形成之埋置區域可在該埋置區域與植入所穿經 之表面之間的一區域中產生一定程度的植入。因此，圖式 中所說明之區域實質上為示意性的且其形狀並不意欲說明 一裝置之一區域之實際形狀且並不意欲限制本發明之範 疇。 圖1A說明可實施實例實施例之橫向無電容器記憶體單元 之實例。如圖1A中所說明，橫向無電容器記憶體單元可包 括基板10。在實例實施例中，基板可為p傳導類型或N傳導 類型基板中之一者。在NMOS電晶體之實例實施例中，基 板10為P傳導類型基板。 記憶體單元可進一步包括基板i 〇上之絕緣層丨2。絕緣層 12為SOI配置之絕緣體。記憶體單元可進一步包括位於絕 緣層12上之具有第一節點丨4及第二節點丨6及浮體丨8之矽 層。在MOS操作中’第一節點14及第二節點16可被稱作源 133200.doc -12· 200915319 極S及汲極D。在BJT操作中，第一節點14及第二節點a可 被稱作發射極E及集極c。請注意，第一節點14及第二節點 16為可互換的。在實例實施例中，第一節點丨*及第二節點 可為N傳導類型或P傳導類型。在nm〇S電晶體之實例實 知例中’第一節點14及第二節點丨6為N傳導類型。 記憶體單元可進一步包括絕緣層12上位於第一節點14與 第二節點16之間的浮體區域18，其可具有與第一節點丨斗及 第二節點1 6相反之傳導類型。在NM0S電晶體之實例實施 例中’在圖1 A中所說明，浮體區域1 8為p傳導類型。结 果’圖1A中所說明之BJT為NPN傳導類型BJT。由於浮體 區域18與基板1〇藉由絕緣層12隔離，浮體區域18為電浮動 式的。如圖1A中所說明，浮體區域18可具有浮體長度 L1 〇 記憶體單元可進一步包括閘極結構G，其可包括閘極絕 緣層20及閘極22。閘極22可具有閘極長度L2。如圖1A$ 所展示’具有浮體18之橫向無電容器記憶體單元可形成於 絕緣層1 2上，絕緣層1 2進一步形成於矽基板1 〇上。如上文 所闡述’節點被視為發射極/源極E/S還是集極/汲極C/D為 相對的；因此，在實例實施例中，利用術語第一節點及第 二節點。 大體而言’發射極/源極E/S為被施加較低電壓之節點， 而集極/汲極C/D為被施加較高電壓之節點。大體而言，L j 可界定發射極/源極E/S與集極/汲極C/D之間的距離且L2可 界定閘極長度。在實例實施例中，L2大於L1 ;大體而言係 133200.doc -13 - 200915319 因為自對準技術或LDD(光摻雜沒極）可用以形成發射極/源 極E/S及集極/汲極c/D且接著應用熱處理使其穩定化。 圖1 B說明可實施實例實施例之垂直無電容器記憶體單元 之實例。如圖1B中所說明，垂直無電容器記憶體單元可包 括基板1 0、垂直堆疊於基板1 〇上之第一節點丨4、浮體區域 1 8及第一節點16。浮體區域18為電浮動式的。如圖丨b中所 示’浮體區域18可具有浮體長度L1。 閘極絕緣層20及閘極22可圍繞浮體1 8。舉例而言，閘極 絕緣層20及閘極22可接觸浮體18之兩個或兩個以上側面之 全部或一部分。在實例實施例中，L2大於Li。 右垂直無電谷為s己憶體单元為NMOS電晶體，則第—節 點14及第二節點16可具有第一傳導類型（例如，N傳導類 型），且洋體區域1 8可具有第二傳導類型（例如，p傳導類 型）。又，垂直電谷器結構可具有SO〗基板或如圖1B中所示 之習知塊體基板。 圖2說明圖1A及圖1B之無電容器記憶體單元之等效電 路。如圖2中所說明，等效電路包括一個NM〇s電晶體及一 個NPN雙極接面電晶體。舉例而言，圖1A及圖⑺之發射極/ 源極E/S、集極/汲極c/D及閘極g形成一 NMOS電晶體。類 似地，圖1A及圖1B之發射極/源極E/s、集極/汲極C/D，及 電浮動式區域18(或基極B)形成一 NPN型之BJT。亦如圖2 中所示，耦合電容器CC可形成kNMOS電晶體之閘極〇與 BJT之基極B之間。 在實例實施例中，BJT用以程式化/寫入以及讀取及再新 133200.doc 14 200915319 記憶體單a。在此方面，阶產生―用以在記憶體單元中 程式化/寫入一資料狀態、讀取記憶體單元之該資料狀 態，及再新記憶體單元之該資料狀態的雙極電晶體電流。 圖3說明根據實例實施例之無電容器記憶體單元之直流 電特徵。如圖3中所說明，舉例而言，當將、分別設定為: 伏特、-1伏特及-2伏特，同時將Vds(或Vee)|〇伏特掃至一 較高電壓肖，單位為#之1〇心(或y經展示為發生變 化。如圖3中所說明，每種狀況下之每一左線可用以識別 資料"1” ’而每種狀況下之右線可用以識別資料"〇"。對於 每一 vg之識別資料”r之左線與識別資料"〇”之右線之間的 差可被稱作感測邊界。對於資料”丨"之浮體區域丨8中之大 多數載流子大於對於資料"〇”之浮體區域18中之大多數載 流子。詳言之，圖3說明在所有三種狀況下當Vds高於15伏 特時的電流突變。下文解釋電流突增。 如圖2及圖3中所示，升高電壓Vds來增加電浮動區域18 或浮體B之電位，其產生一在發射極/源極E/s與基極B之間 的正向偏壓及一在基極B與集極/基極C/D之間的反向偏 壓，所以BJT導通。結果，電子自發射極/源極E/s經由浮 體B遷移至基極B與集極/汲極C/D之間的接面。此等電子碰 撞進入接面中之矽晶格且產生電子-電洞對。此可被稱作 衝擊離子化或帶對帶穿隧。 對於母一電子-電洞對’電子朝向集極/沒極C/d移動且 電洞朝向基極B移動。此外，基極b之電壓升高且來自發 射極/源極E/S之更多電子被注入浮體且經由浮體b到達基 133200.doc 15 200915319 極B與集極/基極C/D之間的接面’進而反覆以上循環。歸 因於此正反饋’增值可能為大’且其可被稱作”突崩產生”。 由於此正反饋’電洞在浮體區域中累冑。此狀態可被稱作 資料狀態” 1，，。200915319 IX. Description of the invention: [Technical field of invention] This month is about the structure of 5 memorandum unit, memory array, memory device, hidden body control state, and memory system' and its manufacturing and operation method . [Prior Art] A conventional memory such as a DRAM may include a transistor and a capacitor. However, due to the capacitor, in detail, due to the size of the capacitor, there is a limit to the scalability of the conventional memory. As a result, a memory including a transistor (1T) and a capacitor-free memory was developed as a memory cell' which is called a "capacitor 〇r_less" memory. A capacitorless 丨T DRAM, hereinafter referred to as a driverless capacitor DRAM, may include an electrically floating body. In general, S, conventional capacitorless memory utilizes a silicon-on-insulator (SC) I) wafer and accumulates most carriers (holes or electrons) in a floating body or by self-floating bodies. Most of the carriers are emitted to identify the data that controls the float voltage. When most carriers accumulate in the floating body, this state is usually represented by the data "1. On the contrary, when most carriers are discharged from the floating body, this state is usually called the data "〇 state . There are two types of operations for conventional capacitorless memory devices. The first type is a feature that uses MOS operation and the second type is a feature that uses BJT operation. In general, the feature of using BJT operation has been introduced and it can have a higher quality than MOS operation and/or better than M 〇s operation. 133200.doc 200915319 SUMMARY OF THE INVENTION Example embodiments are directed to memory cell structures, memory arrays, memory devices, memory controllers, and memory systems, and their manufacture and operation; The example embodiments are directed to memory cell arrays, memory devices, memory controllers, and memory systems for memory cells that operate using BJT. The example embodiment is directed to a memory device comprising: a memory array, the memory array further comprising a plurality of memory cells, each of the memory cells comprising a - floating body transistor having a respective connection: at least - a bit line, a minus-source line, and at least - a [node, a - node, and a gate node of the word line; and - a control unit, # for selecting the at least - source line and the at least - bit In the line - in response to the _ new instruction to perform - new operation 'where the first f material is stored in the memory unit connected to (4) 2, then triggered by the bipolar junction operation - first Current flows. An example embodiment is directed to a memory device that includes a memory array that includes a plurality of memory cells, each _memory single = including - a floating body transistor 'the floating body transistor Having a first node connected to at least one bit line, at least a source line, and at least a word line, a second node and a gate node, and a control unit for using a bit element according to the data information A line write voltage is applied to the at least one bit line, and then a source line write voltage is applied to the 1 $ small _ -J-*C List. The main π main 乂 source line, and then a word line A write voltage is applied to the at least one word line to perform a write operation. The example embodiment is directed to a memory cell structure including an insulator-on-the-ear structure, the insulator upper structure further including a substrate, an insulator, and a layer of 133200.doc 200915319, the layer of the ruthenium layer, and - located The second quality - the node and the second node, the buffer between the floating points of 4 points in the two nodes - and the floating body in the buffer area have a lower than the neighboring node or The impurity concentration of the body and the -φ ^ ^ τ δ 缓冲 buffer & field cover the entire boundary of the first node and the second structure; and - the gate junction structure on the fragment is 1 for the memory cell structure, The method further includes a substrate, an insulator, and a floating layer of a floating body length including a first node and a second node, a bit and a flute between the flutes. The area, and one is located at the first node. a buffer region between the second node and the floating body, wherein the buffer region has a lower impurity concentration than the adjacent node or the floating body; and a gate structure having a gate length on the horizon layer , "The length of the float is greater than the length of the gate. The example embodiment is directed to a memory cell structure including an insulator upper structure, the insulator further comprising a substrate, an insulator, and a germanium layer including an impurity-doped emitter/source and a set a pole/drain floating body region and an auxiliary floating body region between the emitter/source and the floating body, wherein the auxiliary floating body region has a lower impurity concentration than the floating body; and one is located in the crucible layer The gate structure on the top. The example embodiment is directed to a memory cell structure, comprising an insulator upper structure, the insulator upper structure further comprising a substrate, an insulator and a germanium layer, the germanium layer comprising a first node and a second node doped with impurities a floating body region and an extended floating body region adjacent to the floating body region; and a gate structure of the 133200.doc 200915319 on the Shixia layer. The example embodiment is directed to a memory cell structure including an insulating layer on a substrate f, a m-pattern on the insulating layer, and including a second, ie, a sweat-and-sweat region, and a surrounding region of the floating body The gate of the gate 'where the length of the gate is smaller than the floating body region and wherein for a given voltage "to the gate, the voltage difference between the voltage applied to the first node and the second node induces a bipolar (4) The solid state is for the memory cell structure, and includes an insulating layer on a substrate; the germanium pattern on the insulating layer includes a first node, a second node, and a floating body region An extended sub-body region on the floating body region; and a gate structure surrounding the floating body region and the extended floating body region. The example embodiment is for controlling a plurality of non-capacitive memory cells. The method of the memory device of the early element, the method comprising: providing a mode setting for identifying a zone and a part of the re-operation, ", and providing - for renewing the new operation Instruction. Example embodiment For a memory controller including a temporary memory, the temporary storage device stores a deleted instruction for selecting a block renewed and partially renewed 0 == for a capacitorless memory device, which includes a temporary storage structure for storing information for renewing and renewing the block, the insulator upper structure comprising a substrate layer, the buffer layer comprising a first node and a second node instance implementation The example is directed to a memory cell structure including an 'insulator upper edge body and a stone-on-air floating body region, 133200.doc 200915319 and a gate located on the floating body region, and the length of the gate is smaller than the The case where the floating pressure is applied to the gate, the junction operation. The difference between the electric house induces a bipolar system for the memory device, which includes a memory, including a plurality of memory cells, and each memory cell package _: (5) body 'the floating body f crystal has a material connected to at least one 7L line, at least - source line and at least one and idle pole; and a control unit, basin for ❹ = one lang point, second node /, By selecting at least one source line t: ^ does not choose At least - in the word line - to perform a read two 'virtual if the first data is stored in the memory connected to the selected source line, the first one caused by the bipolar junction operation [Embodiment] The example embodiments are described in more detail in the accompanying drawings. Detailed example embodiments are disclosed herein. However, for purposes of describing example embodiments, the specific structural and/or functional details disclosed herein are only However, the present invention is to be understood as being limited to the example embodiments set forth herein. It should be understood that when the component is referred to as "on (another component)" , "Connect to " or % to "when another component" can be directly on another component, connected to: transfer, another component, or there may be an intervention component. In contrast, when a component is There is no intervening component when it is referred to as "directly on (other-component) ", "directly connected to" or "directly coupled to" another component. The term "and/or" as used herein includes any of the - or more of the associated listings and the combination of 133200.doc -10- 200915319. It should be understood that although the terms first, etc. may be used in the context of the description of the various elements, the second component, the component, the region, the layer I, or the portion, the flJ and/or the portion should not be subject to Limitations of these terms This technique 81 is only used to distinguish between a different bundle L, a gossip-, and a 'part, region, layer or knife and another 'one piece, group, r? 0 « ... ° °s, layer or part. Therefore, the first element, the component, the Q, the layer, or the part discussed below may be referred to as the second element, component, region, layer, or Qiu eight level. The teachings of the embodiments. In order to describe the unity between the singularities, you can use the space relative terminology (", "士~1'~-II' α lower part in the article below "," ", "above""upper" and the like, to describe the relationship of one component or feature illustrated in the drawings to another component or feature. It will be understood that such spatially relative terms are intended to encompass different orientations of the device in addition to the orientation depicted by the φ+ in the stencil. The terminology used herein is for the purpose of describing particular example embodiments. It is not intended to be limiting. As used herein, the singular forms """"" , the term "includes" the features, integers, steps, operations, components and/or components set forth in the 'but is not excluded' or a plurality of other features, integers, steps, operations, components and/or components Exist or add. Unless otherwise defined, all terms (incorporated and scientific terms) used herein have the same meaning as commonly understood by the skilled artisan of the example embodiments. It should be further understood that the terms 133200.doc 11 - 200915319 (such as those defined in commonly used dictionaries) should be interpreted as having meanings that are consistent with their meaning in the relevant technical context and should not be idealized or overly formalized. To explain, unless explicitly defined in this article. Reference will now be made to the example embodiments illustrated in the drawings, in which like reference The example embodiments should not be construed as being limited to the particular shapes of the regions illustrated in the drawings, but should include, for example, variations in the shapes resulting from the manufacture. For example, an implanted region illustrated as a rectangle will typically have rounded or curved features and/or implanted concentration gradients at its edges rather than a binary change from the implanted region to the unimplanted region. Similarly, by implanting the embedded region, a degree of implantation can be created in a region between the buried region and the surface through which the implant is placed. The area illustrated in the drawings is, therefore, in the nature of the invention, and is not intended to limit the scope of the invention. Figure 1A illustrates an example of a lateral capacitorless memory cell in which example embodiments may be implemented. As illustrated in Figure 1A, the lateral capacitorless memory unit can include the substrate 10. In an example embodiment, the substrate may be one of a p-conducting type or an N-conducting type substrate. In an example embodiment of an NMOS transistor, the substrate 10 is a P-conducting type substrate. The memory cell may further include an insulating layer 丨2 on the substrate i. The insulating layer 12 is an insulator of the SOI configuration. The memory cell may further include a germanium layer on the insulating layer 12 having a first node 丨4 and a second node 丨6 and a floating body 丨8. In MOS operation, the first node 14 and the second node 16 may be referred to as source 133200.doc -12·200915319 pole S and drain D. In BJT operation, the first node 14 and the second node a may be referred to as an emitter E and a collector c. Please note that the first node 14 and the second node 16 are interchangeable. In an example embodiment, the first node 丨* and the second node may be an N conduction type or a P conduction type. In the example embodiment of the nm〇S transistor, the first node 14 and the second node 丨6 are of the N conduction type. The memory cell can further include a floating body region 18 on the insulating layer 12 between the first node 14 and the second node 16, which can have a conductivity type opposite that of the first node bucket and the second node 16. In an example embodiment of an NMOS transistor, as illustrated in Figure 1A, the floating body region 18 is of the p-conducting type. Results The BJT illustrated in Figure 1A is the NPN conduction type BJT. Since the floating body region 18 is isolated from the substrate 1 by the insulating layer 12, the floating body region 18 is electrically floating. As illustrated in Figure 1A, the floating body region 18 can have a floating body length L1. The memory cell can further include a gate structure G, which can include a gate insulating layer 20 and a gate 22. The gate 22 may have a gate length L2. A lateral capacitorless memory cell having a floating body 18 as shown in Fig. 1A$ can be formed on the insulating layer 12, and an insulating layer 12 is further formed on the germanium substrate 1. As noted above, the 'node is considered to be emitter/source E/S or collector/drain C/D is relative; therefore, in the example embodiment, the terms first node and second node are utilized. In general, the emitter/source E/S is the node to which a lower voltage is applied, and the collector/drain C/D is the node to which a higher voltage is applied. In general, L j can define the distance between the emitter/source E/S and the collector/drain C/D and L2 can define the gate length. In an example embodiment, L2 is greater than L1; generally 133200.doc -13 - 200915319 because self-aligned technology or LDD (light doped immersion) can be used to form emitter/source E/S and collector/ The bucks are c/D and then stabilized by applying heat treatment. Figure 1B illustrates an example of a vertical capacitorless memory cell in which example embodiments may be implemented. As illustrated in FIG. 1B, the vertical capacitorless memory cell can include a substrate 10, a first node 垂直4 stacked vertically on the substrate 1 浮, a floating body region 18, and a first node 16. The floating body region 18 is electrically floating. The floating body region 18 can have a floating body length L1 as shown in Figure b. The gate insulating layer 20 and the gate 22 may surround the floating body 18. For example, gate insulating layer 20 and gate 22 may contact all or a portion of two or more sides of floating body 18. In an example embodiment, L2 is greater than Li. If the right vertical uncharged valley is an NMOS transistor, the first node 14 and the second node 16 may have a first conductivity type (eg, an N conduction type), and the ocean body region 18 may have a second conduction. Type (for example, p-conduction type). Further, the vertical grid structure may have a SO substrate or a conventional bulk substrate as shown in Fig. 1B. Figure 2 illustrates the equivalent circuit of the capacitorless memory cell of Figures 1A and 1B. As illustrated in Figure 2, the equivalent circuit includes an NM〇s transistor and an NPN bipolar junction transistor. For example, the emitter/source E/S, collector/drain c/D, and gate g of Figures 1A and (7) form an NMOS transistor. Similarly, the emitter/source E/s, collector/drain C/D, and electrically floating region 18 (or base B) of Figures 1A and 1B form an NPN-type BJT. As also shown in Fig. 2, the coupling capacitor CC can form between the gate k of the kNMOS transistor and the base B of the BJT. In an example embodiment, the BJT is used for stylization/writing and reading and re-writing. 133200.doc 14 200915319 Memory list a. In this regard, the order generation is used to program/write a data state in the memory cell, read the data state of the memory cell, and reproduce the bipolar transistor current of the data state of the new memory cell. Figure 3 illustrates the DC characteristics of a capacitorless memory cell in accordance with an example embodiment. As illustrated in FIG. 3, for example, when, respectively, are set to: volts, -1 volt, and -2 volts, while Vds (or Vee)|〇V volts is swept to a higher voltage shaw, the unit is # 1 〇 (or y is shown as changing. As illustrated in Figure 3, each left line in each case can be used to identify the data "1" 'and the right line in each case can be used to identify the data&quot ;〇". For each vg identification data, the difference between the left line of r and the right line of the identification data "〇 can be called the sensing boundary. For the floating area of the data "丨" Most of the carriers in 8 are larger than most of the carriers in the floating region 18 of the data "〇.] In detail, Figure 3 illustrates the sudden change in current when Vds is above 15 volts in all three conditions. The current spike is explained below. As shown in Figures 2 and 3, the voltage Vds is raised to increase the potential of the electrically floating region 18 or the floating body B, which produces an emitter/source E/s and a base B. The forward bias between and a reverse bias between the base B and the collector/base C/D, so the BJT is turned on. As a result, the electron self-emitter/ The source E/s migrates via the floating body B to the junction between the base B and the collector/drain C/D. These electrons collide into the germanium lattice in the junction and create an electron-hole pair. It can be called impact ionization or band-to-band tunneling. For the mother-electron-hole pair, the electron moves toward the collector/no-pole C/d and the hole moves toward the base B. In addition, the voltage of the base b More electrons rising and coming from the emitter/source E/S are injected into the floating body and reach the base via the floating body b. 133200.doc 15 200915319 The junction between the pole B and the collector/base C/D' Repeat the above cycle. Due to this positive feedback 'value added may be large' and it may be called "rush collapse". Because this positive feedback 'hole is cumbersome in the floating body area. This state can be called data Status" 1,,.

如圖3中所說明，BJT操作在化〇伏特之情形下比在vy 伏特及Vg=-2伏特之情形下更快地發生。此係因為浮體之 靜態電位Vg，交大且基極_發射極/源極㈣之間的較大 電麼V#較於較小電壓Vg達到正向偏壓。出於類似原因， 資料” Γ’之B JT操作發生地快於資料"〇|，之B JT操作。 圖4說明根據實例實施例之一記憶體裝置。圖4說明包括 記憶體陣列50、列控制單元52及行控制單心之記憶體裝 記憶體陣列50包括複數個無電容器記憶體單元mci至 MCi。每一記憶體單元連接至列控制單元52及行控制單元 54，其令之每一者接收寫入信號WR、讀取信號rd、再新 信號REF及/或位址信號ADD。記憶體單元中之每一者MCi 亦連接至字線WU ... WLi、源極線SL1…su，及位元線 BL1…BLj。如圖4中所示，記憶體單元MCi之每一列具有 相應字線WU及源極線SLi，亦即，字線之數目及源極線之 數目相等。此架構可被稱作獨立源極線架構。在圖4中所 說明之實例實施例中，第一節點連接至源極線SLi且第二 節點連接至位元線BLi。如圖4中所示，字線wu及源極線 SLi可位於相同方向上，而位元線BLi垂直於字線wu及源 極線SLi。 133200.doc * 16 - 200915319 。如圖4中所示，列控制單元52可接收用於回應於寫入信 號WR讀取彳5號RD及再新ref信號中之一者來選擇字線 WLi中之一者及源極線SLi中之至少一者的位址add。行 控制單7L 54可接收用於回應於寫入信號WR、讀取信號 及再新REF信號中之—者來選擇位元線阳中之—者的位 址 ADD。 Γ ,:控制單元54可在一寫入操作期間給所選位元線提供資 料貝訊，且可在一讀取操作期間自所選位元線接收資料資 訊、。又，行控制單元54可在一再新操作期間將一所要電壓 位準供應至位元線BLi中之至少一者。 在實例實施例中’再新REF信號可由外部裝置提供，或 可藉由内部計算一再新週期來產生。 ^管列f^52及行控制單心在圖钟說明為獨立 二。仁疋此等兩個控制單元之功能可實施於單一控制單 圖5自兒明圖4之記情微肽班 說明裝置之賴作的實例時序圖。圖$ ，.，、入呆作（寫入資料，，！，，與資料，，〇 — --S. ¢¢- -1« 7 5賈取操作及 再新刼作之實例時序圖。 中，亨爯叙4 牡卜又所，迷之實例實施例 塊再：… 再新操作或部分再新操作。在區 ^ ，㈣再新所有記憶體單元。區塊再新#作 為較快再新操作，但需要大電流量 =作 同時再新單元之子集(例如，兩個或四個“再:Μ 一 再新每一子隹古丨八個），且連續 /、直至再新所有記憶體單元。 致較慢再新操作，但需要較低電流。卩刀再新綱 133200.doc 200915319 如圖5中所示，時間間隔τ〇、丁3及丁5 充電狀態或待命狀態，其 '’、、狀態或預 摔作之前月/ + 了在寫入刼作、讀取操作或再新 保彳1F之刖及/或之後。本 T . , 間間隔T1及Τ2識別寫入間隔 丁4識別讀取間隔丁_，且7 對於寫入操作期間的BLH及寫入 ^iBL]j lj及寫入、讀取及再新操作期間 的如·』’實線用於f料” 點線用於資們”。 如圖5中所示’連接至WU及SL1之單元之—個完 =在寫入間隔Twrite期間經寫入資料"i”或資料： :間隔Τ一期間經讀出。然而，此僅為-實例，且4; 料可寫入至單元之任何列Mci。 任饤貝 有之前’如時間間隔T〇中所示，位元線叫具As illustrated in Figure 3, the BJT operation occurs faster in the case of volts volts than in the case of vy volts and Vg = -2 volts. This is because the static potential Vg of the floating body is large and the larger voltage between the base_emitter/source (4) is forward biased than the smaller voltage Vg. For similar reasons, the B JT operation of the data "发生" occurs faster than the data "〇|, the B JT operation. Figure 4 illustrates a memory device in accordance with an example embodiment. Figure 4 illustrates a memory array 50, The column control unit 52 and the row control single core memory package memory array 50 include a plurality of capacitorless memory cells mci to MCi. Each memory cell is connected to the column control unit 52 and the row control unit 54 for each One receives the write signal WR, the read signal rd, the renewed signal REF, and/or the address signal ADD. Each of the memory cells MCi is also connected to the word lines WU ... WLi, the source line SL1... Su, and bit lines BL1...BLj. As shown in Fig. 4, each column of the memory cells MCi has a corresponding word line WU and a source line SLi, that is, the number of word lines and the number of source lines are equal. This architecture may be referred to as an independent source line architecture. In the example embodiment illustrated in Figure 4, the first node is connected to the source line SLi and the second node is connected to the bit line BLi. The word line wu and the source line SLi may be in the same direction, and the bit line BLi is perpendicular to the word Wu and the source line SLi 133200.doc * 16 - 200915319. As shown in FIG. 4, the column control unit 52 can receive one of the RD No. 5 RD and the renew ref signal in response to the write signal WR. The address of the at least one of the word line WLi and the source line SLi is selected. The row control unit 7L 54 is receivable for responding to the write signal WR, the read signal, and the renewed REF signal. The address ADD of the bit line is selected. Γ , : The control unit 54 can provide the data bit to the selected bit line during a write operation, and can be used during a read operation. The data information is received from the selected bit line. Further, the row control unit 54 may supply a desired voltage level to at least one of the bit lines BLi during a new operation. In the example embodiment, 'renew REF' The signal can be provided by an external device, or can be generated by an internal calculation of a new cycle. ^ The tube f^52 and the row control single core are described as independent in the figure clock. The functions of the two control units can be implemented in a single Control the single picture 5 from the child's characterization of the micro-peptide class to illustrate the example of the device Figure. Figure $,.,, into the work (write data,,!,, and data,, 〇--S. ¢¢- -1« 7 5 example of the operation and re-creation of the work In the middle, the 爯 爯 4 4 牡 又 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , New operation, but need a large amount of current = a subset of the new unit at the same time (for example, two or four "again: Μ new ones each new eight"), and continuous / until the new memory Body unit. Slower and newer operation, but lower current is required. Scythe re-news 133200.doc 200915319 As shown in Figure 5, the time interval τ 〇, D 3 and D 5 charge state or standby state, its '', state or pre-fall before the month / + is written刼, read, or renew after 1F and/or after. This T., the interval T1 and Τ2 identify the write interval □4 to identify the read interval □, and 7 for the BLH during the write operation and the write ^iBL]j lj and during the write, read and re-operation Such as "" solid line for f material" point line for the capital." As shown in Fig. 5, the 'connected to the unit of WU and SL1' = completed during the write interval Twrite by the data "i" or data: : interval is read during the interval. However, this is only - instance, and 4; material can be written to any column Mci of the unit. 任饤贝有前' as shown in the time interval T〇, the bit line is called

有施加至其的位元線伴持雷厭，在丨LThere is a bit line applied to it that is accompanied by thunder, in the 丨L

(例如，G伏特），源極線SU 其的源極線保持電«(例如，0伏特），且字線 WLi具有施加至其的宝始仅社兩r 其的子線保持電壓（例如，-1伏特），如圖5 T所不。 如圖5中所說明，在τ湘 _ 在Τ期間，右期望將資料”0"寫入至單 元之完整列MC1，則；f千批生，丨《 _广Λ 貝J仃控制早兀54將第一位準（例如，〇5 伙特）之位it線寫人電壓供應至位元線Bu小 若期望將資料” 1 ”耷入5_ 罝早7"之完整列動’則行控制 几將第一位準（例如，〇伏特）之位元線寫入電壓供應至 位凡線BL1〜j。在實例實施例中，位元線寫人電壓之第二 位準可與位域保持電壓相同，例如，〇伏特。 可將早7L之所有其他列MC2..·卜維持於保持狀態，在此 狀態下施加位元線保持電壓（例如，Q伏特）、源極線保持電 133200.doc •18· 200915319 壓（例如，ο伏特）及字線保持電壓（例如，_丨伏特 接著，列控制單元52將源極線寫人電壓（例如，2伏特） 施加至SL1且繼續將源極線保持電壓（例如，〇伏特）施加至 所有其他源極線SL2-i 〇 接考，列控制單元52將字線寫入電壓（例>，0伏特）供 應至WL1且繼續將字線保持電壓（例如，」伏特）供應至所 有其他字線WL2-i。 如圖5中所示，首先，將办& & # '兀*線寫入電壓（其中位準視待 寫入之資料資訊而定）施加至 此扣 。接著，將源極 線寫入電壓施加至源極線su。 取，，，、將子線寫入電壓施 加至字線WL 1。如圖5中所示，告 田對於寫入資料” i ”施加位 π線寫入電壓'源極線寫入 电&及子線寫入電壓時，電流 ι2流經位元線BL1〜j。 v如圖5之時序圖中所說明，對於資料，，ΠΤ1期間， Ο &為2伏特且％為〇伏特’所以根據圖3，流經位元線 BL1〜j之電流i2由BJ丁操作 大朋產生而引發。對於資料 1 ” ’在T2期間，vds為2伏特 吁丑Vg為-1伏特，所以根據圖 3，流經位元線BL1〜j之雷、、* n +丄 J之電机11亦由BJT操作之突崩產生而 W發。如圖5中所示，在日车„ 在時間週期T2期間流經位元線BL1〜j 之電流i 1小於i2，此伟因盔山士人> '、因為由於耦合電容器CC之耦合效應 使净體電位降低所致。 如圖5之時序圖中所說明，對於資料"。"…期間， I，·:伏特且、為0伏特，所以根據圖3,未發生BJ丁操 犬朋產±且電洞可藉由閘極搞合效應排出至位元線 133200.doc 19 200915319 BL1〜j。結果，無電流流經位元線bli〜）。類似地，對於 料〇，在丁 2期間，Vds4l 5伏特且〜為^伏特，所以根據 圖3’未發生BJT操作之突崩產生。結果，無電流流經位元 線B L1〜j。(for example, G volts), the source line SU has its source line held electrically « (for example, 0 volts), and the word line WLi has a sub-wire holding voltage applied thereto (for example, -1 volt), as shown in Figure 5 T. As illustrated in Figure 5, during the period of τ _ Τ, the right expects to write the data "0" to the complete column MC1 of the unit, then; f thousand batches of raw, 丨 " _ Λ Λ 仃 仃 仃 兀 兀 兀 54 Put the first level (for example, 〇5 士特) bit line write voltage supply to the bit line Bu small if you want to put the data "1" into 5_ 罝早7" the full list' then control The bit line write voltage of the first bit (eg, volts) is supplied to the bit lines BL1 djj. In the example embodiment, the second level of the bit line write voltage can be the same as the bit field hold voltage For example, 〇 volt. All other columns of the early 7L MC2..· can be maintained in the hold state, in which the bit line holding voltage (for example, Q volts) is applied, and the source line is kept at 133200.doc • 18· 200915319 Voltage (eg, οvolts) and word line hold voltage (eg, _丨 volts Next, column control unit 52 applies a source line write voltage (eg, 2 volts) to SL1 and continues to maintain the source line A voltage (eg, volts) is applied to all other source lines SL2-i, and the column control unit 52 The word line write voltage (example >, 0 volts) is supplied to WL1 and continues to supply the word line hold voltage (eg, "volts") to all other word lines WL2-i. As shown in Figure 5, first, The &&# '兀* line write voltage (where the level depends on the information to be written) is applied to the buckle. Next, the source line write voltage is applied to the source line su. , the sub-line write voltage is applied to the word line WL 1. As shown in FIG. 5, the field applies a bit π line write voltage 'source line write electric' and sub-line to the write data "i". When the voltage is written, the current ι flows through the bit lines BL1 to j. v As illustrated in the timing chart of Fig. 5, for the data, ΠΤ & 为 & 2 volts and % 〇 volts, so according to Fig. 3 The current i2 flowing through the bit line BL1~j is caused by the BJ Ding operation. For the data 1" ' during the T2, the vds is 2 volts and the Vg is -1 volt, so according to Figure 3, flow through The motor 11 of the bit line BL1~j, and the motor 11 of *n +丄J is also generated by the collapse of the BJT operation and is generated by W. As shown in Fig. 5, in the daylight „ at the time The current i 1 flowing through the bit lines BL1 to j during the period T2 is smaller than i2, which is caused by the reduction of the net body potential due to the coupling effect of the coupling capacitor CC. As shown in the figure, for the data "."... period, I, ·: volts, is 0 volts, so according to Figure 3, there is no BJ Ding dog dog production ± and the hole can be engaged by the gate The effect is discharged to the bit line 133200.doc 19 200915319 BL1~j. As a result, no current flows through the bit line bli~). Similarly, for the crucible, during the D2, Vds4l 5 volts and ~ is ^V, so the collapse of the BJT operation did not occur according to Figure 3'. As a result, no current flows through the bit lines B L1 to j.

位元線寫人電麵在源極線寫人電壓之前施加，因為若 源極線SL1在位元線BL1之前變為2伏特，則集極/沒極㈤ 與發射極/源極E/S之間的電遂Vds變為2伏特。如圖3中所 示’ BJT操作將發生且電洞可累積於浮體B中。結果，不 管所要之資料資訊，而可能重寫入資料”Γ，。 可 入 入 、如圖5中所示，位元線寫入電塵（或任何電麼）之施加 並非瞬時的。因而’位元線寫入電壓可在施加源極線寫 電壓之前開始施加或位元線寫人電麼可在施加源極線寫 電壓之前達到一恆定狀態（例如，第一位準）。 源極線寫入電壓應在字線寫入電壓之前施加，因為若字 線寫入電壓在源極線SL1之前改變為〇伏特，則浮體Β中之 電洞可藉由搞合t容器CC之麵合效應排出至位元線Bu或 SU。結果，+管所要資料資訊，而可能寫入資料"〇"。 又，如圖5之時序圖中所說明，字線保持電壓在源極線保 持電壓重施加於源極線SL1上之前重施加於字線wu上。 類似地，源極線SL1上之源極線保持電壓在位元線保持電 壓重施加於位元線BL1上之前重施加。詳言之，字線保持 電壓在源極線保持電壓重施加於源極線SL1上之前重施加 於字線WL1上，因為若源極線su在字線wu之前改變為〇 伏特，則歸因於浮體B與源極線SL1之間的正向電壓，浮 133200.doc -20- 200915319 體B中之電洞可經移除進入源極線SL1。結果，可損壞寫 入至記憶體單元MCI之資料” 1 ”。 另外，源極線SL1上之源極線保持電壓在位元線保持電 壓重施加於位元線BL1上之前重施加，因為若位元線Bu 在源極線SL1之前改變為〇伏特，則集極/汲極C/D及發射極/ 源極E/S上的電壓vds變為2伏特且BJT操作可發生。結果， 可損壞寫入至記憶體單元MC1之資料。 儘g圖5展不連接WL1及BLl-j (或BLi)之所有記憶體單元 由貝料1及資料"〇"中之一者寫入，但是此係出於簡要解 釋的目的。又’每一記憶體單元可根據相應位元線之電壓 被寫入資料”1"或資料"〇，，。 一圖5亦說明根據實例實施例之一讀取操作。如圖5中所 不，在T4期間針對連接至字線wu及源極線sli之一列單 元執行一讀取操作。 在讀取操作之前’如時間間隔T3中所示，位元線BLi具The bit line writes the power plane before the source line writes the human voltage, because if the source line SL1 becomes 2 volts before the bit line BL1, the collector/nom (5) and the emitter/source E/S The electric 遂Vds between the two becomes 2 volts. As shown in Figure 3, the BJT operation will occur and the holes can be accumulated in the floating body B. As a result, regardless of the desired information, it is possible to rewrite the data "Γ,. Enter, as shown in Figure 5, the application of bit line writes to the dust (or any electricity) is not instantaneous. The bit line write voltage can be applied before the source line write voltage is applied or the bit line writes the power to a constant state (eg, the first level) before the source line write voltage is applied. The write voltage should be applied before the word line write voltage, because if the word line write voltage is changed to 〇 volts before the source line SL1, the hole in the floating body can be made by engaging the surface of the t-container CC The effect is discharged to the bit line Bu or SU. As a result, the information required by the + tube may be written to the data "〇". Again, as illustrated in the timing diagram of Figure 5, the word line hold voltage is maintained at the source line. The voltage is reapplied to the word line wu before being applied to the source line SL1. Similarly, the source line holding voltage on the source line SL1 is reapplied before the bit line holding voltage is heavily applied to the bit line BL1. In detail, the word line hold voltage is applied to the source line to keep the voltage applied to The polarity line SL1 is previously applied to the word line WL1 because if the source line su is changed to 〇V volts before the word line wu, the floating voltage is 133200 due to the forward voltage between the floating body B and the source line SL1. .doc -20- 200915319 The hole in body B can be removed into the source line SL1. As a result, the data written to the memory unit MCI "1" can be damaged. In addition, the source line on the source line SL1 The hold voltage is reapplied before the bit line sustain voltage is applied to the bit line BL1, because if the bit line Bu changes to 〇V volts before the source line SL1, the collector/drain C/D and the emitter/ The voltage vds on the source E/S becomes 2 volts and the BJT operation can occur. As a result, the data written to the memory cell MC1 can be damaged. As shown in Fig. 5, the WL1 and BLl-j (or BLi) are not connected. All memory cells are written by one of the materials 1 and the data "〇", but for the purpose of brief explanation. Also 'each memory cell can be written according to the voltage of the corresponding bit line Information "1" or information "〇,,. Figure 5 also illustrates a read operation in accordance with an example embodiment. As shown in Fig. 5, a read operation is performed for a column unit connected to the word line wu and the source line sli during T4. Before the read operation' as shown in time interval T3, the bit line BLi has

有ώ力至其的位疋線保持電壓（例如，〇伏特），源'極線I 具有施加至其的源極線保持電壓（例如，0伏特），且字線 • ”有&加至其的予線保持電壓（例如，_ 1伏特），如圖5 中所示。 丑接者，列控制單元52將源極線讀取電壓（例如，2伏特） 供應至SU且繼續將源極線保持電壓(例如，0伏特)供應至 二有其他源極線SL2_i。列控制單元Μ繼續將字線保持電 座（例如，_1伏特）供應至WL1 -i。 4實允例中，可藉由僅供應連接至待讀取之記憶體 133200.doc -21 · 200915319 t元之源極線讀取電壓來執行—讀取操作。對於讀取操 ^位7L線BL1〜J在藉由保持電壓預充電之後可為電浮動 ' 』之電壓可根據記憶體單元中所儲存之資料 改變，亦即，行控制單元54不必在讀取操作期間將保持電 壓供應至位元線。艾，本， §將電壓感測放大器用作位元線感 測放大益時，而非在使用電流感測放大器之情形下，以上 解釋為可適用的。 可將單元之所有其他列MC2·.]維持於保持狀態，在該 狀態下施加位元線保持電壓（例如，〇伏特）、源極 壓（例如，〇伏特）及字線保持電壓（例如，韻特）。… 士圖3中所不，—旦汲極及源極上之電壓Vds達到2伏 特，則當V^-i伏特時，BJT操作僅對於資料"丄"單元發生 且未對於資料”0”單元發生。亦即，由BJT操作形成之讀取 $流U對於資料” i ”單元流動且讀取電Μ未對於資料”〇” 早兀流動（感測邊界）。在實例實施例中，寫人電流^可與 讀取電流i 1相同。 ~ 結果，資料可由利用(例如)電流感測放大器或電壓感測 放大器之隨後感測放大來識別。在實例實施例中，在列操 作中’諸如圖5中所說明，需要與位元線同樣多的感測： 大器，因為需讀取位元線中之每一者之資料。 另外，連接至所選源極線SL1之記憶體單元中所儲存之 資料” i ”及資料”0 ”可在-讀取操作期間分別由b jt操作及 耦合效應恢復。 圖5亦說明根據實例實施例之一再新操作。 I33200.doc -22-There is a bit line holding voltage (for example, volts) to which the source 'pole line I has a source line holding voltage (for example, 0 volts) applied thereto, and the word line • has & Its prewire holding voltage (eg, _1 volt) is shown in Figure 5. Ugly, column control unit 52 supplies the source line read voltage (eg, 2 volts) to the SU and continues to source. The line hold voltage (eg, 0 volts) is supplied to the other source line SL2_i. The column control unit Μ continues to supply the word line hold block (eg, _1 volts) to WL1 -i. The read operation is performed by supplying only the source line read voltage connected to the memory 13320.doc -21 · 200915319 t to be read. For the read operation, the 7L lines BL1 to J are held by the voltage The voltage that can be electrically floating after pre-charging can be changed according to the data stored in the memory unit, that is, the row control unit 54 does not have to supply the holding voltage to the bit line during the read operation. Ai, Ben, § Use a voltage sense amplifier as a bit line sense amplifier, rather than using current In the case of a amp, the above explanation is applicable. All other columns MC2·.] of the cell can be maintained in a hold state in which a bit line holding voltage (for example, volts) and source voltage are applied ( For example, 〇 volts and word line hold voltage (for example, rhyme).... In Figure 3, if the voltage Vds on the drain and source reaches 2 volts, then when V^-i volts, BJT operation Only for the data "丄" unit occurs and does not occur for the data "0" unit. That is, the read stream formed by the BJT operation flows for the data "i" unit and the reading power is not for the data" Early flow (sensing boundary). In the example embodiment, the write current ^ can be the same as the read current i 1 . ~ As a result, the data can be utilized by, for example, a sense of a current sense amplifier or a voltage sense amplifier. Amplification is used to identify. In an example embodiment, in column operations, such as illustrated in Figure 5, as much sensing as the bit line is required: large, because each of the bit lines needs to be read. In addition, connect to the selected source line SL1 The data "i" and data "0" stored in the memory unit can be recovered by the bjt operation and the coupling effect during the -read operation, respectively. Figure 5 also illustrates a new operation according to one of the example embodiments. I33200.doc - twenty two-

僅以可在資料單元”"下引發BJT操作之電壓來對源極線 電以再新連接至源極線SLi之所有記憶體單元。亦 即’資料”1”記憶體單元由操作再新且資料"『單元由 祕線與浮體之間的搞合效應再新。列控制單元52繼續將 子’友保持電壓（例如，_丨伏特）供應至WL i ]。 200915319The source line is electrically reconnected to all memory cells of the source line SLi only by the voltage that can initiate the BJT operation under the data unit "". That is, the 'data' 1" memory unit is renewed by operation. And the data " "the unit is renewed by the effect of the secret line and the floating body. The column control unit 52 continues to supply the child 'friend holding voltage (for example, _ 丨 volt) to WL i ].

在一再新操作之前，如時間M w呀間間隔T5中所示，位元線BLi 具有施加至其的位元線保捭雷厭 . 丨卞付冤壓（例如，0伏特），源極線 SLi具有施加至其的源極線伴 冰饰符電壓（例如，0伏特），且字 線WLi具有施加至其的字線伴 丁冰诉符電壓（例如，-1伏特），如 圖5中所示。 田由外部裝置或-内部控制電路發出一再新指令時， 列控制單元52將一再新雷厭，加， • 丹祈電壓（例如，2伏特）供應至所有源極 線S L1 - j。又，列控制罝分ς。π ^ , 早凡52可依X人將該再新電壓供應至 或兩個源極線’使得在再新操作期間可減少電流流 出。在再新操作之時間啟動之源極線的數目可由使用者使 用下文中，合圖20更詳細描述之設定步驟來設定。 (( 中斤示在再新週期丁refresh期間，流經連接至資料 “單兀之位7C線BL之電流u流動。在實例實施例中，再 新電可與讀取電流ii及/或寫入電流u相同。 _在只例實施例中’再新操作可藉由將再新電壓供應至位 元線中之卜_ ^ 一者而非將電壓供應至源極線中之至少一者 來執行。 如圖5中所示 操作之電壓供應 ’正再新所有源極線SLi。 至所有源極線或所有位元 若將可引發BJT 線，則可再新所 133200.doc •23- 200915319 有記憶體單元。此可被稱作區塊再新。 在實例實施例中，用於同時再新操作之所選源極線之數 可為由使用者使用之模式暫存器中的源極線總數之子集 :例如’兩個或四個或八個)’其將在下文中關於圖汕更詳 :地加以描述。如上文所論述，此可被稱作部分再新操 作。 c 在實例實施例中，再新操作之後不必為感測操作。 ，明圖4之記憶體敦置之一個單元操作的時序圖。圖 ^兒明-寫人操作（寫人f料"丨"與㈣，，G")、—讀取操作及 :再新操作之實例時序圖。在下文所論述之實例實施例 該再新操作可為區塊再新操作或部分再新操作。 如圖6中所示，僅對連接至位元線Bu、如及如之一 記憶體單itMCM執行寫人操作及讀取操作，且連接至sli 及wL1之所有其他MC1單元處於抑制狀況。除了寫入操作 及讀取操作兩者之抑制狀況，圖6之描述與圖5的描述相 同。 η。如,文所描述’圖5與圖6之間的差別為，在圖6中，僅 單早7L正被寫入或讀取，而非一整個列。結果，在圖6 中，該列中之單元之未在被寫入或讀取之剩餘單元受抑 制：在實例實施例中’藉由將位元線寫入抑制電壓或位元 線，取抑制電壓分別施加至位元線B L 2〜j來抑制對該列中 之單元之剩餘單元進行寫入或讀取。 對於寫人操作，在TMT2期間，對位元線犯〜】施加位 元線寫入抑制電壓（例如，i伏特）。結果， v d s两i伏特’ 133200.doc -24- 200915319 如圖3中所示，防止了 BJT摔作 保怍且不存在電流。類似地，對 於項取操作，在了4期問，科/ _ 疋線BL2〜j施加位元線讀取 抑制電壓（例如，1伏特）。纟士要v . 一 )、’。果，Vds為1伏特，且如圖3中 所示，防止了 BJT操作且不存在電流。 圖6中所不’關於再新操作，再新操作與圖5相同。 ^ 6之時序圖顯而易見，記憶體單元陣列之隨機存取 操作為可能的。 如圖5及圖ό中所示，記丨音 ^ U體裝置僅需要兩個電壓位準 (子線寫入電壓及字線保持電 电& )用於寫入、讀取及再新操 作’此情形可允許設計者具有更大靈活性。 圖7說明根據實例實施例之圮惰 己隐體裝置。與根據圖4(說 明一獨立源極線架構）中所 再’T所說明之實例實施例之記憶體裝 置相對，根據圖7的實你丨眘& y , 舉圚的貫例實苑例之記憶體裝置說明一 源極線架構，其中鄰近記恃 〇 州迎0己隐體皁兀MC2及MC3共用（例如 相應源極線SL2。圖7之齋|鉻加八 u ) s山〃 ®之剩餘部分之描述與圖4之描述相同 且出於簡要的目的將不再重複。 如圖7中所示，源極線SLk之數目少於字線呢之數目。 :配置之優勢可為減小布局複雜性。另外，如圖4之實例 實施例中所闡明，列控制單 單-控制單元。 早7了控制早❿可建構為 圖8說明圖7之記憶體袭置之-列的時序圖。圖8說明— 寫入操作⑺人資們”與資料”心—讀取操作及一 操作之實例時序圖。在下文八 卜又所淪述之實例實施例中，再新 操作可為區塊再新操作或部分再新操作。 133200.doc •25- 200915319 圖8之時序圖類似於圖5中所說明之時序圖，除了在τ〇、 5期間Vg可更負（例如，如負至_2伏特之程度）於圖$ 中所說明的vg外’因為共用共同源極線sLk之電晶體更有 可能斷開。 在圖8中所說明之實例實施例中，用於位元線BU十源 極線SL1〜j與字線WLH之間的寫人操作之㈣㈣序列 可與圖5中所展示之相同。 如圖8之時序圖中所說明，對於資料””，在。期間， 〜為2伏特且、為〇伏特，所以根據圖3,流經位元線 j之電机13由BJT操作的突崩產生而引發。對於資料 ’T ’在T2期間，儘管^為2伏特且ν§為_2伏特，但是流經 位^缘BL1〜j之電流i4亦由BJT操作之突崩產生而引發因 為浮體電壓可能仍伴牲q ,、，+ & 此仍保持足以在位兀線BL1〜j之間產生正向 偏壓。如圖8中所示，扃拉Μ ·Η 夺間週期Τ2期間，流經位元線 B L1〜j之電流i 4小於ί 3，，th /f备田*人 此係因為耦合電容器CC之耦合效 ί. 應使浮體電位降低所致。 如圖8之時序圖中所說明，對於資料"0"m時間， 物.5伏特且、為〇伏特，所以根據圖 作之突崩產生。結果，盎雷3 & π, J 丁刼 無電流"丨1·經位元線BL1〜j。類似 地，對於資料”〇”，在T2i ， 、 隹12期間，vd4 h5伏特且、為_2伏 特，所以根據圖3,未發生BJT操作之突崩產生。結果，無 電流流經位元線BL1〜j。 … 在實例實施例中，字線寫入電壓可為]伏特，而非。伏 特’如圖5及圖8兩者中所示。 I33200.doc -26- 200915319 如圖8中所說明，儘管替代用於字線WLi之兩位準電壓 而可使用用於字線WLi之三位準電壓（例如，韻特、」伏 特及〇伏特），但是如圖5中所示，亦可使用如圖㈣兩位準 電壓（例如，_ 1伏特及〇伏特）。 在圖8中所說明之實例實施例巾，用於位元線BL1十源 極線SU〜j與字線WL1〜j之間的讀取操作之控制信號序列 可與圖5中所展示之大體上相同，差別如下。 ，圖8中所示，對於讀取操作，列控制單元52將源極線 項取電_如’ 2伏特）供應至su且繼續將源極線保持電 壓（例如，〇伏特）供應至所有其他源極線SL2-i。列控制單 =接著將字線讀取電壓（例如，韻特）供應至wu且繼 ::字線保持電壓(例如’_2伏特)供應至所有其他字線 WL2-1 〇 彡實例實施例中’可藉由僅供應連接至待讀取之記憶體 Ο 早凡之源極線讀取電屋來執行讀取操作。對於讀取操作， 位元線B L 1〜j在 的， 糟由保持電壓預充電之後可為電浮動式 變，:BLH之電壓可根據記憶體單元中所儲存之資料改 雁/、即’行控制單元54不必在讀取操作期間將保持電麼 供應至位元線。s ^ ,^ _ 田電堅感測放大器用作位元線感測放 ^時’而非在使用電流感測放大器之情形下，以上解釋 為可適用的。 如圖3中所示， 特，則當、為-1伏：：汲極及源極上之電壓Vds達到2伏 且未對於資料，^特時，BJT操作僅對於資料T單元發生 早凡發生。亦即，由BJT操作形成之讀取 I33200.doc -27- 200915319 電流ι5對於資料"i ”單元流動且讀取電流i5未對於資料"〇" 單元流動（感測邊界）。 果’負料可由利用（例如）電流感測放大器或電壓感測 放大器之隨後感測放大來識別。 另外，在讀取操作期間，資料"1"及資料"0"可分別藉由 BJT操作及麵合效應來恢復。Before repeated new operations, as shown in the time interval M5 of the time M w , the bit line BLi has a bit line applied thereto, which is 捭 . . . ( ( 例如 例如 例如 ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( SLi has a source line with a squirt voltage applied thereto (eg, 0 volts), and the word line WLi has a word line applied thereto (eg, -1 volt), as in FIG. Shown. When the field is issued a new command by the external device or the internal control circuit, the column control unit 52 supplies a new rush, plus, and a voltage (for example, 2 volts) to all of the source lines S L1 - j. Also, the column control is divided into two categories. π ^ , the early 52 can supply the re-new voltage to the two source lines according to the X person's so that the current can be reduced during the re-operation. The number of source lines activated at the time of the re-operation can be set by the user using the setting steps described in more detail below in connection with FIG. ((In the example embodiment, the new power can be read with the current ii and / or write during the re-refresh period, flowing through the data connected to the data "single-bit 7C line BL". The input current u is the same. _ In the example embodiment, the 'renew operation can be performed by supplying the renewed voltage to the bit line _ ^ instead of supplying the voltage to at least one of the source lines. Execution. The voltage supply as shown in Figure 5 'renews all source lines SLi. To all source lines or all bits can trigger the BJT line, then re-news 133200.doc •23- 200915319 There is a memory unit. This may be referred to as a block renew. In an example embodiment, the number of selected source lines for simultaneous re-operation may be the source in the mode register used by the user. A subset of the total number of lines: for example 'two or four or eight', which will be described in more detail below with respect to the figures. As discussed above, this may be referred to as a partial re-operation. In the example, after the new operation, it is not necessary to be a sensing operation. Timing diagram of the figure - Figure - Writer operation (write man f " 丨 " and (4),, G"), - read operation and: example operation diagram of the new operation. Examples discussed below Embodiments The re-operation may be a new operation or a partial re-operation of the block. As shown in FIG. 6, only the write operation and the read are performed on the connection to the bit line Bu, such as a memory single itMCM. The operation is taken, and all other MC1 units connected to sli and wL1 are in a suppressed state. Except for the suppression states of both the write operation and the read operation, the description of Fig. 6 is the same as that of Fig. 5. η. The difference between Figure 5 and Figure 6 is that in Figure 6, only 7L is being written or read, rather than an entire column. As a result, in Figure 6, the cells in the column are not in The remaining cells to be written or read are suppressed: in the example embodiment, by writing the bit lines to the suppression voltage or the bit lines, the suppression voltages are respectively applied to the bit lines BL 2 to j to suppress the The remaining units of the cells in the column are written or read. For the writer operation, during the TMT2, the bit line is committed~ Applying a bit line write suppression voltage (for example, i volts). As a result, vds two i volts '133200.doc -24- 200915319 as shown in Figure 3, prevents BJT from falling and no current. Ground, for the item fetch operation, in the fourth period, the branch / line _ BL line BL2 ~ j applies the bit line to read the suppression voltage (for example, 1 volt). The gentleman wants v. a), '. fruit, Vds is 1 volt, and as shown in Figure 3, BJT operation is prevented and there is no current. Figure 6 is not the same as the re-new operation, the new operation is the same as Figure 5. The timing diagram of ^ 6 is obvious, the memory cell array Random access operations are possible. As shown in Figure 5 and Figure ,, the recording device requires only two voltage levels (sub-line write voltage and word line hold electric &) for writing, reading and re-operation. 'This situation allows the designer to have more flexibility. Figure 7 illustrates a slotted self-contained device in accordance with an example embodiment. In contrast to the memory device of the example embodiment illustrated in FIG. 4 (which illustrates an independent source line architecture), according to FIG. 7, the example of the example is the case. The memory device illustrates a source line architecture in which the adjacent crypto-sacral saponins MC2 and MC3 are shared (for example, the corresponding source line SL2. Figure 7) | chrome plus eight u) s Hawthorn ® The description of the remainder of the description is the same as that of FIG. 4 and will not be repeated for the sake of brevity. As shown in FIG. 7, the number of source lines SLk is smaller than the number of word lines. : The advantage of configuration can be to reduce layout complexity. Additionally, as illustrated in the example embodiment of Figure 4, the column controls the single-control unit. The early control can be constructed as shown in Fig. 8 to illustrate the timing diagram of the memory hit-column of Fig. 7. Figure 8 illustrates an example timing diagram for the write operation (7) of the "people" and "data" heart-read operations and an operation. In the example embodiments described in the following paragraphs, the re-new operation may be a block re-operation or a partial re-operation. 133200.doc •25- 200915319 The timing diagram of Figure 8 is similar to the timing diagram illustrated in Figure 5, except that during τ〇, 5 Vg can be more negative (for example, as negative to _2 volts) in Figure $ The described vg is 'because the transistor sharing the common source line sLk is more likely to break. In the example embodiment illustrated in Fig. 8, the sequence of (4) (four) for the write operation between the bit line BU source line SL1 to j and the word line WLH may be the same as that shown in Fig. 5. As illustrated in the timing diagram of Figure 8, for the data "", at. During the period, ~ is 2 volts and is volts, so according to Fig. 3, the motor 13 flowing through the bit line j is caused by the collapse of the BJT operation. For the data 'T' during T2, although ^ is 2 volts and ν§ is _2 volts, the current i4 flowing through the edge BL1~j is also caused by the collapse of the BJT operation because the floating body voltage may still be This is still sufficient to generate a forward bias between the bit lines BL1~j. As shown in FIG. 8, during the period Τ2, the current i 4 flowing through the bit lines B L1 to j is less than ί 3 , and the th / f is due to the coupling capacitor CC. Coupling effect. The floating body potential should be reduced. As illustrated in the timing diagram of Fig. 8, for the data "0" m time, the object is 5 volts and is volt-volt, so the collapse is generated according to the figure. As a result, Angstrom 3 & π, J 刼 刼 no current " 丨 1 · meridian line BL1 ~ j. Similarly, for the data "〇", during T2i, 隹12, vd4 h5 volts and _2 volts, so according to Fig. 3, no collapse occurred in the BJT operation. As a result, no current flows through the bit lines BL1 to j. ... In an example embodiment, the word line write voltage can be ] volts instead. Volts are shown in both Figures 5 and 8. I33200.doc -26- 200915319 As illustrated in Fig. 8, although instead of the two quasi-voltage for word line WLi, a three-level voltage for word line WLi (for example, rhyme, volts and volts can be used) ), but as shown in FIG. 5, it is also possible to use a two-level voltage as shown in FIG. 4 (for example, _1 volt and volts). In the example embodiment illustrated in FIG. 8, the control signal sequence for the read operation between the bit line BL1 ten source lines SU to j and the word lines WL1 to j can be substantially the same as that shown in FIG. The same, the difference is as follows. As shown in FIG. 8, for the read operation, the column control unit 52 supplies the source line item power-up, such as '2 volts, to su and continues to supply the source line holding voltage (eg, volts) to all others. Source line SL2-i. Column control list = then supply the word line read voltage (eg, rhyme) to wu and follow: :: word line hold voltage (eg '_2 volts) supplied to all other word lines WL2-1 〇彡 in an example embodiment The reading operation can be performed by supplying only the source line connected to the memory to be read and the source line. For the read operation, the bit lines BL 1 to j are in the form of electric floating type after pre-charging by the holding voltage, and the voltage of the BLH can be changed according to the data stored in the memory unit. Control unit 54 does not have to be powered to supply to the bit line during the read operation. s ^ , ^ _ The field is used as a bit line senser when the sense amplifier is used, rather than in the case of a current sense amplifier, the above explanation is applicable. As shown in Fig. 3, in particular, the voltage Vds on the -1 volt:: drain and source reaches 2 volts and is not for the data, the BJT operation occurs only for the data T unit. That is, the reading formed by the BJT operation I33200.doc -27- 200915319 current ι5 flows for the data "i" unit and the reading current i5 is not for the data "〇" unit flow (sensing boundary). The negative material can be identified by subsequent sensing amplification using, for example, a current sense amplifier or a voltage sense amplifier. Additionally, during the read operation, the data "1" and data"0" can be operated by BJT and Face-to-face effects to recover.

在圖8中所說明之實例實施例中，用於位元線Bu〜』、源 極線SL1〜j與字線WL1〜j之間的再新操作之控制信號序列 可與圖5中所展示的讀取操作大體上相同，除了列控制單 元5 2選擇至少兩個字線w L丨且將字線再新電壓供應至該至 少兩個字線WLi外4線再新電壓可等於字線讀取電壓， 且讀取電流i5可與再新電流i6相同。又，用於圖5之再新操 作之相同解釋可應用於圖8的再新操作。 圖9說明圖7之記憶體裝置之一個單元操作的時序圖。圖 9說明-寫入操作（寫入資料"i，，與資料”❹”）、—讀取操作及 一再新操作之實例時序圖。在下文所論述之實例實施例 中，再新操作可為區塊再新操作或部分再新操作。 如圖9中所*，僅對連接至位元線BU、sLMWLi之一 記憶體單元執行寫入操作及讀取操作，且連接至⑴ 及wu之㈣其他MC1單元處㈣卩魏i除了寫入操作 及知取操作兩者之抑制狀況，圖9之描述與圖峨 同。 差別為，在圖9中，僅 整個列。結果，在圖9 如上文所描述，圖8與圖9之間的 單一單元正被寫入或讀取，而非_ 133200.doc •28· 200915319 制。在實^%之未在被寫人或讀取之剩餘單元受抑 線讀取Γ 中，藉由將位元線寫入抑制電壓或位元 之單元之、電物施加至位元線BL2〜j來抑制對該列中 早70之剩餘單元進行寫入或讀取。 元操作，在T1及T2期間，對位元線叫施加位 、·寫入抑制電壓（例如，i伏特）。結果 如圖3中斯- ds^ 1伏特，且 中所不，防止了 BJT操作且不存在電流。In the example embodiment illustrated in FIG. 8, the control signal sequence for the re-operation between the bit line Bu 〜 』, the source lines SL1 djj and the word lines WL1 djj can be as shown in FIG. The read operation is substantially the same except that the column control unit 52 selects at least two word lines w L 丨 and supplies the word line renewed voltage to the at least two word lines WLi. The new line can be equal to the word line read. The voltage is taken, and the read current i5 can be the same as the renewed current i6. Again, the same explanation for the renewed operation of Figure 5 can be applied to the re-operation of Figure 8. Figure 9 illustrates a timing diagram of a unit operation of the memory device of Figure 7. Figure 9 illustrates an example timing diagram for a write operation (write data "i,, and data"❹), a read operation, and a new operation. In the example embodiments discussed below, the re-new operation may be a block re-operation or a partial re-operation. As shown in FIG. 9, only the write operation and the read operation are performed on one of the memory cells connected to the bit line BU and the sLMWLi, and are connected to (1) and wu (4) at the other MC1 unit (four), except for the write The suppression of both the operation and the known operation, the description of Figure 9 is the same as the figure. The difference is that in Figure 9, only the entire column. As a result, as described above in Fig. 9, a single unit between Fig. 8 and Fig. 9 is being written or read instead of _ 133200.doc • 28· 200915319. In the case where the real part is not written by the written person or the remaining unit of the read line is suppressed, the electric substance is applied to the bit line BL2 by writing the bit line to the cell of the suppression voltage or the bit. j to suppress writing or reading of the remaining cells of the early 70 in the column. The meta-operation, during T1 and T2, applies a bit, write suppression voltage (for example, i volts) to the bit line. As a result, as shown in Figure 3, s-ds^1 volt, and no, prevents BJT operation and no current.

類似地，對於讀取操作，在T4期間，對位元線B 加位元線讀取抑制電壓(例如 ：:： 特，且如阁^ 、、口果，Vds為1伏 圖3中所示，防止了 BJT操作且不存在電流。 ° 9中所示，關於再新操作，再新操作與圖8相同。 自圖9之時序圖顯 操作為可能的。易見心體早4狀隨機存取 ^圖8及圖9中所說明，儘管展示三位準電壓（例如，〇伏 取電2線寫入電昼Μ伏特用於字線再新電麼及字線讀 且2伏特用於字線保持電壓）用於字線WLi，但亦 I使用兩位準電壓（例如，對於字線乳卜〇伏特用於字線 .、、、入電壓且-1伏特用於字線保持電壓、字線讀取電壓及字 線再新電壓，如圖5中所示）。 、回《月根據實例實施例之記憶體裝置。圖】〇說明包括 複數個L己憶體區塊BK1、BK2、BKn以及一列控制單元及 Γ控制單疋之5己憶體裝置。在實例實施例中，每一記憶體 單元區塊可與圖4及圖7中所示之記憶體單元區塊相同或類 、另外’如圖10中所示’感測放大器SA1至SAn可提供 133200.doc •29· 200915319 於。己憶體區塊之間。在實例實施例中，感測放大器s A丄至 S An可為電壓感測放大器或電流感測放大器。 又，圖1 0展示開放位元線結構，然而，圖10之教示亦可 應用於摺疊式位元線架構。 在圖10中所說明之實例實施例中，記憶體單元陣列可包 括諸:it ® 4或圖7中所說明之記憶體單a區塊的複數個記憶 體單元區塊，且可讀取來自所選記憶體單元區塊中之至少 者之貝料且將資料寫入所選記憶體單元區塊中的至少一 者。在：例實施例中，％控制單元52，，可回應於寫入指令 WR ' 4取指令RD及/或位址指令ADD選擇記憶體區塊中之 至夕者及该所選記憶體區塊内之源極線SLi及字線Wu且 供應適當電壓以分別選擇恰當SL及WL。 又’列控制單元52，，可回應於再新信號聊選擇記憶體 者且將一再新電壓 區塊中之至少—本n必 塊中之至少兩個源極線儿丨。又，Similarly, for the read operation, during the period T4, the bit line is read with the bit line to suppress the voltage (for example:::, and, as in the case, the fruit, the Vds is 1 volt as shown in FIG. BJT operation is prevented and there is no current. As shown in Fig. 9, for the new operation, the new operation is the same as that of Fig. 8. It is possible to operate the timing chart from Fig. 9. It is easy to see the heart shape and the memory is early. Take the description of Figure 8 and Figure 9, although the three-level quasi-voltage is shown (for example, the two-line write volts for the word line and the new word line and the word line read and 2 volts for the word Line hold voltage) is used for word line WLi, but I also uses a two-quasi-voltage (for example, for word line 〇 volts for word lines., ,, input voltage and -1 volt for word line hold voltage, word The line read voltage and the word line re-new voltage, as shown in FIG. 5), back to the memory device according to the example embodiment. Figure 〇 Description includes a plurality of L memory blocks BK1, BK2, BKn And a column of control unit and 己 control unit 5 of the memory device. In the example embodiment, each memory unit block can be compared with FIG. 4 and FIG. The memory cell blocks shown are the same or similar, and 'the sense amplifiers SA1 to SAn as shown in FIG. 10 can provide 133200.doc • 29· 200915319 between the memory blocks. In the example embodiment The sense amplifiers s A 丄 S S may be voltage sense amplifiers or current sense amplifiers. Also, FIG. 10 shows an open bit line structure, however, the teaching of FIG. 10 can also be applied to a folded bit line. In the example embodiment illustrated in FIG. 10, the memory cell array may include: it ® 4 or a plurality of memory cell blocks of the memory single a block illustrated in FIG. 7, and is readable. Taking at least one of the selected ones from the selected memory unit block and writing the data to at least one of the selected memory unit blocks. In an example embodiment, the % control unit 52, may respond to The write command WR '4 fetch instruction RD and/or the address command ADD selects the source line SLi and the word line Wu in the memory block and the selected memory block and supplies the appropriate voltage to respectively Select the appropriate SL and WL. Also 'column control unit 52, can respond to the new signal chat Selecting the memory and at least two of the source blocks in the new voltage block will be at least two source lines.

記憶體裝置之所有記 一再新電壓供應至該所選記憶體區 SLi。又，列控制單元52··可當其將 選記憶體區塊中之所有源極線SLi 可藉由將該再新電壓供應至每一記All of the memory device's new voltage is supplied to the selected memory region SLi. Moreover, the column control unit 52·· can supply all of the source lines SLi in the selected memory block by supplying the renewed voltage to each of the records.

133200.doc f丁徑制皁元54"根據視一個列操作或 資料資訊來控制位元線電壓位準。 可藉由將某電壓供應至至少一位元線 。若將該某電壓施加至所有位元線 體單元陣列中之所有記憶體單元。該 -30 - 200915319 某電壓可與供應至一源極線之再新電壓相同。 在圖10中所說明之實例實施例令，每-感測放大區塊 SA1-n可在寫人操作期間將f料資訊供應至相應位元線且 感測及放大記憶體單元之資料。對於_個列操作，可能有 多達感測放大器SAn之數目。對於隨機存取操作，可能有 少於感測放大器SAn之數目。 至此’已根據實例實施例解釋包括無電容器記憶體單元 之記憶體裝置之BJT操作。㈣圖1A及圖1β之記憶體單元 結構可用於上文圖4、圖7及圊1〇所闡明之記憶體裝置，但 下文將描述用於根據實例實施例的圖4、圖7及圖ι〇之記憶 體裝置之額外新記憶體單元結構。出於簡要之目的，以下 圖式中之記憶體單元的相同組件將具有相同參考數字。 圖11A至圖11B說明根據實例實施例之記憶體單元結 構。如所說明，源極線可連接至集極/汲極c/d且位元線可 連接至發射極/源極E/s。在實例實施例中，矽層中之第一 節點14及第二節點16可經N摻雜。在實例實施例中，發射 極/源極E/s之摻雜程度可大於集極/汲極(：/〇(例如，N+)。 在實例實施例中，浮體區域18可經p摻雜。在實例實施例 中，如圖11A中所說明，在閘極與發射極/源極E/S及/或集 極/汲極C/D之間不存在重疊。如圖丨丨a中所示，浮體區域 18與發射極/源極E/s及/或集極/汲極C/D之間的邊界之輪廓 有任何形狀’只要閘極與發射極/源極E/s及/或集極/ 汲極C/D之間不存在重疊。 圖中所示，感測邊界可藉由資料"1"單元與資料"〇"單 133200.doc -31- 200915319 元之間的vds之差來確定。為增加感測邊界，應減小閘極 與浮體之間的閘極G的相對汲極電容CD或源極電容cs之電 容。133200.doc f-small soap unit 54" control the bit line voltage level according to a column operation or data information. By supplying a voltage to at least one bit line. If a certain voltage is applied to all of the memory cells in all of the bit line cell arrays. The -30 - 200915319 voltage can be the same as the renewed voltage supplied to a source line. In the example embodiment illustrated in Figure 10, the per-sensing amplification block SA1-n can supply f-material information to the corresponding bit line and sense and amplify the data of the memory cell during the write operation. For _ column operations, there may be as many as the number of sense amplifiers SAn. For random access operations, there may be fewer than the number of sense amplifiers. Up to now, the BJT operation of the memory device including the capacitorless memory unit has been explained in accordance with an example embodiment. (d) The memory cell structure of FIGS. 1A and 1β can be used for the memory device illustrated in FIGS. 4, 7, and 1 above, but will be described below with reference to FIG. 4, FIG. 7, and FIG. 1 according to an example embodiment. An additional new memory cell structure for the memory device. For the sake of brevity, the same components of the memory cells in the following figures will have the same reference numerals. 11A through 11B illustrate a memory cell structure in accordance with an example embodiment. As illustrated, the source line can be connected to the collector/drain c/d and the bit line can be connected to the emitter/source E/s. In an example embodiment, the first node 14 and the second node 16 in the germanium layer may be N doped. In an example embodiment, the emitter/source E/s may be doped to a greater extent than the collector/drain (:/〇 (eg, N+). In an example embodiment, the floating region 18 may be p-doped. In the example embodiment, as illustrated in Figure 11A, there is no overlap between the gate and emitter/source E/S and/or collector/drain C/D. As shown in Figure 丨丨a It is shown that the contour of the boundary between the floating body region 18 and the emitter/source E/s and/or the collector/drain C/D has any shape 'as long as the gate and emitter/source E/s and/or There is no overlap between the collector/bungee C/D. As shown in the figure, the sensing boundary can be obtained by the data "1"unit &data"〇" single 133200.doc -31- 200915319 The difference in vds is determined. To increase the sensing boundary, the capacitance of the relative gate capacitance CD or the source capacitance cs of the gate G between the gate and the floating body should be reduced.

結果，在閘極與源極及/或汲極之間不存在重疊。由於 閘極G與發射極/源極e/s及集極/汲極C/D之間的大空間， 非重疊s己憶體單元結構可具有慢於圖丨A之記憶體單元結構 之能帶斜率。結果，相比圖1A之記憶體單元結構，可減小 最大電場及/或亦可降低再結合速率。歸因於此等特徵， 圖11A之非重疊記憶體單元結構展示更佳保存時間及，或更 佳漏電特徵。 另外，可減小可降級資料”G"之閘極誘發汲極漏電流 —現象，因為閉極與沒極之間的電容Cgd變得更小。 另外’可藉由使絕緣層2〇更薄央诂 r „ , 尺，寻來補償閘極之降低之電容As a result, there is no overlap between the gate and the source and/or drain. Due to the large space between the gate G and the emitter/source e/s and the collector/drain C/D, the non-overlapping s-resonant cell structure can have a slower memory cell structure than the graph A. With slope. As a result, the maximum electric field can be reduced and/or the recombination rate can be reduced as compared to the memory cell structure of Fig. 1A. Due to these characteristics, the non-overlapping memory cell structure of Figure 11A exhibits better retention time and, or better leakage characteristics. In addition, the gate leakage induced current leakage phenomenon of the degradable data "G" can be reduced because the capacitance Cgd between the closed pole and the pole is made smaller. In addition, the insulating layer 2 can be made thinner.诂 r „ , ruler, find the capacitor to compensate for the lowering of the gate

Lg以保濩閘極與浮體18之間 中，問代I由 稍0電谷。在實例實施例 T閘極長度L2小於浮體長声τ〗 性 又。此等參數可改良可縮放 儘管圖11Α中未圖示，但閘 節點16中之僅一者。舉例而 疊第-節點14及第二 及第二節點16中之在雙極接面操^❹疊第—節點14 電壓之一者。 T 4間接收所施加之較高 感測邊界可視資料"丨，，單元與 所儲存之電荷差而定。因广〇 '單凡之間的浮體中 單元之電荷且因此資料"丨，，之浮 早π具有多於資料”0” 浮體電位，所以BJT操作對^體電仅高於資料"0"單元的 、-料”1”單元比在資料"〇"單 13320〇>(]〇c * 32 - 200915319 元中發生得更快。此可由圖3展示，其中對於所有％資料 ”1”單元位於資料”〇”單元左側。 結果’若在寫人操作期間更多電荷可儲存於資們”軍 元之浮體中，則將達成更佳感測邊界。 又’基極與集極之間電子之散逸或平均自由路徑可長於 圖1A之電子之散逸或平均自由路徑。結果，突崩產生之衝 擊離,化可更易於發生。結果，更多電荷可儲存於資料 二單元之浮體中。在實例實施例中，發射極/源極e/s之雜 貝浪度可大於集極/汲極C/D之雜質濃度。另外，如在實例 實施例中所闡日月，歸因於負的保持字線電壓，藉由bjt操 作累積之電洞可保持於接近閘極〇處。如圖丨ia中所示， 右接近閘極G之浮體區域18可寬於浮體區域18之至少一其 他部分’則可改良保存時間。 圖11B說明根據實例實施例之垂直記憶體單元結構。如 圖11B中所說明，垂直無電容器記憶體單元可包括基板 1〇、垂直堆疊於基板1〇上之第一節點14、浮體區域18及第 二節點16。浮體區域18為電浮動式的。如圖UB中所示， 浮體區域18可具有浮體長度L1。 閘極絕緣層20及閘極22可包圍浮體18。舉例而言，閘極 絕緣層20及閘極22可接觸浮體18之兩個或兩個以上側面之 全部或一部分。若垂直無電容器記憶體單元為NM〇s電晶 體’則第一節點14及第二節點16可具有第一傳導類型（例 如’ N傳導類型），且浮體區域18可具有第二傳導類型（例 如，P傳導類型）。又，垂直電容器結構可具有SOI基板或 133200.doc •33 - 200915319 如圖11B中所示之習知塊體基板。 如所說明，源極線可連接至集極/汲極C/D且位元線可連 接至發射極/源極E/s。在實例實施例中，如圖丨1β中所說 明’在閘電極與發射極/源極^/8及/或集極/汲極c/D之間不 存在重f。上文關於圖11A描述之其他特徵亦可存在於圖 11B之垂直結構中。 圖12A及圖12B說明根據實例實施例之單元結構。如圖Lg is between the gate and the floating body 18, and the generation I is slightly 0. In the example embodiment, the T gate length L2 is smaller than the floating body length τ. These parameters can be improved for scaling. Although not shown in Figure 11, only one of the gate nodes 16 is shown. For example, one of the voltages of the first-node 14 and the second and second nodes 16 in the bipolar junction overlaps the first-node 14 voltage. The higher sensing boundary information (", received by the T4) is determined by the difference between the cell and the stored charge. Because of the charge of the unit in the floating body between the singular and the data "丨, the floating π has more than the data "0" floating body potential, so the BJT operation is only higher than the data " ;0" unit, material "1" unit occurs faster than in the data "〇" single 13320〇>(]〇c * 32 - 200915319 yuan. This can be shown by Figure 3, where for all % The data "1" unit is located on the left side of the data "〇" unit. The result 'If more charge can be stored in the floating body of the military during the writing operation, a better sensing boundary will be achieved. The dissipation or mean free path of electrons between the collector and the collector can be longer than the dissipation or average free path of the electron of Figure 1A. As a result, the impact of the collapse can be more likely to occur. As a result, more charge can be stored in the data. In the floating body of the unit, in the example embodiment, the impurity wave of the emitter/source e/s may be greater than the impurity concentration of the collector/drain C/D. In addition, as illustrated in the example embodiment Month, due to the negative hold word line voltage, the holes accumulated by the bjt operation can be maintained Close to the gate 。. As shown in Figure ia, the right floating body region 18 close to the gate G can be wider than at least one other portion of the floating body region 18 to improve the retention time. Figure 11B illustrates an example implementation. Vertical memory cell structure. As illustrated in FIG. 11B, the vertical capacitorless memory cell can include a substrate 1 , a first node 14 stacked vertically on the substrate 1 , a floating body region 18 , and a second node 16 . The floating body region 18 is electrically floating. As shown in Figure UB, the floating body region 18 can have a floating body length L1. The gate insulating layer 20 and the gate 22 can surround the floating body 18. For example, the gate insulation The layer 20 and the gate 22 may contact all or a portion of two or more sides of the floating body 18. If the vertical capacitorless memory unit is an NM〇s transistor, the first node 14 and the second node 16 may have The first conductivity type (eg, 'N conduction type), and the floating body region 18 can have a second conductivity type (eg, P conduction type). Again, the vertical capacitor structure can have an SOI substrate or 133200.doc • 33 - 200915319 as shown A conventional bulk substrate as shown in 11B. As illustrated, the source line can be connected to the collector/drain C/D and the bit line can be connected to the emitter/source E/s. In an example embodiment, as illustrated in Figure β1β There is no weight f between the electrode and emitter/source/8 and/or collector/drain c/D. Other features described above with respect to Figure 11A may also be present in the vertical structure of Figure 11B. Figure 12A And FIG. 12B illustrates a cell structure according to an example embodiment.

12A至圖12B中所示’為改良增值及突崩產生，可在浮體 與集極/汲極之間形成緩衝區域24。在實例實施例中，緩 衝區域24未提供於浮體與發射極/源極之間。在實例實施 例中，緩衝區域24之雜質濃度可低於集極/沒極之雜質濃 度及/或'予體的雜質濃度。在實例實施例中，純質半導體 可用作緩衝區域24。在實例實施例中，緩衝區域24可為N· 、NM-中之一者。在實例實施财，、緩衝區域μ且有斑 最接近其的節點16相同之高度。在實例實施例中，緩衝區 ^覆蓋與其最接近之節點16之整個邊界。在實例實施例 中，緩衝區域24接觸絕緣層丨2 ^ ::例實施例中，緩衝區域24增加自基極至集極㈣ 办之平均自由路控或散逸。藉由增加散逸路徑，可改 良大崩產生之衝擊離子化。 ””單元中。 -果更夕電何可儲存於資料 在實例實施例中 汲極之雜質濃度。 ’則L2可大於li， ，發射極7源極之雜質濃度可大於集極/ 在實例實施例中，若緩衝區域24具有n_ 而若緩衝區域24具有p-，則L2可小於 I33200.doc 34- 200915319 L1。 面積之 緩衝區 如圖12B中所示’亦可在未增加緩衝區域之布局 情形下建構垂直單元結構，因為如圖12B中所示， 域24在垂直方向上延伸。As shown in Fig. 12A to Fig. 12B, for the purpose of improving the value added and the collapse, a buffer region 24 can be formed between the floating body and the collector/drain. In the example embodiment, the buffer region 24 is not provided between the floating body and the emitter/source. In the example embodiment, the impurity concentration of the buffer region 24 may be lower than the collector/nominal impurity concentration and/or the 'pre-existing impurity concentration. In an example embodiment, a pure semiconductor can be used as the buffer region 24. In an example embodiment, the buffer region 24 may be one of N·, NM-. In the example implementation, the buffer area μ is the same height as the node 16 with the spot closest to it. In the example embodiment, the buffer ^ covers the entire boundary of the node 16 closest to it. In an example embodiment, the buffer region 24 contacts the insulating layer ^ 2 ^ - in the embodiment, the buffer region 24 increases the average free path or dissipation from the base to the collector (4). By increasing the dissipation path, the impact ionization generated by the large collapse can be improved. "" in the unit. - What can be stored in the data? In the example embodiment, the impurity concentration of the bungee. 'L2 may be greater than li, the impurity concentration of the emitter 7 source may be greater than the collector / in the example embodiment, if the buffer region 24 has n_ and if the buffer region 24 has p-, then L2 may be less than I33200.doc 34 - 200915319 L1. The area of the buffer as shown in Fig. 12B can also construct the vertical cell structure without increasing the layout of the buffer area because the field 24 extends in the vertical direction as shown in Fig. 12B.

圖12B*明根據實例實施例之垂直記憶體單元結構。如 圖12B中所說明，垂直無電容器記憶體單元可包括基板 ίο、垂直堆疊於基板10上之第一節點14、浮體區域Η、緩 衝區域24及第二節點16。浮體區域以為電浮動式的。如圖 12B中所示，浮體區域18可具有浮體長度li。 閘極絕緣層20及閘極22可包圍浮體18。舉例而言，閘極 絕緣層20及閘極22可接觸浮體18之兩個或兩個以上側面之 全部或一部分。若垂直無電容器記憶體單元為nm〇s電晶 體，則第一節點14及第二節點16可具有第一傳導類型（例 如，N傳導類型）’且浮體區域18可具有第二傳導類型㈠列 如，P傳導類型）。又，垂直電容器結構可具有s〇i基板或 如圖12B中所示之習知塊體基板。 如所6兒明，為改良增值及突崩產生，可在浮體與集極/ 汲極之間形成緩衝區域24。在實例實施例中，緩衝區域24 未提供於浮體與發射極/源極之間。在實例實施例中，緩 衝區域24之雜質濃度可低於集極/汲極之雜質濃度及/或浮 體的雜質濃度。在實例實施例中，純質半導體可用作緩衝 區域24。在實例實施例中，緩衝區域24可為N-、N或P-中 之一者。在實例實施例中，緩衝區域24具有與最接近其的 節點1 6相同之高度。在實例實施例中，緩衝區域24覆蓋與 133200.doc -35- 200915319 其最接近之印點1 6之整個邊界。在實例實施例中，緩衝區 域24接觸絕緣層12。 如圖12A及12B中所示，浮體區域18、發射極/源極e/s、 集極/汲極C/D及/或緩衝區域24之間的邊界之輪廓可具有 任何形狀。 上文關於圖12A描述之其他特徵亦可存在於圖1 2B之垂 直結構中。 在實例實施例中，垂直結構可具有S0I基板或如圖12B 中所示之習知基板。 圖1 3 A至圖1 3B說明根據實例實施例之記憶體單元結 構。如所示，圖13A及圖13B說明圖11及圖12A至圖12B中 所示之特徵之組合。在圖丨3 A至圖丨3 B中所示之實例實施 例中，L1大於L2，即使緩衝區域以為^^。如上文所論述， 關於圖11八至圖118，圖13八至圖138中所說明之實例實施 例可減小GIDL及/或增加平均自由路徑。 如所說明，源極線可連接至集極/汲極C/D且位元線可連 接至發射極/源極E/S。在實例實施例中，如圖13A中所說 明，閘電極與發射極/集極E/c之間不存在重疊。如圖3中 所示，感測邊界可藉由資料"丨"單元與資料"〇"單元之間的Figure 12B* illustrates a vertical memory cell structure in accordance with an example embodiment. As illustrated in Figure 12B, the vertical capacitorless memory unit can include a substrate ίο, a first node 14 stacked vertically on the substrate 10, a floating body region Η, a buffer region 24, and a second node 16. The floating body area is considered to be electrically floating. As shown in Figure 12B, the float region 18 can have a float length li. The gate insulating layer 20 and the gate 22 may surround the floating body 18. For example, gate insulating layer 20 and gate 22 may contact all or a portion of two or more sides of floating body 18. If the vertical capacitorless memory cell is an nm〇s transistor, the first node 14 and the second node 16 may have a first conductivity type (eg, N conduction type) and the floating body region 18 may have a second conductivity type (1) Columns, P conductivity type). Also, the vertical capacitor structure may have a s〇i substrate or a conventional bulk substrate as shown in Fig. 12B. As shown in Fig. 6, in order to improve the value added and the collapse, a buffer region 24 can be formed between the floating body and the collector/drain. In an example embodiment, buffer region 24 is not provided between the floating body and the emitter/source. In an example embodiment, the impurity concentration of the buffer region 24 may be lower than the collector/drain impurity concentration and/or the impurity concentration of the floating body. In an example embodiment, a pure semiconductor can be used as the buffer region 24. In an example embodiment, buffer region 24 may be one of N-, N, or P-. In the exemplary embodiment, buffer region 24 has the same height as node 16 that is closest to it. In the exemplary embodiment, buffer region 24 covers the entire boundary of print point 16 which is closest to 133200.doc - 35- 200915319. In an example embodiment, buffer region 24 contacts insulating layer 12. As shown in Figures 12A and 12B, the contour of the boundary between the floating body region 18, the emitter/source e/s, the collector/drain C/D and/or the buffer region 24 can have any shape. Other features described above with respect to Figure 12A may also be present in the vertical configuration of Figure 12B. In an example embodiment, the vertical structure may have an SOI substrate or a conventional substrate as shown in FIG. 12B. 1A through 1B illustrate a memory cell structure in accordance with an example embodiment. As shown, Figures 13A and 13B illustrate combinations of features shown in Figures 11 and 12A through 12B. In the example embodiment shown in Figs. 3A to 3B, L1 is larger than L2 even if the buffer area is considered to be ^^. As discussed above, the example embodiments illustrated in Figures 11-8 through 118, Figures 13-8 through 138 may reduce GIDL and/or increase the mean free path. As illustrated, the source line can be connected to the collector/drain C/D and the bit line can be connected to the emitter/source E/S. In the exemplary embodiment, as illustrated in Fig. 13A, there is no overlap between the gate electrode and the emitter/collector E/c. As shown in Figure 3, the sensing boundary can be determined by the data "丨" unit and data"〇"

Vds之差來確定。為增加感測邊界，應減小閘極之相對汲 極電容C/D或源極電容c/s的電容C/G。 軋果，在閘極與源極或汲極之間不存在重疊。另外，可 減]、可降級資料"〇"之閘極誘發汲極漏電流（gi〇l)現象， 因為閘極與汲極上的電容Cgd變得更小。 133200.doc -36- 200915319 另外，可藉由使絕緣層2〇更 cg以保護閘極與 /補償閘極之降低之電容 、子體之間的耦合電 閘極長度L2小於浮體具_τι 电令。在實例實施例中， t歷長度L1。此等夂 感測邊界可視資 *數可改良可縮放性。 所儲存之電荷差而 十〇早兀之間的浮體中 ”〇”單元之電荷且因此資料"”早二具有遠多於資料 的浮體電位，所，作對於資料電 單元中發生得更快。此可由圖31-，# 在_貝料"〇" 於資料，，0”單元左側。 不"中資料”1"單元位 結果，若在寫入操作期間更 元之浮體中，則將達成更佳感測邊界。了。1於資料τ單 又之=與集極之間電子之散逸或平均自由路徑可長於 圖Α之電子之散逸或平均自由。 殽秘7 " 、’、0果’大朋產生之衝 擊離子化可更快發生。結果’ 更夕電何可儲存於資料，，1 ” 單元中。在實例實施例中’發射極/源極之雜質濃度可大 於集極/沒極之雜質濃度。 如圖13 A至圖13B中所示，氐从Α + — μ β甲所不，為改良突增及突崩產生，可 在浮體與集極/汲極之間形成緩衝區域2 4。在實例實施例 中，緩衝區域24未提供於浮體與發射極/源極之間。在實 例實施例中，緩衝區域24之雜質濃度可低於集極/汲極之 雜質濃度及/或浮體的雜質濃度。在實例實施例中，純質 半導體可用作緩衝區域24。在實例實施例中，緩衝區域24 可為Ν-、Ν或Ρ-中之一者。在實例實施例中，緩衝區域24 具有與最接近其的節點1 6相同之高度。在實例實施例中， 133200.doc -37- 200915319 緩衝區域24覆蓋與其最接近之節點丨6之整個邊界。在實例 實施例中，緩衝區域24接觸絕緣層12。 在實例實施例中，緩衝區域24增加自基極至集極/汲極 之電子之平均自由路徑或散逸。藉由增加散逸路徑，可改 良突朋產生之衝擊離子化。結果，更多f荷可儲存於資料 ΜΓ’單元中。 在實例實施例中，發射極/源極之雜質濃度可大於集極/ 汲極之雜質濃度。 如圖13Β中所示，亦可在未增加緩衝區域24之布局面積 之情形下建構垂直單元結構，因為如圖13Β中所示，緩衝 區域24在垂直方向上延伸。 如圖13 Α及1 3Β中所示，浮體區域i 8、發射極/源極、 集極/汲極C/D及/或緩衝區域24之間的邊界之輪廓可具有 任何形狀。 在實例實施例中，垂直結構可具有s〇I基板或如圖ΐ3β 中所示之習知基板。 圖14A至圖UB說明根據實例實施例之記憶體單元結 構。如圖14A至圖14B中所說明’提供輔助浮體區域麻 增加自發射極至浮體18之電子注入效率。在實例實施例 I，輔助浮體區域26之雜質濃度可小於浮體區域18之雜質 /辰度。在實例實施例中’浮體區域i 8長於輔助浮體區域 26。在實例實施例中，辅助浮體區域％接觸發射極/源極 E/S。 在實例實施例中，輔助浮體區域26幫助更多電子注入浮 133200.doc •38- 200915319 體區域1 8且到達基極/集極區域且因此可發生更有效率 操作。在實例實施例中，發射極之雜質濃度高於集極之雜 質濃度及/或基極的雜質濃度。 ” 如圖14B中所示，亦可在未增加輔助浮體區域％之布局 面積之情形下建構垂直單元結構，因為如圖丨4B中所示: 輔助浮體區域26在垂直方向上延伸。 如圖14A及14B中所示，浮體區域18、發射極/源極E/s、 集極/汲極C/D及/或輔助浮體區域26之間的邊界之輪廓可 具有任何形狀。 在實例實施例中，垂直結構可具有s〇I基板或如圖14b 中所示之習知基板。 圖1 5 A至圖1 5C說明圖11至圖14b之特徵之其他實例組 合。圖15A說明圖ιιΑ及圖14A中所示之特徵之組合。詳言 之，圖15A說明閘極22及浮體區域18，其中L1>L2且提供 輔助洋體區域26以增加自發射極/源極E/s之電子注入效 率 〇 如所說明，源極線可連接至集極/汲極C/D且位元線可連 接至發射極/源極E/S。在實例實施例中，如圖11A中所說 月在閘極22與發射極/源極E/S及/或集極/汲極c/D之間不 存在重疊。如圖3中所示，感測邊界可藉由資料"丨"單元與 資料"〇”單元之間的Vds之差來確定。為増加感測邊界，應 減小閘極之相對集極/汲極C/D之電容（例如，汲極cD)或發 射極/源極E/S之電容（例如，源極Cs)的電容Cg。 結果，在閘極22與發射極/源極；e/s及/或集極/汲極匸/!)之 133200.doc -39- 200915319 間不存在重疊。另外，可減次 J 1争級貝枓〇"之閘極誘發 汲極漏電流（GIDL)現象，因為閘極2 ]杈22與汲極上的電容Cgd 變付更小。 另外’可藉由使絕緣層2 〇更薄爽福检 尺存术補彳員閘極之降低之電容 cg以保護閘極22與浮體區域1 8之間的 心间的耦合電容。在實例實 施例中’閘極長度L2小於浮體县声τ 1 » 菔长度L1。此等參數可改良可 縮放性。 感測邊界可視資料"Γ，單元與資料”〇"單元之間的浮體中 所儲存之電荷差而定。因為資料"i"單元具有遠多於資料 單元之電荷且因此資料”丨”之浮# '于菔電位南於資料”0”單元 的浮體電位’所以BJT操作對於資料，' 〇〇 貝针1早兀比在資料”〇” 單元中發生得更快。此可由圖3展干 圃展不，其中資料"1"單元位 於資料”〇，’單元左側。 結果’若在寫入操作期間更多電荷 电<了 J儲存於資料"1 "單 凡之浮體區域1 8中，則將達成更佳感測邊界。 又，基極Β與集極/没極C/D之間電子之散逸或平均自由 路徑可長於圖以之電子之散逸或平均自由路徑“士果* 崩產生之衝擊離子化可更快發生。結果，更多電荷2 於資料”1"單元中。在實例實施例中，發射極/源極E/S之雜 質濃度可大於集極/汲極C/D之雜質濃度。 在實例實施例中，辅助浮體區域26之 雜貝濃度可小於浮 體區域18之雜質濃度。在實例實施例中，浮體區域a、、 輔助浮體區域26。在實例實施例中’辅助浮體：域2:: 發射極/源極E/S。 ％ 133200.doc -40- 200915319 在實例實施例中’辅助浮體區域26幫助更多電子注入浮 體區域18且到達基極B/集極/汲極C/D區域且因此可發生更 有效率BJT操作。在實例實施例中，發射極/源極e/s之雜 質濃度高於集極/汲極C/D之雜質濃度及/或基極B的雜質濃 度。 亦可在未增加辅助浮體區域26之布局面積之情形下建構 垂直單元結構，因為如圖丨4B中所示，輔助浮體區域26在 垂直方向上延伸。 在實例實施例中，垂直結構亦可具有圖15A之特徵。在 實例實施例中，垂直結構可具有s〇I基板，如圖15八中所 示，或習知基板。 圖15B說明圖12A及圖14A中所示之特徵之組合。如圖 15B中所示，為改良增值及突崩產生，可在浮體區域邮 集極/汲極C/D之間形成緩衝區域24。在實例實施例中，緩 衝區域24未提供於浮體區域18與發射極/源極E/S之間。在 實例實施針 '緩衝區域24之雜質濃度可低於集極/汲極 C/D之雜質濃度及/或浮體區域18的雜質濃度。在實例實施 例中，純質半導體可用作緩衝區域24。在實例實施例中， 緩衝區域24可為N_' up•中之―者。在實例實施例中， 緩衝區域24具有與最接近其的節點16相同之高度。在實例 實施例中，緩衝區域24覆蓋與其最接近之節點16之整個邊 界。在實例實施例中，緩衝區域24接觸絕緣層12。 在實例實施例中’緩衝區域24增加自基極B至集極遣極 C/D之電子之平均自由路徑或散逸。#由増加散逸路徑， 133200.doc -41 - 200915319 可改良穴崩產生之衝擊離子化。結果，更多電荷可儲存於 資料”1”單元中。 在實例實施例中，發射極/源極E/s之雜質濃度可大於集 極/汲極C/D之雜質濃度。在實例實施例中，若緩衝區域24 具有N-，則L2可大於L1，而若緩衝區域24具有p_，則匕2可 小於L1。 如圖1 5B中所說明，提供輔助浮體區域26以增加自發射 極/源極E/S之電子注入效率。在實例實施例中，輔助浮體 區域26之雜質濃度可小於浮體區域丨8之雜質濃度。在實例 實施例中，浮體區域1 8長於辅助浮體區域26。在實例實施 例中’輔助浮體區域26接觸發射極/源極e/s。 在實例實施例中，輔助浮體區域26幫助更多電子注入浮 體區域18且到達基極B/集極/汲極C/D區域且因此可發生更 有效率BJT操作。在實例實施例中，發射極/源極E/s之雜 質濃度高於集極/汲極C/D之雜質濃度及/或基極b的雜質濃 度。 亦可在未增加緩衝區域24及輔助浮體區域26之布局面積 之情形下建構垂直單元結構，因為如圖13B及圖14B中所 示’緩衝區域24及輔助浮體區域26在垂直方向上延伸。 在實例實施例中，垂直結構亦可具有圖15B之特徵。在 實例實施例中’垂直結構可具有SOI基板，如圖15B中所 示，或習知基板。 圖15C說明圖11A、圖12A及圖14A中所示之特徵之組 合。如圖1 5 C中所示，源極線可連接至集極/沒極c/D且位 133200.doc -42- 200915319 元線可連接至發射極/源極Ε/S。在實例實施例中，如圖 ΠΑ中所說明，在閘極22與發射極/源極E/S及/或集極/汲極 C/D之間不存在重疊。如圖3中所示，感測邊界可藉由資料 "1”單元與資料”0”單元之間的Vds之差來確定。為增加感測 邊界，應減小閘極之相對汲極電容心或源極電容&的電容 CG。 結果，在閘極22與發射極/源極E/S及/或集極/汲極C/D之 間不存在重疊。另彳，可減]、可降級f㈣，，之閘極誘發 汲極漏電流（CHDL)現象，因為閘極與汲極上的電容cy變 得更小。 力外，可肖由使絕緣層20更料補冑問極之降低之電容The difference between Vds is determined. To increase the sensing boundary, reduce the relative cathode capacitance C/D of the gate or the capacitance C/G of the source capacitance c/s. Rolling fruit, there is no overlap between the gate and the source or drain. In addition, it is possible to reduce the leakage current (gi〇l) induced by the gate of the data "〇" because the capacitance Cgd on the gate and the drain becomes smaller. 133200.doc -36- 200915319 In addition, by making the insulating layer 2 ccg to protect the gate and/compensate the reduced capacitance of the gate, the coupling electric gate length L2 between the sub-body is smaller than the floating body _τι make. In an example embodiment, t is a length L1. These 感 sensing boundary visualizations improve scalability. The stored charge difference is different from the charge of the "〇" cell in the floating body between the tenth and the early, and therefore the data has a much more floating body potential than the data, so that it occurs in the data unit. Faster. This can be done by Figure 31-, #在_贝料"〇" in the data, on the left side of the 0" unit. If the data is not in the floating position of the unit during the write operation, a better sensing boundary will be achieved. 1 In the data τ single = the electron between the collector and the collector The escaping or mean free path can be longer than the escaping or average freedom of the electrons in the figure. Confucius 7 ", ', 0 fruit' The impact ionization produced by the big friends can occur faster. Information, in the 1" unit. In the example embodiment, the emitter/source impurity concentration may be greater than the collector/nominal impurity concentration. As shown in Fig. 13A to Fig. 13B, 氐 from Α + - μ β 甲, for improved spurt and sag formation, a buffer region 24 can be formed between the floating body and the collector/drain. In the example embodiment, buffer region 24 is not provided between the floating body and the emitter/source. In an embodiment, the impurity concentration of the buffer region 24 may be lower than the collector/drain impurity concentration and/or the impurity concentration of the floating body. In an example embodiment, a pure semiconductor can be used as the buffer region 24. In an example embodiment, the buffer region 24 may be one of Ν-, Ν or Ρ-. In the example embodiment, buffer region 24 has the same height as node 16 that is closest to it. In an example embodiment, 133200.doc -37- 200915319 buffer area 24 covers the entire boundary of node 丨6 closest thereto. In an example embodiment, the buffer region 24 contacts the insulating layer 12. In an example embodiment, buffer region 24 increases the average free path or dissipation of electrons from the base to the collector/drain. By increasing the dissipation path, the impact ionization generated by the sudden friends can be improved. As a result, more f charges can be stored in the data ΜΓ' unit. In an example embodiment, the emitter/source impurity concentration may be greater than the collector/drain impurity concentration. As shown in Fig. 13A, the vertical cell structure can also be constructed without increasing the layout area of the buffer region 24, since the buffer region 24 extends in the vertical direction as shown in Fig. 13A. As shown in Figs. 13 and 13, the outline of the boundary between the floating body region i8, the emitter/source, the collector/drain C/D, and/or the buffer region 24 may have any shape. In an example embodiment, the vertical structure may have a s〇I substrate or a conventional substrate as shown in FIG. 3β. 14A through UB illustrate a memory cell structure in accordance with an example embodiment. Providing the auxiliary floating body region as shown in Figs. 14A to 14B increases the electron injection efficiency from the emitter to the floating body 18. In Example Embodiment 1, the impurity concentration of the auxiliary floating body region 26 may be smaller than the impurity/length of the floating body region 18. In the exemplary embodiment, the 'floating body area i 8 is longer than the auxiliary floating body area 26. In an example embodiment, the auxiliary floating body region % contacts the emitter/source E/S. In an example embodiment, the auxiliary floating body region 26 helps more electrons to be injected into the body region 18 and reaches the base/collector region and thus more efficient operation can occur. In an example embodiment, the impurity concentration of the emitter is higher than the impurity concentration of the collector and/or the impurity concentration of the base. As shown in Fig. 14B, the vertical cell structure can also be constructed without increasing the layout area of the auxiliary floating body region %, because as shown in Fig. 4B: the auxiliary floating body region 26 extends in the vertical direction. 14A and 14B, the contour of the boundary between the floating body region 18, the emitter/source E/s, the collector/drain C/D, and/or the auxiliary floating body region 26 may have any shape. In an example embodiment, the vertical structure may have a s〇I substrate or a conventional substrate as shown in Fig. 14b. Fig. 15A to Fig. 1C illustrate other example combinations of the features of Figs. 11 to 14b. Fig. 15A illustrates ιιΑ and the combination of features shown in Figure 14A. In detail, Figure 15A illustrates gate 22 and floating body region 18, where L1 > L2 and provides an auxiliary oceanic region 26 to increase self-emitter/source E/s Electron Injection Efficiency As explained, the source line can be connected to the collector/drain C/D and the bit line can be connected to the emitter/source E/S. In an example embodiment, as in Figure 11A There is no overlap between gate 22 and emitter/source E/S and/or collector/drain c/D. As shown in Figure 3, the sensing boundary can be Square "Vds of the difference between the determined unit; the data " Shu " data unit & quot. To add a sense boundary, reduce the capacitance of the gate's relative collector/drain C/D (eg, drain cD) or emitter/source E/S (eg, source Cs) capacitance. Cg. As a result, there is no overlap between the gate 22 and the emitter/source; e/s and/or collector/drain 匸/!) 133200.doc -39- 200915319. In addition, the gate leakage induced current leakage (GIDL) phenomenon can be reduced by the J 1 grade, because the gate 2 ] 杈 22 and the capacitance Cgd on the drain are smaller. In addition, the coupling capacitance between the gate 22 and the floating body region 18 can be protected by making the insulating layer 2 thinner and reducing the capacitance cg of the gate of the employee. In the example embodiment, the gate length L2 is smaller than the floating body county τ 1 » 菔 length L1. These parameters improve scalability. Sensing boundary visual data "Γ, unit and data" 〇" the difference in charge stored in the floating body between the units. Because the data "i" unit has far more charge than the data unit and therefore the data"丨"之浮# 'Yu potential is south of the floating body potential of the data "0" unit' so BJT operation for the data, 'mussel needle 1 early 发生 occurs faster in the data 〇" unit. Figure 3 shows the exhibition, and the data "1" unit is located on the left side of the unit. As a result, if more charge is stored during the write operation, J is stored in the data "1 " single floating body area 18, a better sensing boundary will be achieved. Moreover, the electron escaping or mean free path between the base Β and the collector/nothing C/D can be longer than the escaping or mean free path of the electrons in the figure. As a result, more charge 2 is in the data "1" unit. In an example embodiment, the impurity concentration of the emitter/source E/S may be greater than the impurity concentration of the collector/drain C/D. In an example embodiment, the miscellaneous concentration of the auxiliary floating body region 26 may be less than the impurity concentration of the floating body region 18. In an example embodiment, the floating body region a, the auxiliary floating body region 26. In the example embodiment 'auxiliary float: domain 2:: emitter/source E/S. % 133200.doc -40- 200915319 In the example embodiment the 'auxiliary floating body region 26 helps more electrons to be injected into the floating body region 18 and reaches the base B/collector/drain C/D region and thus can occur more efficiently BJT operation. In the exemplary embodiment, the impurity concentration of the emitter/source e/s is higher than the impurity concentration of the collector/drain C/D and/or the impurity concentration of the base B. It is also possible to construct the vertical cell structure without increasing the layout area of the auxiliary floating body region 26, since the auxiliary floating body region 26 extends in the vertical direction as shown in Fig. 4B. In an example embodiment, the vertical structure may also have the features of Figure 15A. In an example embodiment, the vertical structure may have a s〇I substrate, as shown in Figure 15 or a conventional substrate. Figure 15B illustrates a combination of features shown in Figures 12A and 14A. As shown in Fig. 15B, in order to improve the value added and the collapse generation, a buffer region 24 may be formed between the collector/drain C/D of the floating body region. In the example embodiment, the buffer region 24 is not provided between the floating body region 18 and the emitter/source E/S. In the example implementation, the impurity concentration of the buffer region 24 may be lower than the impurity concentration of the collector/drain C/D and/or the impurity concentration of the floating body region 18. In an example embodiment, a pure semiconductor can be used as the buffer region 24. In an example embodiment, buffer area 24 may be N_'up•. In an example embodiment, buffer region 24 has the same height as node 16 that is closest to it. In the exemplary embodiment, buffer region 24 covers the entire boundary of node 16 closest thereto. In an example embodiment, the buffer region 24 contacts the insulating layer 12. In the example embodiment, the buffer region 24 increases the average free path or dissipation of electrons from the base B to the collector C/D. #由増散散逸, 133200.doc -41 - 200915319 can improve the impact ionization caused by avalanche. As a result, more charge can be stored in the "1" unit of the data. In an example embodiment, the impurity concentration of the emitter/source E/s may be greater than the impurity concentration of the collector/drain C/D. In an example embodiment, if buffer region 24 has N-, then L2 may be greater than L1, and if buffer region 24 has p_, then 匕2 may be less than L1. As illustrated in Figure 15B, an auxiliary floating body region 26 is provided to increase the electron injection efficiency from the emitter/source E/S. In an example embodiment, the impurity concentration of the auxiliary floating body region 26 may be smaller than the impurity concentration of the floating body region 丨8. In the exemplary embodiment, the floating body region 18 is longer than the auxiliary floating body region 26. In the example embodiment, the auxiliary floating body region 26 contacts the emitter/source e/s. In an example embodiment, the auxiliary floating body region 26 helps more electrons to be injected into the floating body region 18 and reach the base B/collector/drain C/D region and thus more efficient BJT operation can occur. In an exemplary embodiment, the impurity concentration of the emitter/source E/s is higher than the impurity concentration of the collector/drain C/D and/or the impurity concentration of the base b. The vertical cell structure can also be constructed without increasing the layout area of the buffer region 24 and the auxiliary floating body region 26 because the buffer region 24 and the auxiliary floating body region 26 extend in the vertical direction as shown in FIGS. 13B and 14B. . In an example embodiment, the vertical structure may also have the features of Figure 15B. In an example embodiment, the 'vertical structure' may have an SOI substrate, as shown in Figure 15B, or a conventional substrate. Figure 15C illustrates a combination of features shown in Figures 11A, 12A and 14A. As shown in Figure 5 5 C, the source line can be connected to the collector/depolar c/D and the bit 133200.doc -42- 200915319 can be connected to the emitter/source Ε/S. In the exemplary embodiment, as illustrated in Figure 不, there is no overlap between gate 22 and emitter/source E/S and/or collector/drain C/D. As shown in Figure 3, the sensing boundary can be determined by the difference between the Vds between the data "1" unit and the data "0" unit. To increase the sensing boundary, the relative gate capacitance of the gate should be reduced. The capacitance of the core or source capacitance & CG. As a result, there is no overlap between the gate 22 and the emitter/source E/S and/or the collector/drain C/D. Alternatively, it can be subtracted] The step (f) can be degraded, and the gate induces a drain leakage current (CHDL) phenomenon, because the capacitance cy on the gate and the drain becomes smaller. In addition, the insulation layer 20 can be made more difficult to compensate. Capacitance

Cg以保護閘極22與浮體區域18之間的輕合電容。在實例實 施例中’問極長度L2小於浮體長度u。此等參改可 縮放性。 感測邊界可視資料”1"單元與資料，，0”單元之間的浮體中 所儲存之電荷差而定。因為資 , 勹貝枓1早兀具有遠多於資料 …電何且因此資料"i"之浮 的浮體電位，所以阶操作對於 、=早凡 單元中發生得更快。此可由圖3展:/二=她 於資料”0"單元左側。 〃、=貝料丨"單元位 結果，若在寫入操作期間更多 元之浮體中，則將達成更佳感測邊界。+於貢料”1”單 又’基極與集極之間電子之散逸或 圖1Α之電子之散逸或平均自由路徑_果=可長於 、、·°果，突崩產生之衝 133200.doc •43- 200915319 擊離子化可更快發生。結果，更多電荷可儲存於資料"厂, 單元十。在實例實施例中，發射極/源極Ε/S之雜質濃度可 大於集極/汲極C/D之雜質濃度。 如圖15C中所示，為改良增值及突崩產生，可在浮體區 域1 8與集極/汲極C/D之間形成緩衝區域24。在實例實施例 中，緩衝區域24未提供於浮體區域18與發射極/源極E/s之 間。在實例實施例中，緩衝區域24之雜質濃度可低於集極/ 汲極C/D之雜質濃度及/或浮體區域28的雜質濃度。在實例 實施例中，純質半導體可用作緩衝區域24。在實例實施例 中，緩衝區域24可為N_、N*p•中之一者。在實例實施例 中，緩衝區域24具有與最接近其的節點16相同之高度。在 實例實施例中，緩衝區域24覆蓋與其最接近之節點“之整 個邊界。在實例實施财，、緩衝區域Μ接觸絕緣層& 在實例實施例中，緩衝區域24增加自基極B至集極/汲極 C/D之電子之平均自由路徑或散逸。藉由增加散逸路徑， 可改良突崩產生之衝擊離子化。結果’更多電荷可儲存於 資料” 1"單元中。 在實例實施例中，發射極/源極E/s之雜質濃度可大於集 極/汲極C/D之雜質濃度。 如圖1 5C中所說明，提供輔助浮體區域26以增加自發射 極/源極E/S之電子注入效率。在實例實施例中，輔助浮體 區域26之雜質濃度可小於浮體區域18之雜質濃度。在實例 實施例中，浮體區域1 8長於輔助浮體區域26。在實例實施 例中，輔助浮體區域26接觸發射極/源極E/s。 133200.doc -44 - 200915319 在實例實施例中，輔助浮體區域26幫助更多電子注入浮 體區域18且到達基極/集極/汲極C/D區域且因此可發生更 有效率BJT操作。在實例實施例中，發射極/源極E/s之雜 質濃度高於集極/汲極C/D之雜質濃度及/或基極B的雜質濃 度。 亦可在未增加緩衝區域24及輔助浮體區域26之布局面積 之情形下建構垂直單元結構，因為如圖13B及圖14B中所 示，緩衝£域24及辅助浮體區域26在垂直方向上延伸。 如圖11A及圖14B中所示，任何區域之間的邊界之輪廓 可具有任何形狀。 在實例實施例中，垂直結構亦可具有圖15C之特徵。在 實例實施例中，垂直結構可具有s〇I基板，如圖丨5C中所 不’或習知基板。 圖16A說明根據實例實施例之記憶體單元結構之平面 圖。如圖16 A中所示，記憶體單元結構可包括第一節點 14(例如，發射極/源極E/S)、第二節點16(例如，集極/汲極 C/D)、浮體區域1 8、字線21、延伸浮體區域27、第一接點 30、第二接點32、源極線34及/或位元線36。在實例實施 例中’延伸浮體區域27可位於字線21下且自浮體區域丨8之 一側延伸以充當額外電荷儲存區域。在實例實施例中，延 伸浮體區域27可改良無電容器記憶體之電荷保存能力。 圖1 6B說明圖1 6A之方向Ι-Γ之橫截面圖且如圖1 6B中所 不’ a己憶體早元結構可包括基板1 〇、絕緣層1 2、第一節點 14(例如’發射極/源極E/S)、第二節點16(例如’集極/汲極 133200.doc -45· 200915319 C/D)及浮體區域1 8。記憶體單元可進一步包括鄰近第一節 點14及第二節點16之隔離層44。記憶體單元可進一步包括 第一接點30及源極線34、第二接點48及位元線36、包括閘 極絕緣層20及閘極層22之閘極21，及絕緣層42及46。如圖 16B中所示’ L1>L2。延伸浮體區域27在圖16B中不可見。 圖16C說明沿圖16A中所示之方向ll-π，之橫截面圖。圖 16C說明基板1 〇、絕緣層12、浮體區域1 8 '延伸浮體區域 27、隔離層44、閘極21、絕緣層42及46及位元線36。延伸 浮體區域27在圖16C中展示為浮體區域18之延伸。 請注意，圖16A至圖16C之延伸浮體區域27可與上文在 圖11至圖15C中所闡明之任何或所有特徵組合利用。 另外，電洞儲集器140可形成於浮體區域18下方，如圖 17中所示。電洞儲集器14〇可埋置於絕緣層12中。電洞儲 集器140可包括可具有高於Si價帶之價帶的半導體材料或 金屬材料。舉例而言，電洞儲集器14〇可包括Ge、Si_Ge、Cg protects the light coupling capacitance between the gate 22 and the floating body region 18. In the example embodiment, the length of the pole is L2 smaller than the length u of the float. These changes can be scaled. The sensing boundary is visually related to the difference in charge stored in the floating body between the unit and the data, 0" unit. Because of the capital, the mussels have a far more floating body potential than the data ... and therefore the data "i" float, so the order operation occurs faster in the unit. This can be shown in Figure 3: / two = she is on the left side of the data "0" unit. 〃, = 贝 丨 quot quot; unit position results, if more floating in the floating body during the write operation, it will achieve a better feeling Measure the boundary. + In the tribute "1" single and 'the dissipation of electrons between the base and the collector or the dissipation or average free path of the electrons in Fig. 1 _ fruit = can be longer than,, · °, the rush of the collapse 133200.doc •43- 200915319 Ionization can occur faster. As a result, more charge can be stored in the data "factor, unit 10. In the example embodiment, the emitter/source Ε/S impurity concentration can be greater than The impurity concentration of the collector/drain C/D. As shown in Fig. 15C, a buffer region 24 may be formed between the floating body region 18 and the collector/drain C/D for improved value addition and collapse generation. In an example embodiment, the buffer region 24 is not provided between the floating body region 18 and the emitter/source E/s. In an example embodiment, the buffer region 24 may have a lower impurity concentration than the collector/drain C/ The impurity concentration of D and/or the impurity concentration of the floating body region 28. In an example embodiment, a pure semiconductor can be used as the buffer region 24. In an embodiment, buffer region 24 can be one of N_, N*p•. In an example embodiment, buffer region 24 has the same height as node 16 that is closest thereto. In an example embodiment, buffer region 24 Cover the entire boundary of the node closest to it. In an example implementation, buffer region Μ contact insulating layer & In an example embodiment, buffer region 24 increases the average free path or dissipation of electrons from base B to collector/drain C/D. By increasing the dissipation path, the impact ionization generated by the collapse can be improved. As a result, 'more charge can be stored in the data"1" unit. In the example embodiment, the impurity concentration of the emitter/source E/s can be greater than the impurity concentration of the collector/drain C/D. As explained, the auxiliary floating body region 26 is provided to increase the electron injection efficiency from the emitter/source E/S. In an example embodiment, the auxiliary floating body region 26 may have an impurity concentration that is less than the impurity concentration of the floating body region 18. In an example embodiment, the floating body region 18 is longer than the auxiliary floating body region 26. In the example embodiment, the auxiliary floating body region 26 contacts the emitter/source E/s. 133200.doc -44 - 200915319 In an example embodiment The auxiliary floating body region 26 helps more electrons to be injected into the floating body region 18 and reaches the base/collector/drain C/D region and thus more efficient BJT operation can occur. In an example embodiment, the emitter/source The impurity concentration of the pole E/s is higher than the impurity concentration of the collector/drain C/D and/or the impurity concentration of the base B. The layout area of the buffer region 24 and the auxiliary floating body region 26 may not be increased. The vertical cell structure is constructed because, as shown in FIGS. 13B and 14B, the buffer domain 24 is constructed. The auxiliary float region 26 extends in the vertical direction. As shown in Figures 11A and 14B, the contour of the boundary between any of the regions may have any shape. In an example embodiment, the vertical structure may also have the features of Figure 15C. In an example embodiment, the vertical structure may have a substrate, as shown in FIG. 5C or a conventional substrate. Figure 16A illustrates a plan view of a memory cell structure in accordance with an example embodiment, as shown in Figure 16A. The memory cell structure may include a first node 14 (eg, emitter/source E/S), a second node 16 (eg, collector/drain C/D), a floating body region 18, and a word line 21 Extending the floating body region 27, the first contact 30, the second contact 32, the source line 34, and/or the bit line 36. In the example embodiment, the 'extending floating body region 27 may be located under the word line 21 and One side of the floating body region 8 extends to serve as an additional charge storage region. In an example embodiment, the extended floating body region 27 can improve the charge retention capability of the capacitorless memory. Figure 1 6B illustrates the direction of Figure 6A. A cross-sectional view and as shown in FIG. 16B, the structure may include a substrate 1 〇, insulating layer 1 2. First node 14 (eg 'emitter/source E/S), second node 16 (eg 'collector/bungee 133200.doc -45· 200915319 C/D) and floating The body region 18. The memory unit may further include an isolation layer 44 adjacent to the first node 14 and the second node 16. The memory unit may further include a first contact 30 and a source line 34, a second contact 48, and a bit. The line 36 includes a gate insulating layer 20 and a gate 21 of the gate layer 22, and insulating layers 42 and 46. As shown in Fig. 16B, 'L1> L2. The extended float region 27 is not visible in Figure 16B. Figure 16C illustrates a cross-sectional view taken along the direction ll-π shown in Figure 16A. Figure 16C illustrates substrate 1, germanium, insulating layer 12, floating body region 18' extending floating body region 27, isolation layer 44, gate 21, insulating layers 42 and 46, and bit line 36. The extended float region 27 is shown in Figure 16C as an extension of the floating body region 18. Note that the extended floating body region 27 of Figures 16A-16C can be utilized in combination with any or all of the features set forth above in Figures 11-15C. Additionally, a hole reservoir 140 can be formed below the floating body region 18, as shown in FIG. The hole reservoir 14A can be buried in the insulating layer 12. The hole reservoir 140 can include a semiconductor material or a metal material that can have a valence band above the Si valence band. For example, the hole reservoir 14A may include Ge, Si_Ge,

Al-Sb及Ga-Sb中之任一者。因為電洞儲集器14〇之價帶高 於Si之價帶，所以電洞可更易於累積於電洞儲集器140 中電/同儲集器140可與發射極/源極E/S及集極/汲極c/D隔 離，且因此可藉由減少接面漏電流來改良資料保存性質。 因此，根據實例實施例之無電容器記憶體可具有改良資料 保存性質。關於電洞儲集器之額外細節可在申請於2〇〇7年 12月 27 日之題為”CAPACIT〇R_LESS dram and meth〇ds OF MANUFACTURING THE SAME"的美國第 ^/005,399號 中找到，該案之全文以引用之方式併入本文中。 I33200.doc -46- 200915319 又，基於塊體矽基板之習知〇河(^技術已展示小於約4〇 nm之閘極通道長度的嚴重短通道效應。歸因於習知m〇s 裝置之侷限性，已在FinFET裝置之領域進行積極研究。 圖18展示根據實例實施例之記憶體單元結構。圖18中所 示之FinFET記憶體單元製造於基板1〇上之絕緣層12上。 FinFET記憶體單元包括絕緣層12上之具有第一節點14、第 二節點16及/或浮體區域18之矽圖案。ΠηρΈτ記憶體單元 進一步包括閘極絕緣層20及閘極22。閘極22圍繞浮體18。 舉例而言，閘極絕緣層20及閘極22可接觸浮體18之兩個或 兩個以上側面之全部或一部分。如圖18中所示，開極2〇及 閘極22接觸浮體丨8之三個側面之部分。 在實例實施例中，如圖18中所說明，閘極22與第一節點 14或第二節點16之間不存在重疊。亦即，閘極長度小於浮 體長度，例如，如圖11A中所示。，然而，在替代性實施例 中，閘極22可重疊第一節點14及第二節點16中之一者或兩 者。 以相同方式，上文在實例實施例中闡明之緩衝區域以及/ 或輔助浮體區域26可結合圖18之FinFET裝置使用。 圖19展示根據實例實施例之記憶體單元結構。圖19中所 示之記憶體單元結構具有與圖18之記憶體單元結構相同的 、’、。構除了其可包括在浮體區域1 8上且位於閘極結構2〇及 22下的延伸浮體區域27外。閘極結構20及22圍繞浮體區域 及延伸浮體區域27。充當額外電荷儲存區域27之延伸浮體 區域27可改良記憶體裝置之電荷保存能力。在實例實施例 133200.doc •47- 200915319 中，如圖1 8中所示，記憶體裝置亦可包括位於第一節點14 及第二節點1 6中之一者之間的緩衝區咸24及/或辅助浮體 區域2 6。 儘管上文已描述實例實施例，但是可以多種方式增補或 修改此等實施例。上文結合圖11A至圖丨9論述之變化及/或 替代性實施例中之任一者亦可應用於圖1A至圖1〇中所說明 的實例實施例。更-般而言，本說明書揭示具有若干不同Any of Al-Sb and Ga-Sb. Since the valence band of the hole reservoir 14 is higher than the valence band of Si, the hole can be more easily accumulated in the hole reservoir 140. The electricity/same reservoir 140 can be combined with the emitter/source E/S. And collector/drain c/D isolation, and thus can improve data retention properties by reducing junction leakage current. Therefore, the capacitorless memory according to example embodiments may have improved data retention properties. Additional details regarding the hole reservoir can be found in U.S. No. ^/005,399, filed on December 27, 2008, entitled "CAPACIT〇R_LESS dram and meth〇ds OF MANUFACTURING THE SAME" The full text of the case is incorporated herein by reference. I33200.doc -46- 200915319 Also, based on the knowledge of the bulk 矽 substrate, the technology has shown a severe short channel of gate length less than about 4 〇 nm. Effect. Due to the limitations of conventional m〇s devices, active research has been conducted in the field of FinFET devices. Figure 18 shows a memory cell structure according to an example embodiment. The FinFET memory cell shown in Figure 18 is fabricated in The FinFET memory cell includes a meander pattern on the insulating layer 12 having a first node 14, a second node 16, and/or a floating body region 18. The ΠηρΈτ memory cell further includes a gate insulating Layer 20 and gate 22. Gate 22 surrounds floating body 18. For example, gate insulating layer 20 and gate 22 may contact all or a portion of two or more sides of floating body 18. As shown, open pole 2 闸 and gate 22 Touching portions of the three sides of the floating body 丨 8. In the example embodiment, as illustrated in Figure 18, there is no overlap between the gate 22 and the first node 14 or the second node 16. That is, the gate length Less than the float length, for example, as shown in FIG. 11A. However, in an alternative embodiment, the gate 22 may overlap one or both of the first node 14 and the second node 16. In the same manner, The buffer regions and/or auxiliary floating region 26 set forth above in the example embodiments can be used in conjunction with the FinFET device of Figure 18. Figure 19 shows a memory cell structure in accordance with an example embodiment. The structure has the same structure as the memory cell structure of Fig. 18, except that it may be included on the floating body region 18 and outside the extended floating body region 27 under the gate structures 2A and 22. The gate structure 20 And 22 surrounding the floating body region and extending the floating body region 27. The extended floating body region 27 acting as the additional charge storage region 27 can improve the charge retention capability of the memory device. In the example embodiment 13320.doc • 47-200915319, Memory device shown in Figure 18. A buffer salt 24 and/or an auxiliary floating body region 26 may be included between one of the first node 14 and the second node 16. Although the example embodiments have been described above, they may be supplemented or modified in a variety of ways. These embodiments. Any of the variations and/or alternative embodiments discussed above in connection with Figures 11A through 9 can also be applied to the example embodiments illustrated in Figures 1A through 1A. In this regard, this specification reveals several differences

特徵之若干實例實施例。可以任何組合使用此等特徵中之 每一者。 圖20說明根據實例實施例之記憶體系統。如圖2〇中所 示，記憶體系統可包括記憶體控制器18〇〇及無電容器記憶 體裝置1802。在實例實施例中’無電容器記憶體裝置⑽2 可為上文在圖4、圖7及圖10中所論述之記憶體中之任一 者。又，記憶體控制器刪可包括於執行其他特定功能之 積體電路中，例如，CPU或圖形控制器。 如圖2〇中所示’記憶體控制器義將指令CMD及位址 ADDR提供至記憶體裝置刪且記憶體控制器刪及記憶 體裝置18 02雙向交換資料（DATA)。 記憶體控制器1 800可包括暫在哭〇 ”。 括暫存益211且記憶體裝置1 802 可匕括暫存器22卜暫存器211、221中之每_者可儲# 裝置1802以區塊再新模式還是部分再新模式操: 之貝訊。又，若確定記憶體18〇2裝 :Γ:211、221中之每一者可儲存部分再:模=時 啟動之源極線或位元線的數目。 133200.doc -48· 200915319 如圖2 1中所示，在眘眘 實例實施例中，無電容器記憶體裝置 1802可為包括複數個 热电谷益δ己憶體裝置1 802(例如，X記 憶體裝置1 802χ，# ，、中x為大於專於丨之整數）之記憶體模組 1804以增加記憶體容量。 在實例實施例中，記憶體模組1804可含有暫存器231(例Several example embodiments of features. Each of these features can be used in any combination. Figure 20 illustrates a memory system in accordance with an example embodiment. As shown in Figure 2A, the memory system can include a memory controller 18A and a capacitorless memory device 1802. In the example embodiment, the 'capacitorless memory device (10) 2 may be any of the memories discussed above in Figures 4, 7 and 10. Also, the memory controller deletion may be included in an integrated circuit that performs other specific functions, such as a CPU or a graphics controller. As shown in Fig. 2A, the memory controller provides the instruction CMD and the address ADDR to the memory device to delete and the memory controller to delete the memory device 18 02 to exchange the data (DATA). The memory controller 1 800 can include a temporary memory 211 and the memory device 1 802 can include each of the temporary registers 22 211, 221 to store the device 1802 Block re-new mode or partial re-new mode operation: Beixun. Also, if you determine the memory 18〇2 installed: Γ: 211, 221 each can store part of the re-source: when the source line starts Or the number of bit lines. 133200.doc -48· 200915319 As shown in FIG. 21, in the discreet example embodiment, the capacitorless memory device 1802 may include a plurality of thermoelectric valleys 802 (eg, X memory device 1 802 χ, # , , where x is greater than an integer specific to 丨) memory module 1804 to increase memory capacity. In an example embodiment, memory module 1804 may contain a temporary 231 (example)

如’ EEPR〇M)，其館存CL⑽潛時）、tRCD (RAS至CAS 延時）、表不部分再新模式或區塊再新模式之指示符，及/ ΟSuch as ' EEPR 〇 M), its library CL (10) latent time), tRCD (RAS to CAS delay), indicator of partial renew mode or block renew mode, and / Ο

或部分再新模式中待同時再新之源極線的數目及/或位元 線之數目。 在實例實施例中’ c憶體控制器18GG可在記憶體系統接 通之後自記憶體模組暫存器231讀取所儲存之值，將資訊 寫入至記憶體控制器暫存器211，且接著使用模式暫存器 設定（MRS)指令將值中之—或多者寫人至記憶體模組刪 中之相應記憶體裝置1802χ中之每一者的暫存器22“。舉例 而言’記憶體控制器18〇〇可提供用於確定區塊再新模式及 部分再新模St之-者之MRS指令且接著提供用於再新操 作的再新指令。 當確定為部分再新時’ MRS指令可包括在再新操作中待 同時啟動之在記憶體裝置1802χ中之源極線（或位元線）的數 目0 記憶體控制器丨800中之暫存器211及記憶體裝置18〇^中 之暫存器221χ可經修改且可設定為當記憶體系統通電或Χ重 設時發生的初始化序列之部分。 圖22Α說明習知記憶體系統之習知時序圖。如圖中 133200.doc -49- 200915319 所示，根據時脈信號CLK，習知記憶體控制器可提供啟動 指令ACT連同列位址R_ADDR以根據列位址啟動指定字 線。在時間延遲tRCD之後，記憶體控制器可發出寫入指 令WR、行位址C_ADDR ’且提供待寫入至由列位址r_ ADDR及行位址C-ADDR指定之記憶體單元之資料WD。對 於根據列位址自連接至所啟動字線之記憶體單元進行之讀 取操作，習知記憶體控制器發出讀取指令RE結合行位址c_ ADDR且接著自記憶體裝置讀取RD資料。若讀取指令处並 非針對同一列位址，則記憶體控制器必須針對該讀取指令 發出另一啟動指令ACT。 圖22B說明與根據圖2〇或圖21之記憶體系統相符之時序 圖。如圖22B中所說明，記憶體控制器不必發出字線啟動 指令ACT。替代地，記憶體控制器可輸出寫入指令職以 及位址ADDR，包括指示啟動哪個字線之列位址及選擇連 接至所啟動字線之無電容器記憶體單元的行位址，且將資 料：D寫入至無電容器記憶體裝置中之所選無電容器記憶 體早兀，如上文已說明之實例實施例中所描述。Or the number of new source lines and/or the number of bit lines to be renewed in the partial renew mode. In the example embodiment, the 'c memory controller 18GG can read the stored value from the memory module register 231 after the memory system is turned on, and write the information to the memory controller register 211. And then using the mode register setting (MRS) command to write one or more of the values to the register 22 of each of the corresponding memory devices 1802 删 in the memory module deletion. For example The 'memory controller 18' may provide an MRS instruction for determining the block renew mode and the partial remodeling mode St and then provide a renewed instruction for the renew operation. When it is determined to be partially renewed The MRS command may include the number of source lines (or bit lines) in the memory device 1802χ to be simultaneously activated in the renew operation. The scratchpad 211 and the memory device 18 in the memory controller 丨800. The register 221 〇 can be modified and can be set as part of the initialization sequence that occurs when the memory system is powered up or reset. Figure 22A illustrates a conventional timing diagram of a conventional memory system, as shown in Figure 133200. .doc -49- 200915319, according to the clock signal CLK, The memory controller can provide a start command ACT along with the column address R_ADDR to start the specified word line according to the column address. After the time delay tRCD, the memory controller can issue the write command WR, the row address C_ADDR 'and provide Writing to the data WD of the memory unit specified by the column address r_ADDR and the row address C-ADDR. For the read operation of the memory unit connected to the activated word line according to the column address, the conventional memory The body controller issues a read command RE combined with the row address c_ADDR and then reads the RD data from the memory device. If the read command is not for the same column address, the memory controller must issue another for the read command A start command ACT. Figure 22B illustrates a timing diagram consistent with the memory system according to Figure 2A or Figure 21. As illustrated in Figure 22B, the memory controller does not have to issue the word line enable command ACT. Alternatively, memory control The device can output a write command job and an address ADDR, including a column address indicating which word line is activated and a row address of the capacitorless memory unit connected to the activated word line, and writing the data: D The selected capacitorless memory in the capacitorless memory device is as early as described in the example embodiments described above.

。在習知記憶體控制器中， 133200.doc w命叫呀輸出列位址及行 需要獨立控制電路來輸出 -50- 200915319 列位址及行位址。 如圖22B中所示，在實例實施例中，記憶體控制器可發. In the conventional memory controller, the output column address and row require independent control circuits to output the -50-200915319 column address and row address. As shown in FIG. 22B, in an example embodiment, the memory controller can be issued

出用於選擇區塊再新模式及部分再新模式中之一者之MRS 指令且若選擇部分再新模式，則MRS指令可包括對於部分 再新操作可同時啟動之源極線乩或位元線81之數目。記 憶體控制器可接著在MRS指令之後發出再新指令尺£1?。 上文結合圖20至圖22B論述之變化及/或替代性實施例中The MRS instruction for selecting one of the block renew mode and the partial renew mode and if a partial renew mode is selected, the MRS instruction may include a source line or bit that can be simultaneously activated for partial renew operation The number of lines 81. The memory controller can then issue a new command rule £1 after the MRS command. Variations and/or alternative embodiments discussed above in connection with Figures 20-22B

之任一者亦可應用於圖1A至圖1〇或圖11A至圖19中所說明 的實例實施例。更一般而言，本說明書揭示具有若干不同 特徵之若干實例實施例。可以任何組合使用此等特徵中之 每—者0 疇内 因此，在已描述實例實施例之情況下，明顯可以許多方 式改變該等實例實施例。此等變化不應被視為偏離實例實 施例’且所有此等修改意欲包括於附加申請專利範圍之範 【圖式簡單說明】 憶體單元 圖1A說明可實施實例實施例之橫向無電容器 結構。 D。 結構 圖職明可實施㈣實㈤y直無電容^憶體單元 器記憶體單元之等 圖2 3兒明可實施實例實施例之無電容 效電路 元之直流 圖3說明根據實例實施例之無電容器記憶 電特徵。 133200.doc -51 - 200915319 圖4說明可實施實例眘 Μ#, &例之根據具有一獨立源極線架 構之實例實施例的記憶體裝置。 圖5說明根據具有一猸 ^ , 獨立源極線架構之實例實施例之用 於一列操作的實例時序圖。 圖6說明根據具有—猫&，s “人 獨立源極線架構之實例實施例之用 於一個單元操作的實例時序圖。 圖7說明可實施實例實施例之根據具有—共同源極線架 構之實例實施例的記憶體裝置。Any of the embodiments of the embodiment illustrated in Figures 1A to 1A or 11A to 19 can also be applied. More generally, the present specification discloses several example embodiments having several different features. Any of these features may be used in any combination. Thus, in the case of the example embodiments, the example embodiments may be modified in many ways. Such variations are not to be regarded as a departure from the example embodiment' and all such modifications are intended to be included in the scope of the appended claims. FIG. 1A illustrates a lateral capacitorless structure in which example embodiments may be implemented. D. The structure diagram can be implemented (4) real (5) y straight no capacitor ^ memorandum unit memory unit, etc. Figure 2 3 can be implemented as a non-capacitive circuit element of the example embodiment of the DC Figure 3 illustrates a capacitor-free according to an example embodiment Memory characteristics. 133200.doc -51 - 200915319 Figure 4 illustrates an embodiment of a memory device according to an example embodiment having an independent source line architecture. Figure 5 illustrates an example timing diagram for a column of operations in accordance with an example embodiment having an independent source line architecture. Figure 6 illustrates an example timing diagram for one unit operation in accordance with an example embodiment having a -cat &, "human independent source line architecture. Figure 7 illustrates a basis for implementing an example embodiment having a common source line architecture A memory device of an example embodiment.

圖8说明根據具有一共同源極線架構之實例實施例之用 於一列操作的實例時序圖。 圖9說明根據具有一共同源極線架構之實例實施例之用 於一個單元操作的時序圖。 圖10說明可實施實例實施例之另一記憶體裝置。 圖11 A至圖11B說明根據實例實施例之無電容器記憶體 單元結構。 圖1 2 A及圖1 2B說明根據實例實施例之無電容器記憶體 單元結構。 圖13A至圖13B說明根據實例實施例之無電容器記憶體 單元結構。 圖14A至圖14B說明根據實例實施例之無電容器記憶體 單元結構。 圖1 5 A至圖1 5 C說明根據實例實施例之無電容器記憶體 單元結構。 圖1 6 A說明根據實例實施例之記憶體單元結構之平面 133200.doc -52· 200915319 圖。 圖16B說明圖16A之方向Μ，之橫截面圖。 圖16C說明沿圖16A中所示之方向11-11，之橫截面圖。 圖17說明根據實例實施例之無電容器記憶體之橫戴面 圖。 圖1 8說明根據實例實施例之具有FinFET結構之無電容器 記憶體。 圖1 9說明根據實例實施例之使用FinFET結構之另一無電 容器記憶體。 圖20說明根據實例實施例之記憶體系統。 圖21說明根據實例實施例之另一記憶體系統。 圖22 A說明習知記憶體系統之習知時序圖。 圖22B說明與根據實例實施例之記憶體系統相符之時序 圖。 【主要元件符號說明】 10 基板 12 絕緣層 14 第一節點 16 第二節點 18 浮體區域 20 閘極絕緣層 21 字線 22 閘極 24 緩衝區域 133200.doc 200915319 26 輔助浮體區域 27 延伸浮體區域 30 第一接點 32 弟二接點 34 源極線 36 位元線 42 絕緣層 44 隔離層 46 絕緣層 48 第二接點 50 記憶體陣列 50' 記憶體陣列 52 列控制單元 52， 列控制單元 52" 列控制單元 54 行控制單元 54' 行控制單元 54" 行控制單元 140 電洞儲集器 211 暫存器 221 暫存器 221,.x 暫存器 231 暫存器 1800 記憶體控制器 133200.doc -54- 200915319 1802 無電容器記憶體裝置 1802,.x 無電容器記憶體裝置 1804 記憶體模組 B 基極 BLl~j 位元線 CC 耦合電容 C(D) 集極/汲極 E(S) 發射極/源極 G 閘極 il 電流 i2 電流 i3 電流 i4 電流 i5 電流 i6 電流 iBLl 〜j 位元線 LI 浮體長度 L2 閘極長度 MC1-I 記憶體單元 SLi 〜I 源極線 TO 時間間隔 T1 時間間隔 T2 時間間隔 T3 時間間隔 133200.doc -55- 200915319 Τ4 時間間隔 Τ5 時間間隔 Τ6 時間間隔 WLi 〜I 字線 133200.doc -56Figure 8 illustrates an example timing diagram for a column of operations in accordance with an example embodiment having a common source line architecture. Figure 9 illustrates a timing diagram for a unit operation in accordance with an example embodiment having a common source line architecture. Figure 10 illustrates another memory device in which example embodiments may be implemented. 11A through 11B illustrate a capacitorless memory cell structure in accordance with an example embodiment. 1 2 A and 1 2B illustrate a capacitorless memory cell structure in accordance with an example embodiment. 13A through 13B illustrate a capacitorless memory cell structure in accordance with an example embodiment. 14A through 14B illustrate a capacitorless memory cell structure in accordance with an example embodiment. Fig. 15A to Fig. 1C illustrate a capacitorless memory cell structure according to an example embodiment. Figure 146A illustrates a plane of a memory cell structure according to an example embodiment 133200.doc -52· 200915319. Figure 16B illustrates a cross-sectional view of the direction of Figure 16A. Figure 16C illustrates a cross-sectional view along the direction 11-11 shown in Figure 16A. Figure 17 illustrates a cross-sectional view of a capacitorless memory in accordance with an example embodiment. Figure 18 illustrates a capacitorless memory having a FinFET structure in accordance with an example embodiment. Figure 19 illustrates another non-regular memory using a FinFET structure in accordance with an example embodiment. Figure 20 illustrates a memory system in accordance with an example embodiment. Figure 21 illustrates another memory system in accordance with an example embodiment. Figure 22A illustrates a conventional timing diagram of a conventional memory system. Figure 22B illustrates a timing diagram consistent with a memory system in accordance with an example embodiment. [Main component symbol description] 10 Substrate 12 Insulation layer 14 First node 16 Second node 18 Floating body region 20 Gate insulating layer 21 Word line 22 Gate 24 Buffer region 13320.doc 200915319 26 Auxiliary floating body region 27 Extended floating body Area 30 First contact 32 Dipole contact 34 Source line 36 Bit line 42 Insulation layer 44 Isolation layer 46 Insulation layer 48 Second contact 50 Memory array 50' Memory array 52 Column control unit 52, Column control Unit 52" Column Control Unit 54 Line Control Unit 54' Row Control Unit 54" Row Control Unit 140 Hole Reservoir 211 Register 221 Register 221, .x Register 231 Register 1800 Memory Controller 133200.doc -54- 200915319 1802 Capacitor-free memory device 1802, .x Capacitor-free memory device 1804 Memory module B Base BL1~j Bit line CC Coupling capacitor C(D) Collector/drain E ( S) emitter/source G gate il current i2 current i3 current i4 current i5 current i6 current iBLl ~j bit line LI float length L2 gate length MC1-I memory unit S Li ~ I source line TO time interval T1 time interval T2 time interval T3 time interval 133200.doc -55- 200915319 Τ4 time interval Τ5 time interval Τ6 time interval WLi ~I word line 133200.doc -56

Claims (1)

200915319 十、申請專利範圍： 1. 一種記憶體裝置，其包含： :記憶體陣列，其包括複數個記憶體單元，每— 體單凡包括一浮體電晶體，該浮體 具有分別連接 μ 一位^線、至少-源極線及至少-字線之—第— 節點、—第二節點及一閘極節點；及 1二控制單元’其用於藉由選擇該至少_源極線及該至 C L V-位凡線中之一者來回應於一再新指令執行一再新操 作:其中若將第-資料儲存於連接至該所選線之 體單元處，則由雙極接面操作引發的一第一電流流動丫 2.如凊未们之記憶體裝置，其中若將第二資料儲存於連 接至該所選線之該記憶體單元處，則由雙極接面操作引 發的—電流不流動。 汝明求項1之記憶體裝置，該複數個記憶體單元中之每 I者包括位於該第一節點與該第二節點之間的一浮體區 4. 如明求項3之記憶體裝置，其中該浮體區域具有一浮體 長度且該閘極具有一閘極長度，其中該閘極長度小於該 浮體長度。 Λ 5. 如請求項1之記憶體裝置，其中源極線之數目等於字線 的數目。 、' 6. 如請求項5之記憶體裝置，其中，對於—給定電壓施加 至該至少一字線之情況’施加至該至少—源極線及該至 少一仅元線之一電壓之間的一差誘發該雙極接面操作。 133200.doc 200915319 7·如請求項丨之記憶體裝置’該控制單元包括—用於控制 该至少-源極線及該至少—字線之列控制單元及一用於 控制該至少一位元線的行控制單元。 8. 如請求項1之記憶體農置，其中源極線之數目小於字線 的數目。 9. 如請求項8之記憶體裝置，其中一位元線方向 =單元共用該等至少-源極線中之-者，該控制單 ^由進_步㈣^少―字線來進—步執行該再新操 10. —種記憶體裝置，其包含； 。己I*體陣列’其包括複數個記憶體單元，每一記憶 體早疋包括一浮體電晶體 心 至至少-位元線、至少一…=電阳體具有分別連接 4 原極線及至少—字線之一第一 即』、—第二節點及-閘極節點；及 -控制單元，其用於藉由根 入雷厭A s ^ , 貝7寸貝0K將—位7L線寫 入電壓施加至該至少—位元線 壓施加至該至少一源極線，且接著將一二=線寫入電 加至該至少-字線來執行一寫入操作。、、、“.、入電壓施 η.==之記憶體農置，其中該源極線 8亥位疋線寫人電壓及該字線“電壓。 12. 如請求項丨丨之記憶體裝置，装 ^ ^ ·&amp; ^ w ’、對於該字線寫入電壓， 該源極線寫入電壓與該位元線“㈣壓 該資料資訊引發雙極接面操作。 的-差根據 13. 如請求項10之記憶體裴置，該抑 上】早7L精由將一字線保 133200.doc 200915319 持電壓施加至該至少一字線，接著將一源極線保持電壓 施加至該至少一源極線，且接著將—位元線保持電壓施 加至該至少一位元線來進一步執行該寫入操作。 14.如請求項1()之記憶體裝置，其中該控制單元藉由將不多 於兩個電壓位準施加至該至少—字線來進一步執行該寫 入操作、一讀取操作及一再新操作。 ， .如請求項H)之記憶體裝置，其中源極線之數目等 的數目。 、' 1 6·如請求項丨〇之記憶體裝置， 的數目。 /、中雜線之數目小於字線 17，一種記憶體單元結構，其包含： 一絕緣體上矽結構，直句 層，兮㈣h Ά括一基板、一絕緣體及-石夕 體區域，及一位㈣第一/即及第一郎點、一浮 ，心触 ' χ弟卽點及該第二節點中之一者盥 忒沣體之間的緩衝區 者/、 鄰近節中該緩衝區域具有-低於該 种丨ϋ即點或該洋體併 第-節畔及哕笫/其中該緩衝區域覆蓋該 广及㈣—節點中之該—者的整個邊界；及 -間極結構，其位於該矽層上。 18. 如請求項17之記憶體單元社 與點及該第二節點中之該—者 、有 19. 如睛求項17之記憶 之阿度。 絕緣體。 ， 兀、’、°構’纟中該緩衝區域接觸該 2〇_ 一種記憶體單元結構，其包含： 一絕緣體上矽結構， 八C括一基板、一絕緣體，及一 133200.doc 200915319 夕層°亥矽層包括摻雜雜質之第一節點及第二節點、一 位於其間的具有-浮體長度之浮體區域，及-位於該第 /節點及该第二節點中之一者與該浮體之間的緩衝區 域’其中_緩衝區域具有—低於該鄰近節點或該浮體之 雜質濃度；及 位於該石夕層上具有一閘極長度之閘極結構，其中該 浮體長度大於該閘極長度。 21. 一種記憶體單元結構，其包含： 、、-邑緣體上矽結構，其包括一基板、一絕緣體及一矽 層，該矽層包括摻雜雜質之一發射極/源極及一集極/汲 極 浮體區域，及一位於該發射極/源極與該浮體之間 的輔助浮體區域，其中該輔助浮體區域具有一低於該浮 體之雜質濃度之雜質濃度；及 一閘極結構，其位於該石夕層上。 22·如明求項2 1之记憶體單元結構，其中該輔助浮體區域覆 蓋該發射極/源極之全部。 23. 如％求項21之記憶體單元結構，其中該浮體區域長於該 輔助浮體區域。 24. —種記憶體單元結構，其包含： —絕緣體上矽結構，其包括一基板、一絕緣體，及一 石夕層，該矽層包括摻雜雜質之第一節點及第二節點、一 浮體區域，及一鄰近該浮體區域之延伸浮體區域；及 &quot;閘極結構，其位於該石夕層上。 25. 如凊求項24之記憶體單元結構，其中該延伸浮體區域在 133200.doc 200915319 一與該第一節點及該第二節點及該浮體之—方向正交的 方向上延伸。 26. 如請求項24之記憶體單元結構，其中該延伸浮體區域在 該閘極結構下一方向上延伸。 27. —種記憶體單元結構，其包含： 一絕緣層，其位於一基板上； 一矽圖案’其位於該絕緣層上且包括一第一節點、一 第二節點及一浮體區域；及 一閘極，其圍繞該浮體區域， 其中該閘極之長度小於該浮體區域且其中對於一給定 電壓施加至該閘極之情況，施加至該第一節點及該第二 節點之電壓之間的一電壓差誘發一雙極接面操作。 28. 如請求項27之記憶體單元，其進一步包含： 一緩衝區域，其位於該浮體區域與該第一節點及該第 二節點中之一者之間，其中該緩衝區域具有一低於該第 一即點及該第二節點中之該一者之雜質濃度的雜質濃 度。 ' 29. —種記憶體單元結構，其包含： 一絕緣層，其位於—基板上； 一碎圖案’其位於該絕緣層上，其包括一第一節點、 一第二節點及一浮體區域； 延伸浮體區域’其位於該浮體區域上；及 一閘極結構，其圍繞該浮體區域及該延伸浮體區域。 3〇.如請求項29之記憶體單元，其中該閘極長度小於該浮體 133200.doc 200915319 區域之長度。 31,如請求項29之記憶體單元，兑 八延 步包含： 一緩衝區域，其位於該浮體 一— 丄 體&amp;域與該第一節點及該第 二郎點中之一者之間，其中 … 吐 Τ β亥緩衝區域具有一低於該第 一郎點及該第二節點中之哕一 ^者之雜質濃度的雜質濃 度0 3 2· —種用於控制一包括複數 极数個無電容器記憶體單元之記憶 體裝置之一再新操作的方法，其包含. 提供一用於識別該記憶體裝置之一區塊再新操作及一 部分再新操作中之-者的模式暫存器設定指令；及 提供一用於該再新操作之再新指令。 33·如請求項32之方法，該模式暫存器設定指令在該部分再 新操作得到確定時進—步識㈣記憶體裝置中之在該再 新操作中啟動之源極線及位元線中的一者之數目。 34_如請求項32之方法，其進一步包含：200915319 X. Patent Application Range: 1. A memory device comprising: a memory array comprising a plurality of memory cells, each body comprising a floating body transistor, the floating body having a connection μ a bit line, at least a source line and at least a word line - a node - a second node and a gate node; and a second control unit 'for selecting the at least _ source line and the One of the CL V-bit lines responds to repeated new instructions to perform a new operation: if the first data is stored in the body unit connected to the selected line, the bipolar junction operation is triggered. a first current flowing 丫 2. For example, if the second data is stored in the memory unit connected to the selected line, the current is not caused by the bipolar junction operation. flow. The memory device of claim 1, wherein each of the plurality of memory cells includes a floating body region between the first node and the second node. 4. The memory device of claim 3 Wherein the floating body region has a floating body length and the gate has a gate length, wherein the gate length is less than the floating body length. Λ 5. The memory device of claim 1, wherein the number of source lines is equal to the number of word lines. 6. The memory device of claim 5, wherein a case where a given voltage is applied to the at least one word line is applied between the at least one source line and the voltage of the at least one only line A difference in the induced bipolar junction operation. 133200.doc 200915319 7. The memory device of the request item </ RTI> includes: - a control unit for controlling the at least - source line and the at least - word line and a control unit for controlling the at least one bit line Line control unit. 8. If the memory of claim 1 is farmed, the number of source lines is less than the number of word lines. 9. The memory device of claim 8, wherein one of the element line directions = the unit shares the at least one of the source lines, the control unit is stepped by the step _ step (four) ^ less "word line" Performing the renewed operation 10. A memory device, which includes; The I* body array includes a plurality of memory cells, each of which includes a floating body transistor core to at least a bit line, at least one...=electric anode having a connection to the 4th polarity line and at least - one of the word lines, ie, the first node and the -th gate node; and - the control unit, which is used to write the bit 7L line by rooting into the Ray A A s ^ A voltage is applied to the at least one bit line voltage applied to the at least one source line, and then a two = line write is applied to the at least one word line to perform a write operation. ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 12. If the memory device of the request item is installed, ^^ ·&amp; ^ w ', write voltage to the word line, the source line write voltage and the bit line "(4) press the data information to cause double The polarity of the operation is as follows: 13. According to the memory device of claim 10, the suppression is as early as 7L fine by applying a word line to 133200.doc 200915319 holding voltage to the at least one word line, and then A source line holding voltage is applied to the at least one source line, and then a bit line holding voltage is applied to the at least one bit line to further perform the writing operation. 14. Memory of claim 1() The device, wherein the control unit further performs the write operation, a read operation, and a new operation by applying no more than two voltage levels to the at least one word line, as in claim H) The number of the memory devices, in which the number of source lines, etc., '1 6 · the number of memory devices as requested, /, the number of miscellaneous lines is smaller than word line 17, a memory cell structure, It consists of: an insulator on the raft structure, straight layer, 兮(d) h including a substrate, an insulator and a stone body area, and a (four) first / ie and the first Lang point, a float, the heart touch 'χ 卽 卽 point and one of the second node 盥忒The buffer zone between the carcasses/, the buffer zone in the adjacent section has - below the point, the point or the body and the section - and / / the buffer zone covers the wide (4) - node The entire boundary of the one; and - the interpole structure, which is located on the layer. 18. As in the memory unit of the claim 17 and the point and the second node, there are 19. The memory of the item 17 is a degree of insulation. The insulator, the 兀, ', 构 纟 ' 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 缓冲 缓冲 缓冲 缓冲 缓冲 缓冲 缓冲 缓冲 缓冲 缓冲 缓冲 缓冲 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆An insulator, and a 133200.doc 200915319 layer includes a first node and a second node doped with impurities, a floating body region having a floating body length therebetween, and - located at the /th node And a buffer area between the one of the second nodes and the floating body The domain has a concentration of impurities lower than the adjacent node or the floating body; and a gate structure having a gate length on the layer, wherein the length of the floating body is greater than the length of the gate. The structure comprises: a germanium structure, comprising a substrate, an insulator and a germanium layer, the germanium layer comprising one of the doping impurities, an emitter/source and a collector/drain floating body a region, and an auxiliary floating body region between the emitter/source and the floating body, wherein the auxiliary floating body region has an impurity concentration lower than an impurity concentration of the floating body; and a gate structure Located on the Shishi layer. 22. The memory cell structure of claim 2, wherein the auxiliary floating body region covers all of the emitter/source. 23. The memory cell structure of claim 21, wherein the floating body region is longer than the auxiliary floating body region. 24. A memory cell structure comprising: - an insulator overlying structure comprising a substrate, an insulator, and a layer comprising a first node and a second node doped with impurities, and a floating body a region, and an extended floating body region adjacent to the floating body region; and a &quot; gate structure on which the rock layer is located. 25. The memory cell structure of claim 24, wherein the extended floating body region extends in a direction orthogonal to the direction of the first node and the second node and the floating body at 133200.doc 200915319. 26. The memory cell structure of claim 24, wherein the extended floating body region extends in a next direction of the gate structure. 27. A memory cell structure comprising: an insulating layer on a substrate; a germanium pattern on the insulating layer and including a first node, a second node, and a floating body region; a gate surrounding the floating body region, wherein the length of the gate is less than the floating body region and wherein a voltage applied to the first node and the second node is applied to the gate for a given voltage A voltage difference between them induces a bipolar junction operation. 28. The memory unit of claim 27, further comprising: a buffer region between the floating body region and one of the first node and the second node, wherein the buffer region has a lower The impurity concentration of the impurity concentration of the one of the first point and the second node. 29. A memory cell structure comprising: an insulating layer on a substrate; a broken pattern 'on the insulating layer, comprising a first node, a second node, and a floating body region Extending the floating body region 'which is located on the floating body region; and a gate structure surrounding the floating body region and the extended floating body region. 3. The memory unit of claim 29, wherein the gate length is less than the length of the floating body 133200.doc 200915319 region. 31. The memory unit of claim 29, wherein the acknowledgment comprises: a buffer region between the floating body-body &amp; field and one of the first node and the second lang point , wherein... the 亥 Τ 亥 缓冲 buffer region has an impurity concentration lower than the impurity concentration of the first lang point and the second node of the second node 0 3 2 · for controlling one including a plurality of poles A method for re-operating a memory device of a capacitorless memory unit, comprising: providing a mode register setting for identifying a block new operation and a part of the refresh operation of the memory device An instruction; and a new instruction for the re-operation. 33. The method of claim 32, wherein the mode register setting instruction is in the step-by-step identification (four) of the source line and the bit line activated in the re-operation in the memory device. The number of one of them. 34. The method of claim 32, further comprising: 在無任何先前列啟動指令之情形下將一寫入指令提供 至該記憶體裝置；及 將寫入資料、一第一列位址及一第一行位址提供至該 記憶體裴置。 35·如請求項34之方法，其進一步包含： 在無任何先前字線啟動指令之情形下將一讀取指令提 供至該記憶體裝置； 將一第二列位址及一第二行位址提供至該記憶體裝 置；及 133200.doc 200915319 自該δ己憶體裝置接收讀取資料。 3 6. —種記憶體控制器，其包含： -第-暫存器，其儲存—用於選擇_記憶體裝置之區 塊再新及—部分㈣巾之―者的料暫存㈣定指令。 37.如請求項35之記憶體控制器，其進一步包含： 第-暫存器，其儲存關於該記憶體裝置中啟動之源 極線及位元線中之至少一者的數目之資訊。 38_ —種無電容器記憶體裝置，其包含： -第-暫存器，其儲存用於選擇一區塊再新及一部分 再新中之一者之一再新操作的資訊。 39. 如請求項38之無電容器記憶體裝置，其進一步包含： -第二暫存器，其儲存關於在該部分再新中啟動之源 極線及位元線中之至少—者的數目之資訊。 、 40. —種記憶體單元結構，其包含： ，、邑緣體上@結構，其包括—基板、—絕緣體及—石夕 層，該石夕層包括第一節點及第二節點、一浮體區域；及 一閘極，其位於該浮體區域上， 其中該閘極之長度小於該浮體之長度，且其中對於一 給叱電壓施加至該閘極之情況，施加至該第一節點及該 第二節點的電壓之間的一差誘發一雙極接面操作。^ 41. 如請求項40之記憶體單元結構，其中該閘極未重疊該第 一節點及該第二節點。 42. 如請求項40之記憶體單元結構，其中該閘極未重疊該第 一節點及該第二節點中之至少一者。 133200.doc 200915319 —ρ求項42之5己憶體單元結構，其中該第一節點及該第 中之4者接收一較高施加電壓用於該雙極接面 操作。 44. 一種記憶體裝置，其包含： π :己It體陣列，其包括複數個記憶體單元，每一記憶 π包括-浮體電晶體’該浮體電晶體具有分別連接 =至少—位元線、至少一源極線及至少一字線之一第一 節點、一第二節點及一閘極；及 一控制單元，其用於藉由選擇該至少一源極線中之一 者且藉由不_該等至少-字線中之者來執行一讀 取操作’其巾若將[㈣儲存於—連接至該所選源極 線的記憶體單元處，則由雙極接面操作引發之—第 流流動。 45. 如請求項44之記憶體裝置，其中若將第二資料儲存於連 接至該所選源極線之該記憶體單元處，則由雙極接面操 作引發的一第二電流不流動。 46. 如請求項44之記憶體裝置，其中該控制單元對該等至少 源極線中之該所選者施加一源極線讀取電壓且對該至 少一字線施加一字線保持電壓。 47. 如請求項46之記憶體裝置，其中該控制單元藉由選擇該 等至少一源極線中之一者、該等至少一字線中的—者及= 等至少一位元線中之至少一者來進一步執行一寫入操作 48. 如請求項β之記憶體裝置，其中該控制單元針對兮寫 操作對該等至少一源極線中之該所選者施加_ : 你極線寫 133200.doc -8 - 200915319 入電壓且對該等至少 入電壓。 —子線中的該所選者施加一字線寫 49. 如請求項48之記憶體 該源極線寫入電壓。 50. 如請求項47之記憶體 等源極線中之至少兩 一者來進一步執行一 裝置，其中該源極線讀取電壓等於 裝置，其中該控制單元藉由選擇該 者且不選擇該等至少一字線中的任 再新操作。 51.A write command is provided to the memory device without any previous column start command; and the write data, a first column address, and a first row address are provided to the memory device. 35. The method of claim 34, further comprising: providing a read command to the memory device without any previous word line enable command; placing a second column address and a second row address Provided to the memory device; and 133200.doc 200915319 receiving read data from the delta recall device. 3 6. A memory controller, comprising: - a - register, which is stored - for selecting a block of the memory device and a part - (four) towel - temporary storage (four) instructions . 37. The memory controller of claim 35, further comprising: a first register that stores information regarding the number of at least one of the source line and the bit line activated in the memory device. 38_ — A capacitorless memory device comprising: - a first register, storing information for selecting one of a block renewed and a portion of a new one to re-new operation. 39. The capacitorless memory device of claim 38, further comprising: - a second register storing the number of at least one of a source line and a bit line activated in the portion of the regeneration News. 40. A memory cell structure, comprising: a structure on the edge of the body, comprising: a substrate, an insulator, and a stone layer, the stone layer comprising a first node and a second node, a floating a body region; and a gate on the floating body region, wherein the gate has a length smaller than a length of the floating body, and wherein a first applied voltage is applied to the first node for a given voltage And a difference between the voltages of the second node induces a bipolar junction operation. 41. The memory cell structure of claim 40, wherein the gate does not overlap the first node and the second node. 42. The memory cell structure of claim 40, wherein the gate does not overlap at least one of the first node and the second node. 133200.doc 200915319 - ρ Resolving item 42 of the five-member cell structure, wherein the first node and the fourth one receive a higher applied voltage for the bipolar junction operation. 44. A memory device comprising: a π:hex body array comprising a plurality of memory cells, each memory π comprising a -float transistor 'the floating body transistor having a connection = at least - a bit line And at least one source line and at least one of the word lines, a first node, a second node, and a gate; and a control unit for selecting one of the at least one source line by using Do not use the at least one of the word lines to perform a read operation. If the wiper stores [(4) in the memory cell connected to the selected source line, it is caused by the bipolar junction operation. - The first flow. 45. The memory device of claim 44, wherein if the second data is stored at the memory unit connected to the selected source line, a second current induced by the bipolar junction operation does not flow. 46. The memory device of claim 44, wherein the control unit applies a source line read voltage to the selected one of the at least source lines and applies a word line hold voltage to the at least one word line. 47. The memory device of claim 46, wherein the control unit comprises at least one of the at least one source line, the at least one of the at least one word line, and the at least one element line At least one further performs a write operation 48. The memory device of claim item β, wherein the control unit applies _ to the selected one of the at least one source line for a write operation: 133200.doc -8 - 200915319 Incoming voltage and at least the voltage. - The selected one of the sub-lines applies a word line write. 49. The memory of claim 48 is the source line write voltage. 50. Performing at least two of the source lines, such as the memory of claim 47, to further perform a device, wherein the source line read voltage is equal to the device, wherein the control unit selects the person and does not select the Any new operation in at least one word line. 51. 如請求項5 〇之記憶體 操作對該等源極線中 新電壓且對該至少— 裝置，其中該控制單元針對該再新 之該所選至少兩者施加一源極線再 字線施加該字線保持電壓。 52. 如請求項51之記憶體裝置，其中該源極線讀取電壓等於 該源極線寫入電壓及該源極線再新電壓。 、 53.如5肖求項51之記憶體裝置，其中該控制單元藉由對該至 少一字線施加不多於該字線保持電壓及該字線寫入電壓 來進一步執行該寫入操作、該讀取操作及該再新操作。The memory of claim 5 operates a new voltage in the source line and applies to the at least device, wherein the control unit applies a source line to the word line for the selected at least two of the renewed The word line holds the voltage. 52. The memory device of claim 51, wherein the source line read voltage is equal to the source line write voltage and the source line renew voltage. 53. The memory device of claim 5, wherein the control unit further performs the writing operation by applying no more than the word line holding voltage and the word line write voltage to the at least one word line, The read operation and the renew operation. 54·如請求項44之記憶體裝置，其進一步包含： 一感測單元，其用於感測該第一電流及該第二電流且 為一電壓感測放大器及一電流感測放大器中之—者。 5 5.如睛求項44之記憶體裝置，該複數個記憶體單元中之每 一者包括一位於該第一節點與該第二節點之間的浮體區 域’其中該浮體區域具有一浮體長度且該閘極具有一閘 極長度，其中該閘極長度小於該浮體長度。 56.如請求項54之記憶體裝置’其中源極線之數目等於字線 的數目。 133200.doc54. The memory device of claim 44, further comprising: a sensing unit for sensing the first current and the second current and being in a voltage sense amplifier and a current sense amplifier - By. 5. The memory device of claim 44, each of the plurality of memory cells including a floating body region between the first node and the second node, wherein the floating body region has a The length of the float and the gate has a gate length, wherein the gate length is less than the length of the float. 56. The memory device of claim 54 wherein the number of source lines is equal to the number of word lines. 133200.doc
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