TW200910356A

TW200910356A - Flash storeage chip and flash array storage system

Info

Publication number: TW200910356A
Application number: TW96132488A
Authority: TW
Inventors: Khein-Seng Pua; Chih-Ling Wang; Wee-Kuan Gan
Original assignee: Phison Electronics Corp
Priority date: 2007-08-31
Filing date: 2007-08-31
Publication date: 2009-03-01
Also published as: TWI349284B

Abstract

A flash storage chip is provided. The flash storage chip includes a single circuit board, a microcontroller, a flash memory and a PCI Express connecting interface. The microcontroller, the flash memory and the PCI Express connecting interface are embedded at the single circuit board, and the microcontroller includes a flash memory interface and a PCI Express interface. When a host writes data into the flash storage chip, the microcontroller receives the data though the PCI Express interface and stores the data in the flash memory though the flash memory interface. When the host reads data form the flash storage chip, the microcontroller reads the data from the flash memory though the flash memory and transmits the data to the host though the PCI Express interface.

Description

200910356 PSPD-20U7-U016 24992twf.doc/n 九、發明說明：【發明所屬之技術領域】本發明是有關於-種儲存裝置，且特別是有快閃儲存晶片與快閃陣列儲存系統。、—種【先前技術】隨著電子工業在半導體技術上的不斷地渾進，品已朝向提升處理速度以及多功能化等方 ^產 ^統中’邏輯處理元件（例如中央處理器）以及纪情^ 處理速度亦在此一趨勢之下不斷地提升。％體之然而，在電腦系統中除了邏輯處理元件以及處理速度影響著電㈣統之運作效料，存^之 =)的存取速度亦是影響電腦純之運作效^的 t二由於ΓΓ裝置無法突破自身的技術障礙來提升其二、、又’使付其存取速度仍無法與中央處理器以及記憶理速度配合，因而造成電腦线的整體效能無法有效地提升。 ” 傳輸資料的速度取決於匯流排的傳輸速度，為了能使電腦的效能提升’相關業者不斷研發提生魏的介面，例如整合式驅動電子（IDE)介面、周邊組件互連（PCI)介面、高速周邊組件互連（PCIEXPress)連接介面等。此外，為了提升電腦系統中存取裝置的存取速度，習知技術提出一種磁碟陣列（Redundant Array of Independent200910356 PSPD-20U7-U016 24992twf.doc/n IX. Description of the Invention: [Technical Field] The present invention relates to a storage device, and particularly to a flash memory chip and a flash array storage system. , - [Prior Art] With the continuous advancement of the electronics industry in semiconductor technology, the product has been oriented to improve the processing speed and multi-functionalization of the 'logic processing components (such as the central processing unit) and The processing speed of love ^ is also constantly improving under this trend. However, in the computer system, in addition to the logic processing components and processing speed affects the operation of the electricity (four) system, the access speed of the memory is also affecting the operation of the computer purely. It is impossible to break through its own technical obstacles to improve its second, and 'the speed of its access is still not compatible with the CPU and memory speed, thus the overall performance of the computer line can not be effectively improved. The speed of transferring data depends on the transmission speed of the bus, in order to improve the performance of the computer. [Related operators continue to develop the interface of the Wisdom, such as the integrated driver electronics (IDE) interface, peripheral component interconnect (PCI) interface, High-speed peripheral component interconnection (PCIEXPress) connection interface, etc. In addition, in order to improve the access speed of the access device in the computer system, the prior art proposes a disk array (Redundant Array of Independent

Disks，RAID )的妓。磁辦舰將乡個次存取裝置組合 200910356 PSPD-2007-0016 24992twf.doc/n 為裝置。當存取裝置進行資料的存取時，資料會 t I夕辦分’之後_鮮行地存取於多個次存取裝置内。因此磁碟_能提供較快速的存取逮度。為了避免因為某-實體磁碟機毀損所造成的資料遺失， Π工:術更利用同位元檢查的觀念，協助必要時的資料然而，由於此種磁辦_技術必須制多個 ^因此體魏大，所以紐應祕—糾、㈣帶式電腦 …、因此’有其需要發展能夠應用於小型電腦裝置中用的磁碟陣列系統。 r便【發明内容】體積小可適用本發明提供一種快閃陣列儲存系統，其於小型電腦系統。本發明提供一種快閃陣列儲存系統，其體積小可、南於小型電腦线，可相容於主齡_整合式驅 ^Disks, RAID). The magnetic ship will combine the secondary access devices 200910356 PSPD-2007-0016 24992twf.doc/n as the device. When the access device accesses the data, the data is accessed in a plurality of secondary access devices. Therefore, Disk_ can provide faster access capture. In order to avoid the loss of data caused by the destruction of a certain physical disk drive, the completion of the work: the use of the concept of the same bit check to assist the necessary information, however, because of this magnetic _ technology must make multiple ^ so Big, so New should be secret - correct, (four) tape computer ..., so there is a need to develop a disk array system that can be used in small computer devices. r [Explanation] Small size is applicable The present invention provides a flash array storage system for a small computer system. The invention provides a flash array storage system, which is small in size and small in the south, and is compatible with the main age _ integrated drive ^

面。卞W 本發明提供一種快閃儲存晶片，其是封裝為單一曰片，因此可使整體快閃陣列儲存系統的體積縮小，= 於小型電腦线。適用本發明提供一種快閃儲存晶片，其是封襞為單一晶片，因此可使整體快閃陣列儲存系統的體積縮小，以適: 於小型電腦系統，並且可相容於主機系統的整合式辕带子介面。鄆包 200910356 PSPD-2007-0016 24992twf.doc/n # t ^提出—種快閃陣列儲存系統，其包括多個快閃，存a曰片、—快閃陣列控制器與—資料傳輪介面。快閃陣列型式排列’其中每-快閃儲存晶片包括- I;:反制器、至少一個快閃記憶體以及-高surface. The present invention provides a flash memory wafer that is packaged as a single chip, thereby reducing the overall flash array storage system size to a small computer line. The present invention provides a flash memory wafer that is packaged as a single wafer, thereby reducing the size of the overall flash array storage system to fit a small computer system and is compatible with the integrated system of the host system. Tape interface. 2009包 200910356 PSPD-2007-0016 24992twf.doc/n # t ^Proposed a flash array storage system, which includes a plurality of flashes, a chip, a flash array controller and a data transfer interface. Flash array type arrangement 'where each-flash memory chip includes -I;: counter, at least one flash memory, and - high

Explfpan^ (/!riPheral C〇m— —ect m Express)連接介面。微控制器封路板上且具有一快閃記憶體介 ^ 閃記憶體封裝在單—電路杯介面。快 H 轉接至微控制器，用以儲至微連接介面封裝在單—電路板上且輕接 •接至快閃陣列控制器，用以連接至系統主機與快閃陣列儲存系統之間傳輸指令與 =主機欲寫入資料至快閃陣列儲存^ 存，至少其中之-來== 連接入Μ P、摘存晶片的微控制11會透過PCI Express 體介二寫Express介面接收資料並且透過快閃記憶存在快閃記憶體。其中當系統主機欲讀取儲尋儲存此系、統的資料時’則快閃陣列控制器會搜存晶片的辭制哭2存晶片，並且儲存此資料的快閃儲記憶體中會透過快閃記憶體介面讀取儲存在快閃連接介面傳二ί =且透過PCI Express介面與PCI Express 在本發明之—實施例中，上述之每—快閃儲存晶片中 200910356 PSPD-2007-0016 24992twf.doc/n 至少一個快閃記憶體為一 SLC (Single Level Cell)快閃記十思體或一 MLC (Multi Level Cell)反及（NAND )快閃記憶Explfpan^ (/!riPheral C〇m— — ect m Express) connection interface. The microcontroller board has a flash memory package that is packaged in a single-circuit cup interface. Fast H is transferred to the microcontroller for storage to the micro-connector interface packaged on the single-board and lightly connected to the flash array controller for connection between the system host and the flash array storage system Command and = host wants to write data to the flash array storage, at least - the == connection into the Μ P, the micro-control 11 of the memory will be received through the PCI Express body to write the Express interface and through the fast Flash memory exists in flash memory. When the system host wants to read and store the data stored in the system, the flash array controller will search for the wafer's reciting crying memory, and the flash memory storing the data will pass through the fast memory. Flash memory interface read and store in flash connection interface and through PCI Express interface and PCI Express. In the embodiment of the present invention, each of the above-mentioned flash memory chips is 200910356 PSPD-2007-0016 24992twf. Doc/n At least one flash memory is an SLC (Single Level Cell) flash or a MLC (Multi Level Cell) and (NAND) flash memory.

在本發明之一實施例中，上述之每一快閃儲存晶片中將微控制器及快閃記憶體封裝於單一電路板上四邊扁平無接腳式（QFN)、平面陣列式（LGA)、錫球陣列式（BGA)、超薄平面型塑膠粒承載式（LQFp)、方塊形扁平縣式（QFp)、晶粒式（DIE)直接封裝式（COB)或單排腳封裝式（SIp)封裴法。隹本《明之一實施例令，上述之快閃儲存晶片與快閃車列儲存系統在傳輸資料的實體層可由至組成發送端（Tx)與接收端（Rx)。、、早、運鮮ίΓΓ提出—種快閃陣列儲存系統，其包括多個快閃 Ξΐ:二列驅動程式。快閃儲存晶片是以陣列 =:，一快閃健存晶片包括-單-電路板、- 面。微控制器封封裝在單—電路板連接" 介面、一 PrT Ρ 入板上且具有一快閃記憶體 ra Express介面與—虛擬整合式驅動電 egrated Device Electronics, IDE) IDp 具有用以接收IM指令的整mf虛擬咖拉組以執行咖指令的咖褒^式^電付面主控端與用器執行的勒體程式來實‘二由微控制上且轉接至微控制器，用以储存^體=在早—電路板面封裝在單—電路板」ΡαΕχρ峨連接介祸得至微控制器，用以連接至系 200910356 PSPD-2007-〇〇,6 24992twf.doc/n 統主機 -汧閃陣列驅動程式安裝在系統主機中丑日士^ 主機來執行咕制在快_存晶片中讀取與儲存系統 :當系統主機欲讀取儲存在快閃陣列儲存系統^ ^In one embodiment of the present invention, the flash memory and the flash memory are packaged on a single circuit board in a four-sided flat pinless (QFN), planar array (LGA), Solder ball array (BGA), ultra-thin flat plastic particle-loaded (LQFp), square flat county (QFp), grained (DIE) direct package (COB) or single-row package (SIp) Sealing method. In one embodiment of the present invention, the above-mentioned flash memory chip and flash memory array system can be used to form a transmitting end (Tx) and a receiving end (Rx) in a physical layer for transmitting data. , early, and fresh, a flash array storage system that includes multiple flash ports: a two-column driver. The flash memory chip is array =:, a flash memory chip includes - single-board, - face. The microcontroller package is packaged on a single-board connection & interface, a PrT input board and has a flash memory ra Express interface and a virtual integrated driver (Egrated Device Electronics, IDE) IDp for receiving IM The instruction of the whole mf virtual coffee group is executed by the coffee machine, the coffee machine, the electronic control unit, and the user-executed program, and is transferred from the micro controller to the microcontroller for Storage ^ body = in the early - circuit board package in a single-board" ΡαΕχρ峨 connection to the microcontroller, used to connect to the system 200910356 PSPD-2007-〇〇, 6 24992twf.doc/n host -汧阵列 Array driver is installed in the system host ugly 士 ^ host to perform the system in the fast _ memory wafer read and store system: when the system host wants to read and store in the flash array storage system ^ ^

叶’則快閃陣列驅動程式會搜尋儲存此資料的快閃曰斗片，亚且儲存此資料的快閃儲存晶片的虛擬咖=:日日收與，行系統主機所下達的IDE指令，並且此資料閃記憶體介面來讀取以及由ρα Εχρ_介面轉換^ Ο ΕΧΡ腦連接介面所能接㈣格式來傳送，射當系欲寫入貧料至快閃陣列儲存系統時，則快_列驅動程式會指派快_存晶片的至少其中之―來寫人此資料，纽所指派的快_存晶片的虛擬IDE模組會接收與執行系統主機所下達的IDE指令，並且欲寫人的資料會由ρα Express連接介面與PCI Express介面來接收且由快閃記憶體介面轉換為朗記憶體所能接㈣格絲寫人 ; 憶體。 °Leaf's flash array driver will search for the flash bucket that stores this data, and the virtual coffee of the flash storage chip that stores this data =: day-to-day receipt, the IDE command issued by the system host, and This data flash memory interface is read and transmitted by ρα Εχρ_interface conversion ^ ΕΧΡ ΕΧΡ 连接连接连接连接连接连接连接连接连接连接连接连接连接连接连接连接至至至至至至至至至至至至至至至至至至至至The driver will assign at least one of the fast_storage chips to write this data, and the virtual IDE module assigned by the button will receive and execute the IDE command issued by the system host, and the data to be written is written. It will be received by the ρα Express connection interface and the PCI Express interface and converted from the flash memory interface to the memory of the memory (4). °

在本發明之一實施例中，上述之每一快閃儲存晶片中至少一個快閃記憶體為一 SLC (Single Level Cell)或MLC (Multi Level Cell)反及（NAND)快閃記憶體。在本發明之一實施例中，上述之在每一快閃儲存晶片中將微控制器及快閃記憶體封裝於單一電路板上的方法包括四邊扁平無接腳式（QFN)、平面陣列式（LGA)、錫球陣列式（BGA)、超薄平面型塑膠粒承載式（LQFP)、方塊形扁平封裝式（QFP)、晶粒式（DIE)、晶片直接封裝式（COB)或單排腳封裝式（SIp)封裝法。 200910356 ^u-zmi-OOib 24992twf.doc/n 在本發明之-實施例中，上述之整合式驅動電子介面指令相容於ΑΤΑ規格或序列ata規格。本發明提出一種快閃儲存晶片，其包括一單一電路板、一微控制盗、至少一個快閃記憶體以及一 pciEx以ess 連接介面。微控制器封裝在單一電路板上且具有—快閃記憶體介面與一 PCI Express介面。快閃記憶體封裝在單一電路板上且耦接至微控制器，用以儲存資料。 Γ、接介面封裝在單一電路板上且耦接至微控制器。其中當系統主機欲寫入資料至快閃儲存晶片時，則微控制器會透過 PCI~ Express介面接收資料並且透過快閃記憶體介面寫入此資料至快閃記憶體。其中當系統主機欲讀取儲存在快閃儲存晶片的資料時，則微控制器會透過快閃記憶體介面讀取快閃記憶體中的資料，並且透過PCI Express介面經由 PCI Express連接介面傳送至系統主機。在本發明之一實施例中，上述之至少一個快閃記憶體為一 SLC (Single Level Cell)或 MLC (Multi Level Cell)反及〇 ( nand )快閃記憶體。在本發明之一實施例中，上述之微控制器及快閃記憶體封裝於單一電路板上的方法包括四邊扁平無接腳式 (QFN)、平面陣列式（LGA)、錫球陣列式（BGA)、超薄平面型塑膠粒承載式（LQFP)、方塊形扁平封裝式 (QFP)、晶粒式（DIE)、晶片直接封裝式（C0B)或單排腳封裝式（SIP)封裝法。在本發明之一實施例中，上述之快閃儲存晶片，其封 200910356 FSPD-2007~00it> 24992twf.doc/n 裝後的腳位至少包括PERST#、、 ΡΕΤρΟ、ΡΕΤηΟ、PERpO、PERn〇、P〇wer、Gr〇und 等腳位。本發明提出一種快閃儲存晶片，其包括一單一電路板、一微控制器、至少一個快閃記憶體以及一 pciExpress 連接介面。微控制器封封裝在單一電路板上且具有一快閃記憶體介面、一 PCI Express介面與一虛擬IDE模組，虛擬IDE模組具有用以接收ide指令的IDE主控端與用以執 (―、行1D1S扣令的IDE裝置端，虛擬IDE模組是以可由微控制器執行的韌體程式來實作。快閃記憶體封裝在單一電路板上且耦接至微控制器，用以儲存資料。PCIExpress連接介面封裝在單一電路板上且耦接至微控制器。其中當系統主機欲讀取儲存在快閃記憶體_的資料時，則系統主機所下達的IDE指令會發送至虛擬IDE模組以由虛擬Ι〇Ε模組執仃，亚且儲存在快閃記憶體中的資料會藉由快閃記憶體介面來讀取且由PCI Express介面轉換為PCI Express連接介「輯，接㈣格式⑽送至系統域。其中當純主機欲以寫入資料至快閃記憶體時’則系統主機所下達的IDE指令會發送至虛擬IDE模組以由虛擬IDE模組執行，並且欲寫入的資料會透過PCI Express介面來接收且透過快閃記憶體介面轉換為快閃記憶體所能接收的格式以寫入至快^ 憶體。、° 在本發明之-實施例中，上述之至少一個快閃記憶體 :’、、(Single Level Cell)或 MLC (Multi Level Cell)反及 (NAND )快閃記憶體。 11In an embodiment of the invention, at least one flash memory in each of the flash memory chips is an SLC (Single Level Cell) or an MLC (Multi Level Cell) inverse (NAND) flash memory. In an embodiment of the invention, the method for packaging the microcontroller and the flash memory on a single circuit board in each of the flash memory chips comprises a quad flat no-pin (QFN), planar array (LGA), solder ball array (BGA), ultra-thin planar plastic particle-loaded (LQFP), square-shaped flat package (QFP), die-type (DIE), wafer direct package (COB) or single row Foot package (SIp) package method. 200910356 ^u-zmi-OOib 24992twf.doc/n In the embodiment of the invention, the integrated drive electronic interface command described above is compatible with the ΑΤΑ specification or the sequence ata specification. The present invention provides a flash memory die that includes a single circuit board, a micro control thief, at least one flash memory, and a pciEx ess connection interface. The microcontroller is packaged on a single board and has a flash memory interface and a PCI Express interface. The flash memory is packaged on a single circuit board and coupled to a microcontroller for storing data. The interface is packaged on a single circuit board and coupled to the microcontroller. When the system host wants to write data to the flash memory chip, the microcontroller will receive the data through the PCI~Express interface and write the data to the flash memory through the flash memory interface. When the system host wants to read the data stored in the flash memory chip, the microcontroller reads the data in the flash memory through the flash memory interface, and transmits the data to the PCI Express interface through the PCI Express interface through the PCI Express interface. System host. In an embodiment of the invention, the at least one flash memory is an SLC (Single Level Cell) or an MLC (Multi Level Cell) and a nand flash memory. In an embodiment of the invention, the method for packaging the above-mentioned microcontroller and the flash memory on a single circuit board comprises a quad flat no-pin (QFN), a planar array (LGA), a solder ball array ( BGA), ultra-thin planar plastic grain-loaded (LQFP), square-shaped flat package (QFP), die-type (DIE), wafer direct package (C0B) or single-row package (SIP) package. In an embodiment of the present invention, the above-mentioned flash memory chip is sealed by 200910356 FSPD-2007~00it> 24992twf.doc/n. The installed pin includes at least PERST#, ΡΕΤρΟ, ΡΕΤηΟ, PERpO, PERn〇, P〇wer, Gr〇und and other feet. The present invention provides a flash memory die that includes a single circuit board, a microcontroller, at least one flash memory, and a pciExpress connection interface. The microcontroller package is packaged on a single circuit board and has a flash memory interface, a PCI Express interface and a virtual IDE module. The virtual IDE module has an IDE host for receiving ide commands and is used for execution ( ―, the IDE device side of the 1D1S deduction, the virtual IDE module is implemented by a firmware program executable by the microcontroller. The flash memory is packaged on a single circuit board and coupled to the microcontroller for The PCI Express connection interface is packaged on a single circuit board and coupled to the microcontroller. When the system host wants to read the data stored in the flash memory, the IDE command issued by the system host is sent to the virtual The IDE module is executed by the virtual module, and the data stored in the flash memory is read by the flash memory interface and converted from the PCI Express interface to the PCI Express interface. The (4) format (10) is sent to the system domain. When the pure host wants to write data to the flash memory, the IDE command issued by the system host is sent to the virtual IDE module for execution by the virtual IDE module, and Written It is received through the PCI Express interface and converted to a format that can be received by the flash memory through the flash memory interface to be written to the memory. In the embodiment of the present invention, at least one of the above Flash memory: ', (Single Level Cell) or MLC (Multi Level Cell) reverse (NAND) flash memory. 11

200910356 PSPD-2007-0016 24992twf.doc/n 在本發明之-實施财，上述之微㈣體封裝於單-電路板上的方法包括四ϋ (QFN)、平面陣列式（LGA)、錫球陣列式（BG接^式超涛平面型_粒承載式（LQFp)、方塊形扁平封 (QFP)、晶粒式（膽）、晶片直接封裝式（c & 排腳封裝式（SIP)封裝法。 4早在本發明之-實施财，上述之腿指令相容或序列ΑΤΑ規格。 Α 本發明提出-独_存晶片，其包括—單—電路板、一微控制器、多個快閃記憶體以及一 ραΕχρκΜ =面。微控制器封餘單―電路板上且具有—快閃記憶體介面與一 PCI Express介面。快閃記憶體封裝在單一電路板上且耦接，微控制器，用以齡fi^pciExp職連接介面封裝在單一電路板上且耦接至微控制器。其中當系統主機欲寫人㈣至，_儲存晶㈣，顺控會透過pci Express介面接”舰且透過快閃記雜介面寫入此資料至f夬憶體。其中當系統主機欲讀取儲存在快閃儲存曰曰片的資料日守，則微控制器會透過快閃記憶體介面讀取快閃記憶體中的資料’並且透過Ρα Εχρ觀介面經由ρα Express it接介面傳送至系統主機。其中該独閃記憶體的資料讀取與寫入是以一平行處理方式進行。、在本發明之一實施例中，上述之至少一個快閃記憶體為一 SLC (Single Level Cell)或 MLC (Multi Level Cell)反及 (NAND)快閃記憶體。 12 200910356 PSPD-2007-0016 24992twf.doc/n 在本發明之一實施例中，上述之微控制器及快閃記憶體封裝於單一電路板上的方法包括四邊扁平無接腳式 (QFN)、平面陣列式（LGA)、錫球陣列式（bga)、超薄平面型塑膠粒承載式（LQFP)、方塊形扁平封裝式 (QFP)、晶粒式（mE)、晶片直接封裝式（c〇B)或單排腳封裝式（SIP)封裝法。在本發明之一實施例中，上述之快閃儲存晶片，其封 r 裝後的腳位至少包括PERST#、REFCLK+、REFCLK-、 PETpO、PETnO、PERp0、pERn0、Power、Gr〇und 等腳位。在本發明之一實施例中，上述之系統主機與快閃儲存晶片在傳輸資料的實體層可由至少一組單工通道組成發送端（TX)與接收端（Rx)。在本發明之一實施例中，上述之微控制器更包括一虛擬IDE模組，虛擬IDE模組具有用以接收IDE指令的，控端與用以執行腹指令的IDE裝置端，虛擬IDE模組是以可由微控制器執行的韌體程式來實作。本發棚採用具有pci Express介面之㈣錯存晶片的快閃陣列儲存系統，因此可縮小儲存媒體的體提升資料傳輸速率。、于 >為讓本發明之上料徵和優减更日，下文舉較佳實關，她合騎圖式，作詳細說明如下。【實施方式】自快閃記憶體問世以來以低耗能非揮發性、耐震、高 13 200910356 PSPD-2007-0016 24992twf.doc/n 儲存密度等特性，在許多可# eeprom或電磁供電的記憶體^式裝置中，漸漸取代益精進，快閃記憶體的儲存密^目刖半導體技術曰的成長。因此，本發明使用快傳輪速度更是突飛猛進硬式硬碟以實現小型化的目的。°己憶體取代磁碟陣列中的 [第一實施例] 圖1是根據本發明第一會塊圖。 Μ續示快閃儲存系統的方請參照圖1，快閃陣列儲控制器102、一資料傳輸介子糸统1〇〇包括一快閃陣列 1〇6_1至106-η。〇4與多個快閃儲存晶片快閃陣列控制器1〇2是用 100中資料寫入的分配與讀取次:制在快閃陣列儲存系統閃陣列控制器1()2會將多^料的搜索。具體來說，快在邏輯上視為連續的儲存媒體，人儲存晶片106-1至勝η 示）的指令來對快閃儲存曰，亚且接收系統主機（未繪儲存與讀取。料魅機^至廳-η進行資料的器搬會指派哪幾個=寫入時’則快閃陣列控制資料’而當系統主機指令為：：：106-1至來寫入資料的快閃儲存晶片丨〇6 時，則搜索儲存欲讀取的 102 0 # 器搬是透過資料至糸統主機，並且快閃陣列控制存系_之間_==在系統主機與快閃陣列儲 14 200910356 PSPD-2007-0016 24992twf.doc/n 在本發明實施例中，在傳輪資料的實體層可由至小ι、^閃陣列錯存系統端（Tx)與接收端（Rx)。、’’且單工通道組成發送快閃儲存晶片106-丨$ g 接至快閃陣列控制器1〇2，並且:疋以陣列型式排列且輕晶片购至_具有相同的結快閃儲存閃儲存晶片106-1為例進行說明] 以下將以快圖2是繪示圖1所示伊明參恥圖2，快閃儲存晶片 = 112、一微控制器114、匕括早—電路板邮跳連接介面118。至/個快閃記憶體出與-PCi 亓株路板112是用以將快閃儲存晶片购的所有兀件封裝在一起的基板。町所有 $控制益114疋封裝在單一電路板112上。微控制器 14用以控制快閃儲存晶片1 1的整體運作。微控制器 4具有-快閃記憶體介面122與—ρα Εχρ簡介面 124。快閃記憶體介面122是用以存取快閃記憶體ιΐ6的介面。而PCI Express介面124是用以將資料轉換為ρα200910356 PSPD-2007-0016 24992twf.doc/n In the present invention, the micro-four-body package on a single-circuit board includes a four-turn (QFN), planar array (LGA), solder ball array. (BG connection type super Tao plane type granule load type (LQFp), square flat seal (QFP), grain type (bile), wafer direct package type (c & foot package (SIP) package method 4 As far as the present invention is implemented, the above-mentioned leg command compatibility or serial port specification. Α The present invention proposes a memory chip comprising a single circuit board, a microcontroller, and a plurality of flash memories. The body and a ραΕχρκΜ=face. The microcontroller has a single-board on the circuit board and has a flash memory interface and a PCI Express interface. The flash memory is packaged on a single circuit board and coupled to the microcontroller. The age-old fi^pciExp interface is packaged on a single circuit board and coupled to the microcontroller. When the system host wants to write (4) to _ storage crystal (4), the sequencer will connect to the ship through the pci Express interface. The flash memory interface writes this data to the memory system. To read the data stored in the flash memory, the microcontroller reads the data in the flash memory through the flash memory interface and transmits it via the ρα Εχρ interface through the ρα Express it interface. The data is read and written in a parallel processing manner. In an embodiment of the present invention, the at least one flash memory is an SLC (Single Level Cell). Or MLC (Multi Level Cell) reverse (NAND) flash memory. 12 200910356 PSPD-2007-0016 24992twf.doc/n In one embodiment of the invention, the above-described microcontroller and flash memory package The methods on a single board include four-sided flat pinless (QFN), planar array (LGA), solder ball array (bga), ultra-thin flat plastic particle-loaded (LQFP), square-shaped flat package (QFP), grained (mE), wafer direct package (c〇B) or single row package (SIP) package method. In one embodiment of the invention, the above flash memory chip is sealed r The installed pin includes at least PERST#, REFCLK+, REFCLK-, PETpO, PETnO, PERp0, pERn0, Power, Gr〇und, etc. In an embodiment of the present invention, the system host and the flash storage chip are at least one set of simplex in the physical layer for transmitting data. The channel constitutes a transmitting end (TX) and a receiving end (Rx). In an embodiment of the present invention, the above-mentioned microcontroller further includes a virtual IDE module, and the virtual IDE module has a control terminal for receiving the IDE command. With the IDE device side for executing the abdominal command, the virtual IDE module is implemented as a firmware program executable by the microcontroller. The flash studio uses a flash array storage system with a (ci) memory chip with a pci Express interface, thereby reducing the volume of the storage medium and increasing the data transfer rate. In order to make the above-mentioned materials and advantages of the present invention more effective, the following is a better example. [Embodiment] Since the advent of flash memory, low energy consumption, non-volatile, shock-resistant, high 13 200910356 PSPD-2007-0016 24992twf.doc/n storage density and other characteristics, in many eeprom or electromagnetically powered memory In the ^-type device, it gradually replaced Yi Jingjin, and the storage of flash memory was the growth of semiconductor technology. Therefore, the present invention uses the fast-transmitting wheel speed to advance the hard disk hard disk for miniaturization. [First Embodiment] Replacing a Disk Array [First Embodiment] Fig. 1 is a first block diagram according to the present invention. Referring to FIG. 1, the flash array storage controller 102 and a data transmission meson system 1A include a flash array 1〇6_1 to 106-η. 〇4 and multiple flash storage chip flash array controllers 1〇2 are allocated and read times with 100 data writes: the flash array controller 1()2 in the flash array storage system will be more ^ Search for materials. Specifically, it is logically regarded as a continuous storage medium, and the person stores the instructions of the chip 106-1 to the flash memory to store the flash memory, and the receiving system host (unpainted and read. Machine ^ to hall - η data transfer will assign which number = when writing 'flash array control data' and when the system host command is ::: 106-1 to write data flash memory chip丨〇6, the search storage to read the 102 0 # device is transmitted through the data to the system host, and the flash array control system _ between _== in the system host and flash array storage 14 200910356 PSPD- 2007-0016 24992twf.doc/n In the embodiment of the present invention, the physical layer of the transmission data may be from the system (Tx) and the receiving end (Rx) of the system, and the simplex. The channel component transmits a flash memory chip 106-丨$g to the flash array controller 1〇2, and: 疋 is arranged in an array pattern and the light wafer is purchased to have the same junction flash memory flash memory chip 106-1. Example for explanation] The following will be a quick diagram 2 showing the Yiming ginseng diagram of FIG. = 112, a microcontroller 114, 匕早 early - board mail jump interface 118. / / flash memory and - PCi 路 road board 112 is used to purchase all components of the flash memory chip The substrates are packaged together. The town control unit 114 is packaged on a single circuit board 112. The microcontroller 14 is used to control the overall operation of the flash memory chip 11. The microcontroller 4 has a flash memory interface 122. And ρα Εχρ introduction surface 124. The flash memory interface 122 is used to access the interface of the flash memory ιΐ6, and the PCI Express interface 124 is used to convert the data into ρα

Express連接介面1 i 8所能接受的格式，以透過犯帥咖連接介面118來傳輸。此外，微控制器1M還包括快閃管理模組126，其用以執行快閃記憶體區塊管理、資料錯誤扠正（error correcting )、電源管理等功能。快閃記憶體區塊官理功能例如是執行平均磨損（wear leveling)、壞區塊管理、維護對映表（mapping table)等。在本發明實施例 15 200910356 PSPD-2007-0016 24992twf.d〇c/n 中，將微控制器114封裝於單一電路板112上的方法邊扁平無接腳式（QFN)。但必須瞭解的是，本發明亦= 使用平面陣列式（LGA)、錫球陣列式（BGA)、超面型塑膠粒承載S(LQFP)、方塊形扁平封裝式（QfH 晶粒式（DIE)、晶片直接封裝式（c〇B)或單排式（SIP)等封裝法。丁衮快閃記憶體116亦是封裝在單一電路板1丨2上，並耦接至微控制器114。快閃記憶體H6用以儲存主機系統欲寫入的資料。在本實施例中，快閃記憶體116是一 slc (Single Level Cell)反及（NAND)快閃記憶體。但必須瞭解的是在本發明另一實施例中，快閃記憶體116可以是 MLC (Multi Level Cell)反及（NAND)快閃記憶體。另外，在本發明實施例中，將快閃記憶體116封裝於單一電路板 112的方法為四邊扁平無接腳式（QFN)。但必須瞭解的是，本發明亦可使用平面陣列s(LGA)、錫球陣列式 (BGA)、超薄平面型塑膠粒承載式（LQFp)、方塊形扁平封裝式（QFP)、晶粒式（DIE)、晶片直接封裝式（c〇B) 或單排腳封裝式（SIP)等封裝法。 PCI Express連接介面118亦是封裝在單一電路板112 上並且輕接至微控制114’其用以傳輸資料。具體來說，快閃儲存晶片106-1會依據PCI Express連接介面118的規格（如圖5所示）至少包括PERST#、REFCLK+、R£rcLK：_、 PETpO、PETnO、PERP〇、PERnO、Power、Ground 等腳位。在本實施例中’當系統主機欲寫入資料至快閃陣列儲 16The format that the Express connection interface 1 i 8 can accept is transmitted through the connection interface 118. In addition, the microcontroller 1M further includes a flash management module 126 for performing functions such as flash memory block management, data error correcting, and power management. The flash memory block function is, for example, performing wear leveling, bad block management, maintenance mapping table, and the like. In the embodiment of the invention 15 200910356 PSPD-2007-0016 24992twf.d〇c/n, the method of packaging the microcontroller 114 on a single circuit board 112 is flat and pin-free (QFN). However, it must be understood that the present invention also uses a planar array type (LGA), a solder ball array type (BGA), a super-face type plastic particle-bearing S (LQFP), and a square-shaped flat package type (QfH grain type (DIE)). The package method is a direct package (c〇B) or a single row (SIP). The Ding flash memory 116 is also packaged on a single circuit board 1丨2 and coupled to the microcontroller 114. The flash memory H6 is used to store the data to be written by the host system. In this embodiment, the flash memory 116 is a slc (Single Level Cell) and (NAND) flash memory, but it must be understood that In another embodiment of the present invention, the flash memory 116 may be an MLC (Multi Level Cell) reverse (NAND) flash memory. In addition, in the embodiment of the present invention, the flash memory 116 is packaged in a single circuit. The method of the board 112 is a four-sided flat pinless type (QFN), but it must be understood that the present invention can also use a planar array s (LGA), a solder ball array (BGA), an ultra-thin planar plastic particle-loaded type ( LQFp), square flat package (QFP), die (DIE), wafer direct package (c〇B) or A package method such as a pin-in package (SIP). The PCI Express connection interface 118 is also packaged on a single circuit board 112 and is connected to the micro-control 114' for transmitting data. Specifically, the flash memory chip 106-1 According to the specification of the PCI Express connection interface 118 (as shown in FIG. 5), at least the PERST#, REFCLK+, R£rcLK:_, PETpO, PETnO, PERP〇, PERnO, Power, Ground, and the like are included. In this embodiment, 'When the system host wants to write data to the flash array storage 16

200910356 PSPD-2007-0016 24992twf.doc/n f系統100時，則快閃陣列控制器102會接收系統主機的指令丄並謂所寫人的㈣分割為多個部分，並且平均分配傳运至少-個快閃餚存晶片廳]至1G6_n。而接收到此分割資料的快閃儲存晶片觸]至lG6-n的微控制器114 會透過PCI Express連接介面118與ρα Εχρ·介面124 接收資料並且透過'_記憶體介面122儲存至快閃記憶體 116。 /在本實施例中，系統主機欲讀取儲存在快閃陣列儲存系統100的資料時，則快閃陣列控制器1〇2會依照系統主機的指令搜尋其欲讀取的資料，並且儲存此資料的至少一個快閃儲存晶片106_1至1〇6-n的微控制器114會透過快閃記憶體介面122讀取儲存在快閃記憶體116中的此資料’並且透過PCI Express介面124轉換與pCI Express連接”面118傳送此資料。也就是說’透過pCI Express連接介面接收的資料會透過快閃記憶體介面轉換為快閃記憶體所接雙的格式，而從快閃記憶體讀取的資料會透過pc】 Express介面轉換為PCI Express連接介面所接受的格式。在本發明實施例中’快閃儲存晶片106-1至i〇6-n是封裝為單一晶片’因此可使整體快閃陣列儲存系統100的體積縮小，以適用於小型電腦系統。再者，在本實施例中，快閃儲存晶片106-1至106-n的對外傳輸介面是使用高速 PCI Express介面，其傳輸速率於1 Lane單通道(PCIe xl) 時尚達250MB/S。基此’在本實施例中，可有效提升陣列儲存系統的資料傳輸速度。 17 200910356 PSFD-2UU/-UU16 24992twf.doc/n [弟二實施例] 圖3是根據本發明第二實施例繪示快閃陣列儲存系統的方塊圖。請參照圖3，快閃陣列儲存系統300包括—快閃陣列驅動程式302與多個快閃儲存晶片306-1至3〇6-n。快閃陣列驅動程式302是由系統主機來執行，並且用以控制在快閃陣列儲存系統3 00中資料寫入的分配與讀取資料的搜索。具體來說，快閃陣列驅動程式3〇2會^ =個快閃儲存晶片306-1至306-n在邏輯上視為連續的儲存媒體，並且接收系統主機（未繪示）的指令來對快閃儲存曰至306-n進行資料的儲存與讀取。當系統主機;; 時，則快閃陣列驅動程式搬會指派哪幾個遍]至3G6_n來寫人資料，而當系統主機指令至ΪΓ。’則搜索儲存欲讀取的資料的快_存晶片306-ι 接至晶片306-1至30“是以陣列型式排列且耦接至糸社機，並制·存料〗且耦至具有相同的結構，因此广二，存晶片_ 為例進行說明。下將讀閃儲存晶片圖4是繪示圖3所示快閃儲存晶請參照圖4’快閃儲存晶片：二：=。 312、—微控制器314、至少—個 ^早—電路板200910356 PSPD-2007-0016 24992twf.doc/nf system 100, then the flash array controller 102 will receive the command of the system host and divide the written person into four parts, and distribute the distribution at least one Flash food store in the wafer hall] to 1G6_n. The flash memory chip 114 that receives the split data touches the lG6-n and receives the data through the PCI Express connection interface 118 and the ρα Εχρ interface 124 and stores it to the flash memory through the '_memory interface 122. Body 116. In this embodiment, when the system host wants to read the data stored in the flash array storage system 100, the flash array controller 1〇2 searches for the data to be read according to the instruction of the system host, and stores the data. The at least one flash memory chip 106_1 to 1〇6-n of the data store 114 reads the data stored in the flash memory 116 through the flash memory interface 122 and converts it through the PCI Express interface 124. The pCI Express connection side 118 transmits this data. That is to say, the data received through the pCI Express connection interface is converted to the format of the flash memory by the flash memory interface, and is read from the flash memory. The data is converted to the format accepted by the PCI Express connection interface through the pc] Express interface. In the embodiment of the present invention, the 'flash memory chips 106-1 to i〇6-n are packaged as a single chip' so that the overall flash can be made The array storage system 100 is reduced in size for use in a small computer system. Further, in this embodiment, the external transfer interface of the flash storage chips 106-1 to 106-n uses a high speed PCI Express interface. Its transmission rate is 1MB single channel (PCIe xl) fashion up to 250MB / S. Based on this, in this embodiment, the data transmission speed of the array storage system can be effectively improved. 17 200910356 PSFD-2UU/-UU16 24992twf.doc /n [Different Embodiments] Figure 3 is a block diagram showing a flash array storage system according to a second embodiment of the present invention. Referring to Figure 3, the flash array storage system 300 includes a flash array driver 302 and more. Flash flash memory chips 306-1 to 3〇6-n. The flash array driver 302 is executed by the system host and is used to control the allocation and reading of data in the flash array storage system 300. Specifically, the flash array driver 3〇2 will be a flash storage chip 306-1 to 306-n logically regarded as a continuous storage medium and received by the system host (not shown). The instruction is to store and read the data to the flash storage port 306-n. When the system host;;, then the flash array driver moves to specify which times] to 3G6_n to write the person data, and when the system Host command to ΪΓ. 'Search for the data to be read The fast_storage wafer 306-ι is connected to the wafers 306-1 to 30" "arranged in an array pattern and coupled to the 糸机 machine, and is stored and stored" and coupled to have the same structure, so the DRAM is stored. Give an example for explanation. FIG. 4 is a view showing the flash memory crystal shown in FIG. 3. Referring to FIG. 4' flash memory wafer: 2:=. 312, - microcontroller 314, at least - early ^ circuit board

Express連接介面318。、。己丨思體316與一Pci 早-電路板312是用以將快閃儲存晶片 306-1 的所有 18 200910356 PSPD-2007-0016 24992twf.doc/n 元件封裝在一起的基板。微控制器314是封裝在單一電路板312上。微控制器 314用以控制快閃儲存晶片3064的整體運作。微控制器 314具有决閃5己思體介面322、一 PCI Express介面324 與一虛擬IDE模組326。快閃記憶體介面322是用以存取快閃記憶體316的介面。而PCIExpress介面324是用以將資料轉換為PCI Express連接介面318所能接受的格式，以透過PCI Express連接介面318來傳輪。虛擬IDE模組326 具有用以接收IDE指令的一 ide主控端326a與用以執行 IDE私γ的一 Π)Ε裝置端326b。在本發明中，虛擬IDe 模組326是以可由微控制器314執行的韌體程式來實作。此外，微控制器314還包括快閃管理模組328，其用以行快閃記憶體區塊管S (例>執行+均磨損 l:velmg)、壞區塊管理、維護對映表(m—ingtabie))、貧料錯誤校正（error CGrrecting)、電源管理等功能。在本發明實施例中，將微控制器314封裝於單一板312上的方法為四邊扇平無接腳式（qfn)。但解的是本發明亦可制平面_式（LGA)、錫球7 (崎）、超薄平面型歸粒承载式（LQFp)、方塊^ 3，_)'_式咖）、晶片直接封裝式（咖) 或早排腳封裝式（SIP)等封裝法。 ) 快閃記㈣控制器3M。快閃記憶體316用以儲存主機*** 奴儲存的貧料。在本實施中，快閃記憶體316是一处 19 200910356 PSPD-2007-UUi6 24992twf.doc/n (Single Level Cell)反及（NAND)快閃記憶體。但必須瞭解的是在本發明另一實施例中，快閃記憶體316可以是 MLC (Multi Level Cell)反及（NAND)快閃記憶體。另外，在本發明實施例中，將快閃記憶體316封裝於單一電路板 312的方法為四邊扁平無接腳式（qfn)。但必須瞭解的是本發明亦可使用平面陣列式（LGA)、錫球陣列式 (BGA)、超薄平面型塑膠粒承載式（LQFP)、方塊形扁平封裝式（QFP)、晶粒式（Dffi)、晶片直接封裝式（C〇B) 或單排腳封裝式（SIP)等封裝法。 PCI Express連接介面318亦是封裝在單一電路板312 上並且耦接至微控制器314,其用以傳輸資料。具體來說，快閃儲存晶片306-1會依據PCI Express連接介面318的規格（如圖5所示）至少包括PERST#、REFCLK+、REFCLK-、 PETpO、PETnO、PERpO、PERnO、Power、Ground 等腳位。在本實施例中，當將快閃陣列儲存系統3〇0運作時，系統主機會執行快閃陣列驅動程式3〇2,並且微控制器314 6 σ知糸統主機快閃儲存晶片306-1至306-n為IDE儲存裝置。基此，當系統主機欲讀取儲存在快閃陣列儲存系統 300申的資料時，則快閃陣列驅動程式3〇2會依照系統主機的讀取指令，例如IDE指令，搜尋其欲讀取的資料，並且將此IDE指令傳送至儲存此資料的至少一個快閃儲存晶片306-1至306_n。之後’儲存此資料的快閃儲存晶片3064 至306-n的虛擬IDE模組326會執行此IDE指令，而儲存 20 200910356 PSPD-2007-ϋϋ 16 24992twf. doc/n 此資料的快閃儲存晶片306-1至306-n的微控制器314會依此指令透過快閃記憶體介面322讀取在快閃記憶體316 中欲讀取的資料，並且儲存在快閃記憶體316中的資料會由PCI Express介面324轉換為PCI Express連接介面318 所能接收的格式來傳送至系統主機。此外’當系統主機欲寫入資料至快閃陣列儲存系統 3〇〇時，則快閃陣列驅動程式302會接收到系統主機的寫 f 入指令，例如1〇£指令，並且將所寫入的資料分割為多個部分，並且將分割的資料與IDE指令一起傳送給至少一個快閃儲存晶片306-1至306-n。之後，接收到指令與資料的快閃儲存晶片306-1至306-n的虛擬Π)Ε模組326會執行此IDE指令’並且欲寫入的資料會由快閃記憶體介面η〗轉換為快閃記憶體316所能接收的格式來寫入至快閃記憶體 316。在本發明實施例中’例如，IDE指令相容於ΑΤΑ規格。、、 I- 在本發明另一實施例中，IDE指令例如相容於序列 ΑΤΑ規格。在本實施例中，快閃儲存晶片306-1至306-n是封裝為單一晶片，因此可使整體快閃陣列儲存系統3〇〇的體積縮小’以適用於小型電腦系統。此外，在本實施例中，快閃儲存晶片306-1至306-n的對外傳輪介面是使用ρα Express介面，其傳輸速率於1 Lane單通道(pcie xl)時高達250MB/S。基此，在本實施例中，可有效提升陣列儲存 21 200910356 PSPD-2007-U016 24992twf.doc/n 系統的資料傳輸速度。特別是，在本實施例中，微控制哭具有虛擬IDE介面模組，因此可使系統主機存取資料時可達到PCI Express介面的速度，同時亦擁用有相容於的特性。基此，可不改變主機系統的環境介面下，使用pd Express介面傳輸資料。 (Express connection interface 318. ,. The 316 and PCI early-circuit boards 312 are substrates used to package all of the 18 200910356 PSPD-2007-0016 24992 twf.doc/n components of the flash memory die 306-1. Microcontroller 314 is packaged on a single circuit board 312. Microcontroller 314 is used to control the overall operation of flash memory die 3064. The microcontroller 314 has a flashback interface 322, a PCI Express interface 324 and a virtual IDE module 326. The flash memory interface 322 is an interface for accessing the flash memory 316. The PCI Express interface 324 is used to convert data into a format acceptable to the PCI Express interface 318 for transport through the PCI Express interface 318. The virtual IDE module 326 has an ide master 326a for receiving IDE commands and a device 326b for executing IDE gamma. In the present invention, virtual IDe module 326 is implemented as a firmware program executable by microcontroller 314. In addition, the microcontroller 314 further includes a flash management module 328 for flashing the memory block pipe S (for example, performing + both wear l: velmg), bad block management, and maintaining the mapping table ( M—ingtabie)), error CGrrecting, power management and other functions. In the embodiment of the present invention, the method of packaging the microcontroller 314 on the single board 312 is a four-sided fanless pinless type (qfn). However, the solution is that the invention can also be used to produce a planar type (LGA), a solder ball 7 (saki), an ultra-thin planar type of granulated load-bearing type (LQFp), a square ^ 3, _) '-type coffee, and a direct wafer package. Encapsulation methods such as (coffee) or early-package (SIP). ) Flash (4) Controller 3M. The flash memory 316 is used to store the poor materials stored in the host system slave. In the present embodiment, the flash memory 316 is a 19 200910356 PSPD-2007-UUi6 24992twf.doc/n (Single Level Cell) reverse (NAND) flash memory. However, it must be understood that in another embodiment of the present invention, the flash memory 316 may be an MLC (Multi Level Cell) reverse (NAND) flash memory. In addition, in the embodiment of the present invention, the method of packaging the flash memory 316 on the single circuit board 312 is a four-sided flat pinless type (qfn). However, it must be understood that the present invention can also use a planar array (LGA), a solder ball array (BGA), an ultra-thin planar plastic particle-loaded (LQFP), a square-shaped flat package (QFP), a grain type ( Dffi), wafer direct package (C〇B) or single row package (SIP) and other packaging methods. The PCI Express interface 318 is also packaged on a single circuit board 312 and coupled to a microcontroller 314 for transmitting data. Specifically, the flash memory chip 306-1 may include at least the PERST#, REFCLK+, REFCLK-, PETpO, PETnO, PERpO, PERnO, Power, Ground, etc. according to the specifications of the PCI Express connection interface 318 (as shown in FIG. 5). Bit. In this embodiment, when the flash array storage system 3 〇 0 is operated, the system host executes the flash array driver 3 〇 2, and the microcontroller 314 6 糸 knows the 主机 host flash storage chip 306-1 To 306-n is an IDE storage device. Therefore, when the system host wants to read the data stored in the flash array storage system 300, the flash array driver 3〇2 searches for the information to be read according to the system host's read command, such as an IDE command. The data is transmitted to the at least one flash storage chip 306-1 to 306_n storing the material. The virtual IDE module 326 of the flash memory chips 3064 to 306-n storing the data will then execute the IDE command and store 20 200910356 PSPD-2007-ϋϋ 16 24992twf. doc/n the flash memory chip 306 of this material. The microcontroller 314 of -1 to 306-n reads the data to be read in the flash memory 316 through the flash memory interface 322 according to the instruction, and the data stored in the flash memory 316 is The PCI Express interface 324 is converted to the format that the PCI Express interface 318 can receive for transmission to the system host. In addition, when the system host wants to write data to the flash array storage system 3, the flash array driver 302 receives the write command of the system host, for example, a command, and will write the The data is divided into a plurality of sections and the segmented material is transmitted with the IDE instructions to at least one of the flash storage wafers 306-1 through 306-n. Thereafter, the virtual flash memory of the flash memory chips 306-1 to 306-n that receives the command and data will execute the IDE command 'and the data to be written will be converted from the flash memory interface η to The format that the flash memory 316 can receive is written to the flash memory 316. In the embodiment of the present invention, for example, the IDE instruction is compatible with the ΑΤΑ specification. I, In another embodiment of the invention, the IDE instructions are, for example, compatible with the sequence specification. In the present embodiment, the flash memory wafers 306-1 through 306-n are packaged as a single wafer, thereby reducing the overall flash array storage system 3' size for use in small computer systems. Further, in the present embodiment, the external transfer interface of the flash memory chips 306-1 to 306-n uses the ρα Express interface, and the transfer rate is as high as 250 MB/s at 1 Lane single channel (pcie xl). Therefore, in this embodiment, the data transmission speed of the array storage 21 200910356 PSPD-2007-U016 24992twf.doc/n system can be effectively improved. In particular, in this embodiment, the micro-control cry has a virtual IDE interface module, so that the system host can access the data to achieve the PCI Express interface speed, and also has compatible features. Based on this, the data can be transmitted using the pd Express interface without changing the environment of the host system. (

值得-提的是，當本發明第一與第二實施例中所使用的快閃儲存晶片是由多個快閃記憶體來封裝時，此些記憶體可以平行方式電性連接至微控繼（如圖6所示、 =是J據本發㈣—實_料朗料晶片的詳 Ϊ，在:不圖6，由於圖6的組件是相同於圖2所 106-1，具有兩個快閃同的是’快閃儲存晶片體116a與ll6b是以平y二，、116b。並且，快閃記憶由此’透過平行處裡方式可微控制器m ’ 亦可應用於圖4中。速貧料的傳輸。類似的概念在本發明上述實施中雖的快閃陣列儲存系統來實了疋以/、有夕個快閃儲存晶片本發明所述之快閃儲存晶然而，必須瞭解的是，由於此快閃儲存晶片亦可單^ 曰具有完整的儲存裝置架構，因閃儲存晶片可直接镶私在為装·置的儲存設備。例如，快備，例如取代硬碟機以I，機板上，作為電腦的儲存設晶片也可應用於嵌入式系電鵰的體積。或者，快閃儲存衛星定位系統、機上各d 例如手機、個人數位助理、由此可得此類裝置更為_eH〇P-B〇x)或嵌入式伺服器等’ …至、薄輿小巧。 22 200910356 PSPD-2007-0016 24992twf, doc/n 使整體快辦顺㈣統的體_小，^翻於小此外，快閃儲存晶片的對外傳輪介面是使用高邊邊組件互連介面，可有效提升_儲存系統的資料傳= ，。再者，本發明亦具有虛擬整合式縣好介面模电，、因此可I魏主機存取㈣時可達料互遠人面的速度，同時亦制有整合式驅動電子介面的雖然本發明已以較佳實施例揭露如上，铁豆限定本發明’任何所屬技術職巾具有知縣 = 脫離本發明之精神和範圍内，當可作些許之更不 =本發明之賴制當視後社申請專利範_界定者【圖式簡單說明】It is worth mentioning that when the flash memory chips used in the first and second embodiments of the present invention are packaged by a plurality of flash memories, the memories can be electrically connected to the micro-control in a parallel manner. (As shown in Figure 6, = is J according to the hair (four) - the actual material of the material of the wafer, in: not Figure 6, because the components of Figure 6 is the same as the 106-1 of Figure 2, with two fast The same is true that the 'flash memory cell bodies 116a and ll6b are flat y ii, 116b. Moreover, the flash memory can be applied to the micro-controller m ' in a parallel manner. FIG. 4 can also be applied. Transmission of poor materials. A similar concept in the above-described implementation of the present invention, although the flash array storage system is implemented as a flash memory chip of the present invention, however, it must be understood that Since the flash memory chip can also have a complete storage device architecture, the flash memory chip can be directly embedded in the storage device for loading and unloading. For example, fast standby, for example, replacing the hard disk drive with I, the machine On the board, the storage chip as a computer can also be applied to the volume of the embedded electric carving. Quick flash storage Satellite positioning system, on-board d such as mobile phones, personal digital assistants, and thus such devices are more _eH〇P-B〇x) or embedded servers, etc., to be thin and compact. 22 200910356 PSPD-2007-0016 24992twf, doc/n makes the overall fast-running (four) system body _ small, ^ turn small in addition, the flash memory chip's external transfer interface is using the high-edge component interconnection interface, Effectively improve the data transfer of the storage system = , . Furthermore, the present invention also has a virtual integrated county interface mode power, so that the access speed of the device can be reached when the host access is (4), and the integrated drive electronic interface is also provided. The invention is disclosed in the preferred embodiment as described above, and the present invention is in accordance with the invention. Any technical job towel having the knowledge of the present invention is within the spirit and scope of the present invention, and when it is possible to make a little more than the present invention, the invention is patented. Fan_Definator [Simple description]

L 的方^是根據本發明第—實施滑示快_存陣列系統圖2是繪示圖！所示快閃儲存晶片的詳細的方Z是根據本發㈣二實施_邱_附特系統圖4是繪示圖3所示快閃儲存晶#的詳細圖5是繪示PCI Express的腳位標準規柊回細方=是根據本發明另一實施例緣示快閃儲存晶片的詳 23 200910356 PSPD-2007-0016 24992twf.doc/n 【主要元件符號說明】 100 :快閃陣列儲存系統 102 :快閃陣列控制器 104 :資料傳輸介面 106-1、106-2、106-3、106-n :快閃儲存晶片 112 :單一電路板 114 :微控制器 f 116、116a、116b :快閃記憶體 118 : PCI Express 連接介面 122 :快閃記憶體介面 124 : PCI Express 介面 126 :快閃管理模組 300 :快閃陣列儲存系統 302 :快閃陣列驅動程式 306-1、306-2、306-3、306-n :快閃儲存晶片 312 :單一電路板 Ο 314:微控制器 316 :快閃記憶體 318 : PCI Express 連接介面 322 :快閃記憶體介面 324 : PCI Express 介面 326 : IDE 模組 326a : IDE主控端 326b : IDE裝置端 328 :快閃管理模組 24The square of L is the first embodiment of the invention according to the present invention. Figure 2 is a diagram! The detailed square Z of the flash memory storage chip is implemented according to the present invention. The system is shown in detail in FIG. 3. FIG. 4 is a detailed view of the flash memory crystal shown in FIG. 3. FIG. 5 is a diagram showing the PCI Express pin. The standard specification is a detailed description of the flash memory chip according to another embodiment of the present invention. 200910356 PSPD-2007-0016 24992twf.doc/n [Main component symbol description] 100: Flash array storage system 102: Flash Array Controller 104: Data Transfer Interface 106-1, 106-2, 106-3, 106-n: Flash Storage Chip 112: Single Board 114: Microcontroller f 116, 116a, 116b: Flash Memory Body 118: PCI Express Connection Interface 122: Flash Memory Interface 124: PCI Express Interface 126: Flash Management Module 300: Flash Array Storage System 302: Flash Array Drivers 306-1, 306-2, 306- 3, 306-n: flash memory chip 312: single board Ο 314: microcontroller 316: flash memory 318: PCI Express connection interface 322: flash memory interface 324: PCI Express interface 326: IDE module 326a: IDE host 326b: IDE device 328: flash management module 24

Claims

200910356 PSPD-2007-00I6 24992twf.d〇c/n 申請專利範圍： 1.一種快閃陣列儲存系統，包括：每一快閃儲存晶片包括多個快閃儲存晶蹲列型式排列單一電路板；一微控制器，封裝在該單— =憶體介面與-高速周邊組件互連輕_微控制器’：儲電路板上且且耗接接介面，封農在該單—電路板上一快閃陣列控制器，耦接至該此制在該些快閃儲存晶片中讀取與儲;資接至二面，耦接至該快閃陣列控制器，用以連之間傳該系統主機與該快閃陣列齡*** 快並且透過該快閃記憶體介面寫入該資料至該其中當該$齡機欲讀賴存在雜閃_儲存*** 25 200910356 PSJeD-2UU/-UUl〇 24992twf.doc/n 的資料時’則該快閃陣列控制器會搜尋儲存該#料的快閃儲存晶片，並且儲存該資料的快閃儲存晶片的微控制器會透過該快閃記憶體介面讀取儲存在該快閃記憶體中的^ 料，並且透過該PCI Express介面與該pci Express連接介面傳送該資料。 2. 如申請專利範圍第1項所述之快閃陣列儲存系統，其中在每一快閃儲存晶片中該至少—個快閃記憶體為一 SLC (Single Level Cell)或 MLC (Multi Level Cell)反及 (NAND )快閃記憶體。 3. =申請專利範圍第丨項所述之快閃陣列儲存系統，其中在每一快閃儲存晶片中將該微控制器及該至少一個快閃記憶體封裝於該單—電路板上的方法包括四邊扁平無接腳式（QFN)、平面陣列式（LGA)、錫球陣列式（BGA)、超薄平面型塑膠粒承載式（LQFP)、方塊形爲平封裝式 (QFP)、晶粒式（DIE)、晶片直接封裝式（COB)或單排腳封裝式（SIP)封裝法。 4. 如申請專利範圍第1項所述之快閃陣列儲存系統， 2中該快閃陣列控制器與該些快閃儲存晶片在傳輸資料的實體層可由至少—組單工通道組成發送端（Tx)與接收端 (Rx)。 5. —種快閃陣列儲存系統，包括：多個快閃儲存晶片，以陣列型式排列，每一快閃儲存晶片包括：一單一電路板； 26 200910356 PSFU-200/-0Ult, 24992twf.doc/n —微控制器，封裝在該單一電路板上且1 =記憶體介面…PCIE啊SS介面與—虛擬整= 接收一聊指令的一咖主控端與用以執行 2令的-IDE裝置端’誠擬咖模岐控制器執行的韌體程式來實作；田5茨微至少一個快閃記憶體，封裝在該單— 耦接至該微控制器，用以儲存資料；以及一 PCI Express連接介面，封裝在該且輕接至該微控制器，用以連接至―系統^路= /一㈣陣列驅動程式’安裝在該系統 = :域來執行以控制在該些快閃儲存晶以讀取Si 其巾t㈣、、齡機欲讀取儲存在紐統中的資料時，則該快閃陣列驅動的快閃儲存晶片，並且儲存該資料^ 科 IDE模組會接收盥執行嗲系、]儲存昍片的虛擬並且該㈣會由令， PCI EXp介面轉換為該些p 由忒些收的格式來料， press連接；1面所能接绵系統主機欲寫入資料至該快閃陣列儲存季至，其==派該些快“= 的虛擬IDE模組會接收^ 指=的块閃錯存晶片、執仃該系統主機所下達的該IDE 27 200910356 PSPD-20U7-0016 24992twf.d〇c/n 指令’並且欲寫入的該資料會由該PCI Express連接介面與該PCI Express介面來接收且由該些快閃記憶體介面轉換為該些快閃記憶體所能接收的格式來寫入至該些快閃記憶體。 6. 如申請專利範圍第5項所述之快閃陣列儲存系統，其中在每一快閃儲存晶片中該至少一個快閃記憶體為一 SLC (Single Level Cell)或 MLC (Multi Level Cell)反及 (NAND)快閃記憶體。 7. 如申睛專利範圍第5項所述之快閃陣列儲存系統，其中在每一快閃儲存晶片中將該微控制器及該至少一個快閃記憶體封裝於該單一電路板上的方法包括四邊扁平無接腳式（QFN)、平面陣列式（lga)、錫球陣列式（BGA)、超薄平面型塑膠粒承載式（LQFP)、方塊形扁平封裝式 (QFP)、晶粒式（DIE)、晶片直接封裝式（c〇B)或單排腳封裝式（SIP )封裝法。 8. 如申凊專利範圍第5項所述之快閃陣列儲存系統，其中該IDE指令相容於ΑΤΑ規格或序列ATA規格。 9. 一種快閃儲存晶片，包括：一單一電路板； -微控制H ’封裝在該單—電路板上且具有—快閃記憶體介面與一 PCI Express介面；至少-個快閃記憶體，封裝在該單一電路板上且· 至該微控制器，用以儲存資料；以及一 PCI Express連接介面，封裝在該單一電路板上且 28 200910356 ^ί>^ΐ-)-2υυ/-υυιο 24992twf.d〇c/n 耦接至該微控制器主機，用以將該快_存晶^接至一系殊其中當該系統主機欲寫入資料至該快閃時’則該微控制器會透過該PCI Express介面接收 ^ 且透過該快閃記憶齡©寫人該資料至該快閃記^體Ί 其中當該系統主機欲讀取儲存在該快閃儲資料時，則該微㈣器會透過該㈣記憶體介面閃記憶體中的資料，並且透過該PCI Εχρ峨介^由= Express連接介面傳送至該系統主機。 1 10. 如申請專利範圍第9項所述之快閃儲存晶片，該至少一個快閃記憶體為一SLC (Single Uvd ^ MLC (Multi Level Cell)反及（NAND )快閃記憶體。或 11. 如申請專利範圍第9項所述之快閃儲存晶片，其將該微控制器及該至少一個快閃記憶體封裝於該單一電略板上的方法包括四邊扁平無接腳式（QFN)、平面陣列 (LGA)、錫球陣列式（BGA)、超薄平面型塑膠粒承^ C 式（LQFP)、方塊开>爲平封裝式（QFP)、晶粒式（die)、晶片直接封裝式（COB)或單排腳封裝式（SIp)封裝法。 12.如申睛專利範圍第π項所述之快閃儲存晶片，其封裝後的腳位至少包括PERST#、REFCUC+、RJErcUC_、 PETpO、PETnO、PERpO、PERnO、Power、Ground 等腳位。 13·—種快閃儲存晶片，包括：一單一電路板；一微控制器，封裝在該單一電路板上且具有一快閃記 29 200910356 Fi>FU-2UU/-uui6 24992twf.doc/n 憶體介面、-PCI EXpress介面與—虛擬咖擬腿模組具有用以接收-咖指令的一舰控= 以執行該！_令的-IDE裝置端，該虛擬ide= = 可由該微控制斋執行的韌體程式來實作；個快閃記憶體，封裝在該單—電路板上且輕接至該微控制器，用以儲存資料；以及一 PC〗 Express連接介面，封裝在該單一電路板上且輕接至該微控制m將該㈣儲存晶片域至該系統主機， —其中當該纟統主機欲讀取儲存在難閃記憶體中的資料時，則該系統主機所下達的該IDE指令會發送至該虛擬腿模組以由該虛擬咖模組執行，並且儲〖在該= 記憶體中的資料會藉由織閃記憶體介面來讀取且由該 PCI Express介面轉換為該PCI Εχρ職連接介面所能接= 的格式以傳送至該系統主機，其中當該系統主機欲寫入資料至該快閃記憶體時，則該系統主機所下達的該IDE指令會發送至該虛擬舰模組以由該虛擬IDE模組執行，並且欲寫入的該資料會透過該 PCI Express介面來接收且透過該快閃記憶體介面轉換為該快閃記憶體所能接收的格式以寫入至該快閃記憶體。 14. 如申請專利範圍第丨3項所述之快閃儲存晶片，其中該至少一個快閃記憶體為一 SLC (single Levd Cdl)或 MLC (Multi Level Cell)反及（NAND)快閃記憶體。 15. 如申清專利範圍第i3項所述之快閃儲存晶片，其 30 200910356 則 7-觀0 24992twf.doc/n 中將該微控制器及該至少-個快閃路板上的方法包括四料平無接腳^ ^ 式〇、錫球陣列式（BGA)、超薄平載式⑽昨方塊形扁平封裝式（QFp)m(Dif 晶片直接封裝式（C0B)或單排聊封裝式⑽）封士 16.如申請專利範圍第13項所述之快閃儲存晶片^ 中該IDE指令相容於ATA或序列Ata規格。乃其200910356 PSPD-2007-00I6 24992twf.d〇c/n Patent Application Range: 1. A flash array storage system comprising: each flash storage chip comprising a plurality of flash memory wafers arranged in a single circuit board; The microcontroller is packaged in the single-=memory interface and the high-speed peripheral component interconnect light_microcontroller': on the storage circuit board and consumes the interface, and the farmer flashes on the single-board An array controller coupled to the system for reading and storing in the flash memory chips; coupled to the two sides, coupled to the flash array controller for transmitting the system host and the The flash array age system is fast and writes the data to the flash memory interface to the middle of the flash memory storage system 25 200910356 PSJeD-2UU/-UUl〇24992twf.doc/n When the data is present, the flash array controller searches for the flash memory chip storing the material, and the flash memory chip storing the data is read and stored in the flash memory through the flash memory interface. The material in the memory and through the PC The I Express interface transmits the data to the pci Express connection interface. 2. The flash array storage system of claim 1, wherein the at least one flash memory is an SLC (Single Level Cell) or an MLC (Multi Level Cell) in each flash memory chip. Reverse (NAND) flash memory. 3. The flash array storage system of claim 2, wherein the method of packaging the microcontroller and the at least one flash memory on the single-circuit board in each flash memory chip Including four-sided flat pinless (QFN), planar array (LGA), solder ball array (BGA), ultra-thin planar plastic particle-loaded (LQFP), square-shaped flat package (QFP), die Formula (DIE), wafer direct package (COB) or single row package (SIP) package. 4. The flash array storage system according to claim 1, wherein the flash array controller and the flash storage chips are at a physical layer of the transmission data, and the transmission layer is formed by at least a group of simple channels. Tx) and receiver (Rx). 5. A flash array storage system comprising: a plurality of flash memory chips arranged in an array, each flash memory chip comprising: a single circuit board; 26 200910356 PSFU-200/-0Ult, 24992twf.doc/ n - Microcontroller, packaged on the single circuit board and 1 = memory interface... PCIE s SS interface and - virtual whole = one coffee host receiving a chat command and -IDE device for executing 2 commands 'The firmware program executed by the controller is implemented. The field is at least one flash memory, packaged in the single-coupled to the microcontroller for storing data; and a PCI Express a connection interface, packaged in the lighter and connected to the microcontroller, for connecting to the "system ^ road = / one (four) array driver 'installed in the system = : domain to execute to control the flash memory crystals in the Reading the wiper t (four), when the machine wants to read the data stored in the button, the flash array drives the flash to store the chip, and stores the data. The IDE module receives the execution system, ] storing the virtual of the cymbal and the (four) will be ordered by The PCI EXp interface is converted to the p formatted by some of the received formats, and the press is connected; the 1st surface can be connected to the system host to write data to the flash array storage season, and its == send the faster "= The virtual IDE module will receive the block flash memory chip and execute the IDE 27 200910356 PSPD-20U7-0016 24992twf.d〇c/n command issued by the system host and the data to be written The flash memory is received by the PCI Express connection interface and the PCI Express interface, and is converted into the flash memory by the flash memory interface to be received by the flash memory. The flash array storage system of claim 5, wherein the at least one flash memory is an SLC (Single Level Cell) or an MLC (Multi Level Cell) inverse (NAND) in each flash memory chip. The flash memory storage system of claim 5, wherein the microcontroller and the at least one flash memory are packaged in each of the flash memory chips The method on a single board includes four sides flat and no connection Foot type (QFN), planar array type (lga), solder ball array type (BGA), ultra-thin planar plastic particle-loaded (LQFP), square-shaped flat package (QFP), die-type (DIE), wafer A direct-packaged (c〇B) or single-row package (SIP) package. 8. The flash array storage system of claim 5, wherein the IDE instruction is compatible with a ΑΤΑ specification or sequence ATA specifications. 9. A flash memory chip, comprising: a single circuit board; - a micro control H' packaged on the single circuit board and having a flash memory interface and a PCI Express interface; at least one flash memory, Packaged on the single circuit board and to the microcontroller for storing data; and a PCI Express connection interface, packaged on the single circuit board and 28 200910356 ^ί>^ΐ-)-2υυ/-υυιο 24992twf .d〇c/n is coupled to the microcontroller host, to connect the fast memory to a system, wherein when the system host wants to write data to the flash, then the microcontroller will Receiving the data through the PCI Express interface and writing the data to the flash memory through the flash memory age. When the system host wants to read and store the data stored in the flash memory, the micro (four) device will pass through The data in the (4) memory interface flash memory is transmitted to the system host through the PCI interface. 1 10. The flash memory chip according to claim 9, wherein the at least one flash memory is an SLC (Single Uvd ^ MLC (Multi Level Cell) reverse (NAND) flash memory. The flash memory chip of claim 9, wherein the method of packaging the microcontroller and the at least one flash memory on the single electrical board comprises a quad flat no-pin (QFN) , planar array (LGA), solder ball array (BGA), ultra-thin flat plastic pellets (LQFP), block open > flat package (QFP), die (die), wafer directly Packaged (COB) or single-row package (SIp) package method. 12. The flash memory chip according to the πth patent scope, the packaged pin includes at least PERST#, REFCUC+, RJErcUC_, PETpO, PETnO, PERpO, PERnO, Power, Ground, etc. 13. A flash memory chip, comprising: a single circuit board; a microcontroller packaged on the single circuit board and having a flash flash 29 200910356 Fi>FU-2UU/-uui6 24992twf.doc/n Remembrance interface, -PCI EXpress And the virtual coffee leg module has a ship control for receiving the - coffee command = to execute the !_ command - the IDE device side, the virtual ide = = can be executed by the firmware program executed by the micro control a flash memory, packaged on the single-circuit board and lightly connected to the microcontroller for storing data; and a PC Express connection interface, packaged on the single circuit board and lightly connected to the The micro control m stores the (4) memory chip domain to the system host, wherein when the system host wants to read the data stored in the flash memory, the IDE command issued by the system host is sent to the virtual The leg module is executed by the virtual coffee module, and the data stored in the memory is read by the flash memory interface and converted by the PCI Express interface into the PCI interface. The format of the connection = is transmitted to the system host, wherein when the system host wants to write data to the flash memory, the IDE command issued by the system host is sent to the virtual ship module to be IDE module execution, and want to write The incoming data is received through the PCI Express interface and converted to the flash memory by the flash memory interface to be formatted by the flash memory. 14. For example, the scope of the patent application is The flash memory chip of claim 3, wherein the at least one flash memory is an SLC (single Levd Cdl) or an MLC (Multi Level Cell) inverse (NAND) flash memory. 15. If the flash memory chip described in the patent scope i3 is applied, the method of the microcontroller and the at least one flash circuit board is included in the method of 30 200910356 7-view 0 24992 twf.doc/n Four-material flat no-pin ^ ^ type 锡, solder ball array (BGA), ultra-thin flat-load type (10) yesterday square-shaped flat package (QFp) m (Dif wafer direct package (C0B) or single row chat package (10)) Seal 16. The flash command of the flash memory chip described in claim 13 is compatible with the ATA or Serial Ata specifications. It

17·—種快閃儲存晶片，包括：一單一電路板； -微控㈣’封裝在該單—電路板上且具有— 憶體介面與一 PCI Express介面； ° 多個快閃記憶體，封裝在該單—電路板上且分別地接至該微控制器，用以儲存資料；以及一 PCI Express連接介面’封裝在該單一電路板上且耦接至該微控制ϋ，用以將該快觸存晶片祕至一系統主機，其中當該系統主機欲寫入資料至該快閃儲存晶片時’則s亥微控制器會透過該PCI Express介面接收該資料並且透過該快閃記憶體介面寫入該資料至該些快閃=憶體其中當該系統主機欲讀取儲存在該快閃儲存晶片的資料時，則該微控制器會透過該快閃記憶體介面讀=該些快閃記憶體中的資料，並且透過該PCI Express介面經由 PCI Express連接介面傳送至該系統主機，、工其中該些快閃記憶體的資料讀取與寫入是以一平行 31 200910356 FSJeu-2UU /-υυ I o 24992twf.doc/n 處理方式進行。 18·如申請專利範圍第17項所述之快閃儲存晶片，其中每一該些快閃記憶體分別為一 SLC (Single Level Cell)或 MLC (Multi Level Cell)反及（NAND)快閃記憶體。 19. 如申請專利範圍第17項所述之快閃儲存晶片，其中將該微控制器及該些快閃記憶體封裝於該單一電路板上的方法包括四邊扁平無接腳式（qFN)、平面陣列式 (LGA)、錫球陣列式（BGA)、超薄平面型塑膠粒承載式（LQFP)、方塊形扁平封裝式（QFp)、晶粒式（DIE)、晶片直接封裝式（COB)或單排腳封裝式（SIp)封裝法。 20. 如申凊專利範圍第19項所述之快閃儲存晶片，其封裝後的腳位至少包括PERST#、REF(XK+、REF(：u^ PETp0、PETn0、PERp〇、PERn〇、ρ〇·Γ、Gr〇und 等腳位。如申請專利範圍第17項所述之快閃儲存晶片，其中該系統主機與職_存晶片在傳輸#_實體層可: 至少-組單工通道組成發送端（Τχ)與接收端（Rx)。 22.如申請專利範圍第17項所述之快閃儲存晶片，其該微控制H更包括-虛擬舰馳，該虛擬咖模组^ 齡的—IDE主控端與用以執行該IDE 器執行的她^ 彳由該微控制 3217·- flash memory chip, comprising: a single circuit board; - micro-control (four) ' packaged on the single-board with - memory interface and a PCI Express interface; ° multiple flash memory, package Connected to the microcontroller on the single-board and separately connected to store data; and a PCI Express connection interface is packaged on the single circuit board and coupled to the micro-controller for fasting Touching the chip to a system host, wherein when the system host wants to write data to the flash memory chip, the microcontroller will receive the data through the PCI Express interface and write through the flash memory interface. Inserting the data into the flash memory = when the system host wants to read the data stored in the flash memory chip, the microcontroller reads through the flash memory interface = the flash memory The data in the body is transmitted to the system host through the PCI Express interface through the PCI Express interface, and the data reading and writing of the flash memory are parallel 31 200910356 FSJeu-2UU /-υυ I o 24992twf.doc/n Processing method. 18. The flash memory chip of claim 17, wherein each of the flash memories is an SLC (Single Level Cell) or an MLC (Multi Level Cell) inverse (NAND) flash memory. body. 19. The flash memory chip of claim 17, wherein the method of packaging the microcontroller and the flash memory on the single circuit board comprises a quad flat no-pin (qFN), Planar Array (LGA), Tin Ball Array (BGA), Ultra-Thin Planar Plastic Granular Load (LQFP), Square Flat Package (QFp), Die (DIE), Wafer Direct Package (COB) Or single-row package (SIp) package. 20. The flash memory chip of claim 19, wherein the packaged pin comprises at least PERST#, REF(XK+, REF(:u^PETp0, PETn0, PERp〇, PERn〇, ρ〇). Γ, Gr〇und, etc. The flash memory chip according to claim 17 of the patent application, wherein the system host and the service chip are in the transmission #_ physical layer: at least - a group of simple channels are configured to transmit 22. The flash memory storage chip of claim 17, wherein the micro control H further comprises a virtual voyage, the virtual coffee module is an IDE. The master and the client for performing the execution of the IDE are controlled by the micro control 32