TW200910311A - Display driving device and display device - Google Patents

Abstract

A delay selection circuit (9) is arranged on a data driver (31) which outputs display data (gradation voltage) to a liquid crystal display panel. A data load signal (LOAD) decides a timing for acquiring the gradation data (DATA) latched by a latch circuit unit (5), into a hold circuit unit (6). The delay selection circuit (9) delays a data load signal (LOAD) with the delay time decided according to a selection control signal (SEL) inputted from a selection control terminal (19). By varying the selection control signal (SEL) between a plurality of data drivers (31) mounted on the liquid crystal display panel, the data drivers (31) can vary the timing for acquiring the gradation data (DATA) into the hold circuit unit (6). This enables shift of the output timing of the drive signal in the display device without increasing the chip area.

Description

200910311 九、發明說明： f發明所屬之技術領域】 本發明係闕於用於驅動液S翻-壯m 囉動… 装置等顯示裝置之顯示 【先前技術】 驅動裝置及具有其之顯示裝置。 近年來，液晶顯示裝置等平板式 , 攸式顯不裝置不斷大型化. ψ 5 構成將顯示資料（灰階電 D輸出至顯不面板之驅動 用的身枓驅動器之半導體積體 私路中’讯號輸出端子之端子數 , 千數不斷杧加，或輸出緩衝器 之驅動迠力不斷擴大。 首先’對先前之資料驅動3|用 _ 切為用之半導體積體電路（以下 稱作驅動器積體電路）構 ;〈偁成加以况明。圖11係表示可分 別自n根訊號輸出端子lll_l〜ln n鈐山七卜 ^ U-n輸出111灰階之輸出電壓 之該驅動器積體電路構成的方塊圖。 驅動器積體電路101中1為用於自外部輸入訊號之端 八有·時脈輸入端子丨〇2 ;含有複數個訊號輸入端 子之灰階資料輪人端子1G3; LQAD|fi號輸人端子1〇4;及 / ^•原端子105〜1〇9。又’驅動器積體電路中，作為 用於向液晶顯示面板輸出訊號之端子，而具有η個訊號輸 出端子111-1〜200910311 IX. Description of the Invention: Field of the Invention The present invention relates to display of a display device such as a device for driving a liquid S. [Prior Art] A driving device and a display device having the same. In recent years, flat-panel type devices such as liquid crystal display devices have been continuously enlarged. ψ 5 constitutes a display device (the gray-scale electric D is output to the semiconductor integrated circuit of the body drive for driving the panel) The number of terminals of the signal output terminal, the number of thousands is constantly increasing, or the driving force of the output buffer is constantly expanding. First, the semiconductor integrated circuit (hereinafter referred to as the driver product) for the previous data driving 3| The structure of the driver circuit is shown in Fig. 11. Fig. 11 shows the block formed by the driver integrated circuit which can output the output voltage of the gray scale from the n signal output terminals 111_1 to ln n. In the driver integrated circuit 101, 1 is a terminal for inputting signals from the outside, and has a clock input terminal 丨〇2; a gray-scale data wheel terminal 1G3 including a plurality of signal input terminals; LQAD|fi is input Terminals 1〇4; and /^• original terminals 105~1〇9. In the 'driver integrated circuit, as the terminal for outputting signals to the liquid crystal display panel, there are n signal output terminals 111-1~

In °其中’有時將訊號輸出端子lu_ 1〜111-η總稱為訊號輪出端子丨^。 卜驅動器積體電路101中，作為設置於内部之電 -J '* jj /、 *考電源校正電路12 1、指標用之移位暫存器 電路12 3、销在齋& 子電路邛124、保持電路部125、D/A轉換器 130392,doc 200910311 (Dlgltal t0 Anai〇g c_erter，數位類比轉換器）部⑶（以 下，稱作DAC部126)、及輸出緩衝器部127。 心心用移位暫存器電路123*n級移位暫存器〜123_ η構成。鎖存電路部124由„個鎖存電路mmn構成。 保持電路部125由n個保持電路125_!〜125_n構成。DAC部 ⑶由說電路咖1〜12“構成。輸出緩衝器部127，1 運算放大器所構成之輸出緩衝器構成， 指標用移位暫存器電路123,根據輸入至時脈輸入端子 102之時脈訊號，選擇鎖存電路中之一者。於 該狀態下’自灰階資料輸入端子1〇3輸入灰階資料後，將 該灰階資料儲存於所選擇之鎖存電路中。 又’自指標用移位暫存H電路123輸出之鎖存電路選擇 訊號’根據自時脈輸入端子1〇2輸入之時脈訊號而依序自 第1級鎖存電路^心丨選擇至第n級鎖存電路124_n。由此， 於輸入η個時脈之情形時，可將資料記憶於所有鎖存電路 124-卜124_种。又，鎖存電路⑶心心可記憶值互不 相同之資料。根據f料載人訊號l〇)ad，將鎖存電路⑶· 1〜12“中所記憶之資料，分別向相應之n個保持電路⑵_ 1〜125-η傳送，*成為DAC之數位輸人資料。 DAC電路以6·1〜12“，根據上述數位資料，自輸入之m 種灰階電壓中選擇一種灰階電塵並加以輸出。也種灰階電 壓，係根據分別自參考電源端子1〇5〜1〇9輸入之參考電壓 V0〜V4，藉由參考電源校正電路121而產生。 進而，自DAC電路126-1〜126-n輸出之灰階電壓，藉由 130392.doc 200910311 輸出緩衝器部127而進行阻抗轉換後，分別自輸出端子 1 1 1 -1〜111 -η作為液晶顯示面板之驅動訊號而輸出。 如上所述’為了根據資料載入訊號而一併進行資料傳 送’使灰階電壓同時變化。故而，驅動器積體電路1〇1中 瞬間產生較大之電流。該電流，會因訊號輪出端子丨丨丨之 增加’及輸出緩衝器部127之驅動能力之增大而成為非常 大之值。因此’不僅導致驅動器積體電路1 〇丨之消耗電流 、 增大’而且因該電流而產生之多餘輻射亦成問題。 ( 由此，專利文獻1中有如下記載，即為了防止因電流集 中而導致峰值電流增大，藉由使半導體積體電路内部用於 鎖存顯示資料之訊號延遲，而錯開驅動輸出之變化時序。 專利文獻1所揭示之源極驅動器（半導體積體電路）中，如圖 12所示’藉由保持記憶體電路24〇，基於水平同步訊號 LS(資料載入訊號）而將取樣記憶體所取樣之顯示資料加以 鎖存，且保持至輸入下一水平同步訊號LS為止。保持記憶 。 冑電路240具有對顯示資料之各位元進行鎖存且加以保持 之保持鎖存單元330 ,及複數個延遲電路32〇。用於對顯示 資料進行鎖存之水平同步訊號！^，係依序延遲必需程度並 以組單位提供至分成組之保持鎖存單元33〇。 _ [專利文獻U曰本公開專利公報「日本專利特開〗^^ 3〇 1946號公報（2004年10月28日公開）」 【發明内容】 專利文獻1之構成中，為了於半導體積體電路内延遲水 平同步訊號而必須設置並配置有複數個電路。故而，必需 130392.doc 200910311 有自延遲電路至保持鎖存單元之配線或延遲電路自身之安 裝區域，因此產生驅動器積體電路之晶片面積增大之 題。 4 本發明係鑒於上述問題而完成者，其目的在於，不増大 晶片面積便可使顯示裝置之驅動訊號之輸出時序錯開/ f o 本發明之顯示驅動裝置，為了達成上述目的而包括選擇 輸出電路’該選擇輸出電路根據輸入之顯示資料而自複數 個灰階電壓中選擇一個輸出，顯示裝置中以級聯連接狀態 搭載之被積體化者，包括可變時延遲電路，該可變時㈣In °, sometimes the signal output terminals lu_ 1 to 111-η are collectively referred to as signal wheel terminals 丨^. In the driver integrated circuit 101, as the internal power -J '* jj /, * test power supply correction circuit 12 1 , index shift register circuit 12 3 , pin in the fast & sub-circuit 124 The holding circuit unit 125, the D/A converter 130392, the doc 200910311 (Dlgltal t0 Anai〇g c_erter, digital analog converter) unit (3) (hereinafter referred to as the DAC unit 126), and the output buffer unit 127. The heart is configured by a shift register circuit 123*n shift register register -123_n. The latch circuit unit 124 is constituted by a plurality of latch circuits mmn. The hold circuit unit 125 is composed of n holding circuits 125_! to 125_n. The DAC unit (3) is constituted by the circuit makers 1 to 12. The output buffer unit 127,1 constitutes an output buffer composed of an operational amplifier, and the index shift register circuit 123 selects one of the latch circuits based on the clock signal input to the clock input terminal 102. In this state, after the gray scale data is input from the gray scale data input terminal 1〇3, the gray scale data is stored in the selected latch circuit. In addition, the latch circuit selection signal outputted from the index temporary storage H circuit 123 is sequentially selected from the first stage latch circuit according to the clock signal input from the clock input terminal 1〇2. The n-stage latch circuit 124_n. Thus, in the case of inputting n clocks, the data can be memorized in all latch circuits 124-. Further, the latch circuit (3) can memorize data having mutually different values. According to the f-loader signal l〇)ad, the data memorized in the latch circuits (3)·1~12" are respectively transmitted to the corresponding n holding circuits (2)_1~125-η, and the digital input of the DAC becomes the DAC. The DAC circuit selects a gray scale electric dust from the input m kinds of gray scale voltages according to the above digital data and outputs it according to the above digital data. The gray scale voltage is also generated by reference to the power supply correction circuit 121 based on the reference voltages V0 to V4 input from the reference power supply terminals 1〇5 to 1〇9, respectively. Further, the gray scale voltages output from the DAC circuits 126-1 to 126-n are impedance-converted by the output buffer unit 127 of 130392.doc 200910311, and are respectively used as the liquid crystal from the output terminals 1 1 1 -1 to 111 -n. The drive signal of the display panel is output. As described above, "for data transmission based on the data loading signal", the gray scale voltage is simultaneously changed. Therefore, a large current is instantaneously generated in the driver integrated circuit 1〇1. This current becomes a very large value due to an increase in the number of signal wheel terminals ’ and an increase in the driving ability of the output buffer unit 127. Therefore, not only does the current consumption of the driver integrated circuit 1 increase, but also the excess radiation generated by the current is problematic. (Therefore, Patent Document 1 discloses that the timing of the drive output is shifted by the delay of the signal for latching the display data in the semiconductor integrated circuit in order to prevent the peak current from increasing due to the current concentration. In the source driver (semiconductor integrated circuit) disclosed in Patent Document 1, as shown in FIG. 12, by holding the memory circuit 24, the sampling memory is based on the horizontal synchronization signal LS (data loading signal). The sampled display data is latched and held until the next horizontal sync signal LS is input. The memory is held. The circuit 240 has a hold latch unit 330 that latches and holds the bits of the display data, and a plurality of delays. The circuit 32. The horizontal synchronizing signal for latching the display data is sequentially delayed by the necessary degree and supplied to the grouped holding latch unit 33〇 in groups. _ [Patent Document U 曰 Patent Publication Japanese Patent Laid-Open Publication No. Hei. No. 3946 (published on Oct. 28, 2004). SUMMARY OF THE INVENTION In the constitution of Patent Document 1, for the purpose of semiconductor In the body circuit, the horizontal synchronization signal is delayed and a plurality of circuits must be set and configured. Therefore, it is necessary for the 130392.doc 200910311 to have a self-delay circuit to maintain the wiring of the latch unit or the mounting area of the delay circuit itself, thus generating the driver integrated circuit. The present invention has been made in view of the above problems, and an object thereof is to shift the output timing of a driving signal of a display device without a large wafer area. The purpose is to select an output circuit that selects one output from a plurality of gray scale voltages according to the input display data, and the integrated device mounted in the cascade connection state in the display device, including the variable time delay circuit , the variable time (four)

電路根據控制訊號而決定延遲眸 R .. , L 遲時間，且使自上述選擇輸出 電路輸出上述灰階電壓之輸出時序以上述延遲時間延遲。 :述之構成中，藉由可變時延遲電路，以根據控制訊號 而確定之延遲時間而使輸出時序延遲。如此，ϋ由各顯示 驅動裝置/刀別具有可變時延遲電路，而於搭載有複數個顯 I駆動裝置之顯不裝置中，若事先以顯示驅動裝置 時間不同之方式設定控制 ^ 干㈣…… W訊唬，則可使整個顯示裝置中顯 不駆動裝置間之輸出時序不同。 藉此，可獲得ik 4π /、光則技術相同之多餘輻射得以 果。又，於顯示驅動裝置中僅机 -之效 〒僅°又置可變時延遲電路即可， 因此可將顯示驅動裝置右 度。 /置之布局面積之增加抑制至最小限 較好的是，上述顯示觝# ^ ㈣裝置中，上述可變時延遲雷路 包括：解碼器，其係對人亡$ & / 才、遲電路 行解碼，·延遲時間設定 工制汛唬進 疋電路’其係預先設定複數個不同之 130392.doc 200910311 上述延遲時間 之解碼值，自上；：間選擇電路，其係根據上述解碼器 延遲時間中選擇時間設定電路所設定之複數個上述 T丨曰j f選擇一個延 定電路，AMl ' 上述構成中，延遲時間設 可以比較符罝e 彳疋間之延遲電路。藉此， Β早之4而構成可變時延遲電路。 較好的是，上述顯 入由搭載有m 包括輸入端子，其係輸 號n #认貝不裝置所產生之上述控制訊 J 。頁不驅動裝置中設置輸入端子便盔需嗖置 產生控制訊號之電路等， 史’、，、而。又置 積更小。 .因此可使顯示驅動裝置之布局面 利用上二t述顯不驅動裝置中，上述可變時延遲電路 料來作為上述控制訊號。藉此，無需另外 子。生控制訊號’從而無需增加用於輸入控制訊號之端 較好的{’上述顯示驅動裝置中’上述可變時延遲電路 利用—次掃描時最後取人之上述顯示資料來作為 訊號。 < <工市j *較好的a ’該顯示驅動裝置具有保持機構，其係使一欠 掃描時最後取入之上述顯示資料保持於傳輸上述顯示資： 之傳輸配線中n保持機構使顯示資料保持於傳輸配 線中，因此可容易地利用最後取入之顯示資料。 或者，較好的S ’該顯示驅動裝置具有鎖存器，其係保 持-次掃描時最後取入之上述顯示資料。於使顯示資料保 持於上述傳輸配線中之情形時，有時會產生電位不穩定2 130392.doc 200910311 而不會產生上述之不穩定 之顯示資料。 狀態。對此，藉由使用鎖存器， 狀態，從而能可靠地保持所利用 、—本發明之顯示裝置，係、向顯示面板輸出上述灰階電壓之 複數個顯示驅動裝置以級聯連接狀態安裝於上述顯示面板 者其特徵在於.為了解決上述課題，上述顯示驅動裝置 係上述之任一顯示驅動裝置’且上述輸出時序係以於至少 -個上述顯示驅動褒置與其他上述顯示驅動裝置之間不同 之方式設定。The circuit determines the delay 眸 R .. , L delay time according to the control signal, and delays the output timing of outputting the gray scale voltage from the selection output circuit by the delay time. In the above description, the output timing is delayed by the variable time delay circuit with the delay time determined based on the control signal. In this way, the display drive device/knife has a variable-time delay circuit, and in the display device in which a plurality of display-sensing devices are mounted, if the display drive device has different time in advance, the control is set to (4)... ... W signal, the output timing between the display devices in the entire display device can be different. In this way, it is possible to obtain ik 4π /, and the same radiation with the same technique as light. Further, in the display driving device, only the delay effect circuit can be set only in the case of a variable speed, so that the display driving device can be right. Preferably, the increase in the layout area is suppressed to a minimum. In the above display ^#^(4) device, the variable time delay lightning path includes: a decoder, which is a pair of people, $ & /, late circuit Line decoding, delay time setting process, input circuit, 'sets a plurality of different 130392.doc 200910311 decoding value of the above delay time, from top;: inter-selection circuit, which is based on the above decoder delay time A plurality of the above-mentioned T丨曰jf set by the selection time setting circuit selects an extension circuit, and in the above configuration, the delay time is set to compare the delay circuit between the symbols 罝e. Thereby, the variable time delay circuit is constructed as early as four. Preferably, the above-described control signal is generated by mounting m including an input terminal, which is a device that generates an n # acknowledgement device. The page is not equipped with an input terminal, and the helmet needs to be set up to generate a control signal circuit, etc., history, and. The volume is smaller. Therefore, the layout surface of the display driving device can be used as the control signal by using the variable time delay circuit in the above-described display driving device. This way, no additional ones are needed. The control signal ’ thus does not need to be added to the end of the input control signal. The above-mentioned variable-time delay circuit uses the above-mentioned display data of the last person to be used as a signal. <<<>> The market j* is better a' The display driving device has a holding mechanism for holding the display material finally taken in during the underscan, in the transmission wiring for transmitting the display: The display data is held in the transmission wiring, so that the last captured display material can be easily utilized. Alternatively, the preferred S' display drive device has a latch that retains the display data that was last taken in during the second scan. In the case where the display data is held in the above-mentioned transmission wiring, potential instability 2 130392.doc 200910311 may be generated without causing the above-described unstable display material. status. In this regard, by using the state of the latch, the display device of the present invention can be reliably held, and a plurality of display driving devices that output the gray scale voltage to the display panel are mounted in a cascade connection state. The display panel is characterized in that, in order to solve the above problem, the display driving device is any one of the display driving devices described above, and the output timing is different between at least one of the display driving devices and the other display driving devices. The way to set.

i} 藉此，如上所述，可使整個顯示裝置中顯示驅動裝置間 之輸出時序不同。 較好的是，上述顯示驅動襞置進而包括計數器，其係對 與自外部輸人之上述顯示資料之取人時序同步之時脈訊號 進行計數，且於顯示驅動裝置結束上述顯示資料取入之時 點，停止汁數而保持計數值，上述可變時延遲電路利用上 述計數值來作為上述控制訊號。藉此，自外部向顯示驅動 衣置僅提供時脈訊號即可，從而可減少顯示驅動裝置中追 加之端子數。 較好的是，該顯示驅動裝置中，上述計數器於停止計數 之前用預先設定之計數值來重設計數值。由於計數器相應 對計數器進行重設之計數值（重設之時序）而停止時之計數 值不同’故而可藉由適當地設定重設之時序，而設定最佳 之延遲時間。 本發明之其他顯示裝置，係向顯示面板輸出上述灰階電 壓之複數個顯示驅動裝置以級聯連接狀態安裝於上述顯示 130392.doc 200910311 面板者，其中上述顯示駆動裝置係具有上述計數器之顯示 驅動裝置，且上述計數器停止時之計數值係以於至少一個 上述顯示驅動裝置盘jt仙μ、+, 、 /、八他上述顯示驅動裝置之間不同之方 式設定。藉此，可盥上诚骷 忒,.-員不裝置相同地，使整個顯示裝 置中顯示驅動裝置間之輸出時序不同。 本發明之另外其他顯^^· .，，下裝置係向顯示面板輸出上述灰階 電磨之複數個顯示驅動裳詈以妨胳$ 一 ,^ 勒衮置以級聯連接狀態安裝於上述顯 不面板者，其中上述顯 如動衮置係重堍上述計數器之計 门 不㈣裝置’且以上述計數器停止時之計數值不 同之上述顯示驅動裝置之數量達到最大 上述計數器之計數值。藉 — 又疋室0又 夕拄皮、4 猎由取佳5又疋重設之計數值（重設 ^ .. 徇出貝科數，計數器停止 :之计數值不同之顯示驅《置數量達到最大。因此，可 進-步抑制顯示驅動裝置之布局面積之增力” 本發明之顯示驅動裝置如上 路，：i & 〃、有可變時延遲電 路』根據控制訊號而決定延遲時間，且使 輸出電路輸出上述灰階電壓之輸 “、 遲。 斤以上述延遲時間延 上述之構成中，藉由 控制訊號而決定之延遲時間延遲遲 置分別具有可變時延遲電路，而於 2顯示驅動裝 裝置之顯示裴置中，胃 有歿數個顯示驅動 置中右事先以顯示驅動梦w 同之方式設定押制4 $ , 裝置間延遲時間不 &制Λ 5虎，則可使整個顯示 一 裝置間之輸出時序不 、置中顯不驅動 130392.doc 200910311 藉此，可獲得與先前技術相同之多餘輻射降低之效果。 又，僅於顯示驅動裝置中設置可變時延遲電路即可，因此 可將顯不驅動裝置之布局面積之增加抑制至最小限度。因 此，具有如下效果··不增大顯示驅動裝置之晶片面積，而 可使顯示裝置中之驅動訊號(灰階電壓)之輸出時序錯開。 故而，晶片件數越増加’越可期待EMI (mectr(> Magnetie Interference，電磁干擾）降低效果β 【實施方式】i} Thereby, as described above, the output timing between the display drivers in the entire display device can be made different. Preferably, the display driving device further includes a counter for counting a clock signal synchronized with an acquisition timing of the display data from an external input, and ending the display data acquisition by the display driving device. At the time, the number of juices is stopped and the count value is held, and the variable time delay circuit uses the count value as the control signal. Thereby, only the clock signal is supplied from the outside to the display driving device, thereby reducing the number of terminals added in the display driving device. Preferably, in the display driving device, the counter redesigns the value with a preset count value before stopping counting. Since the counter correspondingly resets the count value (reset timing) of the counter and the count value at the time of stop is different, the optimum delay time can be set by appropriately setting the timing of the reset. In another display device of the present invention, a plurality of display driving devices that output the gray scale voltage to the display panel are mounted in a cascade connection state on the panel of the display 130392.doc 200910311, wherein the display scrolling device has the display driving of the counter. And the counting value when the counter is stopped is set in such a manner that at least one of the display driving device disks is different from the display driving device. In this way, it is possible to make a sincerity, and the members do not install the same, so that the output timing between the display drivers in the entire display device is different. According to another aspect of the present invention, the lower device outputs a plurality of display driving dresses of the gray-scale electric grinding to the display panel, so as to be installed in the cascading connection state. In the case of no panel, the above-mentioned display device resets the count gate of the counter to the fourth device, and the number of the display drive devices with different count values when the counter is stopped reaches the maximum count value of the counter. Borrowing - also the room 0 and the evening sable, 4 hunting by the good 5 and reset the count value (reset ^.. 贝 out the Bayco number, the counter stops: the display value is different Therefore, the boosting force of the layout area of the display driving device can be further suppressed. "The display driving device of the present invention is as follows: i & 〃, variable-time delay circuit" determines the delay time according to the control signal, and The output circuit outputs the output of the gray scale voltage, and the delay is delayed by the delay time. The delay time delay determined by the control signal has a variable time delay circuit, and the display delay is 2 In the display device of the device, there are several display drives in the stomach to set the center to the right. In advance, the display drive dream w is set to be controlled 4 $, and the delay time between devices is not & The output timing between one device is not, and the center is not driven. 130392.doc 200910311 Thereby, the same effect of reducing the excess radiation as in the prior art can be obtained. Also, the variable time delay is set only in the display driving device. The circuit can be used, so that the increase in the layout area of the display drive device can be minimized. Therefore, the following effects can be achieved: • The drive signal (gray scale) in the display device can be made without increasing the wafer area of the display drive device. The output timing of the voltage is shifted. Therefore, the more the number of wafers is added, the more EMI (mectr (> Magnetie Interference) reduction effect β can be expected. [Embodiment]

基於圖1至圖1 0對本發明之實施形態作如下說明。 [液晶模組之構成] 圖1表示安裝有用以對液晶顯示面板】進行驅動之模組基 板2之液晶模組1 〇 〇 (顯示裝置）。 如圖1所示’液晶模組_具有液晶顯示面板1、模組基 板2、及資料驅動器液晶顯示面板i，經由η個資料驅動 器3而與模組基板2相連接。資料驅動器3並聯連接於顯示 面板1之-邊側。又’資料驅動器3’係藉由將積體化之驅 動器晶片以COF(ChiP〇nFilm，薄膜覆晶）般之安裝構造安 裝於薄膜基板上而構成者。該資料驅動器3, 4 了驅動『 晶顯示面板1所具有之複數個像素，而對各像素提供驅： 訊號。作為驅動訊號，準備與灰階眘粗 A貝枓所不之灰階相對庳 之灰階電壓。 〜 崎小田板1中，藉由液晶 電容而保持灰階資料。液晶電容’由液日日日顯示面板i之一 側之玻璃基板上所形成之共通電極、 τ谷像素而設置之像 130392.doc -13- 200910311 素電極、及***於該等間之液晶形成。經由由薄膜電晶體 (TFT，Thin-Film Transistor)形成之開關元件而向該像素中 寫入灰階資料。開關元件與複數根資料線及複數根掃描線 連接。該開關元件藉由供給至掃描線之接通（ON)訊號而接 通時’將輸出至資料線之灰階資料（灰階電壓）提供至像素 電極。藉此，將灰階電壓與施加至共通電極之電壓間之差 保持於液晶電容中。 模組基板2’由PWB(PrintedWiringBoard，印刷線路板） ^ 等構成，藉由搭載於該PWB上之控制器（未圖示），而產生 驅動液晶顯示面板1所需之時序訊號。又，模組基板2，具 有與各資料驅動器3相對應而設置之配線圖案（未圖示）。該 配線圖案包含複數根配線（未圖示），用以傳輸供給至各資 料驅動器3之灰階資料DATA(資料）或各種控制訊號，或者 施加電源電壓。控制訊號係時脈訊號(：^£、資料載入訊號 L〇AD、提供至後述之延遲選擇電路9、24、25、27之外部 U 訊號等。電源電壓係用以產生灰階電壓之參考電源電壓 V0〜V4或用以驅動資料驅動器3之電源電壓等。 再者，上述控制器亦可設置於模組基板2之外部。 [第1資料驅動器] ® 2表示作為資料驅動器3而使用之第丄資料驅動器b之 構成。 再者’以下說明之第2至第4資料驅動器η，參照圖 5、之圖7:及圖9)中’對具有與資料黯動器η之構成要素同 此之構成要素，附以相同符號並省略其說明。 130392.doc -14- 200910311 圖所不，資料驅動器31具有指標用移位暫存器電路 予電路5、保持電路部6、D/A轉換器（Digital to Analog Converter)部7(以下’稱作dac部7)、輸出緩衝器 8延遲選擇電路9、及參考電源校正電路10。又，資料 作為輸人端Μ具有時脈輸人端子u、灰階 ，；*輸端子12、資料載入訊號輸入端子1 3、參考電源端 子14〜1 8、及選擇控制端子19。 0 :丨：料驅動器31中’作為用以向液晶顯示面板1輸出 S 又置之輸出端子，具有n個訊號輸出端子20-1〜20- b虎輪出端子2(Μ〜2Q_n，分別與上述之各資料線連 接。 兩時脈f入端子11，設置為用以輸入向指標用移位暫存器 2路4提供之時脈訊號CLK。灰階資料輸入端子12，包含 〃 *數個位疋之灰階資料之各位元相對應之複數個訊號輸 入鳊子。貧料载入訊號輸入端子13，設置為用以輸入向延 〇 遲、擇電路9提供之資料載人訊號l〇ad。該資料載入訊號 D用作如下控制訊冑，此控制m號用以使保持電路部6 =持18由鎖存電路部4鎖存之灰階資料DATA。參考電源端子 8 °又置為用以輸入分別向參考電壓校正電路9提供之 參考電壓v〇〜V4。選擇控制端子19，設置為用以輸入向延 遲選擇電路9提供之選擇控制訊號SEL。 訊號輸出端子2(Μ〜2〇·η，分別對應於構成輸 部8之輪出崾；^。。〇 « 。 緩衡哭《設置’且設置為用以將自輸出 时〜8-Π輸出之灰階電壓，輸出至液晶顯示面板卜 130392.doc 200910311 指標用移位智左$ 暫存電路4，由複數級移位暫存 該指標用移位暫在哭φ A 盗構成。 暫存器電路4,藉由各級移位暫存 入至時脈輸人端子U之時脈替CLK^^ ^而使輸 況唬CLK產生移位後，自各級 移位暫存器輸出鎖存電路 路4,藉由鎖存電路選… 位暫存器電 之第!… 依序自構成鎖存電路部5 弟、.及鎖存電路5]選擇至第η級鎖存電路5-n。 鎖存電路部5 ’ “個鎖存電路5·1〜5_n構成。鎖存電路5_Embodiments of the present invention will be described below based on Figs. 1 to 10 . [Configuration of Liquid Crystal Module] Fig. 1 shows a liquid crystal module 1 显示 (display device) to which a module substrate 2 for driving a liquid crystal display panel is mounted. As shown in Fig. 1, the 'liquid crystal module _ has a liquid crystal display panel 1, a module substrate 2, and a data driver liquid crystal display panel i, which are connected to the module substrate 2 via n data drivers 3. The data driver 3 is connected in parallel to the side of the display panel 1. Further, the data driver 3' is constructed by mounting an integrated driver wafer on a film substrate in a COF (ChiP〇n Film, film-wrapped) mounting structure. The data driver 3, 4 drives the plurality of pixels of the crystal display panel 1, and provides a drive signal to each pixel. As the driving signal, prepare the gray-scale voltage relative to the gray-scale cautious A grayscale. ~ In the small field board of Saki, the gray scale data is maintained by the liquid crystal capacitor. The liquid crystal capacitor 'is a common electrode formed on the glass substrate on one side of the liquid display panel i, and an image 130392.doc -13-200910311 provided by the τ valley pixel, and a liquid crystal inserted therebetween . Gray scale data is written into the pixel via a switching element formed by a thin film transistor (TFT). The switching element is connected to a plurality of data lines and a plurality of scanning lines. When the switching element is turned on by the ON signal supplied to the scanning line, the gray scale data (grayscale voltage) outputted to the data line is supplied to the pixel electrode. Thereby, the difference between the gray scale voltage and the voltage applied to the common electrode is held in the liquid crystal capacitor. The module substrate 2' is composed of a PWB (Printed Wiring Board) or the like, and a timing signal required to drive the liquid crystal display panel 1 is generated by a controller (not shown) mounted on the PWB. Further, the module board 2 has a wiring pattern (not shown) provided corresponding to each of the material drivers 3. The wiring pattern includes a plurality of wirings (not shown) for transmitting gray scale data DATA or various control signals supplied to the respective material drivers 3, or applying a power supply voltage. The control signal is a clock signal (:, £, data loading signal L〇AD, an external U signal supplied to a delay selection circuit 9, 24, 25, 27, etc., which will be described later. The power supply voltage is used to generate a reference of the gray scale voltage. The power supply voltages V0 to V4 or the power supply voltage for driving the data driver 3. The controller may be provided outside the module substrate 2. The [first data driver] ® 2 is used as the data driver 3. The configuration of the second data driver b. In addition, the second to fourth data drivers η described below, with reference to FIG. 5, FIG. 7 and FIG. 9), have the same components as the data actuator η. The constituent elements are denoted by the same reference numerals and the description thereof will be omitted. 130392.doc -14- 200910311 The data driver 31 has a pointer shift register circuit pre-circuit 5, a holding circuit unit 6, and a D/A converter (Digital to Analog Converter) unit 7 (hereinafter referred to as 'the following' The dac portion 7), the output buffer 8 delay selection circuit 9, and the reference power source correction circuit 10. Further, the data as the input terminal has a clock input terminal u, a gray scale, a * terminal 12, a data loading signal input terminal 13, a reference power terminal 14 to 18, and a selection control terminal 19. 0: 丨: in the material driver 31 'as an output terminal for outputting S to the liquid crystal display panel 1 , having n signal output terminals 20-1 to 20- b tiger wheel output terminal 2 (Μ~2Q_n, respectively The above-mentioned data lines are connected. The two clocks f are input to the terminal 11, and are arranged to input the clock signal CLK supplied to the index shift register 2, and the gray scale data input terminal 12 includes 〃 * The plurality of signals corresponding to the bits of the gray scale data are input into the dice. The poor material is loaded into the signal input terminal 13, and is set to input the information provided to the delay circuit and the circuit 9 to carry the signal. The data loading signal D is used as a control signal for causing the holding circuit portion 6 to hold the gray scale data DATA latched by the latch circuit portion 4. The reference power terminal 8 is again set to It is used to input the reference voltages v 〇 V V4 respectively supplied to the reference voltage correction circuit 9. The selection control terminal 19 is provided for inputting the selection control signal SEL supplied to the delay selection circuit 9. The signal output terminal 2 (Μ~2〇) η corresponds to the round 崾 constituting the transport unit 8; ^. The balance is crying "Settings" and is set to output the grayscale voltage from the output to the LCD panel. The output is displayed on the LCD panel. 130392.doc 200910311 The index is shifted by the left left $ temporary storage circuit 4, by the plural Stage shift temporary storage This indicator is composed of a temporary shift in crying φ A. The register circuit 4 is temporarily stored in the clock input terminal U by the shift of each stage for the CLK^^^ After the transmission condition 唬CLK is shifted, the latch circuit 4 is output from each stage of the shift register, and the latch circuit is selected... The bit register is the first!... The self-constituting latch circuit unit 5 And the latch circuit 5] is selected to the n-th stage latch circuit 5-n. The latch circuit unit 5' constitutes one latch circuit 5·1 to 5_n. The latch circuit 5_

1〜5-n ’當輸人上述鎖存電路選擇訊號時，成為可 灰階資料輸入端子！2輸人之灰階資料咖八之有效狀離。 於該狀態T，可於鎖存電路5] 〜、 ω值各不相同之 ^由此’於將時脈訊號CLK^個時脈輸人至指標用 移位暫存器電路4中之情形時，所有鎖存電路Η〜5_n可記 憶與各資料線相應之灰階資料。於該狀態下，當自灰阡資 料輸入端子12輸入灰階資料時，該灰階資料將選擇性:儲 存於相應之各鎖存電路^丨〜、^中。 保持電路部6由n個保持電路6]〜6_n構成。保持電路& l+η，將各自對應之鎖存電路5]〜^中記憶之資料，以 育料載入訊號LOAD成$有效（例位準）之時序加以同時 取入並保持’保持電路“〜“中保持之資料，成為輸入 至DAC部7之DAC電路7-1〜7-n之數位資料。 DAC部7，由DAC電路μ〜7_n構成。DAc電路w〜&， 根據上述之數位資料’選擇自參考電壓校正電路1〇輸入之 m種灰階電壓中之【種灰階電壓並加以輸出。關於dac電路 7-1〜7-n之詳情，例如於日本專利特開2〇〇3_ι；3〇92ι號公報 130392.doc 200910311 中已有。己载，故而此處省略其說明。 校正電路10’根據分別自參考電源端― 輸入之參考電壓V0〜V4,產生m種灰階電壓。例如， 電壓校正電路10,包含串聯連接有複數個分壓電阻： 路，且藉由參考電壓V0〜V4之組合與該分壓電阻 種灰階電壓。 n m 輸出緩衝器部8，由輸出緩衝器8_丨 0 , 0 n稱戍。輸出緩衝 Ο “’對分別自峨電路Μ〜“輸出之灰階電壓進 订阻抗轉換。自輸出緩衝器8_丨〜“輸出之灰階電壓，分 別自訊號輸出端子2(M〜2G_n作為灰階資料而輸 出至液晶顯示面板1。 延遲選擇電路9’以根據選擇控制訊號咖而選擇之延 遲量來延遲提供W呆持電路6 _丨〜6 _ n之資料載入訊號 LOAD。具體而言’延遲選擇電路9,對自資料載入訊號： 入端子u輸人之資料載人訊號L〇AD，提供藉由選擇㈣ 訊號SEL之值而選擇之延遲時間並作為資料載入 L〇AD(DL’ data 1〇ad)而加以輸出。以下，對延遲選擇電 路9加以詳細說明。 圖3表示延遲選擇電路9之構成。 如圖3所示，延遲選擇電路9包含解碼器21、^個延遲電 路22、及16個開關SW0〜SW15。 解碼器21具有輸入4個位元之選擇控制訊號肌之#個輸 入端子A〜D，及輸出解碼結果之16個輸出端子γ〇〜γΐ5。 解碼器21，對輸入至輸入端子A〜D之選擇控制訊號sel進 130392.doc 200910311 之任一者輸出有效（例如 行解碼後，自輸出端子Y0〜Y15中 Η位準）之開關選擇訊號。 開關SWG〜SW15並聯連接著，且㈣载人訊號LOAD輸 广至該等之-端。又，開關sw〇之另一端成為資料載入訊 號load(dl)之輸出端，開關SW1〜SW15之另—端分別1~5-n ’ becomes the grayscale data input terminal when inputting the above latch circuit selection signal! 2 The grayscale data of the loser is valid. In this state T, the latch circuit 5]~, the value of ω may be different, thereby when the clock signal CLK^ clock is input to the index shift register circuit 4 All the latch circuits Η~5_n can memorize the gray scale data corresponding to each data line. In this state, when gray scale data is input from the ash data input terminal 12, the gray scale data is selectively stored in the corresponding latch circuits ^ 丨 ~, ^. The holding circuit unit 6 is composed of n holding circuits 6] to 6_n. Holding the circuit & l+η, the data stored in the corresponding latch circuit 5]~^ is simultaneously taken in and maintained by the incubation load signal LOAD into a valid (example) sequence. The data held in "~" is the digital data input to the DAC circuits 7-1 to 7-n of the DAC unit 7. The DAC unit 7 is composed of DAC circuits μ to 7_n. The DAc circuit w~& selects and outputs the grayscale voltage among the m kinds of grayscale voltages input from the reference voltage correction circuit 1〇 according to the above-mentioned digital data. For details of the dac circuit 7-1 to 7-n, for example, Japanese Patent Laid-Open No. 2〇〇3_ι; 3〇92. It is already loaded, so the description thereof is omitted here. The correction circuit 10' generates m kinds of gray scale voltages based on the reference voltages V0 to V4 input from the reference power supply terminals, respectively. For example, the voltage correction circuit 10 includes a plurality of voltage dividing resistors connected in series, and a gray scale voltage is combined with the voltage dividing resistor by a combination of reference voltages V0 VV4. The n m output buffer unit 8 is referred to as an output buffer 8_丨 0 , 0 n . The output buffer Ο “’ pairs the self-twisting circuit Μ ~ “output gray scale voltage to customize the impedance conversion. From the output buffer 8_丨~"the output grayscale voltage, respectively, from the signal output terminal 2 (M~2G_n is output as grayscale data to the liquid crystal display panel 1. The delay selection circuit 9' is selected according to the selection control signal coffee The delay amount is used to delay the data loading signal LOAD of the W holding circuit 6 _丨~6 _ n. Specifically, the delay selecting circuit 9 loads the signal from the data: the input signal of the input terminal u is input. L〇AD provides a delay time selected by selecting the value of the (4) signal SEL and outputs it as L 〇 AD (DL' data 1〇ad). Hereinafter, the delay selection circuit 9 will be described in detail. 3 shows the configuration of the delay selection circuit 9. As shown in Fig. 3, the delay selection circuit 9 includes a decoder 21, a delay circuit 22, and 16 switches SW0 to SW15. The decoder 21 has a selection control of inputting 4 bits. The signal input terminals A to D, and the 16 output terminals γ〇~γΐ5 of the output decoding result. The decoder 21 selects the control signal sel input to the input terminals A to D into 130392.doc 200910311 The output is valid (for example, the line After the code, the switch selects the signal from the output terminals Y0~Y15. The switches SWG~SW15 are connected in parallel, and (4) the manned signal LOAD is transmitted to the end of the terminal. In addition, the other end of the switch sw〇 Become the output end of the data loading signal load(dl), and the other ends of the switches SW1~SW15 respectively

u 與相對應之延遲電路22之輸入端子連接。開關 SW0〜SW15，分別與輸出端子YQ〜Y15相對應，且當來自輸 出端子Υ0〜Υ15之開關選擇訊號有效時接通。 延遲電路22,彼此串聯連接著成串聯電路之延遲電 路22中，輸入端子連接著開關SW1之一端之延遲電路^的 輸出端子成為資料載入訊號L〇AD(DL)之輸出端， 對以上述方式構成之延遲選擇電路9之動作加以說明。 例如，於選擇控制訊號SEL為"〇〇〇〇 ”之情形時，解碼器 21自輸出端子γ〇輸出有效之開關選擇訊號，因此僅開關 swo接通。該情形時，資料載入訊號L〇AD，無需經由開 關SW0而延遲，而是作為資料載入訊號£〇八〇⑴加以輸 出0 又’於選擇控制訊號SEL為”0001 ”之情形時，解碼器21 自輸出端子Y1輸出有效之開關選擇訊號，因此開關SW1接 通。該情形時，資料載入訊號L〇AD，以由第丨級延遲電路 22提供之1級程度之延遲時間進行延遲後，作為資料載入 tfl號LOAD(DL)而輸出。 如此’藉由自輸入端子A〜D輸入之選擇控制訊號SEL而 使延遲時間不同。故而，於選擇控制訊號SEL為"111 1" 130392.doc • 18- 200910311 日"Γ ’資料載入訊號LOAD通過延遲電路22’因此以最大之 1 5級程度之延遲時間延遲。 圖4(a)至（c) ’表示與選擇控制訊號SEL相對應之灰階資 料之傳送時序。 如圖4(a)所示，於選擇控制訊號SEL為，，〇〇〇〇，，之情形 時，如上所述，僅開關SW0接通，藉此並不延遲而是作為 資料載入訊號LOAD(DL)加以輸出。該情形時，灰階資料 DATA以資料載入訊號LOAD(DL)所規定之時序，自鎖存 電路5-1〜5-n取入至保持電路6-1〜6_n。 繼而’如圖4(b)所示，於選擇控制訊號SEL為，，〇111，，之 情形時，僅開關SW7接通，藉此以7級程度之延遲電路22 之延遲時間Ta進行延遲後作為資料載入訊號L〇AD(DL)而 輸出。該情形時，較之圖4(a)之情形，灰階資料DATA以 資料載入afL號LOAD(DL)所規定之時序，延遲有延遲時間 Ta後自鎖存電路5 -1〜5-n取入至保持電路1〜6-n。 進而，如圖4(c)所示’於選擇控制訊號SEL為” im"之 情形時’僅開關S W1 5接通，藉此以1 5級程度之延遲電路 22之延遲時間Tb進行延遲後作為資料載入訊號l〇ad(dl) 而加以輸出。該情形時，較之圖4(a)之情形，灰階資料 DATA以資料載入訊號LOAD(DL)所規定之時序，延遲有 延遲時間Tb後自鎖存電路5-1〜5-n取入至保持電路6_丨〜6_ η ° 如圖2所示’保持電路部6保持有DAC部7選擇灰階電壓 時所用之灰階資料DATA。故而，藉由將灰階資料取入至 130392.doc -19- 200910311 保持電路部6(保持電路 化 中保持之灰階資料DATA產生變 }而使自DAC部7輪出之灰卿帝茂*从嫩 為，產生變化之灰階”產生變化。其結果 ^ ^ 1、，坐由輸出緩衝器部8而輸出，且 &供至液晶顯示面板〗 ^且 φ ^ 各像素。由此，藉由延遲向# # 電路部6之灰階f#DA _保持 , 心取入（貝科傳送），而使自資料 ㈣"3Ι輸出之灰階電麗（驅動訊號）亦延遲。 又，如圖2所示，資料 f： 19。藉此，若使各資料1Γ 有選擇控制端子 右使各貝科驅動器31間輸 以之選擇控制訊號SEL ^擇戰子 器取驅動輸出以相同時序變化。…則可防止各資料驅動 牛”矿序先别之電路中’於資料驅動器内部使水平同 線。與此相對，資料驅動器 j應之配 load延遲之類 對僅有-貝料载入訊號 線。 之早-時序進行調整，因此無需追加配 Ο 如此，資料驅動器31中，並夫 動輪出之3#床彳上边之先前電路般使驅 個液：、變化’而是於資料驅動器31間，即於整 個液晶顯不面板!中變更驅動輪出之， 獲得與先前技術相同之多餘輕射得以降低之效果藉I: 圖12所示之先前之電路般， 動輸出產生變化之時序，而於資料^驅動器内部變更驅 塊中設置延遲電路，或者於每個分割方 至各分割方塊。與此相對，資料路且配線 設置使資料葡Λ 43 1中’僅於輸入部 、^L〇AD延遲之延遲電路22即可，從而 I30392.doc •20· 200910311 可將布局面積之增加抑制至最小限度’且亦不會使傳輸資 料載入訊號L〇AD(DL)之配線數增力” 吏傳輸貝 再者，較好的是，於所有資料驅動器31間驅動輸出之 化時序不同。然而，即便於至少一個資料驅動器3 資料驅動器3 1間驅動給屮#傲儿〇 士广 ”、 J %勒輸出之變化時序不同，亦可最低 地獲得上述之效果。 -又 [第2資料驅動器] Γ u 圖5表示作為資料驅動器3而使用之第2資料驅動器32之 構成。圖6表示資料驅動器32中之延遲選擇電路24之構 成0 如圖5所示，與資料驅動 寸％動窃31相同，貧料驅動器32呈有 :標用移位暫存器電路4、鎖存電路部5、保持電路部6、 繼部7、輸出緩衝器部8、參考電源校正電路1〇。 料驅動器32，呈有征巧、瞾视雨 、 ^有ι遲選擇電路24而代替上述延遲選擇電 路9。 如圖6所示’延遲選擇電路24,與上述延遲選擇電路9相 包含解碼器21、15個延遲電路22 。2 & 開關 因此4略對解碼器21、延遲電路22以 關8貿0〜SW15之詳細說明。 乂及開 然而’資料驅動器32中之解 ^ 鮮馬夯21，將灰階資料data 中之下位之4個位元杆椋μ、+、Λ 士 SFT 替述之來自外部之選擇控制訊號 EL，而輸入至輸入端子A〜 旲體而s，自傳輸下位之4 個位το之傳輸線輸入第丨位 弟2位凡D1、第3位元D2 义及弟4個位元〇4(以下，稱作 稱作下位之4個位元D〇〜〇4)，該 130392.doc 200910311 等下位之4個位元係傳輸灰階資料DATA之灰階資料匯流排 23中之下位之4個位元。 鎖存電路5-1〜5-n，對自上述模組基板2傳輸至資料驅動 器32之灰階資料〇八丁八加以鎖存。其中，於鎖存電路5_ • 1〜5-n取入所有灰階資料data之後，使資料驅動器32不接 夂來自模組基板2之灰階資料DATA。來自模組基板2之灰 階貝料DATA為所有資料驅動器32所共用，因此若自資料 p 驅動器32之灰階資料輸入端子12輸入灰階資料DATA ’則 因資料驅動器32之輸入緩衝器或灰階資料匯流排23進行動 作而多餘消耗電流。 由此，於鎖存電路5_丨〜5_n取入灰階資料DATA之後，使 資料驅動器3 2内部之灰階資料匯流排2 3與灰階資料輸入端 子12斷開而成為浮接狀態。具體而言，如圖5所示，預先 於灰階資料匯流排23中設置開關29。該開關29係如下者， 即當根據鎖存電路5]〜5_n之輸出變化，而確認出鎖存電 U 路5-1〜5-n中鎖存有灰階資料data時，於灰階資料匯流排 23中，斷開上述開關29。對開關29之控制係藉由自指標用 移位暫存器電路4中之最後級移位暫存器輸出之鎖存電路 达擇訊號END或者根據該訊號產生之控制訊號而進行者。 - 如此，藉由於資料驅動器32之内部對開關29進行控制，而 無需自外部向資料驅動器32輸入用於控制開關29之訊號。 由此，不會增加資料驅動器32之端子。 如此，藉由使灰階資料匯流排23與灰階資料輸入端子12 斷開，而利用灰階資料匯流排23之配線電容，使鎖存電路 130392.doc -22- 200910311 5 η所鎖存之進行-次掃描時之最後之灰階資料殘留 於灰階資料匯流排23中。對該殘留之灰階資料DATA之下 位之4個位tgDO〜D4進行解碼而使延遲選擇電路24動作， 藉此確定資料載入訊號L〇AD(DL)之延遲時間。 此處對使用灰階貧料DATA之下位之4個位元〜D4之 理由作以下說明。u is connected to the input terminal of the corresponding delay circuit 22. The switches SW0 to SW15 correspond to the output terminals YQ to Y15, respectively, and are turned on when the switch selection signals from the output terminals Υ0 to Υ15 are valid. The delay circuit 22 is connected in series with the series circuit of the delay circuit 22, and the output terminal of the delay circuit connected to one end of the switch SW1 is the output terminal of the data loading signal L〇AD (DL). The operation of the delay selection circuit 9 configured as a mode will be described. For example, when the control signal SEL is selected as "〇〇〇〇, the decoder 21 outputs a valid switch selection signal from the output terminal γ〇, so only the switch swo is turned on. In this case, the data loading signal L 〇AD, without delay via switch SW0, but as data load signal 〇 〇 〇 (1) to output 0 and 'when selection control signal SEL is "0001", decoder 21 output from output terminal Y1 is valid The switch selects the signal, so the switch SW1 is turned on. In this case, the data loading signal L〇AD is delayed by the delay time of the first-order degree provided by the second-stage delay circuit 22, and is loaded as the data tfl number LOAD ( DL) is output. Thus, the delay time is different by the selection control signal SEL input from the input terminals A to D. Therefore, the control signal SEL is selected as "111 1" 130392.doc • 18-200910311 " Γ 'The data load signal LOAD is delayed by the delay circuit 22' by a maximum delay of 15 degrees. Fig. 4(a) to (c)' show the transmission of gray scale data corresponding to the selection control signal SEL. As shown in Fig. 4(a), when the control signal SEL is selected as ",", as described above, only the switch SW0 is turned on, thereby being loaded as data without delay. The signal LOAD (DL) is output. In this case, the gray scale data DATA is taken into the hold circuit 6-1 from the latch circuits 5-1 to 5-n at the timing specified by the data load signal LOAD (DL). 6_n. Then, as shown in Fig. 4(b), in the case where the selection control signal SEL is 〇111,, only the switch SW7 is turned on, thereby performing the delay time Ta of the delay circuit 22 of the 7th order. After the delay, it is output as the data loading signal L〇AD(DL). In this case, compared with the case of Fig. 4(a), the grayscale data DATA is delayed by the data loading time specified by the afL LOAD (DL). After the delay time Ta, the latch circuits 5-1 to 5-n are taken in to the holding circuits 1 to 6-n. Further, as shown in Fig. 4(c), when the control signal SEL is selected as "im" Only the switch S W1 5 is turned on, whereby the delay time Tb of the delay circuit 22 of the level 15 is delayed, and then output as the data load signal l〇ad(dl). In this case, compared with the case of FIG. 4(a), the gray scale data DATA is at the timing specified by the data loading signal LOAD (DL), and the delay is delayed by the delay time Tb and is taken from the latch circuits 5-1 to 5-n. Into the holding circuit 6_丨~6_ η ° As shown in Fig. 2, the holding circuit unit 6 holds the gray scale data DATA used when the DAC unit 7 selects the gray scale voltage. Therefore, by taking the grayscale data into 130392.doc -19-200910311, the holding circuit section 6 (maintaining the grayscale data DATA which is maintained in the circuitization) is turned off from the DAC section 7 From the tenderness, the gray level of the change is changed. The result is ^^1, the output is output by the output buffer unit 8, and & is supplied to the liquid crystal display panel ^ and φ ^ each pixel. The gray level f#DA__ is held by the delay to the ## circuit unit 6, and the heart is taken in (becael transmission), and the gray level electric (drive signal) output from the data (4) "3Ι is also delayed. 2, the data f: 19. Thereby, if each data 1 Γ has a control terminal right, the selection control signal SEL is input between each Beca driver 31, and the drive output is changed by the same timing.... In this way, it is possible to prevent each data from driving the cattle in the circuit of the first order in the circuit to make the horizontal line in the data driver. In contrast, the data driver j should be equipped with a load delay or the like to load the signal line only. Early-time adjustment, so no additional configuration is required. So, data driver In the 31st, the previous circuit of the 3# bed on the side of the squadron makes the liquid drive: change "but in the data drive 31, that is, in the entire liquid crystal display panel! The effect of reducing the excess light shots of the prior art is as follows: I. As in the previous circuit shown in Fig. 12, the dynamic output produces a timing of change, and the delay circuit is set in the internal drive block of the data drive, or for each split. In contrast, the data path and the wiring setting enable the delay circuit 22 of the data port 43 1 to be delayed only by the input unit and the ^L〇AD, so that I30392.doc •20· 200910311 can be The increase in the layout area is suppressed to a minimum 'and does not increase the number of wirings of the transmission data into the signal L〇AD(DL). 吏Transfer, and preferably, drive output between all data drivers 31 The timing is different. However, even if the timing of the change of the output of the at least one data driver 3 data driver 3 to the 傲#傲儿〇士广”, J%勒 output is different, the above effect can be obtained at the lowest. [ 2 data driver] Γ u Fig. 5 shows the configuration of the second data driver 32 used as the data driver 3. Fig. 6 shows the configuration of the delay selection circuit 24 in the data driver 32 as shown in Fig. 5, and the data drive inch% Similarly to the burglary 31, the lean drive driver 32 includes a shift register circuit 4, a latch circuit unit 5, a hold circuit unit 6, a relay unit 7, an output buffer unit 8, and a reference power source correction circuit 1A. The material driver 32 is provided with a trickle selection circuit 24 instead of the above-described delay selection circuit 9. The delay selection circuit 24 shown in Fig. 6 includes a decoder 21 and 15 delay circuits 22 in association with the delay selection circuit 9. 2 & Switch Therefore, 4 is a detailed description of the decoder 21 and the delay circuit 22 in relation to 8 to 0 to SW15.乂 开 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' Input to input terminal A~ body and s, from the transmission line of the lower 4 bits το input to the second place, 2nd place D1, 3rd bit D2, and 4th place 〇4 (hereinafter referred to as It is called the lower 4 bits D〇~〇4), and the lower 4 bits of the 130392.doc 200910311 are the 4 bits below the gray level data bus 23 of the grayscale data DATA. The latch circuits 5-1 to 5-n latch the gray scale data transmitted from the module substrate 2 to the data driver 32. After the latch circuits 5_•1~5-n take in all the grayscale data, the data driver 32 is not connected to the grayscale data DATA from the module substrate 2. The gray scale material DATA from the module substrate 2 is shared by all the data drivers 32. Therefore, if the gray scale data input terminal 12 of the data p driver 32 is input with the gray scale data DATA ', the input buffer or gray of the data driver 32 is used. The order data bus 23 operates to consume excess current. Thus, after the latch circuits 5_丨 to 5_n take in the gray scale data DATA, the gray scale data bus 2 in the data driver 32 is disconnected from the gray scale data input terminal 12 to be in a floating state. Specifically, as shown in Fig. 5, a switch 29 is provided in advance in the gray scale data bus. The switch 29 is such that when the output data of the latch circuits 5] to 5_n is changed, it is confirmed that the gray scale data is latched in the latch U paths 5-1 to 5-n. In the bus bar 23, the above switch 29 is turned off. The control of the switch 29 is performed by the latch circuit of the last stage shift register output from the index shift register circuit 4 to select the signal END or the control signal generated based on the signal. - Thus, by controlling the switch 29 inside the data drive 32, there is no need to input a signal for controlling the switch 29 from the external data driver 32. Thus, the terminals of the data drive 32 are not increased. Thus, by disconnecting the gray scale data bus 23 from the gray scale data input terminal 12, the wiring capacitance of the gray scale data bus 23 is utilized to latch the latch circuit 130392.doc -22- 200910311 5 η The last gray scale data at the time of performing the scan is left in the gray scale data bus 23 . The four bits tgDO to D4 below the remaining gray scale data DATA are decoded to operate the delay selection circuit 24, thereby determining the delay time of the data loading signal L〇AD(DL). Here, the reason for using the 4 bits to D4 below the gray scale lean material DATA will be described below.

ϋ ，將灰階資料DATA用於確定延遲時間日寺，以顯示之内容 為並非單色晝面之圖像(靜態圖像或者動態圖像)為前 提。故而，1個水平掃描期間之灰階資料必然產生變化， 因此於複數個資料驅動器32間灰階資料data不同之可能 性（概率）高於單一色晝面之情形。 通常之圖像顯示時’灰階資料DATA之下位位元表示微 j之灰I5白义化，1¾上位位元表示較大之灰階變化。於並非 顯示單-色之情形時’圖像必然產生變化，但於灰階差較 少之情形時’可認為上位位元不產生變化，而下位位元不 同口此#由於資料驅動器32間利用灰階資料DATA不 同之下位位7L DG〜D4 ’而較之利用上位位元之情形，延遲 選擇電路24中之延遲時間於資料驅動器”間不同之可能性 (概率）更高。 再者，於大多係顯示灰階差較大之圖像之情形時，並未 限於下位位請〜D4 ’亦可利用灰階f料data之上位之4 個位元等其他資料位元。 士此f料驅動|§32中，提供至延遲選擇電路24之灰階 資料data之下位之4個位於驅動器32間不同之概率較高， 130392.doc -23· 200910311 因此可防止各資粗 + 貝料驅動器32之驅動輸出以相同時序產 化，藉此，與資粗妥 ㈣相同’可獲得多餘韓射得以降 低之政果，且可知 抑制-貝料驅動器32之布局面積或傳輸資料 ’ D(DL)之配線數之增加。而且，將灰階資料 此二 1二分用於資料載入訊EL0AD之延遲控制，因 此“上述-貝料驅動器31中所使用之選 此’可肖料驅㈣取料數， Γ [第3資料驅動器] 為資㈣動器3而使用之第3資料驅動器^ 構成。圖8表不音 # 1 枓驅動15 33中之延遲選擇電路25之構 成0 如圖7所示，盘杳极 一、科驅動器叫目同，資料驅動器33具有 才日ί示用移位暫存器雷饮 ...^ 、鎖存電路部5、保持電路部ό、 〇八（：#7、輸出緩衝器邱 及參考電源校正電路10〇又， 負料驅動器3 3，1古.犯 電路9。 ” 擇電路25而代替上述延遲選擇 如圖8所示，與上述延遲 啟選擇電路24相同，延遲選擇電 路25具有解碼器2〗、丨 sw〇〜sWl5。缺而，資…遲“22、及16個開關 , ，、、、 貝科驅動器33進而包含鎖存器％。 鎖存器2 6為4位元D刑趨六。。 々仅Μ型鎖存盗，對上述灰階資料data_ 之下位之4個位元D0~D4進行 ηΛ 返仃鎖存。故而，下位之4個位元 D0〜D4，輸入至鎖存器％ 谷、及輸入知子D。又，鎖存 ° 輸出端Μ，分別連接於解碼器21之相岸輸入 端子Λ〜D。又，銷在雷玖嚶神 寻目㈣入 選擇矾號END輸入至鎖存器26之 I30392.doc -24- 200910311 各級時脈輸入端子k。 標用移位暫存号電跋鎖存電路選擇訊號END，係自指 路選擇訊號。 <最後級移位暫存器輸出之鎖存電 end有式:二:資料驅動器33中，鎖存電路選擇訊號 D…二？電路部5中之鎖存電路“鎖存灰階資料 由鎖存哭二 料〇似之下位之4個位元D。* B〇 、子而輪入至解碼器2】。藉此，解碼器21對下 ^立之4個位元D0〜D4進行解碼而選擇開關SW0〜SW15中2 此：資料‘驅動器33，與資料驅動器32相同，亦可押得 =輕射得以降低之效果，且可抑制資料驅動器33之;局 、或傳輸載入訊號L〇AD(DL)之配線數或端子 加。 日 上述資料驅動器32中’於向鎖存電路部5取入灰階資料 〇ΑΤΑ之後’設為不再接受來自模組基板2之灰階資料 DATA/ X ’資料驅動器32中，必須以灰階資料匯流排^ 呆持取後取樣之灰階資料DATA之方式，使灰階資料匯流 排23與灰階資料輸入端子。斷開而成為浮接狀態。 與此相對，資料驅動器33中，將用於選擇延遲時間之資 料财子於鎖存m故而，藉由將灰階f料輸人端子12 口定於GND(接地)電位等，而防止輸入緩衝器或内部匯流 排動作即可，纟需如資料驅動器32般設灰階資料匯流排Μ 2浮接狀態。通常，浮接狀態之匯流排中保持之電位不穩 又，有可能會因外部干擾而消失。因此，資料驅動器33， 13〇392.d〇c •25_ 200910311 較之資料驅動器32可提 [第4資料驅動器] 持之可罪性。 圖9係表示作為資料驅動 之構成。圖10表示資料驅動㈣：之第4貧科驅動器34 成。 動器3种之延遲選擇電路27之構 如圖9所示，盥眘粗雖心„口 指標用移位& A’31相同，請驅動器34具有 DAC部7 電路4、鎖存電路部5、保持電路部6、 c ㉟出緩衝器部8、及參考 資料驅動考U 曰— 电得1ϋ。又， 電路，且延遲選擇電路27而代替上述延遲選擇 且具有計數器28。 π十數益2 8，传耕白咨粗 CLK1、隹〜 … 枓動器34之外部輸入之時脈訊妒 數數之4位元計數器。該計數器28，-〇進㈣ 數3 ( 1 3個時脈、g洋φ目 ' 出現以位而使計數值COUNT歸〇，# & 上述鎖存電路選擇訊號咖而停止計數。 错由 ο =之時脈訊號⑽具有與時脈訊號咖（移位時脈）相 i週期:其中，該時脈訊號CLK1，係自模組基板# :二與貝料驅動器3 4之灰階資料D A T A之取樣(資料取 輸入。當資料取樣結束時停止供給時脈訊 " '核@ 28對時脈訊號CLK進行計數之情 因資料取樣後計數器28便停止計數故而無妨。與此相董， 於:數器28開始動作時’為了使計數正常地開始動作，計 數器28必須於開始進行資料取樣之前進行動作。然而，時 :訊號CLK，與灰階資料DATA同時開始向資料驅動器W ί、給。故而，計數器28，無法於資料取樣前開始進行動 130392.doc -26- 200910311 作。由此，必須將與資料取 、關而持續輸入之時脈訊號 CLK1取入至資料駆動器34 之内。P且提供至計數器28。 如圖10所示，延遲選擇雷 冤路27中，將計數器28之計數 COUNT輸入至輸入端子 丨双徂 。解碼器21，對該計數值 COUNT進行解碼而選擇開關s w()〜s^ $中之一者。 此處，表1表示使240個輸出之資料驅動器34進行動作之 情形時向解碼器21之輸入端子a〜d輸入之值。 表1 資料驅動器 之連接順序 計數器停止前 之時脈數 計數器之 溢位次數 之計數 解碼器之輪入僅 1 240 18 一 D c Β A 2 480 36 6 0 1 1 0 3 720 55 --___ 1 1 0 0 4 960 73 —_5 0 1 0 1 5 1200 92 —_il 1 0 1 1 6 1440 110 0 1 0 0 7 1680 129 ---!〇 1 0 1 0 8 1920 147 —_3 卜0 0 卜1 卜1 9 10 2160 166 —-Λ. —__2 1 Λ 0 n 0 1 1 11 2400 2640 184 203 1 u 0 1 0 0 0 12 2880 221 0 0 0 1 13 3120 240 7 Λ 0 1 1 1 υ •~~— 0 0 0 0 π "呢初斋甲，敢平輸入有 灰階資料DATA之第i級資料驅動器34，對洲固輪出程度 之灰階資料DATA進行取樣。故而，於輸人有時脈訊號 CLKm4G個時脈時，即取人有μ個灰階資❹ΑτΑ時， 财子電路部5結束鎖存，與此同時計數器28停止計數。此 時，輸入至解碼器21之計數器值c〇UNTm〇進制表示時 為 6([DCBA] = [01l〇])。 上述第1級資料驅動器34之下—與液晶顯示面連接之 130392.doc -27- 200910311 貝料驅動β 34 ’以第1級資料驅動器34取樣後之謂個時脈 完成取樣。此時，計數器28停止計》。其計數器值 COUNT以10進制表示時為。 同樣’直至第13級資料驅動器34為止，作為輸入至解碼 器21之輸人端子A_D^f料，可設㈣種組合。自第从級 資料驅動器34開始’係對第1級資料驅動器34以下之重 複，但對變更輸出時序而言為充足之組合數。ϋ The grayscale data DATA is used to determine the delay time of the temple, so that the content is not a monochrome image (still image or moving image). Therefore, the gray scale data during one horizontal scanning period necessarily changes, so that the possibility (probability) of the gray scale data between the plurality of data drivers 32 is higher than that of the single color plane. In the normal image display, the bit position under the gray scale data DATA indicates that the gray of the micro j is white, and the upper bit of the 13⁄4 represents a large gray scale change. In the case where the single-color is not displayed, the image must change, but when the gray-scale difference is small, it can be considered that the upper-level bit does not change, and the lower-order bit is different. This is due to the use of the data driver 32. The gray level data DATA differs from the bit 7L DG to D4 ', and the delay time in the delay selection circuit 24 is higher (probability) between the data driver" than in the case of using the upper bit. In most cases where an image with a large gray-scale difference is displayed, it is not limited to the lower position. Please use D4' to use other data bits such as 4 bits above the gray-scale f-data. In §32, the probability that the four bits below the grayscale data of the delay selection circuit 24 are located between the drivers 32 is higher, 130392.doc -23·200910311 thus preventing the respective coarse + feed drivers 32 The drive output is produced at the same timing, whereby the same as the capital (four) is the same as the fact that the excess Han shot can be reduced, and the layout area of the suppression-bedding driver 32 or the wiring of the transmission data 'D(DL) can be known. The number has increased. The gray level data is used for the delay control of the data loading EL0AD, so "the selected one used in the above-mentioned beaker driver 31 can be used to read the number of materials (4), Γ [3rd data driver] The third data driver ^ used for the (four) actuator 3 is constructed. Fig. 8 shows the structure of the delay selection circuit 25 in the 枓 drive 15 33. As shown in Fig. 7, the disk drive 1 and the drive are called the same, and the data drive 33 has the shift register. Thunder drink...^, latch circuit unit 5, hold circuit unit ό, 〇8 (:#7, output buffer qiu and reference power supply correction circuit 10〇, negative material driver 3 3,1 ancient. 9. The circuit 25 is selected instead of the delay selection as shown in FIG. 8. Like the delay start selection circuit 24 described above, the delay selection circuit 25 has the decoder 2, 丨sw〇~sWl5. And 16 switches, , , , , and the Bec driver 33 in turn contain the latch %. The latch 26 is a 4-bit D penalty. 6. Only the 锁存 type latch thief, the above gray scale data data_ The lower four bits D0~D4 perform ηΛ return latching. Therefore, the lower four bits D0~D4 are input to the latch % valley and the input knower D. Also, the latch output terminal Μ Connected to the phase input terminals Λ~D of the decoder 21 respectively. In addition, the pin is input to the latch in the Thunder God search (4) input selection END END 26 I30392.doc -24- 200910311 Clock input terminal k of each level. The shift register temporary number is used to select the signal END, which is the self-referential signal. <Last stage shift register output The latched electric end has the following formula: 2: in the data driver 33, the latch circuit selects the signal D... The latch circuit in the circuit unit 5 "latches the gray scale data by latching the crying binary material like the lower 4 The bit D.*B〇, the sub-wheel is inserted into the decoder 2]. Thus, the decoder 21 decodes the lower four bits D0 to D4 and selects the switches SW0 to SW15. The driver 33, like the data driver 32, can also be used to reduce the effect of light radiation, and can suppress the number of wirings or terminals of the data driver 33 or the transmission load signal L〇AD (DL). In the above data driver 32, 'after the grayscale data is taken into the latch circuit section 5' is set to no longer accept the grayscale data DATA/X' from the module substrate 2, and the data driver 32 must be grayscale. Data bus row ^ Stay in the grayscale data DATA of the sample after sampling, so that the grayscale data bus 23 and grayscale The data input terminal is disconnected to be in a floating state. On the other hand, in the data driver 33, the data for selecting the delay time is latched, so that the gray-scale f-material input terminal 12 is fixed. At the GND (ground) potential, etc., to prevent the input buffer or internal busbar action, it is not necessary to set the gray-scale data busbar Μ 2 floating state as the data driver 32. Usually, the floating state bus is kept in the busbar. The potential is unstable and may disappear due to external interference. Therefore, the data driver 33, 13〇392.d〇c •25_ 200910311 is more sinful than the data driver 32 [4th data driver]. Fig. 9 shows the configuration as a data drive. Figure 10 shows the data driven (4): the 4th poor driver 34. The configuration of the delay selection circuit 27 of the three types of actuators is as shown in FIG. 9. The drive index 34 has the DAC unit 7 circuit 4 and the latch circuit unit 5, although the heart index is the same as the shift & A'31. The hold circuit unit 6, the c 35 output buffer unit 8, and the reference data drive test unit are further connected to the reference data drive unit. Further, the circuit and the delay selection circuit 27 are substituted for the delay selection and have the counter 28. π 十数益2 8, the ploughing white CLK1, 隹~ ... The 4-bit counter of the external input of the pulsator 34. The counter 28, - 〇 (4) number 3 (1 3 clocks, g The ocean φ mesh ' appears in bits to make the count value COUNT blame, # & The above latch circuit selects the signal coffee and stops counting. The error clock signal (10) with ο = has the clock signal (shift clock) Phase i period: wherein the clock signal CLK1 is sampled from the module substrate #: 2 and the gray material data DATA of the material feeder 34 (data input input. When the data sampling ends, the supply pulse is stopped). 'Nuclear @ 28 counts the clock signal CLK. After the data is sampled, the counter 28 stops counting, so there is no In response to this, when the counter 28 starts to operate, the counter 28 must operate before starting the data sampling in order to start the counting normally. However, the signal CLK starts at the same time as the grayscale data DATA. The data driver W ί, is given. Therefore, the counter 28 cannot be started before the data sampling 130392.doc -26- 200910311. Therefore, the clock signal CLK1 with the data input and off and continuous input must be taken into Within the data actuator 34, P is supplied to the counter 28. As shown in Fig. 10, in the delay selection ramp 27, the count COUNT of the counter 28 is input to the input terminal 徂 double 徂. The decoder 21, the count value COUNT decodes and selects one of the switches sw() to s^$. Here, Table 1 shows the values input to the input terminals a to d of the decoder 21 when the 240 output data drivers 34 are operated. Table 1 Data driver connection sequence count before the counter stop pulse count counter overflow count decoder wheel only 1 240 18 a D c Β A 2 480 36 6 0 1 1 0 3 720 55 --___ 1 1 0 0 4 960 73 —_5 0 1 0 1 5 1200 92 —_il 1 0 1 1 6 1440 110 0 1 0 0 7 1680 129 ---!〇1 0 1 0 8 1920 147 —_3 Bu 0 0 Bu 1 Bu 1 9 10 2160 166 —-Λ. —__2 1 Λ 0 n 0 1 1 11 2400 2640 184 203 1 u 0 1 0 0 0 12 2880 221 0 0 0 1 13 3120 240 7 Λ 0 1 1 1 υ •~~— 0 0 0 0 π " At the beginning of the year, Ding Ping input the gray level data DATA of the i-th level data driver 34, and sample the gray level data DATA of the degree of the continent. Therefore, when the input pulse signal CLKm4G clocks, that is, when there are μ grayscale resources τΑ, the financial circuit unit 5 ends the latch, and at the same time, the counter 28 stops counting. At this time, the counter value c 〇 UNTm input to the decoder 21 is 6 ([DCBA] = [01l 〇]). The above-mentioned first level data driver 34 is connected to the liquid crystal display surface 130392.doc -27- 200910311. The material driving β 34 ' is sampled after the first level data driver 34 is sampled. At this time, the counter 28 stops counting. When the counter value COUNT is expressed in decimal. Similarly, up to the 13th level data driver 34, as the input terminal A_D^f input to the decoder 21, (four) combinations can be set. Since the slave data driver 34 starts to repeat the first level data driver 34, it is a sufficient combination number for changing the output timing.

可藉由設置進行上述動作之計數器28，而與資料驅動器 32相同地’使向保持電路部6取入灰階資料之時序於資料 驅動器34間不同。藉此，可獲得多餘輻射得以降低之效 果，並且可抑制資料驅動器34之布局面積，或傳輸資料載 入訊號L〇AD(DL)之配線數之增加。又，與上述資料驅動 器32相同，不使用選擇控制訊號肌，因此提供至延遲選 擇電路27之輸入訊號僅為時脈訊號CLK]即可。故而，於】 個資料驅動器34中追加用於輸人時脈訊號clkr輸入端 子。因此’可抑制端子數增加，且可將各資料驅動器^之 輸出時序可靠地設置為不同時序。 此處’將計數器28之重設值（溢位值）設定為13。然而， 必須根據資料驅動器3 4之輸出數而將重設值變更為適當 值。 作為極端之示例’表2表示於130個輸出 丨口彻出之貧料驅動器34 中使用以13為重設值而進行重設之計數 T數姦28的情形。如 此，向解碼器21之輸入資料，於所有資料驅動器辦均為 pCBA]，_]，且於所有資料驅動器34中輸出之時序均 130392.doc -28- 200910311 相同。 表2 Ρ資料驅動器 之連接順序 計數器停ϋ 之時脈數 計數器之 __溢位次數 停止時之計數 值(10進制） 解碼器之輸入 值 1 D C Β A 2 260~~~'~~ 1U 0 0 0 0 0 3 390~~~~~~ 20 0 0 0 〇 0 4 520 30 0 0 0 〇 0 5 "~650~~~~~ 40 0 0 0 0 0 6 7 780~ 50 ~60~~ 0 0 0 〇 [7〇~~ 0 0 8 910 ZZU〇4〇~~ 70 80 0 0 0 0 0 0 U 0 9 ll7〇 0 0 0 0 0 10 ~~~~Ϊ300 90 0 0 0 0 0 11 "Τ/Ϊ^ΓΡΓ—— 100 0 0 0 0 0 110 120 12 0 〇 0 0 0 0 _1_3_ 姑，卜主 —312α 130 0 — 0 0 0 0 0 0 0 0By setting the counter 28 for performing the above operation, the timing of taking the gray scale data to the holding circuit unit 6 in the same manner as the data driver 32 can be different between the data drivers 34. Thereby, the effect of reducing the excess radiation can be obtained, and the layout area of the data driver 34 can be suppressed, or the number of wirings for transmitting the data carrying signal L〇AD (DL) can be increased. Further, similarly to the above-described data driver 32, the selection control signal muscle is not used, and therefore the input signal supplied to the delay selection circuit 27 is only the clock signal CLK]. Therefore, the data driver 34 is added to the input clock signal clkr input terminal. Therefore, the number of terminals can be suppressed from increasing, and the output timing of each data driver can be reliably set to different timings. Here, the reset value (overflow value) of the counter 28 is set to 13. However, the reset value must be changed to an appropriate value based on the number of outputs of the data drive 34. As an example of extremes, Table 2 shows the case where the count of the resetting of the 130 output switches 34 is repeated using the reset value of 13 as the reset value. Thus, the input data to the decoder 21 is pCBA], _] for all data drivers, and the timings for output in all data drivers 34 are the same 130392.doc -28- 200910311. Table 2 连接 Data driver connection sequence counter stop clock number counter __ count value when the number of overflow times stops (10 decimal) Input value of the decoder 1 DC Β A 2 260~~~'~~ 1U 0 0 0 0 0 3 390~~~~~~ 20 0 0 0 〇0 4 520 30 0 0 0 〇0 5 "~650~~~~~ 40 0 0 0 0 0 6 7 780~ 50 ~60 ~~ 0 0 0 〇[7〇~~ 0 0 8 910 ZZU〇4〇~~ 70 80 0 0 0 0 0 0 U 0 9 ll7〇0 0 0 0 0 10 ~~~~Ϊ300 90 0 0 0 0 0 11 "Τ/Ϊ^ΓΡΓ——100 0 0 0 0 0 110 120 12 0 〇0 0 0 0 _1_3_ 姑,卜主—312α 130 0 — 0 0 0 0 0 0 0 0

一 * ^ %叫又人巧Η，則如表3所示，直至 11級貧料驅動器34為止，解碼器21之輸入資料為不同 值0 _ .可藉由調整重設值，而使解碼器21之輸入資料不 同之貝料驅動器34之數量達到最大。 ϋ 表3 資料驅動器 之連接順序 °「歌器停止前 數 — --- 計數器之 溢位次數 11 停止時之計數 值(〗〇進制） 9 . 解碼器之輪入值 1 2 D 1 C 〇 Β 〇 A 1 3 4 [^3|〇 23 35 ~η~-5~- 0 〇 1 1 1 π 1 1 5 ~~~ 47 3 0 0 υ 1 1 1 6 7 - 59 70 ί ~-10 0 0 0 1 ' 8 ------ 82 8~ 1 —1 0 0 1 0 0 0 9- -^^1040 94 6 10 Ί ^Λπ 106 -4~~~- U 1 1 0 0 1 0 〇 11 118 2 ~— 0 0 1 〇 12 id£〇 130 0 0 — 1 0 Λ 0 Λ 0 13 —JL^6〇 141 9~ --- 153 r _ 7 0 u 1 υ 1 1 1 130392.doc •29- 200910311 再者，使用表】至表3所進行之上述說 為第1之資料驅動器34(最前頭驅動 對接順序 謝錢行取樣時，與液晶顯示面板】連接之^灰^資料 哭34之戶斤有 > 料驅動 』之6十數益28自"_"開始計數。為了 動 以如此方式進行動作，而必須將上述最前彳㈣ 料取樣之時序提供至所有資料驅動器3“然而：始資 則必需有用以輸入提供時序之訊號之端子，因此匕’ 驅動器34之端子數增加。 導致貝料 由：:：為與使資料驅動器34進行動作之電源接 夺’使所有資制動器34之計數㈣進行動作。藉此 有汁數器28之計數值c㈤财僅 >次，丨 只·動态開始進 仃貝枓取樣時之計數器28之計數值 态21之輸入值於資料驅動器“間不同。例如，表1至表3之 值表示最前頭驅動器開始進行資料取樣時，計數器28^ [DCBA] = [0000]開始計數之情形之例，開始進行資料取樣 時之計數值COUNT，不必__]，例如若為陶]，則 各表中之值均僅錯開！，而解碼器21之輸入同樣地為不同 值 [實施形態之適用] 曰本實施形態中，，十資料驅動器3適用於液晶模組ι〇〇(液 晶顯示裝置）之例進行說明。然而，本發明，亦可適用於 可使用相同資料驅動器3之液晶顯示裝置以外之顯示裝 置’例如有機EL(Electro luminescence，電致發光）顯示 置。 •…、义 130392.doc • 30- 200910311 本發明並未限定於上述實施形態，而可 — 範圍内進行各種變更。即，於請求 所不之 當變更之技術方法加以組合而得之實二内進行適 明之技術範圍内。 實施形態亦包含於本發 本發明之顯示驅動裝置，使鎖存電 &入sΑ 崎甲鎖存之灰階資料 取至保持電路之時㈣每個資 獲得多餘輕射得以降低之效果，且可抑制資料驅動= f υ ==配線數之增加。藉此，可將本發明之顯示驅動裝 置軚佳地利用於液晶顯示裝置等顯示裝置中。 【圖式簡單說明】 圖圖1係本發明之一實施形態之液晶模組之構成之方塊 圖2係表示用作上述液晶模組中之資料驅動 驅動器之構成之方塊圖。 、 圖3表不上述第1資料驅動器中之延遲選擇電路 方塊圖。 構成之 圖4(a)至〇)係表示上述延遲選擇電路之動作之時序圖。 驅作上述液晶模組中之資料驅動器之第2資料 驅動器之構成之方塊圖。 圖6表不上述第2資料驅動器中之延遲選擇電 方塊圖。 構成之 圖7係表不用作上述液晶模組中之資料驅動 驅動器之構成之方塊圖。 弟巧枓 圖8係表不上述第3資料驅動器中之延遲選擇電路之構成 I30392.doc 200910311 之方塊圖。 中之資料驅動器之第4資料驅動 圖9係表示用作液晶模組 器之構成之方塊圖。 遲選擇電路之構 、圖1〇係表示上述第4資料驅動器中之延 成之方塊圖。 圖11係表示先前之資料驅動 罚益之構成之方塊圖。 圖12係表示先前之其他資料驅 構成之方_。 an己憶體電路之 【主要元件符號說明】 1 液晶顯示面板 3 資料驅動器 5 鎖存電路部 6 保持電路部 7 DAC部 9 延遲選擇電路 19 選擇控制端子 21 解碼器（解碼器電路） 22 延遲電路（延遲時間設定電 23 灰階資料匯流排 24 > 25 延遲選擇電路 26 鎖存器 27 延遲選擇電路（可變時延遲 28 計數器 31-34 資料驅動器' 130392.doc -32- 200910311 100 液晶核組 CLK1 時脈訊號 COUNT 計數值 DATA 灰階資料（顯示資料） DO 〜D4 下位之4位元 END 鎖存電路選擇訊號 LOAD 資料載入訊號 LOAD(DL) 貧料載入訊號 SEL 選擇控制訊號（控制訊號） SWO 〜SW15 開關（延遲時間選擇電路） doc -33- 130392.docA * ^ % is called a clever trick, as shown in Table 3, until the 11-level lean driver 34, the input data of the decoder 21 is a different value 0 _. The decoder can be adjusted by adjusting the reset value The number of feeders 34 with different input data of 21 is the largest. ϋ Table 3 Data driver connection order ° "Number of songs before stopping - --- Number of overflows of the counter 11 Count value when stopped (〗: 9) Derivative value of the decoder 1 2 D 1 C 〇 Β 〇A 1 3 4 [^3|〇23 35 ~η~-5~- 0 〇1 1 1 π 1 1 5 ~~~ 47 3 0 0 υ 1 1 1 6 7 - 59 70 ί ~-10 0 0 0 1 ' 8 ------ 82 8~ 1 —1 0 0 1 0 0 0 9- -^^1040 94 6 10 Ί ^Λπ 106 -4~~~- U 1 1 0 0 1 0 〇 11 118 2 ~— 0 0 1 〇12 id£〇130 0 0 — 1 0 Λ 0 Λ 0 13 —JL^6〇141 9~ --- 153 r _ 7 0 u 1 υ 1 1 1 130392.doc • 29- 200910311 Furthermore, the above-mentioned data driver 34, which is referred to as Table 1 to Table 3, is connected to the liquid crystal display panel when the front-end drive docking sequence is sampled by the liquid crystal display panel. The user has a > material drive's 6 tens of benefits 28 from "_" to start counting. In order to move in this way, the timing of the above-mentioned first 四 (four) material sampling must be provided to all data drives 3 "however: The capital is required to input the terminal that provides the timing signal, so 匕The number of terminals of the driver 34 is increased. The bedding is caused by ::: is the power supply for the operation of the data driver 34. The counting (4) of all the brakes 34 is operated. Thus, the count value c of the juice counter 28 (five) Only once, the number of input values of the counter value of the counter 28 when the sample is dynamically sampled is different from the data driver. For example, the values of Tables 1 to 3 indicate that the top drive starts. When data sampling is performed, the counter 28^ [DCBA] = [0000] starts counting. The count value COUNT at the time of data sampling is started. It is not necessary to __]. For example, if it is ceramic, the values in each table are The input of the decoder 21 is similarly different. [Application of the Embodiment] In the present embodiment, the ten data driver 3 is applied to an example of a liquid crystal module (liquid crystal display device). However, the present invention is also applicable to a display device other than a liquid crystal display device that can use the same data driver 3, such as an organic EL (Electroluminescence) display. •, 130130.doc • 30-20 0910311 The present invention is not limited to the above embodiments, and various modifications can be made within the scope of the invention. That is, it is within the technical scope of the stipulation that the technical methods of the change are not combined. The embodiment is also included in the display driving device of the present invention, so that when the gray-scale data of the latching power is input to the holding circuit (4), each of the funds obtains the effect of reducing the extra light radiation, and Can suppress data drive = f υ == increase in wiring number. Thereby, the display driving device of the present invention can be preferably used in a display device such as a liquid crystal display device. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of a liquid crystal module according to an embodiment of the present invention. FIG. 2 is a block diagram showing a configuration of a data driving driver used in the above liquid crystal module. Figure 3 shows a block diagram of the delay selection circuit in the first data driver. 4(a) to 〇) are timing charts showing the operation of the delay selection circuit. A block diagram of the structure of the second data driver driving the data driver in the above liquid crystal module. Fig. 6 shows a block diagram of the delay selection in the second data driver. Figure 7 is a block diagram showing the configuration of a data drive driver not used in the above liquid crystal module. Figure 8 is a block diagram showing the composition of the delay selection circuit in the third data driver I30392.doc 200910311. The fourth data drive of the data drive in Fig. 9 is a block diagram showing the configuration of the liquid crystal module. The structure of the late selection circuit, Fig. 1 is a block diagram showing the extension of the above fourth data driver. Figure 11 is a block diagram showing the composition of the prior data driven penalty. Figure 12 is a diagram showing the other constituents of the previous data drive. [Main component symbol description] 1 Liquid crystal display panel 3 Data driver 5 Latch circuit unit 6 Hold circuit unit 7 DAC unit 9 Delay selection circuit 19 Selection control terminal 21 Decoder (decoder circuit) 22 Delay circuit (delay time setting power 23 gray scale data bus 24 > 25 delay selection circuit 26 latch 27 delay selection circuit (variable time delay 28 counter 31-34 data driver '130392.doc -32- 200910311 100 liquid crystal core group CLK1 clock signal COUNT count value DATA gray scale data (display data) DO ~ D4 lower 4 bits END latch circuit selection signal LOAD data loading signal LOAD (DL) poor material loading signal SEL select control signal (control signal ) SWO ~ SW15 switch (delay time selection circuit) doc -33- 130392.doc

Claims (1)

200910311 十、申請專利範園： 1. -種顯示驅動裝置，其係包括根據所輸入之顯示 自複數個灰階電愿中選擇一個輸出之選擇輸出電路，且 於顯示裝置中以級聯（cascade)連接 化者，其特徵在於包括：妾之狀^载之被積體 可交時延遲電路’其係根據控制訊號而決定延遲時 =且使自上述選擇輸出電路輸出上述灰階電塵之輸出 時序以上述延遲時間延遲。 2 ·如凊求項1之顯示驅動裝置，其令 =可變時延遲電路包括：解碼器，其係對含有㈣ :立疋之上述控制訊號進行解碼；延料間設定電路， 係預先設定複數個不同之上 ^ <、逄日守間，及延遲時間 、電路，其係根據上述解碼器之解 邏日卑^之解碼值’自由上述延 :夺間Μ電路所設定之複數個上述延遲時間中選擇— 個。 3’二：！項1之顯示驅動裝置，其令包括輸入端子，其係 ^ :搭載有顯示驅動裝置之顯示裝置所產生之上述控 4·如β求項1之顯示驅動裝置，其中 訊Ϊ述可變時延遲電路利用上述顯示資料作為上述控制 女。月求項1之顯示驅動裝置’其中 t述可變時延遲電路利用一次掃描時最後取入之上述 ‘，、、員不資料作為上述控制訊號。 130392.doc 200910311 6·:之時顯示_置，其中包括保持機構，其係 人=最後取入之上述顯示資料保持 ”貝不育枓之傳輸配線中。 其係保 7. ::未項5之顯示驅動裝置，其中包括鎖存哭 持-次掃描時最後取入之上述顯示資料。 8. 一種顯示裝置，其係向顯示 數個龜_ 攸鞠出上述灰階電壓之複 颂不驅動裝置以級聯連接狀態 者，其特徵在於： 以於上迷顯不面板 動^顯示驅動裝置係如請求項1至7中任—項之顯示驅 上^輪出時序以於至少—個上述顯示驅動裝置與其他 上述頌示驅動裝置之間不同之方式設定。 1 顯示^動裝置，其中包括計數器，其係對 。声^ 之上述顯示資料之取入時序同步之時脈訊 认丁計數，且於顯示驅動裝置結束上述顯示資料取入 之％點停止計數並保持計數值； 上述可變時延遲電路使用上述計數值作為上述控制訊 號。 1〇·如請求項9之顯示驅動裝置，其中 上述計數器於停止計數之前以預先設定之計數值重設 計數值^ 11·種顯不裝置，其係向顯示面板輸出上述灰階電壓之複 數個顯示驅動裝置以級聯連接狀態安裝於上述顯示面板 者’其特徵在於： 130392.doc 200910311 上述顯示驅動裝置係如請求項9或10之顯示驅動裝 置； 上述計數器停止時之計數值以於至少一個上述顯示驅 動裝置與其他上述顯示驅動裝置之間不同之方式設定。 1 2. —種顯示裝置，其係向顯示面板輸出上述灰階電壓之複 數個顯示驅動裝置以級聯連接狀態安裝於上述顯示面板 者，其特徵在於： 上述顯示驅動裝置係如請求項1〇之顯示驅動裝置； 以與上述計數器停止時之計數值不同之上述顯示驅動 衣置的數$達到最大之方式，設定重設上述計數器之計 數值。 130392.doc200910311 X. Patent application garden: 1. A display driving device, which comprises a selection output circuit for selecting one output from a plurality of grayscale electric powers according to the input display, and is cascaded in the display device (cascade) a connector, which is characterized in that: an accommodating body-loaded time-delay circuit is configured to delay the circuit according to the control signal and output the gray-scale electric dust from the selection output circuit The timing is delayed by the above delay time. 2. The display driving device of claim 1, wherein the variable time delay circuit comprises: a decoder for decoding the control signal containing (4): the vertical; and the setting device for the extension, presetting the plural a different above ^ <, the next day, and the delay time, the circuit, according to the decoding value of the above decoder, the decoding value of the above-mentioned delay: the multiple delays set by the circuit Select one of the time. 3’ two:! The display driving device of item 1, comprising: an input terminal, wherein: the display driving device generated by the display device equipped with the display driving device, wherein the display device is driven by a display device The circuit uses the above display data as the above-mentioned control woman. The display driving device of the month 1 of the present invention, wherein the variable delay circuit uses the above-mentioned ‘,,,,,,,,,,,,,,,, 130392.doc 200910311 6:: At the time of display _ set, including the holding mechanism, the person in charge = the last display of the above-mentioned display data to keep in the transmission line of Beyin 。. Its warranty 7. :: 未项 5 The display driving device includes the above display data that is finally taken in when the crying-n-scan is latched. 8. A display device for displaying a plurality of turtles _ 颂 上述 上述 上述 上述 上述The cascading connection state is characterized in that: the display device is driven by the display device, and the display of any of the items 1 to 7 is driven to rotate the timing to at least one of the above display drivers. The device is set differently from the other display driving devices. 1 Displaying a moving device, including a counter, which is a pair. The sound of the above-mentioned display data is synchronized, and the pulse counting is counted, and The display driving device ends the counting of the data entry and stops counting and holds the count value; the variable time delay circuit uses the above-mentioned count value as the control signal. 1) The display drive of claim 9 a moving device, wherein the counter redesigns the value by a preset count value before stopping counting, and the plurality of display driving devices that output the gray scale voltage to the display panel are installed in a cascade connection state. The above display panel is characterized in that: 130392.doc 200910311 The display driving device is the display driving device of claim 9 or 10; the counting value when the counter is stopped is for at least one of the display driving device and the other display driving device The display device is configured to be mounted on the display panel in a cascade connection state by a plurality of display driving devices that output the gray scale voltage to the display panel, and is characterized in that: The device is a display driving device of the request item 1; and resets the counter value of the counter in such a manner that the number of the display driving device that is different from the count value when the counter is stopped is maximized. 130392.doc