TW200905470A - Workload management in virtualized data processing environment - Google Patents
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200905470 九、發明說明: 【發明所屬之技術領域】 本發明大體而言係關於在一資料處理系統中管理工作負 載。更特定而言,本發明係關於在一諸如邏輯分割系統之 分割系統中管理工作負載。 本申請案係關於下列同在申請中之申請案:_______申200905470 IX. INSTRUCTIONS: TECHNICAL FIELD OF THE INVENTION The present invention generally relates to managing workloads in a data processing system. More particularly, the present invention relates to managing workloads in a segmentation system such as a logical segmentation system. This application is related to the following application in the same application: _______
請之名為”於虛擬資料處理環境中管理工作負載 (WORKLOAD MANAGEMENT IN VIRTUALIZED DATA PROCESSING f ENVIRONMENT)”之美國專利申請案第_______號(代理人案 號AUS920060139US2) ;_______申請之名為"於虛擬資料 處理環境中管理工作負載(WORKLOAD MANAGEMENT IN VIRTUALIZED DATA PROCESSING ENVIRONMENT)” 之美國專利 申請案第_______號(代理人案號AUS920060139US3); _______申請之名為”擷取硬體統計資料以用於佔用量計 算、調度效率及排程效率之方法(METHOD TO CAPTURE HARDWARE STATISTICS FOR FOOTPRING CALCULATION, Q DISPATCHING EFFICIENCY AND SCHEDULING EFFICIENCY)11 之 美國專利申請案第_____號(代理人案號AUS920060547US1);。 . 該等申請案已讓與給本發明受讓人,且在此以引用之方式 併入本文中。 【先前技術】 電腦資源之邏輯分割允許在一單一實體機器或處理器組 合體中建立多個系統影像。虛擬化為表示系統成像之術 語,在系統成像中,每一系統影像(亦已知為虛擬機器 129569.doc 200905470 (VM))使用實體電腦系統之共用資源以與其他频邏輯獨立 之方式操作。以此方式,對應sVM之每一邏輯分割可經 獨立地重設、載人對於每—分割可不同m统且使用 不同輸入/輸出(1/〇)裝置操作不同軟體程式。舉例而言, 邏輯刀υ系統之商業實施例包括IBM公司之p〇wer5多處 理器架構。 邏輯分割之一重要態樣為管理各別分割工作負載。舉例 而言,在POWER5中,稱為超管理器(hypervis〇r)之工作負 載管理器管理分割之間的工作負^^在此類型之共用資源 環境中,超管理器使用交錯時槽排程技術(在廣泛意義 上,其類似於通用多任務計算排程)將諸如記憶體、中央 處理單元(CPU)、I/O等之實體系統資源配置至邏輯分割。 超官理器試圖以按需要及/或預配置方式將分割工作作為 邏輯處理器調度至實體系統資源來平衡分割之工作負载: 刀割排程之一態樣具體而言係關於處理器資源利用及共 用。亦即,為了排程目的’將使用來自一共用處理器集區 之處理器容量的分割定義為限定的(capped)或未限定的 (uncapped) ^限定的分割不能超過其經組態之處理器權 利。邏輯分割之未限定支援使未限定分割在於共用處理器 集區中存在未利用之容量的情形下能夠超過其經組態之容 罝。此未利用之容量得自於其他分割未充分利用所有其經組 悲之奋I或共用集區之以其他方式未經完全配置的容量。 當調度時,一邏輯分割包含配置之實體處理器資源作為 邏輯處理器。邏輯處理器(有時被稱作虛擬處理器)之排程 129569.doc 200905470 需要配置處理循環、記憶體及其他實體系統資源經配置用 於由分割在一給定調度窗期間使用之預指定的時間時期或 時間片。舉例而言,在P0WER5上運作之ΑΙχ作業系統具 有預設之10 msec調度窗。可將經配置之調度窗的任一未 使用部分配置至系統中之未限定分割中之一或多者。通常 利用基於未限定分割之優先權級別的樂透機制㈦加7 來判定哪一未限定分割將使原始排程之分割替 換為調度窗之未使用部分。 雖然相對簡單且計算上花f不多,但前述替換調 並不充分地解決關於分割之邏輯結構及功能特性之潛在效 率低下。當在所謂的互動分割之各別調度窗期間替換分割 時,出現導致排程效率低下之重要來源。基於分割對外部 處理事件之依賴及在一給定調度窗期間中斷之可能性 分割表徵為”互動”,或在替代例巾,表徵為"批次”。批次 d很大程度上與來自外部事件之回應 :用:整個調度窗。相反,互動分割在調度窗等待外:: 件回應期間通常暫時中止活動。 為了有利地利㈣度t之在其他方面未使 =動分割已暫時中止工作),超管理器可試圖使用前 多替換暫…的分割,,在許 且因此有可能要求額外即將來臨的外部事件回應 中止之條件下仍將另外^ 雖然在分割之目.前暫時 的任務。 …分割替換之當前調度窗内完成 129569.doc -10- 200905470 若在分割不活動之時期期間未替換暫時中止的分割,則 浪費了調度窗循環。另一方面,雖然致能在其他情況下浪 費的調度窗循環之有利的利用,但習知分割替換技術不能 解決令斷替換的互動分割之互動處理的計算成本。此中斷 導致對替換之互動分割重排仔列且回環返回該仔列以重調 度分割之需要。與專用系統不同,虛擬系統需要對每一調 度重新確立§己憶體佔用量(mem〇ry 。因此,除了 必須重排排入仔列之外,經替換之互動分割必須消耗額外 循%來恢復§己憶體佔用量,此為虛擬系統中之工作負載管 理效率低下之一重要來源。 、 習知邏輯分割管理不能解決關於分割排程及運作時間工 作負載平衡之前述及許多其他問題。因此可瞭解,存在對 管理邏輯分割間之排程及工 ^ F貝戰平衡的方法、系統及電 腦程式產品之需要。本發 其他需求。 月解决先則技術未解決的此等及 【發明内容】 種用於平衡多個邏輯分割間對__採用系統 系統之實m㈣之存取㈣統、方法及 々在啟動時期期間’根據配置之調度窗利用 等邏輯刀割中之每一邏輯分割。判定該等實 之與該等邏輯合宝,丨士 Λ 1 刀。!中之一或多個邏輯分割相 個實體系統資源的效能度量。在該等分割之 :程_中斷無關之硬體债測及追蹤邏輯 量判定。在該等實體系統資源中之一給定組 本文中揭示 虛擬化之電腦 電腦可讀媒體 層級來分類該 體系統資源中 關聯之一或多 調度期間使用 來執行效能度 129569.doc 200905470 實體系統資源經組態用於配置至該等邏輯分割中之一邏輯 分割的一調度窗期間’根據與一替換邏輯分割相關聯之該 等判定之效能度量及該替換邏輯分割之該調度窗利用分類 將該給定組實體系統資源重新配置至該替換邏輯分割。 在另一態樣中,一種用於平衡共用實體系統資源之多個 邏輯分割間之工作負載的方法、系統及電腦程式產品利用 記憶體佔用量統計來判定分割替換合格性及優先權。該方 法包括判定該等實體系統資源中之與該等邏輯分割相關聯 之一或多個實體系統資源的效能度量及使用該等效能度量 判定記憶體佔用量值。在該等實體系統資源中之一給定組 實體系統資源經配置至該等邏輯分割中之一邏輯分割的— 調度窗期μ ’根據該等判定之記憶體佔用量值將該等實體 系統資源中之該給定組實體系統資源重新配置至該等邏輯 分割中之另一邏輯分割。 在另一態樣中,揭示一稀用认知 裡用於動態調諧一排程器之方 法、系統及電腦程式產品,該妯 C, 这排程為在一給定調度窗期間 排程共用實體系統資源之多袖.s 夕個邏輯分割。該方法包括在― 系統啟動時期期間使用預組態 t之調度®時期調度該等邏輯 分割。在邏輯分割調度期間,盘 Α ^ _ /、該專邏輯分割相關聯判定 該等實體系統資源中之_或夕加虫 或多個實體系統資源的效 量。與分割相關聯之該等效能 ^ b度里用U判定該等邏輯分宝 之記憶體佔用量值,在其他姑加_ X寻邈铒刀割 旦值用以在一調声%" 矛“式探中’ 1亥等記憶體佔用 里值用以“度自時期期間動態判 在以下詳細寫出之描述中, 之排权 中本發明之上述以及額外目 129569.doc 200905470 標、特徵及優勢將變得顯而易見。 【實施方式】 本發明之新穎特徵特性闡明於隨附申請 一 D兮刊範圍中。然 而,當結合附圖閱讀時,參照說明性實施 ,…、 J 从下詳細十#· 述將最佳地理解本發明自身,以及其較佳使用模式、’、、田 目標及優勢。 、工、另外 本發明之系統及方法致能在虛擬計算環境 **^- *^· 效 的資源配置及工作負載平衡。一例示性虛擬計算環境包括 多個邏輯分割’其中在該等分割中之兩個或兩個以上:割 間管理工作負載。如本文中所利用’術語”分割"通常指配 置至一作業系統之一資料處理硬體資源子集。分割亦可被 稱作線緒或任—其他計算單元。在下文中參看圖式繪示及 描述實施本發明之系統及方法的較佳實施例,其中,全文 中相同參考數字指示相同及相應零件。 本發明致能在工作負載管理器之指導下在整個邏輯分割 上進行可共用資源的動態再分布。在一態樣中,本發明藉 由使用動態可調整分割排程機制來達成改良的工作負載管 理及系統效率。分割排程機制之特徵表現為一硬體追蹤機 制,在一實施例中,該硬體追蹤機制將關於記憶體佔用量 確立之分割效能度量判定為分割排程度量。在另一態樣 中,本發明利用硬體追蹤之記憶體佔用量度量來動態地調 整各別邏輯分割在調度窗内之排程。 本發明致能在工作負載管理器之指導下在整個邏輯分割 上進行可共用資源之動態再分布,在一實施例中,該工作 129569.doc 200905470 負載管理器可立—1- ^ ^’理态。舉例而言,此等資 CPU資源、邏輯處 寻貝源了包括 译黧 °貝源、1/0資源、共處理器、通道資 :原二在-個實施例中,藉由將超管理器功 及 -體分割監視機制整合在一效能調整反饋迴 :配置之動態調整,於達成工作負载平衡及更= 體系統效率。 在—態樣巾,本發明解決對記憶體存取潛時造成之系統 通量的限制。本發明藉由散及利用分割排程之記憶體存 取統计來減輕記憶體潛時效應。此記憶體敏感分割排程改 良了分割排程決策的制定,且提供更大的調度窗排程靈活 性。在-實施例中,本發明考量在選擇—分割以先佔或在 ”他h况下替換—原始調度之分割中的記憶體佔用量設置 成本。本發明進一步考量對於重調度經替換之分割以回收 其原始調度窗之一部分的狀況下的後續佔用量設置成本。 現參看圖式,其中,全文中相同參考數字指示相同及相 應零件,實施本發明之工作負載管理特徵之虛擬計算環境 的一個實施例繪示於圖1中。其中說明虛擬計算系統1〇〇, 其包括在由 International Business Machines Corporation (Armonk,N.Y.)提供之p〇WER5伺服器中所包括的特徵申之 多數特徵。虛擬計算系統1〇〇通常包含:韌體層資源12〇, 其包括一超管理器Π5;以及硬體層資源122,其包括一共 用處理器集區117及記憶體裝置121及125。共用處理器集 區117較佳地包含多處理器組合體,該多處理器組合體包 含多個處理器108、110、112及114(分別表示為cpw 129569.doc -14- 200905470 cp w),且具有各別與處理器相關聯之快取記憶體从厂偷 121。虛擬計算系統1〇〇進—步包含多個邏輯分割i〇5a_ 105D(分別表不為。超管理器115管理及調整邏輯 分割1 05 A-1 05D間之硬體層資源丨22的指派。 CTi/7-CTW及相關聯之快取記憶體奶_術表示由超管理 器11 5按導致資源虛擬化之方式配置至邏輯分割1户厂χ"之 實體系統資源的-部分。實體系統資源通常為有形的系統 裝置、組件及相關聯之實體現象,例如記憶體裝置、處理Please refer to the US Patent Application No. _______ (Agency No. AUS920060139US2) for "Workload Management IN VIRTUALIZED DATA PROCESSING f ENVIRONMENT"; _______ US Patent Application No. _______ (Agent Case No. AUS920060139US3) in the WORKLOAD MANAGEMENT IN VIRTUALIZED DATA PROCESSING ENVIRONMENT; _______Application Named "Taking Hardware Statistics" US Pat. App. );. The application is hereby incorporated by reference in its entirety by reference in its entirety in its entirety in its entirety herein in its entirety in its entirety in [Prior Art] Logical partitioning of computer resources allows multiple system images to be created in a single physical machine or combination of processors. Virtualization is a term used to represent the system's imaging. In system imaging, each system image (also known as virtual machine 129569.doc 200905470 (VM)) uses the shared resources of the physical computer system to operate in a manner independent of other frequency logic. In this way, each logical segmentation of the corresponding sVM can be independently reset, the manned can be different for each-division, and different software programs can be operated using different input/output (1/〇) devices. For example, a commercial embodiment of a logical blade system includes IBM's p〇wer5 multiprocessor architecture. One of the important aspects of logical segmentation is managing individual split workloads. For example, in POWER5, a workload manager called a hypervisor manages the work between partitions. In this type of shared resource environment, the hypervisor uses interleaved slot scheduling. Techniques (in a broad sense, similar to general multitasking computing schedules) configure physical system resources such as memory, central processing unit (CPU), I/O, etc., to logical partitioning. The hypervisor attempts to balance the partitioned workload by scheduling the partitioning work as a logical processor to the physical system resources as needed and/or preconfigured: One aspect of the knifeing schedule is specifically about processor resource utilization. And sharing. That is, for scheduling purposes, the segmentation using processor capacity from a shared processor pool is defined as capped or undefined. The defined segmentation cannot exceed its configured processor. right. Unrestricted support for logical partitioning enables undefined partitioning to exceed its configured capacity in the presence of unused capacity in the shared processor pool. This unused capacity is derived from other partitions that do not fully utilize all of their sorrowful I or shared pools in other ways that are not fully configured. When scheduling, a logical partition contains the configured physical processor resources as a logical processor. Scheduling of logical processors (sometimes referred to as virtual processors) 129569.doc 200905470 requires configuration of processing loops, memory, and other physical system resources that are configured for pre-specified use by partitioning during a given dispatch window Time period or time slice. For example, an operating system operating on P0WER5 has a preset 10 msec dispatch window. Any unused portion of the configured dispatch window can be configured to one or more of the undefined partitions in the system. The lottery mechanism (7) plus 7 based on the priority level of the undefined split is typically used to determine which undefined split will replace the split of the original schedule with the unused portion of the schedule window. Although relatively simple and computationally insignificant, the aforementioned replacement tuning does not adequately address the potential efficiencies associated with the logical structure and functional characteristics of the segmentation. When the segmentation is replaced during the respective dispatch window of the so-called interactive segmentation, an important source of inefficiency in scheduling occurs. The segmentation is characterized as "interaction" based on the reliance of segmentation on external processing events and the likelihood of interruption during a given scheduling window, or in the alternative case, characterized as "batch." Batch d is largely derived from Response to external events: Use: The entire dispatch window. Conversely, the interactive split waits outside the dispatch window:: The component usually temporarily suspends the activity during the response. In order to benefit profitably, the fourth degree t does not cause the = split to temporarily suspend the work. The hyper-manager can try to use the pre-replacement of the pre-replacement, and it will still be the other task in the case of the division of the external event response. The current scheduling window of the split replacement is completed. 129569.doc -10- 200905470 If the temporary abort split is not replaced during the period of split inactivity, the scheduling window loop is wasted. On the other hand, although it is enabled in other cases, it is wasted. The advantageous use of the scheduling window loop, but the conventional segmentation replacement technique cannot solve the computational cost of the interactive processing of the interactive segmentation that replaces the replacement. This leads to the need to re-schedule the re-scheduled segmentation of the interactive segmentation of the replacement and the loopback to return the row. Unlike the dedicated system, the virtual system needs to re-establish the § memory occupancy for each schedule (mem〇ry. In addition to being re-arranged into the queue, the replaced interactive segmentation must consume an additional % to restore the XX memory occupancy, which is an important source of inefficiency in workload management in virtual systems. Logical partition management does not address the aforementioned and many other issues regarding split scheduling and runtime time workload balancing. Therefore, it can be seen that there are methods, systems, and computer program products for managing the scheduling of logical partitions and balancing the work and the competition. Needs. Other requirements of this issue. This solution is used to balance the multiple logical partitions. __ Use the system system's real m (4) access (four) system, method and 々 During the start-up period, 'depending on the configuration of the dispatch window, use each of the logical cuts in the logical cut. Determine the truth and the logic, the gentleman Λ 1 knife. The performance metric of one or more logically segmented physical system resources. In the segmentation: the process of interrupt-independent hardware debt measurement and tracking logic is determined in these physical system resources. One of the given sets of computer-readable media tiers disclosed herein for classifying the system system resources used to correlate one or more of the scheduling resources used to perform performance 129569.doc 200905470 Entity system resources are configured for configuration to During a scheduling window of one of the logical partitions, 'the performance metric of the determinations associated with a replacement logical partition and the scheduling window of the replacement logical partitioning use the classification to re-create the given group entity system resources Configuring to the alternate logical partition. In another aspect, a method, system, and computer program product for balancing workload between multiple logical partitions of a shared physical system resource utilizes memory occupancy statistics to determine split replacement Sex and priority. The method includes determining a performance metric of one or more physical system resources associated with the logical partitions in the physical system resources and determining the memory occupancy using the equivalent energy metric. One of the physical system resources, a given group of entity system resources, is configured to logically partition one of the logical partitions - a scheduling window μ', the physical system resources according to the determined memory occupancy values The given group of entity system resources are reconfigured to another logical partition in the logical partitions. In another aspect, a method, system, and computer program product for dynamically tuning a scheduler in a rare cognition is disclosed, wherein the schedule is to schedule a shared entity during a given dispatch window. The multi-sleeve of system resources. s logical division. The method includes scheduling the logical partitions using a preconfigured t' scheduling® period during the "system startup period". During the logical partition scheduling, the disk Α ^ _ /, the dedicated logical partition is associated with determining the effectiveness of the _ or the worm or the plurality of physical system resources in the physical system resources. In the equivalent energy level associated with the segmentation, U is used to determine the memory occupancy value of the logic branches, and the other values are used to modulate the denier value for a tuned %" "In the style of exploration, the memory value of the memory such as 1 hai is used to describe the dynamics during the period from the following detailed description. The above and additional 129569.doc 200905470 of the present invention are included in the rights. The advantages will become apparent. [Embodiment] The novel features of the present invention are set forth in the scope of the accompanying application. However, the present invention, as well as its preferred mode of use, ', field goals, and advantages, will be best understood from the following detailed description when read in conjunction with the accompanying drawings. The system and method of the present invention enable resource allocation and workload balancing in a virtual computing environment **^-*^. An exemplary virtual computing environment includes a plurality of logical partitions ‘where two or more of the partitions are: the cut-off manages the workload. As used herein, 'terminology' segmentation " generally refers to a subset of data processing hardware resources that are configured into one operating system. Segmentation may also be referred to as a thread or any other computing unit. The preferred embodiment of the system and method for carrying out the invention is described, wherein like reference numerals indicate the same and corresponding parts throughout. The present invention enables the sharing of resources across the entire logical segmentation under the guidance of the workload manager Dynamic redistribution. In one aspect, the present invention achieves improved workload management and system efficiency by using a dynamically adjustable partition scheduling mechanism. The segmentation scheduling mechanism is characterized by a hardware tracking mechanism, implemented in an implementation. In the example, the hardware tracking mechanism determines the segmentation performance metric established with respect to the memory occupancy as the segmentation level. In another aspect, the present invention dynamically adjusts each of the memory usage metrics by hardware tracking. Do not logically divide the schedule within the dispatch window. The invention enables the entire logical segmentation under the guidance of the workload manager With the dynamic redistribution of resources, in an embodiment, the work 129569.doc 200905470 load manager can be set up -1 - ^ ^' state. For example, the resources of the CPU resources, the logic to find the source includes Translated by Bayi source, 1/0 resource, coprocessor, channel resource: the original two in one embodiment, by integrating the hypervisor function and the body segmentation monitoring mechanism into a performance adjustment feedback back: configuration Dynamic adjustment to achieve workload balancing and more system efficiency. The present invention solves the limitation of system throughput caused by memory access latency. The present invention utilizes split scheduling Memory access statistics to mitigate memory latency effects. This memory-sensitive partitioning schedule improves the formulation of segmentation scheduling decisions and provides greater scheduling window scheduling flexibility. In an embodiment, the present invention Consider the memory footprint setting cost in the segmentation of the selection-segmentation to preempt or replace it in the original schedule. The present invention further contemplates subsequent occupancy setting costs for rescheduling the replaced partition to recover a portion of its original dispatch window. DETAILED DESCRIPTION OF THE INVENTION Referring now to the drawings, wherein the same reference numerals refer to the same and corresponding parts, one embodiment of a virtual computing environment implementing the workload management features of the present invention is illustrated in FIG. There is illustrated a virtual computing system that includes most of the features included in the p〇WER5 server provided by International Business Machines Corporation (Armonk, N.Y.). The virtual computing system 1A generally includes: a firmware layer resource 12A including a hypervisor Π5; and a hardware layer resource 122 including a common processor pool 117 and memory devices 121 and 125. The shared processor pool 117 preferably includes a multiprocessor assembly including a plurality of processors 108, 110, 112, and 114 (represented as cpw 129569.doc -14 - 200905470 cp w, respectively). And the cache memory associated with the processor is stolen from the factory 121. The virtual computing system 1 includes a plurality of logical partitions i〇5a_105D (respectively. The hypervisor 115 manages and adjusts the assignment of the hardware layer resource 丨22 between the logical partitions 1 05 A-1 05D. CTi /7-CTW and associated cache memory milk_skills are represented by the hypervisor 11 5 in a manner that results in resource virtualization to the logical partition of the 1 part of the factory's physical system resources - the physical system resources are usually Physical devices, components, and associated physical phenomena, such as memory devices, processing
器 '驅動H '匯流排、處理器/匯流排循環等,此與諸如 程式分層組織及程式協定(諸如彼等與作業系統相關聯之 程式分層組織及程式協定)之非實體、抽象系統資源區別 開來。亦可將實體系統資源與諸如虛擬機器之邏輯或虛擬 可界定實體區別開來。邏輯分割以中之每一者包括 -或多個邏輯處理器(未明確繪示),其中之每一者表示配 置至該分割的實體處中之一處理器之整個 或一部分。分割105A-105D中之一給定者之邏輯處理器可 專用於該分#j ’使得下層處判:#源保留用於彼分割,或 者可加以共用使得下層處理器資源可用於其他分割。'Drive H' bus, processor/bus cycle, etc., this is a non-physical, abstract system such as program hierarchy organization and program agreement (such as their hierarchical organization and program agreement with the operating system) The resources are different. Physical system resources can also be distinguished from logical or virtual definable entities such as virtual machines. Each of the logical partitions includes - or a plurality of logical processors (not explicitly shown), each of which represents an entire or a portion of one of the processors configured to the split entity. The logical processor of one of the partitions 105A-105D may be dedicated to the sub-section #j' such that the lower layer resolves: #源 Reserved for the split, or may be shared such that the underlying processor resources are available for other partitions.
在所繪示之實施例中,邏輯分割出摘中之每—者充 曰具有駐留作業系統!Q4(其在分割間可不同)及—咬多 個應用程式m之獨立系統。在—實施财,作業系統 104A HMD中之-或多者可為作業系統或由JEM C〇rp〇ratl〇n提供之i5/〇sTM作業系統。另外作業系統 UMA-HMD(或其一子集)包括各別⑽工作負載管理器__ 129569.doc -15· 200905470 106D ’其用於管理在各別分割中之每一者中的應用程式工 作負載^ 在一個實施例中,超管理器115作為不具有授權容量之 隱藏分割而操作。系統資源至邏輯分割之配置係 由超管理器115管理,其可由在處理器上運作 之微碼實施。超管理器呼叫提供用於作業系統ι〇4α·ι〇4〇 中之任一#業系統與超管理器115通信的方 <,其藉由支 援使用在下文進一步詳細解釋之技術來使分割閒置時間最 小化之排程試探來致能實體處理器容量之更有效率的使 用。邏輯分割及s管理器115通常包含駐留於與處 理器⑽/ —⑽蝴關聯之中央記憶體之各別部分中的一或 多個有形程式模組。 圖2為繪示根據本發明之一實施例之用以有助於分割排 釭之一例不性架構2〇〇的高階示意圖。分割排程架構將 h刀割官理單7L (PMU)204與諸如共用處理器集區117、超 管理器115及快取記憶體2〇6之其他系統組件整合。雖然將 PMU 204繪不為圖2中之一明顯模組,但應注意,pMu 2〇4 ^硬體、㈣及軟體組件中之—些或所有組件可整合於超 s理盗115内。此外,應注意,快取記憶體鳩表示由包含 於共用處理器集區117中之cpu⑽、ug、112及114中之 或夕個CPU利用的集體快取記憶體資源⑽-撕中之一些 或所有記憶體資源。 PMU 2G4包括監視針對配置至分割IN IN之資源的實 體系統資源效能度量(例如彼等與記憶體使用相關之效能 129569.doc -16 - 200905470 度量)之邏輯、程式模組及其他硬體、勤體及/或軟體模 組。此等效能度量較佳包括快取㈣,且特定言之為關於 分割中之每—者之快取記憶體佔用^的度量。圖2 之高階示意圖說明PMU 204與致能與邏輯分割相關聯之實 體系統資源的此種監視之其他系統組件之間的整合及互動 介面。 當目前調度之邏輯分割使用來自共用處理器集區ιΐ7之 CPU執行其指令流且經由載人或儲存操作來存取記憶體位 置之内容時,CPU經由CPU_快取介面212將此等請求發出 至其相關聯之快取記憶體2G6。接下來,快取記憶體裏之 任務為狀記憶體内容是否存在於快取記憶體之儲存區 中,且⑷若如此,則將經快取之資料傳回至CPU,或㈦ 右不,則在執仃載入或儲存前,自主記憶體(諸如共用記 憶體125)提取記憶體内容。若請求之記憶體内容已處於快 取記憶體206中,則將資料傳回至㈣,而並不存取共用 記憶體125(諸如’經由快取.記憶體介面21())。此時,不需 要與PMU 204之互動 '然而,料求之資料在快取記憶體 206中不可侍到’則必須經由快取-記憶體介面加自主共 用記憶體125提取資料。 八 參看圖3,其繪示說明如可實施於圖2中所繪示之架構内 之分割監視單元204之内部架構、超管理器115及分割歷史 表305的同階不意圖。輪入側包括pMu 2〇4 ’其說明為包 括一追縱邏輯模組302,·^、6 /In the illustrated embodiment, each of the logically segmented ones has a resident operating system! Q4 (which can vary between splits) and - a separate system that bites multiple applications. In the implementation, the operating system 104A HMD can be an operating system or an i5/〇sTM operating system provided by JEM C〇rp〇ratl〇n. In addition, the operating system UMA-HMD (or a subset thereof) includes separate (10) workload managers __ 129569.doc -15· 200905470 106D 'which is used to manage application work in each of the respective partitions Load ^ In one embodiment, hypervisor 115 operates as a hidden partition without authorized capacity. The system resource to logical partition configuration is managed by hypervisor 115, which can be implemented by microcode running on the processor. The hypervisor call provides a means for communication between any of the operating systems ι〇4α·ι〇4〇 and the hypervisor 115, which supports segmentation by supporting techniques that are explained in further detail below. Scheduled heuristics with minimal idle time to enable more efficient use of physical processor capacity. The logical partitioning and s manager 115 typically includes one or more tangible program modules residing in separate portions of the central memory associated with the processor (10) / (10). FIG. 2 is a high-level diagram showing an example of an erroneous architecture 2 用以 for facilitating partitioning according to an embodiment of the present invention. The split scheduling architecture integrates the HPL 7L (PMU) 204 with other system components such as the shared processor pool 117, hypervisor 115, and cache memory 2〇6. Although the PMU 204 is not depicted as an obvious module in FIG. 2, it should be noted that some or all of the components of the pMu 2〇4^hardware, (4), and software components may be integrated into the SuperStolen. In addition, it should be noted that the cache memory 鸠 indicates some of the collective cache memory resources (10) used by the CPUs included in the CPUs 10, ug, 112, and 114 in the shared processor pool 117 or All memory resources. PMU 2G4 includes logic, program modules, and other hardware, and other functions that monitor physical system resource performance metrics (eg, their performance related to memory usage 129569.doc -16 - 200905470 metrics) for resources configured to split IN IN. Body and / or software modules. This equivalent energy metric preferably includes a cache (four) and, in particular, a measure of the cache memory usage of each of the partitions. The high-level diagram of Figure 2 illustrates the integration and interaction interface between the PMU 204 and other system components that enable such monitoring of the physical system resources associated with the logical partition. When the currently scheduled logical split uses the CPU from the shared processor pool ΐ7 to execute its instruction stream and access the contents of the memory location via a person or store operation, the CPU issues such requests via the CPU_cache interface 212. To its associated cache memory 2G6. Next, the task in the cache memory is whether the content of the memory exists in the storage area of the cache memory, and (4) if so, the cached data is transmitted back to the CPU, or (7) right, then The autonomous memory (such as the shared memory 125) extracts the memory content before it is loaded or stored. If the requested memory content is already in the cache memory 206, the data is passed back to (4) without accessing the shared memory 125 (such as 'via the cache. Memory interface 21()). At this time, there is no need to interact with the PMU 204. However, the information requested is not available in the cache memory 206, and the data must be extracted via the cache-memory interface plus the autonomous shared memory 125. 8 Referring to FIG. 3, a schematic diagram illustrating the internal architecture of the segmentation monitoring unit 204, the hypervisor 115, and the segmentation history table 305, which may be implemented within the architecture illustrated in FIG. 2, illustrates the same order. The wheel entry side includes pMu 2〇4', which is illustrated as including a tracking logic module 302, ·^, 6 /
、、、、 遠追縱邏輯模組3 02處理來自CPU 介面208及快取介面2〗μ "由214之輸入以產生分割向量3〇8、3 10及 129569.doc 200905470 312。在其輸出側上,該架構包含超管理器115及分割歷史 =〇5/在所繪示之實施例中,超管理器⑴包括-優先權 5十算模組304,其處理公宝丨丨a技 处理刀割向量3〇8、31〇及312以產生及更 新分割歷史表305之內玄:。八办,广 刀。丨〗歷史表3 0 5含有針對虛擬計The remote tracking logic module 322 processes the input from the CPU interface 208 and the cache interface 2 μ " from 214 to generate the split vectors 3〇8, 3 10 and 129569.doc 200905470 312. On its output side, the architecture includes a hypervisor 115 and split history = 〇 5 / In the illustrated embodiment, the hypervisor (1) includes a -priority 5 ten-calculation module 304 that processes the public treasure The technique processes the cutter vectors 3〇8, 31〇, and 312 to generate and update the inside of the split history table 305. Eight offices, wide knife.丨〗 History table 3 0 5 contains for virtual meter
算系統1〇0内之所有則固邏輯分割的項目。在所繪示之實施 例中將刀割歷史表305說明為包括以列為主記 錄’每-者對應於系統中之湖邏輯分割中之一者,其中 每-分割記錄纟有多㈤以行為主(c〇lumn wise)資料欄位。 在以行為主攔位巾為針對各別邏輯分财之每—者的邏輯 分識別符欄位以及每指令循環數目⑴叫值、快取列 計數(CLC)值及快取未中計數(CMC)值之搁位,且該等值 將在下文作進一步詳細解釋。除了硬體偵測之CPI、cLc 及CMC值之外,每一分割表項目之以行為主欄位包括針對 記憶體佔用量時期值TFP、佔用量值變化VAR以及快取相 關性(cache affinity ; CA)值之攔位,該等值可自前述 CPI、CLC及CMC值中之一或多者得出。 在PMU 204内’追蹤邏輯模組3〇2包括用於偵測 '處理 及臨時儲存實體系統資源(例如在圖1及圖2中所繪示之處 理及s己憶體資源)之效能度量的邏輯及資料儲存硬體裝 置。效能度量係與諸如記憶體及CPU之實體系統資源在债 測時所配置至之邏輯分割相關聯偵測。所偵測及處理之效 能度量係與實體資源目前所配置至之邏輯分割之識別碼相 關聯儲存。一組給定效能度量與一邏輯分割之間的關聯可 由含有一或多個當前調度之分割之識別碼的CPU介面暫存 129569.doc -18· 200905470 器314提供。較佳在調度決策時設定暫存器3i4内之分鱗 值。 由追縱邏輯模組302收集之例示性效能度量可包括⑽計 數、快取列計數、快取未中計數及可自在哪介面2〇8及/ 或快取介面214上所偵測之信號直接判定或計算判定之與 記憶體存取或處理效率相關的其他度量。可利用處理器利 用貝源暫存器322提供-循環計數來量測將分割於實體處 理器上調度之時間片期間的活動性。在所繪示之實施例 中,由追縱邏輯302偵測之針對當前調纟之分割㈣中之每 一者的CPU計數係儲存於調度之分割向量3〇8中。類似 地,由追蹤邏輯302偵測之針對調度之邏輯分割心所的快取 列計數及快取未中計數係分別儲存於調度之分割向量31〇 及312中。 在一較佳實施例中,追蹤邏輯模組3〇2中之偵測邏輯及 資料儲存裝置包括與程式中斷機制(例如作業系統中斷)無 關地來收集且處理在CPU介面2〇8及快取介面214上之信號 的硬體及動體裝置。此等追縱及儲存裝置可包括諸如邏輯 閘、暫存器等之硬體及諸如系統匯流排窺探程式(sn〇〇p〇r) 所使用之韌體編碼的韌體編碼。追蹤邏輯模組3〇2與軟體 程式中斷無關地在硬體及/或韌體級上執行其偵測、處理 及儲存功能。因此,此等偵測、處理及儲存功能係與作業 系統核心管理約束無關地執行。以此方式,追蹤邏輯模組 3 02收集效能度量之取樣速率可具有用於判定待用於分割 排程及替換(如下文作進一步詳細解釋)之準則資料所需之 129569.doc -19- 200905470 足夠精細的粒度,例如〇 1 m s e c。 在調度之分割向量308、310及3 12内的系統效能度量包 括分別針對-定數目(㈣)個當前或先前調度之邏輯分= 中之每一者的CPI計數、快取列計數及快取未中計數。每 一記錄之分割向量值與一相應邏輯分割之間的關聯係由= 標而直觀地表示於圖3中,其中下標心讲中之每一者表 示一指定邏輯分割。追蹤邏輯3〇2中儲存分割向量“^、 310及312之儲存裝置較佳地為專用暫存器。 由追蹤邏輯302偵測且收集於調度之分割向量3〇8、Calculate all items in the system 1〇0 that are logically partitioned. In the illustrated embodiment, the knife cut history table 305 is illustrated as including a column-based record 'each one corresponding to one of the lake logical partitions in the system, where each-divided record has more (five) to behave The main (c〇lumn wise) data field. The logical sub-identifier field and the number of cycles per instruction (1) called the value, the cache line count (CLC) value, and the cache miss count (CMC) in the behavior of the main blocker. The value of the position, and the value will be explained in further detail below. In addition to the CPI, cLc, and CMC values for hardware detection, the main fields of behavior for each partition table item include the memory occupancy period value TFP, the occupancy value change VAR, and the cache affinity; The CA value interception, which can be derived from one or more of the aforementioned CPI, CLC, and CMC values. The 'tracking logic module 3〇2 in the PMU 204 includes performance metrics for detecting 'processing and temporarily storing physical system resources (such as the processing and suffix resources depicted in Figures 1 and 2). Logic and data storage hardware devices. The performance metric is detected in association with the logical segmentation to which the physical system resources such as memory and CPU are configured during the measurement. The detected and processed performance metrics are stored in association with the logically separated identification code to which the physical resource is currently configured. The association between a given set of performance metrics and a logical partition may be provided by a CPU interface temporary storage 129569.doc -18. 200905470 314 containing one or more currently scheduled partitioned identification codes. Preferably, the scale value in the register 3i4 is set in the scheduling decision. The exemplary performance metrics collected by the tracking logic module 302 can include (10) counting, cache column counts, cache misses, and signals that can be detected directly on the interface 2〇8 and/or the cache interface 214. Other metrics that are determined to be related to memory access or processing efficiency are determined or calculated. The processor can be utilized by the processor to provide a loop count to measure activity during the time slice scheduled to be split on the physical processor. In the illustrated embodiment, the CPU count for each of the current splits (4) detected by the tracking logic 302 is stored in the scheduled split vector 3〇8. Similarly, the cache line count and the cache miss count for the scheduled logical split heart detected by the trace logic 302 are stored in the scheduled split vectors 31A and 312, respectively. In a preferred embodiment, the detection logic and data storage device in the tracking logic module 〇2 includes collection and processing on the CPU interface 2〇8 and cache independently of the program interrupt mechanism (eg, operating system interrupt). Hardware and dynamic devices for signals on interface 214. Such tracking and storage devices may include hardware such as logic gates, scratchpads, etc., and firmware encodings such as firmware encoded by the system bus snooping program (sn〇〇p〇r). The tracking logic module 3〇2 performs its detection, processing and storage functions at the hardware and/or firmware level regardless of the software program interruption. Therefore, such detection, processing, and storage functions are performed independently of the operating system core management constraints. In this manner, the sampling rate of the tracking logic module 322 collecting performance metrics may have the required information for determining the criteria to be used for segmentation scheduling and replacement (as explained in further detail below) 129569.doc -19- 200905470 Fine enough granularity, such as 〇 1 msec. The system performance metrics within the scheduled segmentation vectors 308, 310, and 3 12 include CPI counts, cache column counts, and caches for each of a predetermined number ((iv)) of current or previously scheduled logical scores = Not counting. The relationship between the segmentation vector values of each record and a corresponding logical segmentation is visually represented in Figure 3 by the =, where each of the subscripts represents a specified logical segmentation. The storage device storing the segmentation vectors "^, 310, and 312 in the trace logic 〇2 is preferably a dedicated scratchpad. The segmentation vector detected by the trace logic 302 and collected in the schedule is 3〇8,
及312中的效能度量由超管理器115處理以更新分割歷史表 3〇5。由超管理器115產生或接收之中斷信號判定何時應使 用在調度之分割向量3G8、31G及312中所收集之系統資料 更新分割表305。中斷指示或在其他情況下與調度之分判 ㈣中的至少一者之調度窗之期滿一致。在接收到該中斷 後,優先權值計算模組3〇4擷取且處理分割向量3〇8、31〇 及312以填充或更新分割歷史表3〇5中之項目。在所繪示之 實施例巾,回應於更新巾斷錢,㈣於針對㈣邏輯分 割之記錄的各別以行為主度量項目來比較或以其他方式處 理調度之向量308、31〇及312内的cpi、咖及⑽度量。 假定圖3繪示首先調度邏輯分到 ' 科刀d α-w之一初始系統啟動時 期,則優先權值計算模组3〇4用八堂,丨 . > U4用刀割α-所中之每一者的記錄 項目填充分割歷史表305且將來白&县·2Λ。 府术自向量308、3 10及3 12之分 割向量資料輸入至相應記錄項目中 7貝曰Τ。在系統初始化時期期 間,δ己錄產生程序繼續,亩$ % 士、广/ 置至所有iV個邏輯分割已將記錄 129569.doc -20- 200905470 填充於分割歷史表305中。 在每一邏輯分割之初始調度及隨之的分割記錄產生後, 優先權值計算模組304在每一發出信號更新間隔時繼續處 理調度之向量308、310及312以添加、替換或在其他情況 下修改分割歷史表305中之效能度量及/或替換優先權值項 目(如下文作進一步詳細地解釋)。 圖4為根據本發明之用於判定邏輯分割之排程優先排序 之一序列的高階方塊圖表示。詳言之,圖4繪示例示性臨 時及基於事件之優先排序因數,諸如可由超管理器〗丨5用 於制定調度決策(例如替換或先佔一當前調度之分割)中。 為了在整個分割調度排程中整合作為動態可調整因數之 優先排序,超管理11 5將針對每一邏輯分割之相對或絕 對優先權判定為與快取記憶體佔用量相關之度量的函數, 且因此必須自PMU 204擷取硬體偵測之效能度量。 如上所解釋,直接自記憶體及CPU匯流排介面判定之實 體系統效能度量得以偵測且藉由使用追蹤邏輯模組3〇2中 之硬體層級邏輯及暫存器而得以初始暫存及處理。由追蹤 邏輯模組302偵測或產生之快取記憶體佔用量度量較佳包 括針對每-調度之分割的CPI計數、快取列計數及快取未 中计數,且收集為分割向量3〇8、31〇及312,該等分割向 13 08、31G及312可與其他排程優先權因數組合以得出整 體調度優先權。 。圖5至圖9結合圖4說明如何將分割監視功能性整合至邏 輯刀排程(尤其當該排程係關於在最小分割權限之配置 129569.doc 200905470 後替換或先佔調廑之八宝彳 ' 之刀。J或排程分割時)的例示性實施 例。首先’圖4中所千夕八中,丨+ 〃之刀口丨優先排序序列繪示包括用於 設定及調整分割$ IΛ & 憂先值之硬體偵測之實體系統效能度量 的多個優先因數之累籍穷各丨田 π 又系積及利用。圖6進一步詳細地繪示電 腦實施之程序,藉由缔雷腿杳# 精由忒電腩實施之程序,硬體偵測之實體 系統效能度量(且詳言之為# 叶口 &馬莜寻關於記憶體存取效能之效 π度里)經判疋且加以有形地利用以表徵每一分割之一或 多個为割排程優先排序因數。圖7至圖9說明用於使用與分 割相關聯之記憶體佔用暑择旦点、± 1用里度里來判疋優先權及調諧調度窗 之電腦實施之程庠。諸石 t 斤渚如圖5及圖6中所繪示之優先排序特 徵及/或排程器調諧可與超管理器調度器(例如併入於超管 理器U5中之調度器)—起使用。然而,應注意,本文中所 描述之發明性特徵及技術不必限於所㈣之實施例中的任 何一或多者。熟習此項技術者將易於瞭解及理解:可改變 判定及利时割優先排序之料的各種態樣而不脫離本發 明之精神及範_,且此外,可將本文t描述之機制及程序 之基本態樣與其他排程演算法一起利用。 繼續圖4 ’產生一具有基礎優先權叶^) 4〇2之分割匕, 其初始可為空值或在其他情況下為中性值,使得其對於分 割排程/替換決策不具有影響。基礎優先權值叶(1^可為^ 由超管理器11 5用力制定分割先佔及/或替才奐決策之數字或 其他數量值或標諸。&割卜之整體優先權值425較佳地包 括—動態調整基礎優先權bp(Pi) 402之臨時公平分量。如 圖4中所示,藉由將分割之基礎優先權^(ρ〇升高一些與時 129569.doc -22- 200905470 1相關之〜里d(其累加性地表示為優先權求和叫例)來 用每一時間量來計算在時間t的當前優先權ep(P,,t) 406。 當前優先權cp(Pi,t)4_此包括基礎優先權加上屬於優先 權求和叫404内(視目前時間間隔』而定)之一遞增公平分 量。對於基於非效能度量之分割調度’邏輯分割之優先權 等於當前優先權Cp(Pi,〇 406。 本發明提供-分割排程機制,其進—步提供且併有與分 割相關聯之實體系統效能度量以判定分割P,之排程優先權 425。此暗不·對於使用一共用組實體處理資源(處理器、 5己憶體等)在虛擬系統中執行的多個邏輯分割,在同一時 間下對不同分割之優先權的計算可產生不同值。詳言之,在 每-排程間隔時使—分割之與效能無關的優先權吓⑺,〇 406調整420—基於效能之因數卸418。基於效能之因數知 418表示一系列可能的具體值中之一者,而可使用與一分 割相關聯之系統效能度量來使討論中的分割之優先權級增 加或減少該具體值。在一實施例中,藉由使用一可靠性因 數計算模組ς416來處理快取記憶體佔用量值CFp(Pi),從 而计鼻因數Δρ 418。經由一或多個由快取記憶體佔用量計 算模組Θ 412表示之邏輯函數,將CFp(Pi)自身作為分割匕 之如由本發明之機制量化表示的快取記憶體佔用量值計 算。即,一組一或多個與分割相關聯之實體資源度量 PRM(Pi)由快取記憶體佔用量計算模組@ 412處理以判定可 用於判定分割排程優先權之指定記憶體佔用量值(例如 CFP(Pi))。佔用量計算模組Θ 41 2及可靠性因數計算模組; 129569.doc -23 · 200905470 41 6確定基於效能之因數4】8。如圖4中所示,在時間t時 =分割Pi的整體優先權值因此為基礎分割優先權' 臨時公 平調正及與该分割相關聯量測之實體系統度量的組合函 數。 圖5為根據本發明之如可在超管理器115内實施以用於替 換-經調度但暫時中止之分割之分割調度器狀態的高階方 :圖表示。根據本文中所揭示之方法,產生一替換分割向 量或替換佇列505且由超管理器115動態地調整。存取替換 佇列505以(例如)當一當前運作之分割在調度窗時間量子期 滿前於當前調度窗期間暫時中止處理時,判定絕對或相對 替換優先排序。將替換佇列505組織為經優先排序替換目 標LPa-LPA一佇列’在該佇列中,#一目標含有或在其 情況下鏈接至相應分割控制區塊PCB 5〇2a_5〇2n,每一分 割控制區塊維持分割狀態資訊,諸如分割之經組態及經調 整之調度排程狀態及在其他分割特定資料中的替換優先權 狀態。如圖5中所示,可自”最大,,(亦即,可用替換分割中 之最高優先權)至”最小亦即,可用替換分割中之最低優 先權)來對替換目標LPa-LPn確定優先順序。可有利的利用 替換佇列505之分量來判定排程優先權,此如現參看圖石所 解釋。 參看圖6,其說明根據本發明之繪示由分割監視單元2〇4 及超管理器H5執行以用於判定分割排程優先權值之步驟 的高階流程圖。如在步驟602及604處所示,程序開始於初 始化及識別邏輯分割,例如藉由產生每一分割之相應分割 129569.doc • 24 - 200905470 控制區塊(諸如彼箄^;园 ……圖5中所示之分割控制區塊)。設定該 荨刀口J t之母一者的基礎 « 管狭慢无排序,且如在步驟606 及608處所說明使其遞 a超s理斋U5較佳以圖4中所冷 示之方式設定且遞增該笤八宝丨夕娃她沒 Τ 3 4等刀割之替換優先權,在圖4 利用臨時公平排程函數來 先權值。 數來以某正規化方式動態調整分割優 繼續如在步驟610處所干,卢加者, 理器, 實財,根據由超管 ° 9 、’&、'且4之調度窗配置來調度邏輯分割。在 分割調度窗期間,利用基於硬體之追^ #胃 遯之追蹤裝置及模組(例如 彼等在追蹤邏輯模組3〇2中 之追蹤裝置及模組)追蹤與在調The performance metrics in and 312 are processed by hypervisor 115 to update the segmentation history table 〇5. The interrupt signal generated or received by the hypervisor 115 determines when the system data update partition table 305 collected in the scheduled split vectors 3G8, 31G, and 312 should be used. The interruption indication or, in other cases, coincides with the expiration of the dispatch window of at least one of the sub-segments of the dispatch (4). Upon receiving the interrupt, the priority value calculation module 3〇4 retrieves and processes the segmentation vectors 3〇8, 31〇, and 312 to fill or update the items in the segmentation history table 〇5. In the illustrated embodiment, in response to the update towel, (4) in the records for the (four) logical segmentation, the behavioral master metric items are compared or otherwise processed in the vector 308, 31, and 312 of the schedule. Cpi, coffee, and (10) metrics. Assume that FIG. 3 shows that the first scheduling logic is assigned to one of the initial system startup periods of the 'knife d α-w, then the priority value calculation module 3 〇 4 uses eight halls, 丨. > U4 uses a knife to cut α- Each of the record items fills the split history table 305 and will be white & From the vector 308, 3 10 and 3 12, the cut vector data is input to the corresponding record item. During the system initialization period, the δ record generation process continues, and the increments of $%, 广// to all iV logical divisions have been recorded in the split history table 305 129569.doc -20- 200905470. After the initial scheduling of each logical segmentation and subsequent segmentation records are generated, the priority value calculation module 304 continues to process the scheduled vectors 308, 310, and 312 for each addition, replacement, or other condition at each signal update interval. The performance metrics and/or replacement priority value entries in the segmentation history table 305 are modified (as explained in further detail below). 4 is a high level block diagram representation of a sequence of scheduling prioritization for determining logical partitioning in accordance with the present invention. In particular, Figure 4 depicts an exemplary temporary and event-based prioritization factor, such as may be used by hypervisor 丨5 to make scheduling decisions (e.g., to replace or preempt a current scheduled segmentation). In order to integrate the prioritization as a dynamically adjustable factor throughout the split scheduling schedule, the hypervisor 1 15 determines the relative or absolute priority for each logical partition as a function of the metric associated with the cache memory footprint, and Therefore, the performance metric of hardware detection must be taken from the PMU 204. As explained above, the physical system performance metrics directly determined from the memory and CPU bus interface interface are detected and initially initialized and processed by using the hardware hierarchy logic and the scratchpad in the tracking logic module 3〇2. . The cache memory occupancy metric detected or generated by the tracking logic module 302 preferably includes a CPI count, a cache column count, and a cache miss count for each-scheduled partition, and is collected as a split vector 3〇. 8, 31 〇 and 312, the split directions 13 08, 31 G and 312 can be combined with other schedule priority factors to arrive at an overall scheduling priority. . Figure 5 to Figure 9 illustrates how the split-monitoring functionality is integrated into the logical knife schedule in conjunction with Figure 4 (especially when the schedule is replaced or preemptively after the configuration of the minimum split permission 129569.doc 200905470) An exemplary embodiment of a 'knife. J or a scheduled split. First of all, in the figure of Figure 4, the 排序+〃〃刀 priority sequence shows multiple priorities for the physical system performance metrics used to set and adjust the segmentation of the ISI & The factors of the poor and the poor 丨 丨 系 are combined and utilized. Figure 6 shows in further detail the computer-implemented program, the system performance measure of hardware detection by means of the process of implementing the thunder and squatting (and in detail, #叶口&马莜Finding the effect of memory access efficiency π degrees is judged and tangibly utilized to characterize one or more of each segmentation as a cut schedule prioritization factor. Figures 7 through 9 illustrate the implementation of a computer for use of the memory associated with the segmentation, the use of the latitude to determine the priority, and the tuning of the dispatch window. The prioritization features and/or scheduler tuning as illustrated in Figures 5 and 6 can be used with a hypervisor scheduler (e.g., a scheduler incorporated in hypervisor U5). However, it should be noted that the inventive features and techniques described herein are not necessarily limited to any one or more of the embodiments of (4). Those skilled in the art will readily appreciate and appreciate that various aspects of the determination and prioritization of the material can be varied without departing from the spirit and scope of the present invention, and in addition, the mechanisms and procedures described herein can be Basic aspects are used with other scheduling algorithms. Continuing with Figure 4', a segmentation 具有 having a base priority leaf ^) 4〇2, which may initially be null or otherwise neutral, has no effect on the split schedule/replacement decision. The base priority value leaf (1^ can be ^ by the hypervisor 11 5 to force the division of the preemption and / or substitute value of the number or other quantitative value or the standard. & cut the overall priority value of 425 Preferably, the dynamic fairness component of the base priority bp(Pi) 402 is dynamically adjusted. As shown in FIG. 4, by giving priority to the basis of the segmentation ^(ρ〇 is raised by some time 129569.doc -22- 200905470 1 related to the inner d (which is cumulatively represented as a priority summation example) to calculate the current priority ep(P,,t) 406 at time t with each amount of time. Current priority cp (Pi , t) 4_ This includes the base priority plus one of the priority summations 404 (depending on the current time interval) to increment the fair component. For the non-performance metric based segmentation scheduling, the priority of the logical segmentation is equal to Current priority Cp (Pi, 〇 406. The present invention provides a split scheduling mechanism that provides and has a physical system performance metric associated with the segmentation to determine the partition P, which has a scheduling priority of 425. This dark No. For processing resources using a shared group entity (processor, 5 memory, etc.) Multiple logical partitions performed in a virtual system can produce different values for the calculation of the priority of different partitions at the same time. In detail, the performance of the split-priority-independent priority is scared at every-schedule interval (7) , 〇 406 adjusts 420 - the performance-based factor off 418. The performance-based factor 418 represents one of a series of possible specific values, and the system performance metric associated with a segmentation can be used to cause the segmentation in question The priority level increases or decreases the specific value. In one embodiment, the cache memory occupancy value CFp(Pi) is processed by using a reliability factor calculation module ς416 to calculate the nose factor Δρ 418. Or a plurality of logic functions represented by the cache memory occupancy calculation module 412, and calculating CFp(Pi) itself as a segmentation buffer value calculated by the mechanism of the present invention. One or more entity resource metrics PRM(Pi) associated with the segmentation are processed by the cache memory occupancy calculation module @412 to determine a specified memory occupancy value that can be used to determine the split schedule priority. (eg CFP (Pi)). Occupancy calculation module Θ 41 2 and reliability factor calculation module; 129569.doc -23 · 200905470 41 6 Determine the factor based on performance 4] 8. As shown in Figure 4, Time t = the overall priority value of the split Pi is therefore a combined function of the base split priority 'temporary fair correction and the physical system metric associated with the split. Figure 5 is a super-management according to the present invention. A higher order side of the split scheduler state implemented for replacement-scheduled but temporarily suspended splitter: a representation. A replacement split vector or replacement queue 505 is generated and super-managed according to the methods disclosed herein. The device 115 is dynamically adjusted. The access replacement queue 505 determines absolute or relative replacement prioritization, for example, when a currently operating partition temporarily suspends processing during the current scheduling window before the scheduling window time quantum period expires. The replacement queue 505 is organized as a prioritized replacement target LPa-LPA array in which the #一 target contains or in its case is linked to the corresponding segmentation control block PCB 5〇2a_5〇2n, each The split control block maintains split status information, such as split configuration and adjusted scheduling status and replacement priority status in other partition specific data. As shown in FIG. 5, the replacement target LPa-LPn may be prioritized from "maximum," (ie, the highest priority among the available alternative partitions) to "minimum, that is, the lowest priority among the alternate partitions available". order. It may be advantageous to use the component of the replacement queue 505 to determine the scheduling priority, as will now be explained with reference to the stone. Referring to Figure 6, there is illustrated a high level flow diagram of the steps performed by segmentation monitoring unit 2〇4 and hypervisor H5 for determining a split schedule priority value in accordance with the present invention. As shown at steps 602 and 604, the program begins by initializing and identifying the logical segmentation, for example by generating a corresponding segmentation for each segmentation. 129569.doc • 24 - 200905470 Control block (such as 箄^;园...Fig. 5 The split control block shown in the figure). Setting the base of the one of the jaws J t «the tube is slow and unordered, and as described at steps 606 and 608, it is preferably set in the manner shown in FIG. 4 and Increment the 笤 笤 丨 丨 丨 她 她 她 她 她 她 Τ Τ Τ Τ Τ Τ Τ Τ Τ Τ Τ Τ Τ Τ Τ Τ Τ Τ Τ Τ Τ Τ To dynamically adjust the segmentation in a normalized manner, as in step 610, the Lujia, the processor, the real money, according to the scheduling configuration of the super-controller, the '&,' and 4 scheduling logic segmentation. During the splitting of the dispatch window, tracking and devices based on the hardware-based tracking device and modules (for example, tracking devices and modules in the tracking logic module 3〇2) are used to track and adjust
度囪期間將資源配置至之I 之各別邏輯分割相關聯之實體系統 貧源中之一或多者的效能度 夏^騍615)。在與程式設計中 斷(例如作業系統中斷)益關 )關之硬體層級下執行效能度量追 蹤’且效能度量追蹤軔佔 較佳包括追蹤CPI以及其他實體資 處理度量。 如圖6中所示,追蹤實體資源度量包含以下子步驟’盆 中,調度之分割相關聯追蹤度量,且其中利用硬體债測之 度量來計算或在其他情π m判定可由超管理器115用於分 割替換或其他調度決策之排 一 程優先排序值。如在步驟612 處所繪示,使用硬體層級 、科及瞀存态以一具有記錄時間 增量Δΐε(;之記錄速率收隹β μ 疋手收集及儲存與分割相關聯之實體資源 度量’記錄時間增量^小 ’、 於由大於1之增量因數除由調 度時期界定之分割調度時期τ沾八* 4 1 DP的为數。在實體資源度量 之硬體憤測之收集後及/或結人欠 Λ Q。貫體貝源度S之硬體偵測 129569.doc -25- 200905470 之收集,计算與分割相關聯之優先權值(步驟6丨4)。與分割 相關聯之該等優先權值係由硬體偵測/儲存之實體系統度 量計算或者可為偵測/儲存之度量自身。舉例而言,且參 '、、、圖中所示之實施例,在步驟ό 12處所收集之實體資源度 量包括在調度之分割向量3〇8中所收集之CPI值,而在步驟 6 14處所計算之優先權值包括在以下參看圖8α及圖吒進一 =評細繪示及描述之程序中的自cpi值計算的記憶體佔用 里值。與在步驟615處之效能度量判定之同時,較佳地, 在分割之每—調度窗計算及更新諸如在分割歷史表305内 繪不之VAR值的可靠性因數,如在步驟616處所示。 參看圖8A,提供併入至步驟615中之處理步驟的更詳細 繪不。具體言之,圖8A說明繪示諸如由PMU 2〇4及超管理 器11 5執行以用於判定調度決策所利用之記憶體佔用量效 能值之步驟的高階流程圖。該程序開始於分割調度步驟 61〇且繼續進行至步驟8〇6,步驟8〇6繪示在調度之分割之 調度時期内的一時間間隔點tn判定及記錄之cpi資料。比較 jtn收集之CPI值與用於同一分割之先前記錄的(:1>1值。先 别。己錄的CPI值表示用於同一分割之在調度時期内之—較 早時點時料的。在調度時期循環巾之各種時點所 ,集之CPI資料的一例示性圖形表示展示於圖88中。調度 時期開始及結束之時點在圖8B中分別表示為在由TDP表示 之整個調度時期上的tG及tDP。將CPI f料經判定且記錄於 同一分割之-或多個此等調度中之時點表示為trec。、trecl、 t-2、trec3等。返回圖8八之步驟808 ’ 料值之間的比 129569.doc •26· 200905470 # : u ^ (例如)在時間tree2記錄的cpi值與在trecl記錄的cpi 比較。i ± ~較佳實施例中,在一給定邏輯分割之整個 5調度時期上執行在不同時間增量下的CPI資料判定。 發月考里關於重新確立在每—分割調度上之記憶體佔 置之需要的調度中的實質成本。在步驟繼處執行之比 之目的在於判定分割確立記憶體佔用量所需的時期。記 憶體佔用量確立判定包含判定一拐角點(諸如在圖8B中之 trec3處所繪示)’在該拐角點處,CPI值自在先前調度時期 之先前時間增量處記錄之cpi值位移小於一指定臨限值。 在圖8B中’時間trec3表示一拐角點,在該拐角點處,在 tree3處記錄之CPI值與在La處記錄之值不同,該不同小於 臨限差Δ(:ΡΙΤΗ]^ΗΙ^。佔用量時期Tfp因此為· 之間的 時期。CPI值之間的差異是否小於一具體臨限值之判定繪 示於步驟8 1 0。 回應於未超過臨限CPI差值,在步驟8〇6處記錄的〇1>1值 (亦即’最後CPI值)被記錄(步驟812),且在返回至步驟61〇 處的同一分割之下一個調度前’增加下一個調度時期之記 錄間隔(步驟814)。當一給定比較(例如在tre<;3處收集的cpi 值與先前在trec2處收集的CPI值之間)導致符合臨限準則 時’與諸如在分割歷史表305中之分割之識別碼相關聯記 錄分割的佔用量確立時期(步驟8 1 6)。 參看圖6,且繼續如在步驟618處所示,超管理琴〖η及/ 或PMU 204可判定邏輯分割中之每一者的調度時期利用。 在步驟61 8處之判定用以將每一邏輯分割分類為使用大體 129569.doc -27- 200905470 上所有其組態之調度時期配置的批次分割或者經受處理中 斷之互動勿割’在處理中斷中,在一調度時期期間,分巧 必須等待一外部事件。分類為批次分割之經調度之分割將 利用大體上整個調度時期,而互動分割經受處理中斷,例 如當處理暫時中止且必須等待來自另一程序之回應時。若 -給疋分割之調度時期利用超過m限值(在一實施 例中,該臨限值為95%利用),則將該分割分類為批次分割 (步驟618及步驟622)。否μ,如在步驟川及以❹處所描 繪’將該分割分類為互動。 調度時期利用分類作為一欄位包括於先前在圖5中所繪 不之每-分割的分割控制區塊中,且可由超管理器u5用 作排程優先權準則。舉例而言,超管理器u5可將識別為 互動之分割自替換仔列5G5(見圖5)中的合格替換分割排 除。此外,且如下文參看圖7所解釋,調度時期利用分類 可由超管理器用以判定是否將一調度窗之剩餘部分重新配 置至已先佔或替換之原始分割。 如在步驟624及626處所示,判定分割排程優先權值之程 序結束’其中輸人或更新諸如彼等在分割歷史表3〇5及 PCB 502a-502n中儲存之優先權值的優先權值。如以上參 看圖3至® 5所繪示及解釋,硬體㈣之效能度量與邏輯分 割相關聯(諸如,在分割歷史表3〇5中)且由超管理器⑴用 以判定諸如由替換佇列5〇5確定之優先排序的優先排序。 在一較佳實施例中,可在系統啟動時期期間執行調度時期 利用分類及效能度量判定’可在時間上(例如,五分鐘)或 129569.doc -28- 200905470 者經由分割調度仵列之指定數目的旋轉來量測該系統啟動 時期。在收集至少—初純優先排序資料後,超管理器 出將資料用於經調度之分割及其他排程決策的替換及可 能先佔。 圖7為說明根據本發明之由諸如超管理器115中之調度器 的調度器執行以平衡邏輯分割間之工作負載之步驟的:階 流程圖。如在㈣7〇2及71()處所示’程序開始於超管理器 Π5根據系統組態之分割排程調度下一組一或多個分割。 在目前調度循環期間,記錄及更新包括經調度之分割的 CPI及CLC的實體系、统資源度量(步驟712),且更新諸如彼 等在圖6之步驟614處計算之替換優先排序值的替換優先排 序值(步驟713)。 如在步驟714處所繪示,超管理器115可根據分割替換優 先排序資料判定一給定調度之分割是否可被先佔。如本文 中所利用’分割先佔類似於在替換—調度窗期間已放棄之 經调度之分割中所採用之機制中的許多㈣且包括該等機 制。差異在於:分割先佔可能不需要經替換之分割已暫時 中止處理作為觸發本文中所描述之替換步驟的條件。如在 步驟714及720處所示,回應於判定已符合一給定經調度之 分割之預指定的先佔準則(鑒於諸如彼等包含在分割歷史 表305中之優先排序值的優先排序值),超管理器11 5暫時 中止經調度之分割且將系統資源配置至調度窗中之剩餘者 (可此整個)的一選定分割。以與下文參看步驟718及圖9描 述之排程優先排序步驟相同或類似之方式,根據替換優先 129569.doc -29- 200905470 權資料來選擇替換分割。超管理器115使用替換件列⑽及 分割控制區塊5〇2a_5()2n中之優先排序資料判定下—個待 調度或在其他情況下為目前調度之分割是否將由—選定替 換分割先佔。 自選疋替 若不符合先佔準則(步驟714)且原始排程之分割利用其 整個調度配置時期(亦# ’分割並不暫時中止處理)(步驟 716),則超管理器調度/載入平衡程序,繼續進行步驟71〇 處之下一個調度。 右經调度且未先佔《分割在調丨窗時期期間暫時中止處 理(步驟716) ’則超管理器U5處理可用分割之替換佇列奶 二或分割㈣區塊502a_5〇2n提供之替換優先排序資料判 疋疋否已符合預指定之分割替換準則(步驟7丨8)。 在步驟718處繪示之替換判定較佳地包括評估目前閒置 邏輯分割之替換優先權值以判定該等分割中之哪一者適合 替換目前暫時中止之分割。替換合格性判於強加的限 制(諸如調度窗之受限的剩餘部分)評估包括於分割控制區 塊502a-502nf之分割替換優先權值中的一或多者(例如記 :體佔用量值)。舉例而言,原始調度之分割具有一分割 窗時期tdw,對於IBM之P0WER5架構而言,其為1〇阳“。。 調度®時期TDW由調度增量τ则则有效地相除,咖為 刀割之經組態的最小運作時間增量且因此為超管理器U 5 °替換或先佔一經調度之分割的最小增量。在此等情況 下在步驟71 8處之替換準則判定包括判定可用替換分割 中之哪些係合格的(鑒於由暫時中止之分割之Tdpstch及丁_ 129569.doc •30· 200905470 之其餘部分強加的限制)。 本=括一確保指定排程效率層級之 在流程圖,階二 由刀割排孝王益在判定是否已 在以確保指定處理效率層級之方式選擇及 行的步驟。如在步驟902及904處所示,程序門:^所執 事件’例如符合先佔準則或者經調度之分物;::替換 而促成替換準則判定。在步物處所示之替換準則判! =權T及9°8’其用於使用可用分割之記憶體佔用 憂先榷值以及調度窗之剩餘可用部分兩者來選擇一替換 分割。 、 步物說明如可記錄於分割控制區塊及/或分割歷史表 305中之針對一可用替換分割之佔用量確立時期ip是否小 於調度窗之剩餘部分T—ing的判定。此外,在步驟鶴處 所不之判疋利用一可調諧因數χ,可將該可調諧因數X設定 為:大於1之值以判定針對一分割之Tfp值是否形成可用調 度®時期T_inin之充分小的部分8,使得可達成指定處理效 率層級。舉例而言,在一實施例中,在步驟718處,超管理 器1丨5根據替換邏輯分割是否具有滿足關係式xTfp s Trem仏— (其中X大於1且較佳地至少為10)之判定的記憶體佔用量值g Tfp來制定替換決策。 如在步驟906及908處所示,若不符合替換優先權值評估 準則’則排除該分割作為可能的替換。對分割中之一或多 者執行步驟906,直至符合替換準則,且如在步驟91〇處所 129569.doc -31 - 200905470 示,該程序結束。 返回至圖7,回應於選擇一替換分割,超管理器1丨5自經 替換之分割解除配置調度窗資源且將該等資源配置至選定 替換分割(步驟720)。如參看圖5及圖6所繪示及描述,若已 將替換之分割分類為非互動(亦即,批次),則替換分割消 耗剩餘調度窗時期,且程序返回至下一個調度循環(步驟 722及71〇)。然而,若替換之分割為互動分割(步驟722), 則調度剩餘調度窗時期之一子集的替換分割(步驟723)。在The effectiveness of one or more of the poor systems in the physical system associated with the logical division of the resources to the I during the suffocation. Xia ^ 615). Performing performance metric tracing at the hardware level of the programming interrupt (e.g., operating system outages) and performance metric tracing preferably include tracking CPI and other entity processing metrics. As shown in FIG. 6, the tracking entity resource metric includes the following sub-steps in the bucket, the scheduled partition-associated tracking metric, and wherein the metric is calculated using the hardware debt measure or determined by the hyper-manager 115 A prioritized value used to split replacement or other scheduling decisions. As depicted at step 612, the hardware hierarchy, the section, and the buffer state are used to record an entity resource metric associated with the recording time increment Δΐ ε (the recording rate is 隹β μ 疋 hand collection and storage and partitioning) The time increment ^ small ', in addition to the increment factor greater than 1, divided by the scheduling period defined by the scheduling period τ 八 8 * 4 1 DP is the number. After the collection of hardware intrusion of physical resource metrics and / or The result of the hardware detection of the body detection S. 129569.doc -25- 200905470, the priority value associated with the segmentation is calculated (step 6丨4). The priority value is calculated by the hardware detection/storage entity system metric or may be the detection/storage metric itself. For example, and referring to the embodiment shown in ',, and the figure, at step ό 12 The collected physical resource metric includes the CPI value collected in the scheduled segmentation vector 〇8, and the priority value calculated at step 614 is included in the following description with reference to FIG. 8α and FIG. The memory occupied by the cpi value in the program takes up the value. While determining the performance metric at step 615, preferably, each of the partitioning-scheduling windows calculates and updates a reliability factor such as a VAR value that is not plotted in the segmentation history table 305, as shown at step 616. Referring to Figure 8A, a more detailed depiction of the processing steps incorporated in step 615 is provided. In particular, Figure 8A illustrates the use of, for example, PMU 2〇4 and hypervisor 11 5 for use in determining scheduling decisions. A high-level flow chart of the steps of the memory occupancy performance value. The process begins with the segmentation scheduling step 61 and proceeds to step 8〇6, which depicts a time interval within the scheduling period of the scheduled segmentation. Point tn determines and records the cpi data. Compares the CPI value collected by jtn with the previous record used for the same segmentation (:1>1 value. First, the recorded CPI value indicates that the same segmentation is used during the scheduling period. - an earlier time point. In the scheduling period, an exemplary graphical representation of the CPI data is shown in Figure 88. The starting and ending times of the scheduling period are indicated in Figure 8B as TDP table tG and tDP over the entire scheduling period. The time points at which the CPI f is judged and recorded in the same partition - or a plurality of such schedules are represented as trec., trecl, t-2, trec3, etc. Returning to Figure 8 Step 808 'The ratio between the values 129569.doc •26·200905470 # : u ^ (for example) the cpi value recorded at time tree2 is compared with the cpi recorded in trecl. i ± ~ in the preferred embodiment, in one The CPI data determination at different time increments is performed over the entire 5 scheduling periods of a given logical partition. The substantial cost in the schedule for re-establishing the memory occupancy requirements on each-segmentation schedule. The purpose of the ratio performed at the step is to determine the period required for the segmentation to establish the memory footprint. The memory footprint establishment decision includes determining a corner point (such as depicted at trec3 in FIG. 8B) at which the CPI value is less than a specified displacement from the previous time increment of the previous scheduling period. Threshold. In Fig. 8B, 'time trec3 indicates a corner point at which the CPI value recorded at tree3 is different from the value recorded at La, which is smaller than the margin difference Δ(:ΡΙΤΗ)^ΗΙ^. The quantity period Tfp is therefore the period between ·. The determination of whether the difference between the CPI values is less than a specific threshold is shown in step 8 1 0. In response to not exceeding the threshold CPI difference, at step 8〇6 The recorded 〇1>1 value (i.e., the 'last CPI value') is recorded (step 812), and the recording interval of the next scheduling period is increased before returning to the next division under the same division at step 61 (step 814). When a given comparison (eg, between the cpi value collected at tre<;3 and the CPI value previously collected at trec2) results in compliance with the threshold criteria, the identification with the segmentation such as in the segmentation history table 305 The code associated record partitioned occupancy establishment period (step 8 16). Referring to Figure 6, and continuing as shown at step 618, the hypermanipulation η and / or PMU 204 can determine each of the logical partitions The scheduling period is utilized. The decision at step 61 8 is used to The segmentation is classified as batch splitting using all of its configured scheduling period configurations on 129569.doc -27- 200905470 or interacting with processing interrupts. In processing interrupts, during a scheduling period, the trick must wait An external event. The scheduled segmentation classified as batch segmentation will utilize substantially the entire scheduling period, while the interactive segmentation is subject to processing interruptions, such as when the process is temporarily aborted and must wait for a response from another program. The scheduling period utilizes a value exceeding the m limit (in one embodiment, the threshold is 95% utilized), and the segmentation is classified into batch segmentation (steps 618 and 622). No, as in the step and The segmentation is classified as an interaction as depicted in the ❹. The scheduling period uses the classification as a field included in the split control block previously described in FIG. 5, and can be used as a row by the hypervisor u5. The procedure priority criterion. For example, the hypervisor u5 may exclude the qualified replacement segmentation in the segmentation self-replacement row 5G5 (see Figure 5) identified as an interaction. As explained in Figure 7, the scheduling period utilization classification can be used by the hypervisor to determine whether to reconfigure the remainder of a scheduling window to the original partition that has been preempted or replaced. As shown at steps 624 and 626, the decision to split the scheduling priority is determined. The end of the value program 'inputs or updates such as their priority values stored in the split history table 〇5 and the PCB 502a-502n. As shown and explained above with reference to Figures 3 through 5, The performance metric of hardware (4) is associated with logical partitioning (such as in partitioning history table 〇5) and is used by hypervisor (1) to determine prioritizations such as prioritization determined by replacement queues 5〇5. In a preferred embodiment, the scheduling period can be performed during the system startup period using the classification and performance metrics to determine 'in the time (eg, five minutes) or 129569.doc -28-200905470 through the split scheduling A number of rotations to measure the system startup period. After collecting at least the primary pure prioritization data, the hypervisor uses the data for the replacement of the scheduled segmentation and other scheduling decisions and may preempt. Figure 7 is a flow diagram illustrating the steps performed by a scheduler, such as a scheduler in hypervisor 115, to balance the workload between logical partitions in accordance with the present invention. As shown at (4) 7〇2 and 71(), the program starts with the hypervisor Π5 to schedule the next set of one or more splits according to the system configuration split schedule. During the current scheduling cycle, the real system and system resource metrics including the scheduled split CPI and CLC are recorded and updated (step 712), and the replacement of the replacement prioritized values, such as those calculated at step 614 of FIG. 6, are updated. The value is prioritized (step 713). As depicted at step 714, the hypervisor 115 can determine whether the segmentation of a given schedule can be preempted based on the segmentation replacement priority ranking data. As used herein, "split preemption is similar to many of the mechanisms employed in the scheduled split that have been abandoned during the replacement-scheduling window and includes such mechanisms. The difference is that the split preemption may not require a replacement split that has temporarily aborted processing as a condition to trigger the replacement step described herein. As shown at steps 714 and 720, in response to the pre-specified preemption criteria that determine that a given scheduled partition has been met (in view of the prioritized values such as their prioritized values included in the partition history table 305) The hypervisor 11 5 temporarily suspends the scheduled partitioning and configures the system resources to a selected partition of the remainder of the scheduling window (which may be the whole). The replacement segmentation is selected according to the replacement priority 129569.doc -29-200905470 weighting material in the same or similar manner as the scheduling prioritization step described below with reference to step 718 and FIG. The hypervisor 115 uses the prioritized data in the replacement column (10) and the segmentation control block 5〇2a_5() 2n to determine whether the next segment to be scheduled or otherwise scheduled for the current segment will be replaced by the selected segmentation preemption. If the self-selection does not meet the preemption criteria (step 714) and the partitioning of the original schedule utilizes its entire scheduling configuration period (also # 'division does not temporarily abort processing) (step 716), then the hypervisor dispatch/load balance The program continues with the next step at step 71. The right is scheduled and does not preempt the "temporarily suspend processing during the tuning window period (step 716)." Then the hypervisor U5 processes the replacement partitioning provided by the alternative partitioning or the partitioning (four) block 502a_5〇2n. The data is judged to have met the pre-specified segmentation replacement criteria (steps 7 and 8). The replacement decision depicted at step 718 preferably includes evaluating the replacement priority value of the current idle logical partition to determine which of the partitions is suitable for replacing the currently suspended split. The replacement eligibility is determined by the imposed restrictions (such as the remaining portion of the restricted scheduling window) to evaluate one or more of the segmentation replacement priority values included in the segmentation control blocks 502a-502nf (eg, body occupancy values). . For example, the split of the original schedule has a split window period tdw. For IBM's P0WER5 architecture, it is 1 “ “.. Scheduling® period TDW is effectively divided by the scheduling increment τ, The configured minimum operating time increment and thus the super-manipulator U 5 ° replacement or preemption of the minimum increment of the scheduled segmentation. In this case the replacement criteria decision at step 718 includes determining that the decision is available Which of the subdivisions is qualified (in view of the restrictions imposed by the temporarily discontinued Tdpstch and the remainder of Ding _ 129569.doc • 30· 200905470). This = a path to ensure that the scheduling efficiency level is specified, Step 2 is determined by the knife cut Xiao Wangyi in determining whether or not the steps are selected and executed in a manner to ensure the specified processing efficiency level. As shown at steps 902 and 904, the program gate: ^ the executed event 'for example meets the preemptive criteria Or the dispatched component;:: replaces to facilitate the replacement criterion decision. The replacement criteria shown at the step are judged! = the weight T and 9°8' are used to use the available memory to occupy the stagnation value and Scheduling The remaining available portions are used to select a replacement segment. The step description is as to whether the occupancy period ip for an available replacement segment can be recorded in the segmentation control block and/or the segmentation history table 305 is less than the remaining of the scheduling window. The determination of the partial T-ing. Furthermore, in the case where the step crane does not use a tunable factor χ, the tunable factor X can be set to a value greater than 1 to determine whether a Tfp value for a segmentation forms an available schedule. A sufficiently small portion 8 of the period T_inin, such that a specified level of processing efficiency can be achieved. For example, in an embodiment, at step 718, the hypervisor 1丨5 according to the replacement logic segmentation has a satisfaction relationship xTfp s The memory occupancy value g Tfp of the decision Trem 仏 - (where X is greater than 1 and preferably at least 10) to make an alternative decision. As shown at steps 906 and 908, if the replacement priority value evaluation criteria are not met 'Exclude the segmentation as a possible replacement. Step 906 is performed on one or more of the segments until the replacement criteria are met, and as in step 91, the location 129569.doc -31 - 200905470 The program ends. Returning to Figure 7, in response to selecting a replacement segmentation, the hypervisor 1丨5 deconfigures the scheduling window resources from the replaced segmentation and configures the resources to the selected replacement segmentation (step 720). 5 and FIG. 6 , if the alternative segmentation has been classified as non-interactive (ie, batch), the replacement segmentation consumes the remaining scheduling window period, and the program returns to the next scheduling cycle (step 722 and 71〇). However, if the alternative segmentation is an interactive segmentation (step 722), then a replacement segmentation of a subset of the remaining schedule window periods is scheduled (step 723).
替換調度時期之完成後,將調度窗資源重新配置至原始替 換的分割(步驟724),且程序繼續(步驟726)或結束(步驟 728)。 圖1〇說明根據本發明之在一調度窗内的分割排程。圖1〇 中所示之調度窗經部分定義為具有一組態之調度窗時期 tdw其開始於tstart且結束於tfinish ’且其由超管理器115内 之計數器特徵(在該圖式中未明確地繪示)實施,該計數器 特徵為超管理器115提供在指定調度窗間隔上之分判活動 :定時中斷。在所緣示之實施例中,表示為^户私之 分割由超管理器115以調度窗内之交錯的時間間隔(其分別 ^始於時間tstart、tl及t2)調度。按照邏輯分割排程習慣, :割户”户邮各具有超管理器115將用於排程之預植能 、洞度時期權利以確保分割接收到其各別的最小權利。 在所繪示之實施例中,分割户戶 W中分別綸- 2及匕之取小權利在圖 J繪不為自tstart-t丨、t丨-t2及t2~t3之瞎如, 後為自 寻期。在榷利時期 ’、、、3_ finish之剩餘時期,在該剩餘時期中,分割户、尸 129569.doc -32- 200905470 3了由超官理器115根據公平性 調度。& π ρ 十丨生及排程優先排序因數來 度此外,且如上所解釋, 對分割6在其授權之,… 了暫0"中止處理,如針 议櫂之調度時期内所說明。 圖11為繪示根據本發明之 間t八$1 W 1 如在圖10中所示之調度窗期 間之刀割排程調諧的高階流 千,# #广 白L程圖。如在步驟1102處所繪 f亦 發出開始下一個調度窗之信號的硬 (亦P ’與为割活動無關)中 _ 辦在、滅續如在步驟1104處所 不,對於提供諸如分割p/、 4a ^ ^ μ 2及h中之—者的邏輯分割之 二的循%榷利之時期,調度該分割。參看圖⑺,第— 日期係針對在處調度指定數目個循環之分割户/。 若屬於該經調度之分宝丨丨&览 沒<刀割的邏輯處理器並不暫時中止處理 (步驟1106) ’諸如’對於自調度之分割&,且需要 進-步的權利配置(步驟11〇8),則調度下一個排程之分割 :例如’分割户綱1104)。若在配置最小權利(步驟謂)After completion of the replacement scheduling period, the scheduling window resource is reconfigured to the original replacement partition (step 724), and the program continues (step 726) or ends (step 728). Figure 1 illustrates a split schedule within a dispatch window in accordance with the present invention. The scheduling window shown in FIG. 1A is partially defined as having a configured scheduling window period tdw that begins at tstart and ends at tfinish 'and is characterized by a counter within the hypervisor 115 (not explicitly defined in the schema) The implementation is characterized in that the counter feature provides the hypervisor 115 with a sub-task activity at a specified scheduling window interval: a timed interrupt. In the illustrated embodiment, the segmentation indicated as being private is scheduled by hypervisor 115 at interleaved time intervals within the scheduling window (which respectively begin at times tstart, t1, and t2). According to the logical division of scheduling habits, the cut-off households each have a super-manager 115 that will be used for scheduling pre-planting energy and hole period rights to ensure that the split receives its respective minimum rights. In the embodiment, the right to take the singularity of the singularity of the singularity of the singularity of the singularity of the singularity of the singularity of the singularity of the singularity of the singularity of the singularity of the singularity of the singularity of the singularity During the remainder of the profit period ', , and 3_ finish, in the remaining period, the households and corpses 129569.doc -32- 200905470 3 were dispatched by the super-president 115 according to fairness. & π ρ And the scheduling priority factor is furthermore, and as explained above, for the segmentation 6 in its authorization, ... the suspension process, as explained in the scheduling period of the needle. Figure 11 is a diagram illustrating the invention according to the present invention. Between eight eight $1 W 1 as in the scheduling window shown in Figure 10, the high-order flow of the knife-cut schedule is tuned, ##广白L程图. If the f is drawn at step 1102, the next schedule is also issued. The hard signal of the window (also P' is not related to the cutting activity) _ is in, is not as in step 1104, The segmentation is scheduled to provide a period of profitability such as splitting p/, 4a^^^2, and h. Referring to Figure (7), the first date is a specified number of cycles for scheduling anywhere. The partitioned household /. If it belongs to the scheduled branch, the logical processor that does not cut the knife does not temporarily suspend the processing (step 1106) 'such as 'for self-scheduling split & - Step right configuration (steps 11〇8), then schedule the next schedule partition: for example, 'divided household 1104'. If the minimum right is configured (step is)
後消耗了整個調度窗時期(步驟ni〇),則程序返回至步驟 1102以針對下一個調度窗時期。 除了調度以付合分割權利之外,超管理器! Μ較佳地利 用自其他排程試探中之與分割相關聯之效能度量得出的優 先排序因數(例如記憶體佔用量值)來動態地排程該等分 割。超管理H115將效能度量得出之優先排序用於排程之 :情況展示於圖U中’其作為圖1G中㈣之在分割^已暫 時中止處理之點tsus下的暫時中止的邏輯處理器條件(步驟 1106)。說明於圖n中之其他此種情況為開始於額外循環 仍處於調度窗中之t3處的權利後排程(步驟1108及1110)。 129569.doc -33- 200905470 回應於一分割之暫時中止的處理(步驟1 i 06)或調度窗中 之附加循環之可用性’超管理器i 15開始在步驟720處之調 度’其包括下列子步驟。藉由比較確立分割中之每一者的 記憶體佔用量之時間與調度窗中剩餘之時間,來判定該等 为割之調度合格性(步驟1112)。每一步驟1112合格的分割 接著經根據其各別佔用量確立成本而優先排序,如在步驟 1114處所說明。舉例而言,儲存之統計指示每一分割確立 記憶體佔用量所需之時間量。如上參看圖9所解釋,記憶 體佔用里確立時期可用以判定調度一特定分割之相對效 率,其中保留一受限調度窗時期。在步驟⑴4處執行之優 先排序可因此包括圖4及圖9中所繪示之步驟。如步驟⑴6 處所不來調度根據步驟ln4處之優先排序選擇的分割。 使用提供可用於各電腦或工作站硬體平台上之攜帶型源 碼之目標或目標導向軟體開發環境,可易於將所揭示之方After the entire dispatch window period is consumed (step ni〇), the program returns to step 1102 for the next scheduled window period. In addition to scheduling to pay for splitting rights, Super Manager! Preferably, the prioritization factors (e.g., memory footprint values) derived from the performance metrics associated with the segmentation in other scheduling heuristics are used to dynamically schedule the segments. The super-management H115 prioritizes the performance metrics for scheduling: the situation is shown in Figure U, which is the logical processor condition of the temporary abort under the point tsus of the split ^ temporary abort processing in Figure 1G (4) (Step 1106). The other case illustrated in Figure n is the right post-scheduling (steps 1108 and 1110) starting at t3 in the dispatch window starting with the extra loop. 129569.doc -33- 200905470 Responding to the processing of a split temporary suspension (step 1 i 06) or the availability of an additional loop in the dispatch window 'super manager i 15 starts the scheduling at step 720' which includes the following substeps . The scheduling eligibility for the cuts is determined by comparing the time at which the memory occupancy of each of the partitions is established with the time remaining in the schedule window (step 1112). The qualifying segments for each step 1112 are then prioritized by establishing costs based on their respective occupancy levels, as illustrated at step 1114. For example, the stored statistics indicate the amount of time required for each segment to establish a memory footprint. As explained above with reference to Figure 9, the settling period in memory occupancy can be used to determine the relative efficiency of scheduling a particular segmentation, wherein a restricted scheduling window period is retained. The prioritization performed at step (1) 4 may thus include the steps illustrated in Figures 4 and 9. The segmentation selected according to the prioritization at step ln4 is not scheduled as in step (1)6. It is easy to use the target or target-oriented software development environment that provides portable source code for each computer or workstation hardware platform.
法實施於軟體中。為T 障 可將本發明之方法及系統 :施為谈入於個人電腦上之常式(例如⑽或⑽指、 =為駐留W器或圖形工作站上之資源'實施為嵌人 於專用源碼編輯器管理系統中之 吊式或其類似物。 雖…彳已參照一較佳實祐你丨姓a R _ 孰習此姑 、疋展不及描述了本發明,但 热各此項技術者將理解, 认卜主、σ 不脱離本發明之精神及範择 的情況下對本發明進行形式 f汉軏可 t式及細郎之各種改 實施皆屬於本發明之範疇。 種文變此專替代 【圖式簡單說明】 圖1說明根據本發明之用 以實施工作負載平衡及調度窗 129569.doc •34· 200905470 調諧之虛擬計算系統; 圖2為繪示根據本發明之-實施例之用以促進分割排程 之一例示性架構的高階示意圖; 、為說明如可實施於圖2中所纷示之架構内之—分割監 視早π之内部架構、超管理器及分割歷史表的高階示音、 圖; 〜 圖4為根據本發明之用 月之用於判疋邏輯分割之替換優先排序 之一序列的高階方塊圖表示; 圖5如根據本發明實施之_ 圖表示; 調度益狀態的高階方塢 圖6為繪示根據本發明 ^ t 由刀割監視單元執行之步驟乃 用於判定替換優先權之了之步驟及 又35的向階流程圖; 圖7為說明根據本發明之,划m 輯分割間之,載的分:調… 階流程圖; %序』間執仃之步驟的高 圖8A為繪示根據本發 執行來判定用於調度替換決策分割監視單元 步驟的高階流程圖,·束之記憶體佔用量效能度量之 圖8B為根據本發明之如在 合;te e & 個調度®循核上收隼$ I it …展數目資料的圖形表示; ㈣之母才日 為。兒明由一分割排程器在選擇 步驟的高階流程圖; 营換刀割中執行之 圖10說明根據本發明之在— 圖η為繪示根據本發明之由=内之分割排程;及 由分割監視單元執行用於在— 129569.doc -35- 200905470 調度窗期間動態地調諧分割排程器之步驟的高階流程圖。 【主要元件符號說明】 100 虛擬計鼻糸統 102A 應用程式 102B 應用程式 102C 應用程式 102D 應用程式 104 A 作業系統 104B 作業系統 104C 作業系統 104D 作業系統 105A 邏輯分割 105B 邏輯分割 105C 邏輯分割 105D 邏輯分割 106A OS工作負載管理器 106B OS工作負載管理器 106C OS工作負載管理器 106D OS工作負載管理器 108 處理器CPU 110 處理器CPU 112 處理器CPU 114 處理器CPU 115 超管理器 129569.doc -36- 200905470 117 120 121 122 125 200 204 ^ 206 208 210 212 214 302 304 305 i- 308 310 312 314 322 402 404 406 共用處理器集區 韌體層資源 記憶體裝置 硬體層資源 記憶體裝置/共用記憶體 分割排程架構 分割管理單元/分割監視單 元(PMU) 快取記憶體 CPU介面 快取-記憶體介面 CPU-快取介面 快取介面 追5從邏輯模組 優先權值計算模組 分割歷史表 分割向量 分割向量 分割向量 CPU介面暫存器 處理器利用資源暫存器 基礎優先權bp(Pi) 優先權求和dStj 當前優先權cp(Pi,t) 129569.doc -37- 200905470 412 佔用量計算模組Θ 416 可靠性因數計算模組ς 418 基於效能之因數Δρ 420 調整 425 整體優先權值/排程優先權 502a 分割控制區塊 502b 分割控制區塊 502n 分割控制區塊 505 替換佇列 CA 快取相關性 CLC 快取列計數 CMC 快取未中計數 CPI 每指令循環數目 CPU1、CPU2、CPU3、 CPU4 處理器 LP1 ' LP2........LPa、· ......lpn邏輯分割 Ml、M2、M3、M4 快取記憶體 Pi 分割 P2 分割 P3 分割 PCB 分割控制區塊 t〇 調度時期開始之時點 ti 時間點 h 時間點 h 時間點 129569.doc •38- 200905470The law is implemented in software. The method and system of the present invention can be implemented as a routine on a personal computer (for example, (10) or (10) refers to, = is a resource on a resident W or a graphics workstation' implemented as a dedicated source code editor. In the management system of the crane or the like. Although ... has been referred to a better, you are a surname, a R _ 孰 此 姑 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 描述 描述 描述 描述 描述 描述 描述 描述, the recognition of the master, σ without departing from the spirit and scope of the present invention, the implementation of the present invention, the form f, and the implementation of the various modifications are all within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates a virtual computing system for implementing workload balancing and scheduling windows 129569.doc • 34·200905470 tuning in accordance with the present invention; FIG. 2 is a diagram illustrating an embodiment of the present invention for facilitating A high-level schematic diagram of an exemplary architecture of a partitioning schedule; to illustrate the high-level sounding of the internal architecture, hypervisor, and partition history table of the partitioning monitoring early π, as may be implemented in the architecture illustrated in FIG. Figure; ~ Figure 4 is based on this issue A high-order block diagram representation of a sequence of alternative prioritizations used to determine logical partitioning; FIG. 5 is a representation of a high-order square diagram of a scheduling benefit state; ^ t The steps performed by the knife-cutting monitoring unit are used to determine the step of replacing the priority and the step-by-step flowchart of 35. FIG. 7 is a diagram illustrating the division between the divisions according to the present invention: The high-level flow chart of the steps of the step-by-step flow chart; the process of determining the segmentation monitoring unit for scheduling the replacement decision according to the execution of the present invention, the memory occupancy performance measure of the bundle Figure 8B is a graphical representation of the data of the number of exhibitions received in accordance with the present invention; e e & scheduling ® 循 ; ; ; ; ; ; ; ; ; ; ; ; I I I I I I I I I I I I I I I I I I I I I I Figure 10 is a flowchart of the selection process; — 129569.doc -35- 200905470 Dispatch High-level flow chart for dynamically tuning the steps of dividing the scheduler. [Main component symbol description] 100 virtual computing system 102A application 102B application 102C application 102D application 104 A operating system 104B operating system 104C operating system 104D Operating System 105A Logical Segmentation 105B Logical Segmentation 105C Logical Segmentation 105D Logical Segmentation 106A OS Workload Manager 106B OS Workload Manager 106C OS Workload Manager 106D OS Workload Manager 108 Processor CPU 110 Processor CPU 112 Processor CPU 114 Processor CPU 115 Hypervisor 129569.doc -36- 200905470 117 120 121 122 125 200 204 ^ 206 208 210 212 214 302 304 305 i- 308 310 312 314 322 402 404 406 Shared processor pool firmware layer resource memory Body device hardware layer memory device / shared memory partition scheduling architecture partition management unit / partition monitoring unit (PMU) cache memory CPU interface cache - memory interface CPU - cache interface cache interface 5 slave logic Module priority value calculation module segmentation history table segmentation Split vector partition vector CPU interface register processor utilize resource register base priority bp(Pi) priority sum dStj current priority cp(Pi,t) 129569.doc -37- 200905470 412 occupancy calculation module 416 416 Reliability Factor Calculation Module 418 418 Performance-Based Factor Δρ 420 Adjustment 425 Overall Priority Value/Scheduled Priority 502a Split Control Block 502b Split Control Block 502n Split Control Block 505 Replace 伫 CA CA Cache Correlation CLC cache column count CMC cache miss count CPI number of instruction cycles CPU1, CPU2, CPU3, CPU4 processor LP1 'LP2........LPa, ·...lpn logical split Ml , M2, M3, M4 cache memory Pi split P2 split P3 split PCB split control block t〇 schedule start time point ti time point h time point h time point 129569.doc •38- 200905470
tDP 調度時期結束之時點 Tdp 分割調度時期 Tdw 調度窗時期 tfinish 時間點 Tfp 記憶體佔用量值 Tfp 記憶體佔用量時期值 trec0 時點 tree 1 時點 trec2 時點 trec3 時點 tstart 時間點 tsus 時間點 VAR 佔用量值變化 ACPIthrshld 臨限差 △tree 記錄時間增量 39- 129569.doctDP scheduling period end point Tdp split scheduling period Tdw scheduling window period tfinish time point Tfp memory occupancy value Tfp memory occupancy period value trec0 time point tree 1 time point trec2 time point trec3 time point tstart time point tsus time point VAR occupancy value change ACPIthrshld margin △tree recording time increment 39-129569.doc
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TWI831986B (en) * | 2019-09-19 | 2024-02-11 | 美商英特爾股份有限公司 | Technology for dynamically tuning processor features |
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TWI831986B (en) * | 2019-09-19 | 2024-02-11 | 美商英特爾股份有限公司 | Technology for dynamically tuning processor features |
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