200905217 九、發明說明： 【發明所屬之技術領域】 本發明大體上是關於—種使用於半導體製造中的方法 ’、表1特別疋關於—種用來測試半導體元件可靠度 (reliability)的方法與裝置。 【先前技術】 在現7半‘體積體電路的製造流程中，可靠度測試 (renabilitytest)為—不可或缺的環節。基本上，可靠度 可定義為：在一般的使用環境下，產品或裝置能順利、正 ¥運作的使用週期或壽命。因為半導體的線寬尺寸日益縮 J /、運作之時脈速度越來越快，故相對地，電路結構在 =件，作時所承載之電流與溫度亦就越來越高。在此種嚴 苛的％境下，多種機制都可能導致半導體元件或電路的運 作失效（fail)’像是「熱載子注入」（Hot Carrier Injection， HCI )、「金屬線電致遷移」（mectr〇migrati〇n，舰）、「應 力遷移效應」（stress migration，SM )、依時性介質崩潰 (Time Dependent Dielectric Breakdown，TDDB)、「負偏 [/皿度不穩定性」（Negative Bias Temperature Instability， NBTI )以及「正偏壓溫度不穩定性」（b心 Teniperature Instabmty，pBTI )等。上述各種會造成半導 體電路失效的機制都是由於其某一部份的元件在單一或綜 合的特定條件（例如溫度、電壓、電流以及濕度等）持續 施加下所誘發出來。舉例而言，熱載子效應大部分是因為 问電壓施加到汲極（drain )端，產生能量高的熱載子陷入 200905217 或注入氧化閘極層（gateoxide)造成元件定性的改變。而 金屬線電致遷移則是因為導體（如metalline)中電子與缺 陷晶格作用導致其金屬原子慢慢遷移造成開路或短路了、 圖一為一般半導體裝置中各種的可靠度測試種類以及 錢施加的測試條件。—般而言，表中的各種測試都可以 精由在一定時間内持續施加各種測試條件來達成，其測試 條件大部分為較高的溫度、電壓、電流以及濕度。由於各 種可靠度測試皆有其不同的測試項目、施加部位、施加條 T =、、且σ與大小’故於測試的過程中，能即時監控並同時 穩定各項所施加之測試條件就顯得非常重要。 、相關之專利如美國專利6,724,214射所揭露之可 度測試結構，此專利可實行HCI、tddb以及綱這三 可靠度測試。而美國料“，787,799號中則揭露一難置 用來f試半導體元件在高溫時之可靠度。在上述的專利 中，前者之，試結構雖能提拱三種不同的可靠度測試，但 之：二：° 以及回饋網路之整合’故只能判定元件測試 U而不％調整或敎測試時各項所施加的參數。 ΐ = = ί於只能提供溫度方面的測試條件，並無 法“在其他包含電壓、電流條件的可靠度測試中。故如 ^整合各種不同的測試條件以減少測試所需之時間 本’以及於測試期間提供穩定、多階可調變的施加心牛以 ^空測試時之狀態，是現今可靠度⑽可収 【發明内容】 π 為了達到上述目的 本發明提供一種用於半導體可靠 200905217 度測試之方法與裝置。其裝置主要包含：一整合器 (combiner)，與各施加電路以及待測裝置（dut)連接； 數個不同的測試條件施加電路，包含溫度、電壓與電流等 -種把力u條件來源，其可同時施加多組不同的測試條件到 待測裝置端；-回饋網路’自整合器連接至各施加電路端 與各待測裝置端。在測試開始前，使用者可先於整合器端 設定各項欲施加之測試條件值與（或）測試項目，其設定 可對應配合前述各種條件組合之可靠度測試。在測試期 間’整合ϋ可偵測並監控各待測裝置端的各項施加條件 值，並經由與各施加電路連接之回饋網路傳達動作指令， 要求施加電路提高或降低其施加條件的大小，以達到穩定 測試條件之效果。其監控機制也可讓整合器即時判定其待 測裝置之測試結果，以縮短測試的時間。 【實施方式】 如圖二所示，本發明之組成架構主要為一整人哭 、(combiner) 1與三種不同測試條件之測試模組整合ϋ 成，此二種測試模組包含分別為熱供給模組2，其得提供 多階測試溫度、電壓供給模組3,其得提供多階測試電位 與電流供給模組4，其得提供多階測試電流。整合器丨主 要的功能為穩定並監控所施加之測試條件並偵測判^ 定待 裝置之測試狀態（即測試之通過或失敗）。參照至圖三，為 本發明WLR之測試系統功能示意圖。測試線路所^加: 測試條件，如測試電壓V、測試溫度τ、以及測試電流工 等’會傳送到待測裝置端（DU丁，DeviceUnderT叫:， 7 200905217 整合器1將於其中監控。圖中 浐網攸^儿 虛線代表各電路之間的反 香气鉻杜处％ 其功此在於傳達動作訊息盥 以條件狀態，知行如下：待測裝置6於不同施 : 測試過程中會回饋其含有〃之 連接之整合㈣腺悲之訊號給與其 ㈣之i 4電路i，根據待測裝置6所回饋 設的設定條件值，整合器丨會 11 I、預 狀態而給予Μ連接之❹不同測試條件之 丁 /逑接之不冋施加電路（v，T, j 動作指令。舉例而言，當吾人$ 一 ： ’ 定溫測試，其待測參置6在 〜^為1〇〇°C的 時m以敕a 在 過程中會不斷回饋其即 人^^ΓΓ正口益卜在訊號接收的過程中，假如整 ^!接收到之回饋訊號反應出其受試裝置端之即時严产 超過其H)〇C之預定測試溫度，整合器i就會產生另； 作《給負責提供熱能的熱供給模組2 待測裝置端6的熱能;反之，如果待測裝置6回馈= 反應出其溫度低於預定之測試溫度，整合器i即會要求； 供給模組2提高熱能輸出。同樣的調節機制也能在電驗 給模組3以及電流供給模組4中實行。經由圖中即時回馈 網路FB之訊息傳遞，整人哭】a 梦署“… 夠居中調節並穩定待測 裝置6所被⑯加的各項測試條件，以控制可靠度測試 (Μ·1# teSt)中各種不同測試結構（test Structure )的 施加條件組合，因而能即時監控其受試狀態以保持測試之 精確度。整合器1得令使用者設定選擇所要之測試項目或 施加條件，包括各種晶圓妨& 分粳日日κ級（wafeMevel)或封裝級 (package-level)可靠度測試，如 TDDB、HCI、EM 等， 200905217 或是各項測試參數之預設值（如施加溫度、施加電壓以及 施加電流等）。 參照至圖四，其為圖三中其中一熱供給模組2之示意 圖，該熱供給模組2中配置多階溫度產生器2〇，其包含複 數定值電阻器―）R。電阻器R之材料可為金屬、 多晶矽、n，ell電阻、P_well電阻或是磊晶層等材質。於 測試期間，改變流經電阻器R之電流將可產生不同溫卢之 ，輸出。受到電流的影響，將產生不同程度之熱能=至 又，測裝置端（DUTs) 6。本例中配置的電阻器R之電阻 值疋固定的’其所能產生的溫度輸出主要由流經其中的電 流，來決定（圖中的n、I2以及13即表示不同的電流值）。 於實例中，整合器1能㈣到實際待測裝置端6之溫度。 在比較實際溫度與其預設之施加溫度後，整合器！會經回 饋網路7發出訊號至熱供給模組端2，指示改變其輸入電 流之大小，以穩定待測裝置端6之溫度。此外，熱供給模 組2也可同時提供多組不同的施加溫度到各待測裝置端 6w，如圖f中，丁卜仞及T3可代表三組數值不同的施加 咖度1可讓裝置同時測試三個不同溫度測試項目（或條 件）之待測裝f 6。須注意此實施例係用以說明，於實用 中，使用者可於熱供給模組2中配置更多的電阻器r來產 生更夕階的溫度輸出，並不限於此實施例中所示的三階。 參照至圖五，其為另一實施例中熱供給模組2之示音 圖。不同於上述實施例之實行方式，此實施例是藉由固； 之電流值I配合不同電阻值的電阻（Ri、r2&r3)來達 200905217 到=變其多階熱能輸出之㈣。以類似上—例的方式，在 固定的電流輸入下，經由可變電阻（R1、R2及R3)電阻 值之改、#’可達成我們要的多階熱能輸出，進而使待測裝 置端6達到預定之測試溫度。其整合器丄之調節與監控也 如同上例，經由-回饋網路7來傳送其指令訊號來達成。 參照至圖/、，其為電壓供給模組3中分壓器部位 (voltage divider) 8之示意圖。電壓供給模組3必須提供 一可調變且穩定的施加電壓（st⑽ed讀啊）給與其連 接之待測衆置。如圖所示，分㈣8電路中的第—端與第 二端分別輪合一電壓供應端VDD與一接地端9，其間配置 有數個彼此串連的電阻⑻…⑼及仏豆中盘接地 端相鄰接之電阻R為一電阻值相較電阻幻、们及R3為 小上許多的接地電阻，主要功能為安全防護、突波抑制盘 糸統穩定之用。在接地電阻R與電阻R1之間有一參考電 壓Vref自外部輸入，該參考電壓Vref來源為一能隙參考 jBand_gapreference)電壓，其主要功能為提供整體電路 -穩定、不受溫度或其供應電壓影響的電壓參考值。電壓 供給模組在電壓供應端VDD與參考電邀v 多個可變電阻串連設計，其目的為在電阻與電 Μ及R3之間）產生多個大小不同、可調變之電壓差 (如圖中的Δν卜AV2及㈣），以同時施加多植 電壓（即圖中的V1、V2&V3)至待測裝 ' 同時測試多組電壓施加條件不同的待 ^使其月 ……大小與—―力以及 200905217200905217 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention generally relates to a method for use in semiconductor fabrication, and in particular to a method for testing the reliability of a semiconductor device. Device. [Prior Art] In the current 7-and-a-half-body circuit manufacturing process, the renability test is an indispensable link. Basically, reliability can be defined as: the service life or life of a product or device that can be operated smoothly under normal usage conditions. Because the line width of semiconductors is shrinking J / , the clock speed of operation is getting faster and faster, so the current and temperature of the circuit structure are higher and higher when the circuit structure is in the case. In such a harsh environment, various mechanisms may cause failures in the operation of semiconductor components or circuits, such as "Hot Carrier Injection" (HCI) and "Metal Wire Electromigration" ( Mectr〇migrati〇n, ship), stress migration (SM), Time Dependent Dielectric Breakdown (TDDB), Negative Bias Temperature (Negative Bias Temperature) Instability, NBTI) and "positive bias temperature instability" (b core Teniperature Instabmty, pBTI). The various mechanisms described above that cause the failure of the semiconductor circuit are due to the fact that a certain part of the component is induced by a single or integrated specific condition (such as temperature, voltage, current, humidity, etc.). For example, the hot carrier effect is mostly due to the application of a voltage to the drain terminal, which produces a high-energy hot carrier trapped in 200905217 or injected into the oxide gate layer to cause a qualitative change in the component. The electromigration of metal wires is caused by the slow migration of electron atoms caused by electrons and defect lattices in conductors (such as metalline), causing open circuit or short circuit. Figure 1 shows various types of reliability tests and money application in general semiconductor devices. Test conditions. In general, the various tests in the table can be achieved by continuously applying various test conditions for a certain period of time, and the test conditions are mostly high temperature, voltage, current and humidity. Since various reliability tests have different test items, application sites, application strips T =, and σ and size, it is very timely to monitor and simultaneously stabilize the test conditions applied during the test. important. The related patents, such as the measurable test structure disclosed in U.S. Patent No. 6,724,214, are capable of performing HCI, tddb and the three reliability tests. The United States material ", 787, 799, reveals the difficulty of using f to test the reliability of semiconductor components at high temperatures. In the above patents, the former, although the test structure can be arched three different reliability tests, but: Two: ° and the integration of the feedback network 'so only can determine the component test U and not adjust or 敎 test the parameters applied. ΐ = = ί can only provide temperature test conditions, and can not Other reliability tests involving voltage and current conditions. Therefore, if you integrate various test conditions to reduce the time required for testing, and provide a stable, multi-step adjustable change during the test, the state of the test is the current reliability (10). SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a method and apparatus for semiconductor reliability 200905217 degree testing. The device mainly comprises: a combiner, which is connected with each application circuit and the device to be tested (dut); a plurality of different test condition application circuits, including temperature, voltage and current, etc., a source of force u conditions, Multiple sets of different test conditions can be simultaneously applied to the device end to be tested; the feedback network 'self-integrator is connected to each application circuit end and each device end to be tested. Before the test starts, the user can set the test condition value and/or test item to be applied before the integrator side, and the setting can be matched with the reliability test of the combination of the foregoing various conditions. During the test, the 'integration ϋ can detect and monitor each application condition value of each device end to be tested, and transmit an action instruction via a feedback network connected to each application circuit, requiring the application circuit to increase or decrease the size of the application condition. The effect of achieving stable test conditions. Its monitoring mechanism also allows the integrator to instantly determine the test results of its device under test to reduce test time. [Embodiment] As shown in FIG. 2, the composition of the present invention is mainly composed of a whole person crying, (combiner) 1 and three test modules of different test conditions, and the two test modules respectively include heat supply. The module 2, which provides a multi-stage test temperature and voltage supply module 3, is provided with a multi-stage test potential and current supply module 4, which provides a multi-stage test current. The main function of the integrator is to stabilize and monitor the applied test conditions and to detect the test status of the device to be tested (ie pass or fail of the test). Referring to Figure 3, it is a schematic diagram of the function of the test system of the WLR of the present invention. The test circuit is added: Test conditions, such as test voltage V, test temperature τ, and test current work, etc. will be transmitted to the device to be tested (DU Ding, DeviceUnderT called:, 7 200905217 Integrator 1 will be monitored. The dotted line of the 浐 浐 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表 虚线 虚线 虚线 虚线 虚线 虚线 虚线 虚线 虚线 虚线 虚线 虚线 虚线 虚线 虚线 虚线 虚线 虚线 虚线 虚线 虚线 虚线 虚线 虚线 虚线 虚线 虚线 虚线 虚线 虚线 虚线 虚线The integration of the connection (4) the glandular signal to the (4) i 4 circuit i, according to the set condition value of the device 6 to be tested, the integrator will give 11 I, the pre-state and give the connection to the different test conditions. Ding / 逑 之 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋In the process of 敕a, it will continue to give back to the person ^^ΓΓ正口益卜 in the process of signal reception, if the feedback signal received by the whole ^! reflects the immediate production of its test device end exceeds its H) 〇C's predetermined test temperature, the integrator i will produce another "As the heat supply to the heat supply module 2 responsible for providing thermal energy to the device 6 to be tested; conversely, if the device under test 6 is fed back = the temperature is lower than the predetermined test temperature, the integrator i will request; Group 2 improves the heat output. The same adjustment mechanism can also be implemented in the electricity test module 3 and the current supply module 4. Through the message feedback in the instant feedback network FB, the whole person cries] a dream office "... enough Centering adjusts and stabilizes the test conditions of 16 devices to be tested, to control the combination of application conditions of various test structures in the reliability test (Μ·1# teSt), so that it can be monitored immediately Test state to maintain the accuracy of the test. Integrator 1 allows the user to set the desired test item or application conditions, including various wafers & 粳 κ κ κ wa wa wa wa wa wa 或 或 或 pack pack pack pack pack pack pack pack pack pack wa wa wa wa wa wa Reliability tests, such as TDDB, HCI, EM, etc., 200905217 or preset values of various test parameters (such as applied temperature, applied voltage, and applied current, etc.) Referring to Figure 4, it is one of the heat supplies in Figure 3. A schematic diagram of the group 2, wherein the heat supply module 2 is provided with a multi-stage temperature generator 2A, which comprises a plurality of fixed value resistors -) R. The material of the resistor R can be metal, polysilicon, n, ell resistor, P_well resistor Or a material such as an epitaxial layer. During the test, changing the current flowing through the resistor R will produce different temperatures, and the output will be affected by the current, which will produce different degrees of thermal energy = to again, the measuring device end (DUTs) 6. The resistance value of the resistor R configured in this example is fixed. 'The temperature output that can be generated is mainly determined by the current flowing through it (n, I2 and 13 in the figure indicate different current values) ). In the example, the integrator 1 can (4) reach the temperature of the actual device end 6 to be tested. After comparing the actual temperature with its preset applied temperature, the integrator! The signal is sent back to the heat supply module terminal 2 via the feedback network 7, indicating that the input current is changed to stabilize the temperature of the device terminal 6 to be tested. In addition, the heat supply module 2 can also provide multiple sets of different application temperatures to the end of each device to be tested 6w, as shown in Fig. f, Ding Bu and T3 can represent three sets of different values of application of the coffee 1 to allow the device to simultaneously test three A different temperature test item (or condition) to be tested f 6 . It should be noted that this embodiment is for illustrative purposes. In practice, the user may configure more resistors r in the heat supply module 2 to generate a higher temperature output, which is not limited to the embodiment shown in this embodiment. Third order. Referring to Figure 5, there is shown a sound map of the heat supply module 2 in another embodiment. Different from the implementation manner of the above embodiment, this embodiment uses the current value I of the solid state to match the resistance of different resistance values (Ri, r2 & r3) to reach the multi-step thermal energy output of the 200905217 to = (4). In a similar way to the above, at a fixed current input, the resistance value of the variable resistors (R1, R2, and R3) can be changed to #1 to achieve the multi-order thermal energy output we want, and then the device end 6 to be tested. The predetermined test temperature is reached. The adjustment and monitoring of its integrator is also achieved as in the above example, via its feedback network 7 to transmit its command signals. Referring to Fig. /, it is a schematic diagram of a voltage divider 8 in the voltage supply module 3. The voltage supply module 3 must provide a variable and stable applied voltage (st(10)ed read) to the connected person to be tested. As shown in the figure, the first end and the second end of the sub-fourth (8) circuit respectively rotate a voltage supply end VDD and a ground end 9, respectively, and a plurality of resistors (8)...(9) and the middle ground of the cowpea medium are arranged in series. The adjacent resistor R is a grounding resistor whose resistance value is smaller than that of the resistor, and R3 is much smaller. The main function is safety protection, and the surge suppression is stable. A reference voltage Vref is input from the outside between the grounding resistor R and the resistor R1. The reference voltage Vref is derived from a bandgap reference jBand_gapreference) voltage, and its main function is to provide an overall circuit-stable, unaffected by temperature or its supply voltage. Voltage reference value. The voltage supply module is designed in series with a plurality of variable resistors at a voltage supply terminal VDD and a reference voltage. The purpose of the voltage supply module is to generate a plurality of voltage variations of different sizes and adjustable voltages between the resistors and the power and the R3 (eg, Δν Bu AV2 and (4) in the figure, to simultaneously apply the multi-plant voltage (ie, V1, V2 & V3 in the figure) to the device to be tested' Simultaneously test multiple sets of voltage application conditions to make the month... size and —力 and 200905217
有關係。在本例中，除參考電壓Vref外，其他各個夫 數值都可以依設定改變來達到我們想要的V卜V2及^ 輸出電壓值組合。其V1等於Vref+Avi ; v2等於W + AV2; V3等於Vref+AV3。當然，與上面熱供給模組 的例子相似’整合器！可偵測到待測裝置端6實際的電壓 值，並經由回饋網路要求電壓供給模組改變其電壓輸出大 小VDD或是其中的電阻值R1、们以及R3以穩定待測裝 置端6所接收到的施加電壓。此處要注意的是：實施例中' IU、R2及R3三個電阻之配置僅用以說明此電壓輸出線路 之多重電壓輸出功能’於實際應用上，該領域之熟習技藝 者會因其需求於其中配置其他的電阻以提供額外的電壓輸 出來同時測試更多的裝置。There are relationships. In this example, in addition to the reference voltage Vref, each of the other values can be changed according to the setting to achieve the desired combination of V and V2 and ^ output voltage values. Its V1 is equal to Vref+Avi; v2 is equal to W + AV2; V3 is equal to Vref+AV3. Of course, similar to the example of the heat supply module above, the 'integrator! The actual voltage value of the device end 6 to be tested can be detected, and the voltage supply module is required to change its voltage output size VDD or the resistance values R1, R3 and R3 thereof through the feedback network to stabilize the device end 6 to be tested. The applied voltage. It should be noted here that in the embodiment, the configuration of the three resistors of IU, R2 and R3 is only used to illustrate the multiple voltage output function of this voltage output line. In practical applications, those skilled in the art will have their needs. Other resistors are configured to provide additional voltage output to test more devices simultaneously.
圖七為圖六中參考電壓Vref之一能隙參考電路 ^Band-gap reference)。如圖中所示，首先，電路的第一 端將由一穩定電流源提供一穩定的電流輸入ic，該電流輸 入1C會由其流徑電流計丨〇測量。電流計〗〇後為一雙載子 接面電晶體 U (BJT，Blpolar Juncti〇n Transist〇r)，BJT 在一定的溫度範圍内能提供相當穩定一致的輸出電壓 VBE。而與電路輸出端相接處另有一 ρτΑτ產生器 (Prop〇rti〇nal-to-absolute-temperature，絕對溫度比例產生 器），其產生之電壓Vt可補償BJT產生的負溫度係數電壓 損失，以消除溫度變化對整體電路輸出電壓v〇之影響， Vo 即等於 VBE + 冷（kT/q)。y3 ( kT/q)即為 pTAT 生成 器補償之電壓值Vt。圖八與圖九則為另兩種艮…士式的能 200905217 隙參考電壓Vref之電路設計與其變形，同樣能提供整體電 路系統穩定的參考電壓來源。由於上述所提到各種能隙來 考電路皆是該領域已習知之技術，故此處於其細節處不再 多加贅述。 現在參照至圖十，其為實施例中電流供給模組4之電 路圖，為一電流鏡設計（currentmirr〇r)。首先，電路起始 端會通入一穩定的參考電壓Vref，該參考電壓之來源與上 例中提到之參考電壓來源相同。參考電壓Vref會由一放大 器13的正極端通入，再連接至一場效電晶體i4 (FieidFigure 7 is a band gap reference circuit ^Band-gap reference) of the reference voltage Vref in Figure 6. As shown in the figure, first, the first end of the circuit will provide a stable current input ic from a steady current source, which will be measured by its current path galvanometer. The galvanometer is followed by a pair of carrier junction transistors U (BJT, Blpolar Juncti〇n Transist〇r), which provides a fairly constant output voltage VBE over a range of temperatures. And a ρτΑτ generator (Prop〇rti〇nal-to-absolute-temperature, absolute temperature ratio generator) is connected to the output end of the circuit, and the generated voltage Vt can compensate the negative temperature coefficient voltage loss generated by the BJT, Eliminate the effect of temperature changes on the overall circuit output voltage v〇, which is equal to VBE + cold (kT/q). Y3 ( kT/q) is the voltage value Vt compensated by the pTAT generator. Figure 8 and Figure 9 show the other two kinds of 艮... 士能能200905217 The design of the gap reference voltage Vref and its deformation can also provide a stable reference voltage source for the overall circuit system. Since the various energy gap reference circuits mentioned above are well known in the art, they will not be described again in detail herein. Referring now to FIG. 10, which is a circuit diagram of the current supply module 4 in the embodiment, it is a current mirror design (currentmirr〇r). First, a stable reference voltage Vref is applied to the beginning of the circuit, and the reference voltage is sourced from the same reference voltage source as mentioned in the above example. The reference voltage Vref is passed through the positive terminal of an amplifier 13 and then connected to a field effect transistor i4 (Fieid)
Effect Transistor，FET )之閘極 G ( _ )。場效電晶體" 的源極s (source)與放大器15的負極以及一接地電阻r 相連。該接地電阻R之功能與上面提到的實施相同，為安 全防護、突波之抑制與系統敎之用。場效電晶體14之沒 極D ( Drain )會連至另外數個相互並聯的場效電晶體 (15 16、17及1 8…等）之閘極端。場效電晶體丨6、丄7 及18々之源極端（source)會分別與一電流計（19、及 4 )以及待測襄置（DUT1、DUT2及DUT3…等） 依序連接而成，最後再連至接地端，形成個別的測試條件 ，加電路。場效電晶體16、17及18之功能在於提供待測 咸置（DUT’n )-穩定的施加電流，不會受與其連接之待 、]裝置本身電阻大小影響。而場效電晶體與待測裝置間的 十19、20及21則能測量並監控流過電流之大小。根 據該電流鏡配置之方式’施加一參考電壓Μ，會有—電 流^流經接地電阻R’其中I = Vref/R，意即該電流值會隨 12 200905217 大勺電Ha r大小而變。而其電流鏡之設計會使經過各個 、電路至待測裝置端的輪出電流則分別為 I*N1、I*N2 =I N3 ·.等。故控制電流z之大小以及場效電晶體之配 =能改變並決定各施加電路之輸出電流大小，以同時測 ^夕個具有不同電流測試條件之待測裝置。如同上述實施 I般，假如整合器Η貞測到各待測裝置端之施加電流值 :離使用者所設定之測試值，整合器i會經由回饋網路（未 :)傳達指令訊息改變其中的元件參數來維持穩定的電 =輸出。亦如同上述電壓測試電路之實施例，16、17及18 輸出電路配置僅用以說明此電流供給模組多重的電流 2功能，於實際應用上，該領域之熟習技藝者會應其需 +、其線路中配置更多的輸出線路以同時提供更多的施加 電流來測試更多的裝置。 οσ除了 """控與穩定各項所施加之測試條件的功能，整合 器1也可經由偵測到的參數來判定待測裝置是否失效 例而言，在TDDB測試中，整合器Μ測到其 -受測單元在—定的測試時間後電壓突然急遽升高，即可 斷定該裝置或元件在此項測試條件下失效。 參照至圖十一，此圖與圖三中說明之電路結構類似， /、別在於額外的濕度測試條件Ή被施加在各待測裝置 上。濕度測試條件Η會被應用在THBT (Effect Transistor, FET) gate G ( _ ). The source s (source) of the field effect transistor " is connected to the negative terminal of the amplifier 15 and a grounding resistance r. The function of the grounding resistor R is the same as that of the above-mentioned implementation, and is used for safety protection, surge suppression, and system use. The dipole D (Drain) of the field effect transistor 14 is connected to the gate terminals of a plurality of other field-effect transistors (15 16, 17 and 18, etc.). The source terminals of the field effect transistors 丨6, 丄7 and 18々 are respectively connected with an ammeter (19, and 4) and the devices to be tested (DUT1, DUT2, DUT3, etc.). Finally connected to the ground, forming individual test conditions, add circuit. The function of the field effect transistors 16, 17 and 18 is to provide a stable current (DUT'n)-stabilized applied current, which is not affected by the resistance of the device itself. The tenth, 19th, 20th and 21st between the field effect transistor and the device under test can measure and monitor the magnitude of the current flowing. According to the current mirror configuration, a reference voltage is applied, and the current flows through the grounding resistor R' where I = Vref/R, which means that the current value varies with the size of 12 200905217. The design of the current mirror will cause the currents passing through each circuit and the device to be tested to be I*N1, I*N2 = I N3 ·. Therefore, the magnitude of the control current z and the matching of the field effect transistor can change and determine the output current of each application circuit to simultaneously measure the device under test having different current test conditions. As in the above implementation I, if the integrator detects the applied current value of each device to be tested: from the test value set by the user, the integrator i will change the command message through the feedback network (not:). Component parameters to maintain a stable power = output. Also like the embodiment of the voltage test circuit described above, the output circuit configurations of 16, 17 and 18 are only used to illustrate the multiple current 2 functions of the current supply module. In practical applications, those skilled in the art will need +, More output lines are placed in the line to provide more applied current to test more devices. In addition to the function of "control and stability" of the test conditions applied by the quot;, the integrator 1 can also determine whether the device under test is invalid based on the detected parameters. In the TDDB test, the integrator It is determined that the voltage of the unit under test suddenly rises sharply after a predetermined test time, and it can be concluded that the device or component fails under the test condition. Referring to Figure 11, this figure is similar to the circuit configuration illustrated in Figure 3, and /, in addition to the additional humidity test conditions, applied to each device under test. Humidity test conditions will be applied to THBT (
HunndUy Bmsed Testing ’溫度濕度偏差測試）或是hast (Highly ACCelerated Stress 丁⑽，加速應力測試）等可靠 度測試項目中。如同上述各實施例之方式，整合器可透過 13 200905217 穩疋其施加濕度 與濕度把加單元連結之回饋網路來監控並 之強弱。 請參照至圖十二，其為將電壓v、電流〗、溫度τ三 種不同測試施加條件整合應用之電路圖。此實施例^假: 每種測試施加條件（T、VAI)來源分料提供三種不同又 的測試條件值，以溫度來說即為圖中的T1、丁2及T3 ’·以 電壓來說即為Vs卜Vs2及Vs3;以電流來說即為WW 以及Is3。則在三種不同類型的施加條件與三種不同施加 條件值的整合下，本發明可同時提供九組不同的測試條件 組合來測試各待測裝置（如之可靠产 當然，實際之測試條件組合數目，要視每種施加條：：源 所能提供的測試條件而定，能同時提供的測試條件越多（如 超過實施财說明的三個），那能同時測試的裝置數目 試種類亦就越多。 一“ 本發明之描it包含較佳實施例與其所伴隨之圖式。須 瞭解其中所有的實施例皆只用以說明。因&，本發明也^ 應用在其他不同的實施财，而非侷限於其較佳實施例此 此外，本發明僅受其隨附之專利申請項目與等效範圍所 制，而非其他任何的實施例。 义 【圖式簡單說明】 本發明在某些部份與配置會以物理的方式呈現，其 佳實施例在說明書中會有詳細的描述與圖示，其中：” 乂 圖-為各種可靠度測試與其所對應之各項測試條件之 14 200905217 圖ί*為本發明中各電路單元間連接之示意圖 圖一為本發明中各電路單元與回饋網路之示意圖 圖四為本發明之—熱供給模組之電路圖 固為本4明之另一熱供給模組之電路圖 圖六為本發明中電壓供給模組之電路圖 圖為本毛明中成隙參考電壓電路之電路圖 圖八為本發明中_ Kujlk能隙參考電壓電路之電路圖 圖九為本發明中另-Kujik能隙參考電壓電路之電路 圖十為本發明中電流供給模組之電路圖 圖十一為本發明中包含濕度施加測試之各電路單元 連接之示意圖 a 圖十一為本發明中整合所有施加條件之電路圖 【主要元件符號說明】 1整合器 2 熱供給模組 3 電壓供給模組 4 電流供給模組 5 測試結構 6待測裝置 7 回饋網路 8分壓器 9接地端 1〇電流計 15 200905217 11雙載子接面電晶體 12 絕對溫度比例產生器 13 放大器 14場效電晶體 15 場效電晶體 16場效電晶體 17場效電晶體 18 場效電晶體 19 電流計 20 電流計 21 電流計 16HunndUy Bmsed Testing 'temperature and humidity deviation test' or reliability test items such as hast (Highly ACCelerated Stress D (10), accelerated stress test). In the manner of the above embodiments, the integrator can monitor and monitor the strength of the feedback unit by applying the humidity and humidity to the feedback network of 13 200905217. Please refer to FIG. 12, which is a circuit diagram for integrating the application conditions of voltage v, current, and temperature τ. This example is: each test application condition (T, VAI) source material provides three different test condition values, which are T1, D2 and T3' in the figure of temperature. It is VsBu Vs2 and Vs3; in terms of current, it is WW and Is3. Then, under the integration of three different types of application conditions and three different application condition values, the present invention can simultaneously provide nine different sets of test conditions to test each device to be tested (if reliable, of course, the actual number of test condition combinations, Depending on the test conditions that each source can be: the source can provide, the more test conditions that can be provided at the same time (eg, more than three of the implementation instructions), the more types of devices that can be tested simultaneously The description of the present invention includes the preferred embodiments and the accompanying drawings. It should be understood that all of the embodiments are merely illustrative. The invention is also applied to other different implementations. The present invention is not limited to the preferred embodiments thereof, but the invention is only limited by the scope of the patent application and the equivalents thereof. Parts and configurations are presented in a physical manner, and a preferred embodiment thereof will be described and illustrated in detail in the specification, where: "乂图- for various reliability tests and their corresponding 14 is a schematic diagram of the connection between circuit units in the present invention. FIG. 1 is a schematic diagram of each circuit unit and feedback network in the present invention. FIG. 4 is a schematic diagram of the heat supply module of the present invention. 4 is a circuit diagram of another heat supply module of the present invention. FIG. 6 is a circuit diagram of the voltage supply module of the present invention. FIG. 8 is a circuit diagram of the _ Kujlk energy gap reference voltage circuit of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 11 is a circuit diagram of a current supply module according to the present invention. FIG. 11 is a schematic diagram showing the connection of each circuit unit including a humidity application test in the present invention. FIG. Integrate all the circuit diagrams of the applied conditions [Main component symbol description] 1 Integrator 2 Heat supply module 3 Voltage supply module 4 Current supply module 5 Test structure 6 Device under test 7 Feedback network 8 Voltage divider 9 Ground terminal 1 〇 ammeter 15 200905217 11 double carrier junction transistor 12 absolute temperature ratio generator 13 amplifier 14 field effect transistor 15 field effect transistor 16 field effect Transistor 17 field effect transistor 18 field effect transistor 19 ammeter 20 ammeter 21 ammeter 16