200901421 九、發明說明： 【發明所屬之技術領$ j200901421 IX. Invention Description: [Technology collar of the invention $ j
. 本發明係有關於多個半導體封裝件高密度3 D 的架構，特別係有關於一種以導線架之外引腳焊接 " 導體封裝之堆疊組合。 【先前技術】 隨著電子產品的微小化’其内部電路板亦越 小’表面可供安裝半導體封裝元件的面積亦縮小。 (') 可以將多個半導體封裴件並排（side-by-side)方式 接合到電路板，但在先進的微小化電子產品將無 成，故有人提出可以將多個半導體封裝件縱向3D 以符合小型表面接合面積與高密度元件設置之要才 到半導體封裝之堆疊組合，即稱之為層疊封裳 (Package-On-Package device, POP)。基於成本的考 既有設備的共用性，可以利用外引腳的焊接達到半 封裝之堆疊。 、 請參閱第1及2圖所示，一種習知半導體封装 疊組合1〇〇主要包含一第一半導體封裝件11〇以及 一堆疊在該第一半導體封裝件110上之第二半導 裝件120。該第一半導體封裝件110為習知具有外 的封裝型態’其係包含有一晶片111、一導線架之 個外引腳1 1 2以及一封膠體1 1 3。其中，該些外弓丨胳 係用以表面接合至一外部印刷電路板（圖未繪出）。 二半導體封裝件1 20係包含有一晶片i 2 1、一導線 堆疊 之半 來越 以往 直接 法達 堆疊 ，達 裝置 量與 導體 之堆 至少 體封 引腳 複數 ]112 該第 架之 5 200901421 複數個外引腳122以及一封膠體123。其中，第二半導 體封裝件120之外引腳122係外露於該封膠體ι23，約 為I形腳，以銲料130連接至第一半導體封裝件11〇之 外引腳1 1 2之一區段’其係鄰近該封膠體丨丨3。焊接面 積過於狹窄並且該些引腳122受熱容易位移，當該半導 體封裝之堆疊組合1 0 0受到熱循環、熱衝擊或碰撞衝擊 時’谷易造成録料130之斷裂，或是部分引腳122之斷 裂。 〇 【發明内容】 本發明之主要目的係在於提供一種以導線架之引腳 裁切端面扣接之半導體封裝之堆疊組合，能增加引腳高 /JZL固著力與焊接面積，藉以提高該堆疊組合之抗衝擊性 之功效。 本發明之次一目的係在於提供一種以導線架之引腳 裁切端面扣接之半導體封裝之堆疊組合，外引腳之特定The present invention relates to a high-density 3D architecture for a plurality of semiconductor packages, and more particularly to a stacked combination of lead-welded "conductor packages with leadframes. [Prior Art] As the electronic product is miniaturized, the internal circuit board is smaller. The area on which the surface can be mounted with the semiconductor package component is also reduced. (') Multiple semiconductor packages can be bonded to the board side-by-side, but in advanced miniaturized electronic products, it is proposed that multiple semiconductor packages can be longitudinally 3D. The combination of small surface bonding area and high-density component setting is required to be stacked in a semiconductor package, which is called a package-on-package device (POP). Cost-Based Tests The compatibility of existing devices allows the use of external pins for soldering to a half-package stack. Referring to FIGS. 1 and 2, a conventional semiconductor package stack assembly 1b mainly includes a first semiconductor package 11A and a second semiconductor package stacked on the first semiconductor package 110. 120. The first semiconductor package 110 is of a conventional package type, which comprises a wafer 111, an outer lead 1 1 2 of a lead frame, and a colloid 1 13 . Wherein, the outer bows are used for surface bonding to an external printed circuit board (not shown). The second semiconductor package 1 20 includes a wafer i 2 1 , a half of a wire stack is stacked directly by the conventional method, and the device amount and the conductor stack are at least a body pin number] 112 of the frame 5 200901421 The outer pin 122 and the gel 123. The lead 122 of the second semiconductor package 120 is exposed to the encapsulant ι23, which is about an I-shaped leg, and is connected to the first semiconductor package 11 by a solder 130. 'It is adjacent to the sealant 丨丨3. The soldering area is too narrow and the pins 122 are easily displaced by heat. When the stacking combination of the semiconductor package is subjected to thermal cycling, thermal shock or impact impact, the valley breaks the recording material 130 or is partially pinned. The break. SUMMARY OF THE INVENTION The main object of the present invention is to provide a stacking assembly of a semiconductor package that is fastened by a lead of a lead frame, which can increase the pin height/JZL fixing force and the welding area, thereby improving the stacking combination. The effect of impact resistance. A second object of the present invention is to provide a stacking combination of a semiconductor package that is fastened by a lead of a lead frame, and the outer pin is specified.
形狀能不增加導線架的製造成本與製程步驟，並達到防 止銲接點斷裂之功效。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。依據本發明，一種半導體封裝之堆疊組合 主要包含一第一半導體封裝件以及至少一第二半導體 封裝件。該第一半導體封裝件係包含至少一第一晶片'一 導線架之複數個第-外引腳以及-第-封膠體。該第二半導 體封裝件係設置於該第—半導體封裝件上，該第二半導體封 裝件係包含至少—笛_ a μ 乐一日日片、一導線架之複數個第二外引腳 200901421 以及一第二封膠體’其中該些第二外引腳係外露於= 膠體。其中，至少—第二外引腳係形成有—X第〜封 、 丹有π开5 口之裁切端面，並且該些第二外引腳之裁 V 、 、，， 却面係扣技 亚焊接至對應第—外引之一區段，藉以 β 曰加5亥些引腳 之焊接面積，並提高該堆疊組合之抗衝擊性。另揭示— 種可堆疊之半導體封裝件。 不一 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。The shape can increase the manufacturing cost and process steps of the lead frame and prevent the breakage of the solder joint. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. According to the present invention, a stacked combination of semiconductor packages mainly comprises a first semiconductor package and at least a second semiconductor package. The first semiconductor package comprises a plurality of first-outer pins and a --blocker of at least one first wafer 'a lead frame. The second semiconductor package is disposed on the first semiconductor package, and the second semiconductor package comprises at least a flute-day microphone, a plurality of second outer pins 200901421 of a lead frame, and a second encapsulant 'where the second outer leads are exposed to the = colloid. Wherein, at least the second outer lead is formed with a -X first seal, a tan π open 5 cut end face, and the second outer lead cuts V, ,,, but the face buckle technology Soldering to one of the corresponding first-outer leads, thereby increasing the soldering area of the pins by β 曰 and increasing the impact resistance of the stacked combination. Further disclosed are stackable semiconductor packages. The purpose of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.
在前述之半導體封裝之堆疊組合中，上述门形缺口 之見度係可大致相等於對應第一外引腳之寬度。 在刖述之半導體封裝之堆疊組合中，上述η形缺口之 見度係可不大於對應第二外引腳之寬度，並且該些第一外引 腳於鄰近第-封膠體之區段具有内凹之缺口’藉以縮小引腳 寬度可供該些门形缺口之扣接。 在&述之半導體封裝之堆疊組合中，可另包含有銲 料八係連接该些第二外引腳之裁切端面與對應第一外 引腳之區段。 在剛述之半導體封裝之堆疊組合中’該些第一外引 腳之焊接區段係可鄰近於對應第一外引腳之一彎折處。 在$述之半導體封裝之堆疊組合中，該些第二外引 腳係可為垂直型態之I型腳。 在⑴述之半導體封裝之堆疊組合中，該些第一外引 腳係可為海鶴腳。 在别述之半導體封裝之堆疊組合中，該第二封膠體 7 200901421 係可疊合接觸於該第一封膠體。 在前述之半導體封裝之堆疊組合中，該第一晶片與 該第二晶片係可為記憶體晶片。 【實施方式】 第3圖與第4圖係為本發明之第一具體實施例所揭 不種以導線架之引腳裁切端面扣接之半導體封裝之 堆疊組合。 請參閱第3圖所示，一種半導體封裝之堆疊組合2〇〇 主要包含一第一半導體封裝件21〇以及至少一第二半 導體封裝件220。該第一半導體封裝件21〇係可為單晶片 封裝或多晶片封裝，其係包含至少一第—晶片211、一導線 架之複數個第-外引腳212以及—第—封膠體213。該第一 晶片2 1 1係以利用銲線或凸塊等電性連接至該些第一外引腳 212並被該第—封膠體213封膠固定。該些第一外引聊川 係外露於該第—封膠體213之兩相對側或四周側邊。在本實 知例中1^些第—外引腳212係海鶴腳（gull lead)。 該第二半導體封裝件22〇係設置於該第一半導體封 210上，該第二半導 千導體封裝件220係包含至少一第二晶 2 2 1、一導線架之複數 _ 數個第二外引腳222以及一第二封膠體 223，其中該4b第_ 胗菔 —罘—外引腳222係外露於該第二封膠體 之兩相對側或四周側邊。复 體223 二外引腳如第5圖所示，至少—第 /成有—具有门形缺口 225之裁切端 2 24 ’並且該此篦-从印 。弟-外引腳222之裁切端面224係 並知接至對雁筮_ AL 钱 ’似 卜引腳2 1 2之一區段，藉以增加該妆 200901421 第二外引腳222之焊接面積與提供了门形焊 能承受或吸收更大應力，而提高了該堆疊組 衝擊性、抗掉落性、抗熱循環性與抗熱衝擊 通常該第一晶片2 1 1與該第二晶片22 1 ' 體晶片，如快閃記憶體或是動態隨機存取記 提高記憶體容量又不會增加表面接合面積。 其中，該些第一外引腳2 1 2之一焊接區 該第一封膠體213，或可位於該些第一外引腳 (") 處。而該些第二外引腳222係可為垂直型態 以使該些第二外引腳222之裁切端面224能 第一外引腳212。 如第3圖所示，該半導體封裝之堆疊組 另包含有銲料23 0，其係連接該些第二外引 切端面224與對應第一外引腳2 1 2之區段。 门形缺口 2 2 5之寬度係可大致相等於對應 2 1 2之寬度，以避免在焊接之高溫時該些 ί : 2 2 2受到熱應力而位移產生空焊之情事。 較佳地，該第二封膠體223係可疊合接 封膠體2 1 3，以縮小層疊封裝之厚度並可分 外引腳222所承受之應力。 此外，再如第5圖所示，上述门形缺口 於第二外引腳222之裁切端面224。依該驾 裝件220之製程中，從提供導線架到模封之 口 2 2 5仍未形成。如第6圖所示，該第二封 接表面，故 合2 0 0之抗 性。 係可為記憶 憶體，藉以 段係鄰近於 2 1 2之彎折 ;之I型腳， 焊接至該些 合2 00係可 腳222之裁 較佳地，該 第一外引腳 第二外引腳 觸於該第一 散該些第二 225係形成 5二半導體封 後，Π形缺 膠體223已 200901421 形成，邊些第二外引腳一 ,,.inrt. κ 2係一體連接在一導線架之框 條 3 1 0(11 e bar，稱之柄^ 6士 冉之聯結桿或繫桿，與第二外 為相同金屬材質並报士# )丨腳222 料貝並形成於同-導線架在預定形成门 开> 缺口 225之位置俜可 ι你Ύ為—封閉孔。直到封 化分離時，從導線架 件之早體 禾尤框條3 1 0裁切分斷該虺笫_ 腳222,該些裁切 一第一外引 . 224與其门形缺口 225可為同時 形成，在後續的蠻加# ^ J τ 貝们f折該些第二外引腳222 驟相同，故不會拇λ道始 兴知步 ^力導線架的製造成本與製程步 可達到防止銲接點斷裂之功效。 如第7及8圖所示’本發明所揭示之第二 例用以說明外引腳 /、體Λ鈿 之形狀I化。一種半導體封 組合400主要包含_ 衣之堆《： I匕3第一半導體封裝件41〇以 第二半導體封裝件42〇贫士 夕 述者相同… 元件係與第-實施例所 \ 一 ] 一半導體封裝件410係包含—密封晶片之 第一封膠體412以及由該第—封膠體412延伸出之 之複數個第一外引腳411兮笙丄* 等跟朱 W腳411。該第二半導體封裝件42〇 於該第一半導體封裝件41〇 ^乐一牛導體封裝件420係 包含-密封晶片之第二封膠體422以及由該第二封膠體m 延伸出之-導線架之複數個第二外弓丨腳421。其中，至少一 第二外引腳42 1係形成有一具有门形缺口 424之裁切端 面423，並且該些第二外引腳421之裁切端面々η係扣 接並焊接至對應第一外引腳41丨之一區段，藉以增加該 些引腳之焊接面積。如第8圖所示，上述门形缺口 424 之寬度係可不大於對應第二外引腳421之寬度，並且該些第 200901421 外W腳4J1於鄰近第—封耀體412之區段具有内凹之缺口 413’藉u縮小該些第一外y腳η立於扣谭接區段之寬度， 可仏》亥二门形缺口 4丨3之扣接。因此可以增加上方第二引 腳421之裁切端面423與該些第一外引腳4ΐι之焊接面積 並避免回料發生引腳位移，故不會有空焊與焊接 問題。 並非對 圍當依 人員可 為等同 案的内 任何簡 方案的 以上所述，僅是本發明的較佳實施例而已 本^月作任何开》式上的限制，本發明技術方案範 所附申請專利範圍為準。任何熟悉本專業的技術 利用上述揭示的技術内容作出些許更動或修飾 變化的等效實施例’但凡是未脫離本發明技術方 令，依據本發明的技術實質對以上實施例所作的 單修改、等同變化與修飾，均仍屬於本發明技術 範圍内。 【圖式簡單說明】 第 1圖 :一種習知半導體封裝之堆疊紐 人 • σ 之 前 視 示 意 圖。 第 2圖 ’習知半導體封裝之堆疊組合之 -局 部 側 視 示 意 圖。 第 3圖 :依據本發明 之第一具體實施例， 一 種 半 導 體 封 裝之堆疊組 合之前視示意圖。 第 4圖 :依據本發明 之第一具體實施例， 該 半 導 體 封 裝 之堆疊k合 之局部側視示意圖 0 第 5圖 :依據本發明 之第一具體實施例， 該 半 導 體 封 裝 11 200901421 之堆疊組合之外引腳局部放大立體圖。 第6圖：依據本發明之第一具體實施例，該堆疊組合之 一半導體封裝件在模封後與裁切引腳達到單體分 離之局部不意圖。 第7圖：依據本發明之第二具體實施例，一種半導體封 裝之堆疊組合之局部側視示意圖。 第8圖：依據本發明之第二具體實施例，一種半導體封 裝之堆疊組合之外引腳示意圖。 【主要元件符號說明】 111晶片 113封膠體 12 1晶片 123封膠體 100半導體封裝之堆疊組合 110第一半導體封裝件 112外引腳 120第二半導體封裝件 122外引腳 1 3 0銲料 2 11第一晶片 2 1 3第一封膠體 221第二晶片 223第二封膠體 200半導體封裝之堆疊組合 210第一半導體封裝件 212第一外引腳 220第二半導體封裝件 222第二外引腳 224裁切端面 225门形缺口 230銲料 3 1 0框條 400半導體封裝之堆疊組合 410第一半導體封裝件 12 200901421 • 411第一外引腳 412第一封膠體 413缺口 420第二半導體封裝件 421第二外引腳 422第二封膠體 423裁切端面 424门形缺口In the stacked combination of the foregoing semiconductor packages, the gate notch visibility may be substantially equal to the width of the corresponding first outer pin. In the stacked combination of the semiconductor packages described above, the visibility of the n-type notch may be no greater than the width of the corresponding second outer lead, and the first outer leads have a concave portion adjacent to the first sealing body. The gap 'to reduce the pin width for the fastening of the gate gaps. In the stacked combination of the semiconductor packages described above, a soldering louver may be further included to connect the cut end faces of the second outer leads with the corresponding first outer leads. In the stacked combination of semiconductor packages just described, the solder segments of the first outer leads may be adjacent to one of the corresponding first outer pins. In the stacked combination of the semiconductor packages described above, the second outer leads may be vertical type I pins. In the stacked combination of the semiconductor packages described in (1), the first outer legs may be sea crane feet. In a stacked combination of semiconductor packages, the second encapsulant 7 200901421 may be laminated to the first encapsulant. In the stacked combination of the foregoing semiconductor packages, the first wafer and the second wafer system may be memory chips. [Embodiment] Figs. 3 and 4 show a stacking combination of a semiconductor package in which a lead end of a lead frame is fastened by a lead frame according to a first embodiment of the present invention. Referring to FIG. 3, a stacked package 2A of a semiconductor package mainly includes a first semiconductor package 21A and at least a second semiconductor package 220. The first semiconductor package 21 can be a single-wafer package or a multi-chip package, and includes at least one first wafer 211, a plurality of first-outer pins 212 of a lead frame, and a first sealing body 213. The first wafer 2 1 1 is electrically connected to the first outer leads 212 by a bonding wire or a bump or the like and is fixed by the first sealing body 213. The first outer Licences are exposed on opposite sides or sides of the first sealant 213. In the present example, the first-outer pin 212 is a gull lead. The second semiconductor package 22 is disposed on the first semiconductor package 210, and the second semi-conductor package 220 includes at least one second crystal 2 1 1 , a plurality of lead frames _ several second The outer lead 222 and the second encapsulant 223 are exposed on the opposite sides or sides of the second encapsulant. The second outer lead of the compound 223 is as shown in Fig. 5, at least - the first end has a cutting end 2 24 ' having a gate-shaped notch 225 and the 篦-substrate. The cutting end face 224 of the outer-outer pin 222 is connected to one of the sections of the geese _ AL money's pin 2 1 2, thereby increasing the welding area of the second outer pin 222 of the makeup 200901421 The gate wafer is provided to withstand or absorb more stress, and the stacking group is improved in impact resistance, drop resistance, thermal cycle resistance and thermal shock resistance. Generally, the first wafer 21 and the second wafer 22 1 'Body wafers, such as flash memory or dynamic random access memory, increase memory capacity without increasing surface joint area. Wherein, the first outer leads 2 1 2 are soldered to the first encapsulant 213 or may be located at the first outer pins ("). The second outer leads 222 can be in a vertical configuration such that the cut end faces 224 of the second outer leads 222 can be the first outer leads 212. As shown in FIG. 3, the stacked package of the semiconductor package further includes solder 230 which connects the second outer cut end faces 224 and the corresponding first outer leads 2 1 2 . The width of the gate notch 2 2 5 can be approximately equal to the width of the corresponding 2 1 2 to avoid the situation where the welding is caused by thermal stress at the high temperature of the welding. Preferably, the second encapsulant 223 is capable of laminating the encapsulant 21 to reduce the thickness of the package and to stress the external pins 222. Further, as shown in Fig. 5, the gate shape is notched to the cut end face 224 of the second outer lead 222. In the process of the driver 220, the port 2 2 5 from the lead frame to the die is still not formed. As shown in Fig. 6, the second sealing surface is in combination with the resistance of 200. The system may be a memory memorandum, whereby the segment is bent adjacent to the 2 1 2; the I-shaped leg is soldered to the 2,000-foot 222. Preferably, the first outer pin is the second outer After the pin touches the first portion of the second 225 system to form the 5 second semiconductor package, the 缺-shaped colloid 223 has been formed by 200901421, and the second outer pins are connected to the .inrt. κ 2 system. The frame of the lead frame 3 1 0 (11 e bar, called the handle ^ 6 冉 冉 tie rod or tie rod, the same metal material as the second outer and the sergeant #) 丨 foot 222 material and formed in the same - wire The frame is positioned to form a door opening > a notch 225. Until the sealing separation is separated, the 虺笫_foot 222 is cut and cut from the early body frame strip 3 10 of the lead frame member, and the first outer lead 224 is cut. The 224 and the gate shaped notch 225 can be simultaneously Forming, in the subsequent singular addition, the ^ ^ J τ 们 f F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F The effect of point breakage. As shown in Figs. 7 and 8, the second example disclosed in the present invention is used to explain the shape of the outer pin/body. A semiconductor package assembly 400 mainly includes a stack of "coatings": I 匕 3 first semiconductor package 41 〇 the second semiconductor package 42 is the same as the first... The component is the same as the first embodiment. The semiconductor package 410 includes a first encapsulant 412 that seals the wafer, and a plurality of first outer leads 411兮笙丄* and the like extending from the first encapsulant 412. The second semiconductor package 42 is disposed on the first semiconductor package 41, and includes a second encapsulant 422 of the sealing wafer and a lead frame extending from the second encapsulant m. The plurality of second outer bows are 421. The at least one second outer lead 42 1 is formed with a cut end surface 423 having a gate-shaped notch 424, and the cut end faces θ of the second outer leads 421 are fastened and soldered to the corresponding first outer lead A section of the foot 41 is used to increase the soldering area of the pins. As shown in FIG. 8, the width of the gate-shaped notch 424 may not be greater than the width of the corresponding second outer pin 421, and the outer leg of the 200901421 outer leg 4J1 has a concave portion adjacent to the segment of the first sealing beam 412. The notch 413' is used to reduce the width of the first outer y-foot η to the width of the buckle-joining section, and can be fastened by the two-door notch 4丨3. Therefore, the welding area of the cutting end surface 423 of the upper second pin 421 and the first outer pins 4ΐ1 can be increased and the pin displacement of the returning material can be avoided, so there is no problem of void welding and welding. The above is not a preferred embodiment of the present invention, but is merely a preferred embodiment of the present invention, and has been limited to any one of the following, and the technical application of the present invention is attached. The scope of the patent shall prevail. Any of the equivalents of the above-described embodiments may be modified or modified in accordance with the technical spirit of the present invention without any departure from the technical scope of the present invention. Variations and modifications are still within the technical scope of the present invention. [Simple diagram of the diagram] Figure 1: A stacking of the conventional semiconductor package • σ front view. Figure 2 is a partial view of a stacked combination of conventional semiconductor packages. Figure 3 is a front elevational view of a stacked assembly of a semiconductor package in accordance with a first embodiment of the present invention. 4 is a partial side view of the stack of the semiconductor package according to the first embodiment of the present invention. FIG. 5 is a schematic diagram of a stacked combination of the semiconductor package 11 200901421 according to the first embodiment of the present invention. A partially enlarged perspective view of the outer pin. Figure 6: In accordance with a first embodiment of the present invention, a semiconductor package of the stacked combination is not intended to be partially separated from the dicing pin after molding. Figure 7 is a partial side elevational view of a stacked assembly of semiconductor packages in accordance with a second embodiment of the present invention. Figure 8 is a schematic view of a pin outside of a stacked combination of semiconductor packages in accordance with a second embodiment of the present invention. [Main component symbol description] 111 wafer 113 encapsulant 12 1 wafer 123 encapsulant 100 semiconductor package stack combination 110 first semiconductor package 112 outer pin 120 second semiconductor package 122 outer pin 1 3 0 solder 2 11 a wafer 2 1 3 first encapsulant 221 second wafer 223 second encapsulant 200 semiconductor package stack combination 210 first semiconductor package 212 first outer pin 220 second semiconductor package 222 second outer pin 224 Cutting end face 225 gate notch 230 solder 3 1 0 frame strip 400 semiconductor package stacking combination 410 first semiconductor package 12 200901421 • 411 first outer lead 412 first encapsulant 413 notch 420 second semiconductor package 421 second Outer pin 422 second encapsulant 423 cut end face 424 gate notch
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