TW200901206A

TW200901206A - Method and apparatus that adjust resistance of non-volatile memory using dummy memory cells

Info

Publication number: TW200901206A
Application number: TW97110159A
Authority: TW
Inventors: Henry Chien; Nima Mokhlesi; deng-tao Zhao
Original assignee: Sandisk Corp
Priority date: 2007-03-21
Filing date: 2008-03-21
Publication date: 2009-01-01
Also published as: WO2008115874A1

Abstract

In some non-volatile storage systems, a block of data memory cells is manufactured with a dummy word line at the bottom of the block, at the top of the block, and/or at other locations. By selectively programming memory cells on the dummy word line(s), the resistances associated with the data memory cells can be changed to account for different programmed data patterns.

Description

200901206 九、發明說明：【發明所屬之技術領域】本發明係關於非揮發性儲存器之技術。交叉參照以下申請案，並將其全文以引用的方式併入本文中：200901206 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to the technology of non-volatile storage. Cross-reference the following application and incorporate it in its entirety by reference:

Henry Chin、Nima Mokhlesi 及 Dengtao Zhao 等人的名為「使用虛設記憶體單元來調整非揮發性記憶體之電阻 (Adjusting Resistance Of Non-Volatile Memory Using DummyHenry Chin, Nima Mokhlesi, and Dengtao Zhao, etc., titled "Adjusting Resistance Of Non-Volatile Memory Using Dummy Using Dummy Memory Units"

Memory Cells)」之美國專利申請案第_______號[代理人檔案號碼SAND-01232USO ]，其與本申請案在同一天申請。【先前技術】在各種電子器件中使用半導體記憶體已變得更風行。舉例而言，非揮發性半導體記憶體用於蜂巢式電話、數位相機、個人數位助理、行動計算器件、非行動計算器件及其他器件中。在最風行之非揮發性半導體記憶體中包括電可抹除可程式化唯讀記憶體（EEPROM)及快閃記憶體。 EEPROM及快閃記憶體利用一浮動閘極，該浮動閘極定位於半導體基板中之通道區域上方且與之絕緣。浮動閘極及通道區域定位於源極及汲極區域之間。一控制閘極提供於浮動閘極上方且與之絕緣。電晶體之臨限電壓由保留於浮動閘極上之電荷量控制。亦即，在接通電晶體以准許在其源極與汲極之間的傳導之前，必須施加至控制閘極的最小電壓量由浮動閘極上的電荷位準控制。U.S. Patent Application Serial No. _______ [Attorney Docket No. SAND-01232USO] of Memory Cells), which is filed on the same day as this application. [Prior Art] The use of semiconductor memory in various electronic devices has become more popular. For example, non-volatile semiconductor memory is used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, inactive computing devices, and other devices. Among the most popular non-volatile semiconductor memories are electrically erasable programmable read only memory (EEPROM) and flash memory. The EEPROM and flash memory utilize a floating gate that is positioned above and insulated from the channel region in the semiconductor substrate. The floating gate and channel region are positioned between the source and drain regions. A control gate is provided above and insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge remaining on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate is controlled by the charge level on the floating gate before the transistor is turned on to permit conduction between its source and drain.

在程式化一 EEPROM或一快閃記憶體器件（諸如，NAND 129892.doc 200901206 快閃記憶體器件）時，通常將一程式化電壓施加至控制閘極且將位元線接地。將來自通道之電子注人至浮動問極中。田電子在洋動閘極中積聚時，浮動閘極變得帶負電，且記憶體單元之臨限電壓升高以使得記憶體單元處於程式化狀’4。關於程式化之更多資訊可在題為"s〇㈣e S —When programming an EEPROM or a flash memory device (such as NAND 129892.doc 200901206 flash memory device), a stylized voltage is typically applied to the control gate and the bit line is grounded. The electrons from the channel are injected into the floating question pole. When Tian Electronics accumulates in the oceanic gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell rises to cause the memory cell to be in a stylized '4'. More information about stylization can be found in "s〇(4)e S —

Self Boostmg Technique for N〇n_v〇latUe Mem〇ry"之美國專利 M59,397、題為”Det⑽_ prQgrammed κ 美國專和 6,917,542 及題為”1>1<〇§1^1111]^11§]^〇11_1^〇1扣^ y之美國專利6,888,758中找到，所有三個引述之專利皆以引用的方式全部併入本文中。在+多ί月況下，將程式化電堡作為一系列脈衝（被稱作程式化脈衝）施加至控制閘極，其中該等脈衝之量值在每一脈衝下增加。在程式化脈衝之間，執行-組-或多個驗證操作以判定正經程式化之（多個）記憶體單元是否已達到其目心位準。右—記憶體單元已達到其目標位準，則對於彼 :己憶體單元而言’程式化停止。若一記憶體單元尚未達到 ”目標位準，則對於彼域體單元而言，程式化將繼續。决閃5己憶體系統之—實例使用nand 個選擇閘極之間串聯地配置多 /、"括在兩選擇閘極被稱作Nand串。日日a也之電晶體及二：型ΤΓ閃記憶體器件中，按特定次序程式化 2早7^’其中首絲式化在緊靠源極側選㈣極之字一…隨後’程式化在鄰近字線上的記，體 …接著程式化在下-個鄰近字線上的記憶體單元如 I29892.doc 200901206 此等等’直至程式化在緊靠汲極側選擇閑極之最後字線上的記憶體單元為止。隨著NAND串中更多記憶體單元經程式化，在未選定字線下的通道區之傳導率將減小’因為經程式化之記憶體單元二有比處於抹除狀態下之記憶體單元高的臨限電壓。通道電阻之此增加改變記憶體單元之IV特徵。當一特定記憶體單元正經程式化（及驗證）時，在比選定字線高（靠近汲極側k擇閘極）之予線上的所有記憶體單元仍處於抹除狀態下。因此，在彼等字線下之通道區很好地傳導，此導致在實際驗證操作期間相對高之單元電流。然而，在nand串之所有5己憶體單元已經程式化至其所要狀態之後，在彼等字線下之通道區之傳導率通常減小，因為該等單元中之多數將經鈿式化至程式化狀態中之一者（而較少數目之單元將保持處於抹除狀態下）。結果，由於與在程式化期間執行的先前驗證操作相比，較少電流將流過，所以在隨後讀取操作期間的IV特徵將不同。降低之電流引起記憶體單元之臨限電壓的人工移位，其在讀取資料時可導致誤差。【發明内容】在一些非揮發性儲存器系統中，將資料記憶體單元之一區塊製造為在該區塊之底部、在該區塊之頂部及/或在其他位置處具有一虛設字線。藉由選擇性地程式化虛設字線上之記憶體單元’可改變NAND串（或其他記憶體單元群）之電阻以考量歸因於將資料程式化至NAND串（或其他記憶體單元群）中的電阻移位。 129892.doc 200901206Self Boostmg Technique for N〇n_v〇latUe Mem〇ry" US Patent M59,397, entitled "Det(10)_ prQgrammed κ US and 6,917,542 and entitled "1>1<〇§1^1111]^11§]^〇 All of the three cited patents are incorporated herein by reference in their entirety. In the case of + more months, the stylized electric castle is applied to the control gate as a series of pulses (referred to as stylized pulses), wherein the magnitude of the pulses increases under each pulse. Between the stylized pulses, an execution-group- or multiple verification operations are performed to determine if the memory unit(s) being programmed have reached their centroid level. Right—The memory unit has reached its target level, and the stylization stops for the other: memory unit. If a memory cell has not reached the "target level", the stylization will continue for the domain unit. The flashback 5 memory system - the instance uses nand select gates to be configured in series between multiple /, " Included in the two selection gates is called Nand string. In the Japanese and Japanese: the flash memory device, the program is programmed in a specific order. 2 early 7^' where the first wire is in close proximity The source side selects the (four) pole word one... then 'stylizes the word on the adjacent word line, the body... and then stylizes the memory unit on the next adjacent word line, such as I29892.doc 200901206, etc.' until the stylization is tight By the drain side, the memory cells on the last word line of the idler are selected. As more memory cells in the NAND string are programmed, the conductivity in the channel region under the unselected word line will decrease. The memory cell 2 has a higher threshold voltage than the memory cell in the erased state. This increase in channel resistance changes the IV characteristic of the memory cell. When a particular memory cell is being programmed (and verified) , higher than the selected word line All memory cells on the line near the drain side of the drain are still in the erased state. Therefore, the channel regions under their word lines are well conducted, which results in a relatively high period during the actual verify operation. Cell current. However, after all the 5 memory cells of the nand string have been programmed to their desired state, the conductivity in the channel region under their word lines is usually reduced because most of these cells will pass through. One of the stylized states (while a smaller number of cells will remain in the erase state). As a result, less current will flow because of the previous verify operation performed during the stylization, so The IV characteristics will be different during subsequent read operations. The reduced current causes an artificial shift in the threshold voltage of the memory cell, which can cause errors in reading the data. [Summary] In some non-volatile memory systems One of the blocks of data memory cells is fabricated to have a dummy word line at the bottom of the block, at the top of the block, and/or at other locations. By selectively programming the dummy The memory unit on the word line can change the resistance of the NAND string (or other group of memory cells) to account for the resistance shifting that is programmed into the NAND string (or other group of memory cells). 200901206

ι. 在一實例中，讀取過程可經設計以考量歸因於將資料程式化至NAND串之記憶體單元中的NAND串之預測電阻改變量。然而’並不始終可預測何等資料將儲存於記憶體單元中；因此，NAND串上之記憶體單元之程式化可引起 NAND串之實際電阻改變偏離NAND串之預測電阻改變 1。連接至虛设予線之記憶體單元（下文叫作虛設記憶體單元）可經程式化以使得其可將NAND串之實際電阻改變更改為更靠近NAND串之預測電阻改變量。一實鉍例包括判定指示非揮發性儲存元件之一集合的一電阻特徵之資訊。非揮發性儲存元件之該集合包括資料非揮發性儲存兀件及虛設非揮發性儲存元件。過程進一步包括程式化該等資料非揮發性儲存元件及基於該經判定之電阻資訊而設定一或多個虛設非揮發性儲存元件。另-實施例包括取關於非揮發性儲存元件（包括資料集合的群電阻之資訊，程 ’及基於該經判定之資訊及虛設非揮發性儲存元件）之一式化該等資料非揮發性儲存元件而藉由改變該一或多個戍机非姑夕1U虛β又非揮發性儲存元件之一特徵來調整該群電阻。另-實施例包括判定資料非揮發性儲存元件之—集合之至少一子集的電阻改變相對於-預定義改變的偏離。對於 -給定資料非揮發性健存元件而言，該 ST::儲存元件之前置及後置程式化™ Γΐ: 括資料非揮發性儲存元件及-或多個虛設非揮發性儲存元件。過程亦包括基於電阻改變之該偏 I29892.doc 200901206 離之該判定而識別一最小偏離及一最大偏離，及判定一用於根據-誤差減小準則更改該最小偏離及該最大偏離㈣寺虛設非揮發性儲存元件中之一或多者的條件。非揮發性儲存元件之該集合之該電阻係藉由將該等虛設非揮發性儲存兀件中之該一或多者設定為該經判定之條件而更改。另-實施例包括判定指示非揮發性儲存元件之—集合的一電阻特徵之資訊。非揮發性儲存元件之該集合包括資料非揮發性儲存元件及虛設非揮發性儲存元件。程式化該等貧料非揮發性儲存元件，包括執行驗證操作。該等驗證操作„ (QV⑽Hve VGltage)用於未選定資料非揮發(·生儲存兀件及將一第二過驅動電壓用於虛設資料非揮發性儲存元件。該第一過驅動電壓比該第二過驅動電壓低。-或多個虛設非揮發性儲存元件基於該經判定之電阻 =訊而使其臨限電mm為處於靠近該等虛設非揮發性储子兀件之電荷中性的一臨限電壓範圍内。 —實例實施包括非揮發性儲在保存7°件之—集合及與非揮發性厂件之該集合通信的_或多個管理電路。非揮發性儲存二一之該集合包括資料非揮發性儲存元件及虛設非揮發性儲電路執仃以上所描述之該等過程β 【實施方式】快閃記憶體系铳之_垂点,& m 乎充之貝例使用NAND結構，其包括串聯地配置夾於兩個選擇閘之間的多個電晶體。串聯之電晶體及璉擇閘極被稱作Nand ψ圖1為展不一NAND串之俯為其等效電路。圖1及圖2中所描緣之NAND串包 I29892.doc -10- 200901206 括串聯且夾於第一（或汲極側）選擇閘極120與第二（或源極側）選擇閘極122之間的四個電晶體100、102、104及106。選擇閘極120將NAND串經由位元線接觸126連接至一位元線。選擇閘極122將NAND串連接至源極線128。藉由將適當電壓施加至選擇線SGD來控制選擇閘極120。藉由將適當電壓施加至選擇線SGS來控制選擇閘極122。電晶體In one example, the read process can be designed to account for the predicted resistance variable of the NAND string attributed to the data in the memory cells of the NAND string. However, it is not always predictable what data will be stored in the memory unit; therefore, the stylization of the memory cells on the NAND string can cause the actual resistance change of the NAND string to deviate from the predicted resistance change of the NAND string. A memory unit connected to the dummy line (hereinafter referred to as a dummy memory unit) can be programmed such that it can change the actual resistance change of the NAND string to a predicted resistance change amount closer to the NAND string. A practical example includes determining information indicative of a resistance characteristic of a set of non-volatile storage elements. The collection of non-volatile storage elements includes data non-volatile storage components and dummy non-volatile storage components. The process further includes staging the non-volatile storage elements of the data and setting one or more dummy non-volatile storage elements based on the determined resistance information. Another embodiment includes taking one of the non-volatile storage elements (including information on the group resistance of the data set, and 'based on the determined information and the dummy non-volatile storage element) to formulate the non-volatile storage elements. The group resistance is adjusted by changing one of the characteristics of the one or more downtime 1U virtual beta non-volatile storage elements. Another embodiment includes determining a deviation of a resistance change of at least a subset of the set of data non-volatile storage elements from a predefined change. For a given data non-volatile storage component, the ST:: storage component pre- and post-stylized TM Γΐ includes data non-volatile storage components and/or multiple dummy non-volatile storage components. The process also includes the deviation based on the resistance change, I29892.doc 200901206, identifying a minimum deviation and a maximum deviation from the determination, and determining one for changing the minimum deviation and the maximum deviation according to the -error reduction criterion (4) The condition of one or more of the volatile storage elements. The resistance of the set of non-volatile storage elements is altered by setting the one or more of the dummy non-volatile storage elements to the determined condition. Another embodiment includes determining information indicative of a resistance characteristic of the set of non-volatile storage elements. The collection of non-volatile storage elements includes data non-volatile storage elements and dummy non-volatile storage elements. Stylize these lean non-volatile storage components, including performing verification operations. The verification operation „(QV(10)Hve VGltage) is used for non-selected data non-volatile (·········································· The overdrive voltage is low. - or a plurality of dummy non-volatile storage elements are based on the determined resistance = signal to make their power limit mm a charge neutrality near the dummy non-volatile memory components. Within the voltage limit range - an example implementation includes non-volatile storage in a set of 7° pieces and _ or a plurality of management circuits in communication with the set of non-volatile plants. The set of non-volatile storages includes The non-volatile storage element and the dummy non-volatile storage circuit perform the processes described above. [Embodiment] The flash memory system has a NAND structure, and the NAND structure is used. The method includes arranging a plurality of transistors sandwiched between two selection gates in series. The series transistor and the gate are called Nand. FIG. 1 is an equivalent circuit of the NAND string. And the NAND string I29 depicted in Figure 2 892.doc -10- 200901206 includes four transistors 100, 102, 104 connected in series and sandwiched between the first (or drain side) selection gate 120 and the second (or source side) selection gate 122 106. The select gate 120 connects the NAND string to the one bit line via the bit line contact 126. The select gate 122 connects the NAND string to the source line 128. The select gate is controlled by applying an appropriate voltage to the select line SGD. The pole 120 is controlled by applying an appropriate voltage to the selection line SGS.

100、102、1 04及1 06中之每一者具有一控制閘極及一浮動閘極。舉例而言’電晶體1 〇〇具有控制閘極丨00CG及浮動閘極100FG。電晶體102包括控制閘極102CG及浮動閘極 102FG。電晶體1〇4包括控制閘極1〇4CG及浮動閘極 104FG。電晶體1〇6包括控制閘極i〇6CG及浮動閘極 106FG。控制閘極i〇OCG連接至字線WL3，控制閘極 102CG連接至字線WL2 ’控制閘極i〇4CG連接至字線 WL1，且控制閘極106CG連接至字線WL〇。注思，儘管圖1及圖2展示了 NAND串中之四個記憶體單兀，但四個電晶體之使用僅作為一實例來提供。一 NAND 串可具有少於四個的記憶體單元或多於四個的記憶體單凡。舉例而言，一些NAND串將包括八個記憶體單元、16 個記憶體單元、32個記憶體單元、64個記憶體單元、128 個5己憶體單Td本文中之論述並不限於ΝΑΝβ串中任何特定數目之記憶體單元。使用NAND結構之快閃記憶體系統之典型架構將包括若干NAND串。·^ 一 NAND串藉由由選擇線⑽控制之其源極選擇閘極連接至源極線且藉由由選擇線sgd控制之其沒極 129892.doc -11 - 200901206 選擇閘極連接至其相關聯之位元線。每一位元線及經由一位兀線接觸連接至彼位元線之各別（多個）NAND串包含成打的記憶體單元陣列。多個NAND串共用位元線。通常，位兀線在與字線垂直之方向上在NAND串之頂部延伸且連接至一或多個感測放大器。每—記憶體單元可儲存資料（類比或數位）。當儲存一個位元之數位資料（被稱作二進位記憶體單元）時，將記憶體單元之可能臨限電壓之範圍分為指派有邏輯資料”丨"及” 〇，，之兩個範圍。在NAND類型快閃記憶體之一實例中，臨限電壓在§己憶體經擦除之後為負且定義為邏輯"1"。臨限電壓在^式化之後為正且定義為邏輯，，〇” D當臨限電壓為負且藉由施加0伏至控制閘極來試圖一讀取時，記憶體單元將接通以指不正儲存邏輯i。當臨限電壓為正且藉由施加0 伏至控f’J閘極來試目一讀取操4乍時，記憶體單元將不接通’此指示儲存了邏輯〇。 °己隐體單元亦可儲存多個資訊位準（被稱作多狀態記憶體早兀）。在儲存多個資料位準之情況下，將可能臨限 :壓之範圍分為資料位準之數目。舉例而[若儲存四個 i 位準(；兩個位元之資料）’則將存在四個臨限電壓範圍，對/、扣派貝料值"U”、"10"、，’〇”及，"。在NA則型記憶體之f例中’臨限電壓在擦除操作之後為負且定義為 "11"。正臨限電懕用於”彳Λ，，用於10 、”01"及”〇〇·，之資料狀態。若堵存Mm λ位準（或狀態）(例如，對於三個位元之資料），則將存在八個臨限雪感、電反耗園，對其指派資料值”000”、 129892.doc -12- 200901206 "001" ' "010" "oil”、”100"、，，101”、 110'，及 ”111”。經程式化至記憶體單元中之資料與單元之臨限電壓位準之間的具體關係、視用於單元之資料編碼方㈣定。舉例而言，美國專利第6,222,762號及美國專利中請公開案第 2_/0255_號描述了用於多狀態快閃記憶體單元之各種資料編碼方案，該兩者以引用的方式全部併人本文+。在一實施例中’使用格雷（Gray)碼指派法將資料值指派給臨限電壓範圍，使得若浮動閘極之臨限電|錯誤地移位至其相鄰實體狀態’則僅-個位元將受到影響。在—些實施例中，資料編碼方案可針對不同字線而改變，資料編碼方案可隨時間而改變，或者隨機字線之資料位元可經顛倒或以其他方式隨機化以減少記憶體單元上之資料型樣敏感性及甚至磨損。 NAND型快閃記憶體及其操作之相關實例提供於以下美國專利/專利申請案中（其皆以引用的方式併入本文中）：美國專利第5,570,315號；美國專利第5,774,397號；美國專利第6,046,935號；美國專利第6,456,528號；及美國專利公開案第US 2003/0002348號。本文中之論述亦可適用於除j NAND之外的其他類型之快閃記憶體以及其他類型之非揮發性記憶體。亦可使用除了 NAND快閃記憶體之外的其他類型之非揮發性儲存器件。舉例而言，所謂之TAN〇s結構（其由在矽基板上之TaN-AhCVSiN-SiO2之堆疊層組成）亦可與本發明一起使用，該丁ANOS結構基本上為使用電荷在氮化物層中之捕集（而非使用浮動閘極）的記憶體單元。可用於快閃 129892.doc • 13 · 200901206 eeprom糸統中的另—類型之記憶體單元利用非傳導性介電材料代替傳導性浮動閉極來按非揮發性方式儲存電荷。此早凡描述於Chan等人的論文”A True Single_Transist〇rEach of 100, 102, 104 and 106 has a control gate and a floating gate. For example, the transistor 1 〇〇 has a control gate 丨 00CG and a floating gate 100FG. The transistor 102 includes a control gate 102CG and a floating gate 102FG. The transistor 1〇4 includes a control gate 1〇4CG and a floating gate 104FG. The transistor 1〇6 includes a control gate i〇6CG and a floating gate 106FG. The control gate i〇OCG is connected to the word line WL3, the control gate 102CG is connected to the word line WL2', the gate electrode i〇4CG is connected to the word line WL1, and the control gate 106CG is connected to the word line WL〇. Note that although Figures 1 and 2 show four memory cells in a NAND string, the use of four transistors is provided as an example only. A NAND string can have fewer than four memory cells or more than four memory cells. For example, some NAND strings will include eight memory cells, 16 memory cells, 32 memory cells, 64 memory cells, and 128 memory cells. The discussion in this article is not limited to ΝΑΝβ strings. Any particular number of memory cells. A typical architecture for a flash memory system using a NAND structure would include several NAND strings. ^ A NAND string is connected to the source line by its source select gate controlled by the select line (10) and its gate is connected to its associated by its pole 129892.doc -11 - 200901206 controlled by the select line sgd Linked bit line. Each of the meta-wires and the respective NAND string(s) connected to the bit line via a contact line includes a memory cell array. A plurality of NAND strings share a bit line. Typically, the bit line extends across the top of the NAND string in a direction perpendicular to the word line and is coupled to one or more sense amplifiers. Each memory unit can store data (analog or digital). When storing a bit of digital data (referred to as a binary memory unit), the range of possible threshold voltages of the memory cells is divided into two ranges assigned with logical data "丨" and "," . In one example of a NAND type flash memory, the threshold voltage is negative after the erased body is erased and is defined as a logical "1". The threshold voltage is positive and defined as logic after ^^, and when the threshold voltage is negative and an attempt is made by applying 0 volts to the control gate, the memory unit will be turned on to indicate The logic i is not being stored. When the threshold voltage is positive and the operation is performed by applying 0 volts to the control f'J gate, the memory unit will not turn on. This indication stores the logic 〇. ° The hidden unit can also store multiple information levels (called multi-state memory early). In the case of storing multiple data levels, it is possible to limit: the range of pressure is divided into data levels. For example, [if you store four i levels (two bits of data)], there will be four threshold voltage ranges, for /, deducting the bait value "U", "10" , '〇' and ". In the f case of NA type memory, the threshold voltage is negative after the erase operation and is defined as "11". The threshold is used for "彳Λ,,, For the status of 10, "01" and "〇〇·,]. If the Mm λ level (or state) is blocked (for example, for three bits), there will be eight threshold snow sensations, and the power consumption will be assigned to the data value "000", 129892.doc -12- 200901206 "001" ' "010""oil","100",,,101", 110', and "111". The data and units that are programmed into the memory unit The specific relationship between the voltage levels is determined by the data encoding unit (4). For example, U.S. Patent No. 6,222,762 and U.S. Patent Application Serial No. 2_/0255_ describe the use of multi-state flash. Various data encoding schemes for memory cells, both of which are incorporated herein by reference. In an embodiment, 'Gray code assignment method is used to assign data values to a threshold voltage range, such that if a floating gate Extremely limited power | erroneously shifted to its neighboring entity state ' then only one bit will be affected. In some embodiments, the data encoding scheme can be changed for different word lines, the data encoding scheme can be Time change, or random word line information The elements may be reversed or otherwise randomized to reduce data sensitivities and even wear on the memory cells. NAND type flash memory and related examples of its operation are provided in the following U.S. patent/patent application (which Citations are incorporated herein by reference: U.S. Patent No. 5,570,315; U.S. Patent No. 5,774,397; U.S. Patent No. 6,046,935; U.S. Patent No. 6,456,528; and U.S. Patent Publication No. US 2003/0002348. The discussion can also be applied to other types of flash memory other than j NAND and other types of non-volatile memory. Other types of non-volatile memory devices other than NAND flash memory can also be used. In contrast, the so-called TAN〇s structure, which consists of a stacked layer of TaN-AhCVSiN-SiO2 on a germanium substrate, can also be used with the present invention, which essentially uses a charge in the nitride layer. Memory unit that captures (rather than using a floating gate). Can be used for flash 129892.doc • 13 · 200901206 Another type of memory unit in the eeprom system Replaced with a non-conductive dielectric material conductive floating electrodes for charge storage and closed by a non-volatile manner. This earlier described in Chan et al., Where a paper "A True Single_Transist〇r

Oxide-Nitride-Oxide EEPROM n · 八. ⑽―咖”（IEEE Electron ^Ws，1987年3月’第3期，第祖-8卷，第93至 %頁）中。由氧_、氮切及氧切（”崎，）形成之三層介電質夾於傳導性控制閘極與記憶體單元通道上方之半傳導性基板之表面之間。藉由將來自單元通道之電子注入至氮化物中來程式化單元’在該氮化物令該等電子經捕集並儲存於有限區域中。此經儲存之電荷接著以可積測之方式改變單元之通道之一部分的臨限電壓。藉由將熱電洞注入至氮化物中來抹除記憶體單元。亦參見N〇zaki等人之"A卜 Mb EEPROM with MONOS Memory Cell f〇r Semiconductor Disk Application" (IEEE Journal of Solid-State Circuits ^ 199^4月，第4期，第26卷，第w至5〇i頁），其描述以 ***閘極組態之類似記憶體單元，在該***閘極組態十，一經摻雜之多晶矽閘極在記憶體單元通道之一部分上延伸以形成一獨立選擇電晶體。前述兩篇論文以引用的方式全部併入本文中。由IEEE出版社在1998年出版之由貿⑴化爪 D. Br〇wn及Joe E. Brewer編輯之,,N〇nv〇latiie 以流。油伽 Memory Technology,”的第h2節（其以引用的方式併入本文中）中提及之程式化技術亦在彼節中描述為可應用於介電電荷捕集器件。亦可使用其他類型之記憶體器件。圖3說明可包括一或多個記憶體晶粒或晶片212之非揮發 129892.doc -14· 200901206 性儲存器件210。記憶體晶粒212包括一記憶體單元陣列 (―、准或二維）200、控制電路220及讀取/寫入電路23〇a及 230B。在一實施例中，在陣列之相反側上用對稱方式實施各種周邊電路對記憶體陣列200之存取，以使得每一侧上之存取線及電路的密度減半。讀取/寫入電路23〇入及23〇8 包括多個感測區塊300，其允許並列讀取或程式化一頁記憶體單元。記憶體陣列100可藉由字線經由列解碼器24〇A 及240B以及藉由位元線經由行解碼器242a及242B來定址。在一典型實施例中，一控制器244包括於與該一或多個記憶體晶粒212相同的記憶體器件21 〇(例如，可移除式儲存卡或封裝）中。經由線232在主機與控制器244之間及經由線234在控制器與該一或多個記憶體晶粒212之間轉移命令及資料。一實施可包括多個晶片212。控制電路220與讀取/寫入電路23 〇A及230B合作以對記憶體陣列200執行記憶體操作。控制電路22〇包括一狀態機 222、一晶片上位址解碼器224及一功率控制模組226 ^狀態機222提供記憶體操作之晶片級控制。晶片上位址解碼器224在由主機或記憶體控制器使用之位址與由解碼器 240A、240B、242A及242B使用之硬體位址之間提供一位址介面。功率控制模組226控制在記憶體操作期間供應至字線及位兀線之功率及電壓。在一實施例中，功率控制模組 226包括一或多個電荷泵，其可產生比電源電壓大的電壓。在一實施例中，控制電路220、功率控制電路226、解碼器電路224、狀態機電路222、解碼器電路242A、解碼器電 129892.doc •15- 200901206 路242B、解碼器電路24〇A、解碼器電路24〇b、讀取電路230A、讀取/寫入電路2則及/或控制器⑽之一= 或任何組合可被稱作一或多個管理電路。、口圖4描緣記憶體單元陣列2〇〇之一例示性結構。在—實施例中，將記憶體單元陣列分為Μ個記憶體軍元區塊。= 於快閃ΕΕΡ刪系統所常見之，區塊為抹除之單元。亦即，每一區塊含有一起抹除的最小數目之記憶體單元。通常將每一區塊劃分為若干頁。頁為程式化之單位。資料之一或多個頁通常儲存於一列記憶體單元中。一頁可儲存一或多個區段。一區段包括使用者資料及附加項資料。^加項資料通常包括已根據區段之使用者資料而計算出的錯誤校正碼（ECCH空制器（下文所描述）之一部分在資料經程式化至陣列中時計算ECC，且在正自陣列讀取f料時亦對盆進行檢查。或者，將ECC及/或其他附加項資料儲存於與2 所從屬之使用者資料不㈣f乃至不_區塊中。使用者資料之區段通常為512個位元組，此對應於磁碟驅動機中之區段的大小。大量頁形成-區塊，自8個頁至高達(例如)32、 64、！28或更多的頁。亦可使用不同大小的區塊及配置。在另-實施财，將位元線分為偶數位元線及奇數位元線。在奇數/偶數位元線架構中，沿共同字線且連接至奇數位元線之記憶體單元在-個時_程式化，而沿共同字線且連接至偶數位元線之記憶體單元則在另—時間經程式化。圖4展示記憶體陣列細之區塊；的更多細節。區塊；包括糾個位元線及X+Hi3NAND串。區塊i亦包括Μ個資料字 129892.doc •16- 200901206 線（WL0至WL63)、2個虛設字線（WL_dO及WL_dl)、一沒極側選擇線（SGD)及一源極側選擇線（sos)。每一 NAND串之一端子經由一汲極選擇閘極（連接至選擇線Sgd)連接至一對應位元線，及另一端子機經由一源極選擇閘極（連接至選擇線SGS)連接至源極線。因為存在六十四個資料字線及兩個虛設字線’所以每一 NAND串包括六十四個資料記憶體單元及兩個虛設記憶體單元。在其他實施例中， NAND串可具有多於或少於64個的資料記憶體單元及多於或少於兩個的虛設記憶體單元。資料記憶體單元可餘存使用者或系統資料。虛設記憶體單元通常不用以儲存使用者或系統資料。圖5為經劃分為一核心部分（被稱作感測模組48〇)及一共同部分490的個別感測區塊300之方塊圖。在一實施例中，將存在用於每一位元線之一獨立感測模組48〇及一用於多個感測模組480之一集合的共同部分49〇。在一實例中，一感測區塊將包括一個共同部分490及八個感測模組480。一群中之感測模組中之每一者將經由一資料匯流排472與相關聯之共同部分通信。對於進一步細節而言，參看美國專利申请公開案2006/0140007，其以引用的方式全部併入本文中。感測模組480包含感測電路470，該感測電路470判定一經連接之位元線中之傳導電流是高於還是低於預定臨限位準。在一些實施例中，感測模組480包括一通常被稱作感測放大裔之電路。感測模組480亦包括一位元線鎖存器 129892.doc -17- 200901206 82其用以设疋在故連接之位元線上的電壓條件。舉例 =，—鎖存於位元線鎖存㈣2巾之預定„將導致經之位兀線被牵引至—指定程式化禁止之狀態（例如， Vdd)。共同部分包含—處理器伙、資料鎖存器之一华合例及-搞接於資料鎖存器之該集合494與資料匯流排· 之間的I/O介面496。處理器492執行計算。舉例而言，盆功能中之-者在於判定儲存於經感測之記憶體單元中之資料，且將經判定之資料儲存於資料鎖存器之集合中。資料鎖存器之集合494用以在讀取操作期間儲存由處理器492判定之資料位元。資料鎖存器之集合494亦用以在程式化操作期間儲存自資料匯流排42G輸人之資料位元。該等唾輸入之資料位S表示意欲程式化至記憶體中之寫入資料: "0介面496在資料鎖存器494與資料匯流排42〇之間提供一介面。在讀取或感測期間4統之操作處於狀態機222之控制下，該狀態機222控制不同控制問極電塵至經定址之單元的供應。當感測模組_逐步歷經對應於由記憶體支援之各種記憶體狀態之各種預定義控㈣極電料，感測模电楊可感測到此等電壓中之-者下，且經由匯流排472提供自感測模組480至處理器492之輪出。在彼點處，處理器 492藉由考慮感測模組之（多個）感測事件及關於自狀態機經由輸入線493所施加之控制閘極電壓的資訊判定所得呓= 體狀態。處理器492接著計算記憶體狀態之二進位編碼 129892.doc 200901206 且將所得資料位元儲存廿芏貝枓鎖存姦494中。在核心部分之另—實施例中，位元線销. 深鎖存器482擔當雙重任務，作為用於鎖存感測模組48〇之輪叫勒出的鎖存為及亦作為位元線鎖存器（如上所述）兩者。預料，一些實施將包括多個處理器492。在-實施例中’每—處理器492將包括—輸出線（圖5中未描緣），使得 :等輸出線中之每一者一起經線接或(wired_〇R)。在一些只&例中輸出線在連接至線接或線之前經反轉。此組態使得能夠在m驗證過程㈣快速判定何時完成程式= 過程’因為接收線接或線之狀態機可判定正經程式化之所有位元何時達到所要位準。舉例而言，當每—位元已達到〃所要位準％，用於彼位元之邏輯〇將被發送至線接或線 (或貝料1經反轉）。當所有位元輸出資料〇(或經反轉之資料 1)時，狀態機便知曉終止程式化過程。在每一處理器與八個感測模組通信之實施例中，狀態機可能會（在一些實施例中）需要項取線接或線八次，或者將邏輯添加至處理器 492以積聚相關聯位元線之結果使得狀態機僅需要讀取線接或線一次。在程式化或驗證期間’待程式化之資料藉由資料匯流排 420而儲存於資料鎖存器之集合494中。在狀態機之控制下的程式化操作包含施加至經定址之記憶體單元之控制閘極的一系列程式化電壓脈衝（具有增加之量值）。每一程式化脈衝後跟隨一驗證過程以判定記憶體單元是否已經程式化至所要狀態。處理器492相對於所要記憶體狀態而監視經 129892.doc •19· 200901206 驗證之記憶體狀態。當令田通兩者一致時’處理器492便設定位元線鎖存器482 使侍引起位7G線被牵引至一指定程式化不止之狀態。此舉林举不止辆接至位元線之單元進一步程式卩使其經X其控制間極上之程式化脈衝。在其他實施例中’在驗證過程期間，處理器初始载人位元線鎖存器 482，且感測電路將其設定為禁止值。貝，鎖存器堆疊494含有對應於感測模組的資料鎖存器且在 Μ把例中，每個感測模組4 8 0存在3至5個 (或另、數目之）資料鎖存器。在一實施例中，該等鎖存器亡自為-個位元。在-些實施中(但無需如此)，資料鎖：器經實施為移位暫存器，使得儲存於其中之並列資料經轉換成用於資料匯流排42G之串列資料，且反之亦然。在一較佳實施例中’對應於爪個記憶體單元之讀取/寫入區塊的所有貢料鎖存器可鏈接於一起以形成一區塊移位暫存器’ 使知·可藉由串列傳送而輸入或輸出一區塊之資料。詳言之，讀取/寫入模組之群組經調適以使得其資料鎖存器之集合中之每一者依次將資料移入或移出資料匯流排，如同其為用於整個讀取/寫入區塊之移位暫存器之部分。關於讀取操作及感測放大器之額外資訊可在以下各者中找到：（1)2004年3月25曰發布的美國專利申請公開案第 2004/0057287號’ "Non-Volatile Memory And Method WithOxide-Nitride-Oxide EEPROM n · VIII. (10) “Caf” (IEEE Electron ^Ws, March 1987, Issue 3, ancestor -8, page 93 to %). The three layers of dielectric formed by oxygen cutting ("Saki") are sandwiched between the conductive control gate and the surface of the semiconducting substrate above the memory cell channel. The unit is programmed by injecting electrons from the unit channels into the nitride, where the electrons are trapped and stored in a limited area. This stored charge then changes the threshold voltage of a portion of the channel of the unit in an integrable manner. The memory cell is erased by injecting a thermal hole into the nitride. See also N〇zaki et al., "Ab Mb EEPROM with MONOS Memory Cell f〇r Semiconductor Disk Application" (IEEE Journal of Solid-State Circuits ^ 199 ^ April, No. 4, Vol. 26, p. 5〇i page), which describes a similar memory cell with a split gate configuration, in which the split gate configuration is ten, a doped polysilicon gate extends over a portion of the memory cell channel to form an independent selection Transistor. The foregoing two papers are hereby incorporated by reference in their entirety. Edited by IEEE Press in 1998, edited by D. Br〇wn and Joe E. Brewer, N〇nv〇latiie. The stylization techniques mentioned in Section 2.8 of the Memory Technology, "which is incorporated herein by reference" are also described in this section as being applicable to dielectric charge trapping devices. Other types may also be used. Memory device. Figure 3 illustrates a non-volatile 129892.doc -14.200901206 memory device 210 that may include one or more memory dies or wafers 212. The memory die 212 includes a memory cell array (", Quasi- or two-dimensional) 200, control circuit 220 and read/write circuits 23a and 230B. In one embodiment, various peripheral circuits are accessed symmetrically to memory array 200 on opposite sides of the array. To halve the density of the access lines and circuits on each side. The read/write circuits 23 and 23 〇 8 include a plurality of sensing blocks 300 that allow for parallel reading or staging of a page The memory cell 100 can be addressed by word lines via column decoders 24A and 240B and by bit lines via row decoders 242a and 242B. In an exemplary embodiment, a controller 244 includes Same as the one or more memory dies 212 The memory device 21 (eg, a removable memory card or package) is between the host and the controller 244 via line 232 and between the controller and the one or more memory die 212 via line 234 The transfer command and data may include a plurality of wafers 212. The control circuit 220 cooperates with the read/write circuits 23A and 230B to perform a memory operation on the memory array 200. The control circuit 22 includes a state machine 222. An on-chip address decoder 224 and a power control module 226 ^ state machine 222 provide wafer level control of memory operations. The on-chip address decoder 224 is used by the host or memory controller for the address and decoder An address interface is provided between the hardware addresses used by 240A, 240B, 242A, and 242B. The power control module 226 controls the power and voltage supplied to the word lines and the bit lines during memory operation. In an embodiment, The power control module 226 includes one or more charge pumps that can generate a voltage greater than the supply voltage. In one embodiment, the control circuit 220, the power control circuit 226, the decoder circuit 224, the state machine circuit 222, the solution Circuit 242A, decoder power 129892.doc •15- 200901206 way 242B, decoder circuit 24A, decoder circuit 24〇b, read circuit 230A, read/write circuit 2, and/or controller (10) One of the = or any combination may be referred to as one or more management circuits. An exemplary structure of the memory cell array 2 is shown in FIG. 4. In the embodiment, the memory cell array is divided into Μ Memory cell block. = Common to flashing systems, blocks are erased units. That is, each block contains a minimum number of memory cells that are erased together. Each block is usually divided into several pages. The page is a stylized unit. One or more pages of data are typically stored in a column of memory cells. One page can store one or more sections. A section includes user data and additional item information. ^Additional data usually includes an error correction code that has been calculated from the user data of the segment (the ECCH air compressor (described below) partially calculates the ECC when the data is programmed into the array, and is in the positive self-array The pots are also checked when reading the f. Alternatively, the ECC and/or other additional items are stored in the user data of the 2 subordinates, not in the (4) f or even in the block. The user data section is usually 512. One byte, which corresponds to the size of the segment in the disk drive. A large number of pages form - blocks, from 8 pages up to, for example, 32, 64, !28 or more pages. Also available Different sizes of blocks and configurations. In another implementation, the bit lines are divided into even bit lines and odd bit lines. In the odd/even bit line architecture, along the common word line and connected to the odd bits The memory cells of the line are stylized at a time, while the memory cells along the common word line and connected to the even bit lines are programmed in another time. Figure 4 shows the fine blocks of the memory array; More details. Block; includes a bit line and X+Hi3NAND string. Block i Also includes one data word 129892.doc •16- 200901206 line (WL0 to WL63), 2 dummy word lines (WL_dO and WL_dl), a immersed side select line (SGD) and a source side select line (sos) One terminal of each NAND string is connected to a corresponding bit line via a drain select gate (connected to select line Sgd), and the other terminal is connected via a source select gate (connected to select line SGS) To the source line. Because there are sixty four data word lines and two dummy word lines', each NAND string includes sixty-four data memory cells and two dummy memory cells. In other embodiments, NAND The string may have more or less than 64 data memory units and more or less than two dummy memory units. The data memory unit may retain user or system data. The dummy memory unit is usually not stored. User or system data. Figure 5 is a block diagram of an individual sensing block 300 divided into a core portion (referred to as sensing module 48A) and a common portion 490. In one embodiment, there will be For one of each bit line independent sensing module 48〇 A common portion 49 for a collection of a plurality of sensing modules 480. In one example, a sensing block will include a common portion 490 and eight sensing modules 480. Sensing modes in a group Each of the groups will be in communication with the associated common portion via a data bus 472. For further details, see U.S. Patent Application Publication No. 2006/0140007, which is incorporated herein in its entirety by reference. The module 480 includes a sensing circuit 470 that determines whether the conduction current in a connected bit line is above or below a predetermined threshold level. In some embodiments, the sensing module 480 includes a Often referred to as the circuit of sense amplification. The sensing module 480 also includes a bit line latch 129892.doc -17- 200901206 82 for setting the voltage condition on the bit line of the connection. Example =, - latched in the bit line latch (4) 2 towel predetermined „ will cause the bit line to be pulled to — to specify the stabilizing state (for example, Vdd). Common part contains—processor partner, data lock One of the registers is the I/O interface 496 between the set 494 of the data latches and the data bus. The processor 492 performs the calculation. For example, among the functions of the basin The data stored in the sensed memory unit is determined and the determined data is stored in a set of data latches. The set of data latches 494 is stored by processor 492 during a read operation. The set of data latches 494 is also used to store the data bits from the data bus 42G during the stylization operation. The data bits S of the saliva inputs are intended to be programmed into the memory. The write data: "0 interface 496 provides an interface between the data latch 494 and the data bus 42. The operation of the system during the reading or sensing period is under the control of the state machine 222, the state machine 222 control different control asks the electric dust to the final The supply of the unit. When the sensing module _ gradually passes through various predefined control (four) pole materials corresponding to various memory states supported by the memory, the sensing mode yang can sense the voltage-- The round-trip from the sensing module 480 to the processor 492 is provided via the bus bar 472. At some point, the processor 492 considers the sensing event(s) of the sensing module and the self-state machine The resulting 呓= body state is determined via the information of the control gate voltage applied by the input line 493. The processor 492 then calculates the binary state code of the memory state 129892.doc 200901206 and stores the obtained data bit 廿芏枓枓奸494. In another embodiment of the core portion, the bit line pin. The deep latch 482 acts as a dual task, as a latch for latching the sensing module 48, and also acts as a latch. Both bit line latches (as described above) are expected. Some implementations will include multiple processors 492. In the embodiment - each processor 492 will include an output line (not depicted in Figure 5). So that: each of the output lines are connected by wire or (wi Red_〇R). In some & only examples, the output line is inverted before connecting to the wire or line. This configuration enables a quick decision in the m verification process (4) when the program is completed = process 'because the receive line is connected or The state machine of the line can determine when all the bits that are being programmed have reached the desired level. For example, when each bit has reached the desired level, the logic for the bit will be sent to the line. Or line (or beneficiary 1 is reversed). When all bits output data 或 (or inverted data 1), the state machine knows to terminate the stylization process. In each processor and eight sense modules In an embodiment of group communication, the state machine may (in some embodiments) require items to be picked up or lined eight times, or add logic to processor 492 to accumulate the result of associated bit lines such that the state machine only needs Read the line or line once. The data to be programmed during the stylization or verification is stored in the set 494 of data latches by the data bus 420. The stylized operation under the control of the state machine includes a series of stylized voltage pulses (with increasing magnitude) applied to the control gates of the addressed memory cells. Each stylized pulse is followed by a verification process to determine if the memory cell has been programmed to the desired state. The processor 492 monitors the memory state verified by 129892.doc • 19· 200901206 with respect to the desired memory state. When the rows are both identical, the processor 492 sets the bit line latch 482 to cause the bit 7G line to be pulled to a specified stylized state. In this case, the forest is not only connected to the unit of the bit line, but is further programmed to pass the programmed pulse on the X of its control. In other embodiments, during the verification process, the processor initially loads the bit line latch 482 and the sensing circuit sets it to a disable value. The latch stack 494 contains data latches corresponding to the sensing modules. In the example, each sensing module 48 8 has 3 to 5 (or another number) of data latches. Device. In one embodiment, the latches are self-sufficient bits. In some implementations (but not necessarily), the data lock: is implemented as a shift register such that the parallel data stored therein is converted to the serial data for the data bus 42G and vice versa. In a preferred embodiment, all of the tributary latches corresponding to the read/write blocks of the claw memory cells can be linked together to form a block shift register. Input or output a block of data by serial transmission. In particular, the group of read/write modules is adapted such that each of its set of data latches sequentially shifts data into or out of the data bus as if it were for the entire read/write Part of the shift register into the block. Additional information on read operations and sense amplifiers can be found in (1) US Patent Application Publication No. 2004/0057287, issued March 25, 2004, "Non-Volatile Memory And Method With

Reduced Source Line Bias Errors" ; (2)2004年 6月 l〇日發布的美國專利申請公開案第2004/0109357號，"Non-VolatileReduced Source Line Bias Errors"; (2) June 2004, US Patent Application Publication No. 2004/0109357, "Non-Volatile

Memory And Method with Improved Sensing1’ ；（3)美國專利 J29892.doc -20- 200901206 申請公開案第20050169082號；（4)2005年4月5日申請的發明者為 Jian Chen之題為"Compensating for Coupling During Read Operations of Non-Volatile Memory"的美國專利公開案2006/0221692 ;及（5)2005年12月28日申請的發明者為 Siu Lung Chan 及 Raul-Adrian Cernea 之題為 nReference Sense Amplifier For Non-Volatile Memory"的美國專利申請案第11/321,953號。緊接在上面列出的所有五個專利文獻皆以引用的方式全部併入本文中。在成功之程式化過程（藉由驗證）結束時，記憶體單元之臨限電壓應適當地處於經程式化之記憶體單元的臨限電壓之一或多個分布中或者處於經抹除之記憶體單元的臨限電壓之-分布中。圖6說明當每—記憶體單元儲存四個位元之資料時對應於記憶體單元陣狀㈣狀態的實例臨限電壓分布。然而’其他實施例可針對每一記憶體單元使用多於或少於四個位元的資料。圖6展示經抹除之記憶體單元的第-臨限電壓分布或狀態描緣經程式化之記憶體皁兀的十五個臨限電壓分布或狀態Ui5。在—實施例中，在狀態〇下之臨限電M為負，且在狀態ui5下之臨限電壓為正。士在貝料狀態0至15中之每一者之間為用於自記憶體單元料之讀取參考電壓。藉由輯給定記憶體單元之臨高於還是低於各別讀取參考電壓，系統可判定該 5己憶體單兀處於哪一狀態下。在每—狀態1至15之下邊緣處或附近為驗證參考電 129892.doc 200901206 壓1將記憶體單元程式化至給定狀態時，系統將測試彼等記憶體單元是否具有比驗證參考電壓大或等於驗證參考電壓之臨限電壓。 / 、在一些實施例中，由於ECC可處置處於錯誤中的特定百 :比之單元’戶斤以資料狀態〇至15可部分地重疊。亦注思，Vt軸可能與施加至控制閘極之實際電壓有所偏移，因 2經由源極之體效應或體偏壓用以使負臨限電壓移位至可 1測之正範圍β。另一注意點為’與所展示之16個狀態的同等間隔/寬度相反，各種狀態可具有不同的寬度/間隔，以便容納對滯留損耗的敏感性之變化量。圖6之每資料狀態對應於儲存於經程式化至各別狀態 :記憶體單元中之資料位元的預定值。圖7為提供指派至每一資料狀態0至15之資料值之一實例的表。在一實施例中，一 δ己憶體單元將資料儲存於四個不同頁中。該四個頁被稱作下部頁、上部頁、較高頁及頂頁。W 7料對於每資料狀態0至15之在每一頁中的資料。在一實施例中，每-頁經獨立地程式化。在另-實施例中，—記憶體單元之所有四個資料位元經同時程式化。圖8為提供指派至每一資料狀態〇至15之資料值之另一實例的表。圖8之資料值利用格雷碼指派法，使得在相鄰資料狀態之間僅改變一個位元。此配置減少了在記憶體單元之限電壓太低或太尚的情況下誤差位元之數目。圖9為描述操作非揮發性記憶體單元之一實施例之流程圖在3午多實施中，在程式化之前抹除記憶體單元（按區 129892.doc -22- 200901206 塊或其他單位彳。+ ^ 元)在—實施例中，藉由如下方式抹除記憶井升高至抹除電壓(例如，2。伏) 極:間週期’並使選定區塊之字線接地’同時源極及位凡線在為-動的。歸因於電容輕合，所以未選定字 H 選擇線及源極亦升高至抹除《之顯著部二應I，當泮動閘極之電子通常藉由⑽― 牙隨機制而發射5 1 ^ ^ 00 _ 土則時，一強電場經施加至選定記憶 Γ:Γ道氧化物層，且選定記憶體單元之資料經抹 …電子自浮動閑極轉移至Ρ井區域時，選定單元之臨 2電屋便降低。可對整個記憶體陣列、-區塊或單元之另一早位執行抹除。在抹除了記憶體單元之區塊之後，可如本文令所描述程式化各種記憶體單元。在步驟602中，可視情況執行軟體程式化以使經抹除之記憶體單元的抹除臨限電塵之分布變窄。作為抹除過程之、口果fe體皁元可能處於比必要抹除狀態深的抹除狀〜軟體程式化可施加小的程式化脈衝以將經抹除之記憶體單元之臨限電麼移動至較緊密的臨限電壓分布。在步驟604中，判定每一 NAND串之資料單元的電阻資訊。存在用於執行步驟604之許多不同實施例，且可判定指示關於電阻之不同特徵之不同資訊。舉例而言，步驟 6〇4可包括直接量測電阻（絕對或相對值）或量測可用以判定直接或間接關於電阻（絕對或相對值）之資訊的特性或資料。以下提供不同實施例中之—些的更多細節。本文中所描述之本發明並不限於判定電阻資訊之任何具體方法或者 129892.doc •23- 200901206 =電阻特徵之資訊的任何具體集合。在—實施例中，判疋電阻之步驟由控制器執行或者處於其他實施例中，判定電阻之步驟由狀態機或== 或者處於狀態機或另一組件之指導下。 ^ :步驟606中’用資料(例如，使用者資料)程式化資料記憶體單元。舉例而言，將多個資料頁程式化至連接至 WL0至WL63的記憶體單元中。在步驟咖中，基於在步驟Memory And Method with Improved Sensing1'; (3) US Patent J29892.doc -20-200901206 Application Publication No. 20050169082; (4) The inventor of the application on April 5, 2005 is named "Chen Chen" "Compensating for Coupling During Read Operations of Non-Volatile Memory" US Patent Publication 2006/0221692; and (5) The inventors of the application on December 28, 2005 are Siu Lung Chan and Raul-Adrian Cernea entitled nReference Sense Amplifier For Non -Volatile Memory" U.S. Patent Application Serial No. 11/321,953. All of the five patent documents listed immediately above are hereby incorporated by reference in their entirety. At the end of a successful stylization process (by verification), the threshold voltage of the memory cell should be properly in one or more of the threshold voltages of the programmed memory cell or in erased memory. The threshold voltage distribution of the body unit. Figure 6 illustrates an example threshold voltage distribution corresponding to the state of the memory cell array (4) when each memory cell stores four bits of data. However, other embodiments may use more or less than four bits of data for each memory unit. Figure 6 shows fifteen threshold voltage distributions or states Ui5 of the first threshold voltage distribution or state traced memory sapons of the erased memory cells. In the embodiment, the power limit M in the state is negative, and the threshold voltage in the state ui5 is positive. The reading reference voltage for the self-memory unit is used between each of the batting states 0 to 15. By comparing whether the given memory cell is higher or lower than the respective read reference voltages, the system can determine which state the 5 memory cells are in. At or near the lower edge of each state 1 to 15, the verification reference is 129892.doc 200901206. When the memory unit is programmed to a given state, the system will test whether their memory cells have a larger than the verification reference voltage. Or equal to the threshold voltage of the verification reference voltage. / In some embodiments, since the ECC can handle a particular one that is in error: the unit can be partially overlapped by the data state 〇 15 . It is also noted that the Vt axis may be offset from the actual voltage applied to the control gate, because the body effect or body bias via the source is used to shift the negative threshold voltage to a positive range of beta. . Another point to note is that 'with the same spacing/width as the 16 states shown, the various states may have different widths/intervals to accommodate the amount of change in sensitivity to retention losses. Each data state of Figure 6 corresponds to a predetermined value stored in a data bit that is programmed into a respective state: memory unit. Figure 7 is a table providing an example of one of the data values assigned to each of the data states 0 through 15. In one embodiment, a delta-recall unit stores data in four different pages. The four pages are called the lower page, the upper page, the upper page, and the top page. W 7 is the material in each page for each data state 0 to 15. In an embodiment, each page is independently programmed. In another embodiment, all four data bits of the memory unit are simultaneously programmed. Figure 8 is a table providing another example of data values assigned to each of the data states 〇 to 15. The data values of Figure 8 utilize the Gray code assignment method such that only one bit is changed between adjacent data states. This configuration reduces the number of error bits in the event that the limit voltage of the memory cell is too low or too high. Figure 9 is a flow diagram depicting one embodiment of operating a non-volatile memory unit. In a three-noon implementation, the memory cells are erased prior to programming (by block 129892.doc -22-200901206 blocks or other units). + ^ element) In the embodiment, the memory well is raised to the erase voltage (for example, 2 volts) by the following method: the period 'and the word line of the selected block is grounded' while the source and The line is in motion. Due to the light coupling of the capacitor, the unselected word H selection line and source are also raised to erase the significant portion of the second I, when the electrons that twitch the gate are usually emitted by (10)-tooth random 5 1 ^ ^ 00 _ soil, a strong electric field is applied to the selected memory Γ: the channel oxide layer, and the data of the selected memory unit is wiped... the electron is transferred from the floating to the well area, the selected unit is 2 The electric house will be lowered. Erasing can be performed on the entire memory array, -block, or another early bit of the cell. After erasing the block of memory cells, various memory cells can be programmed as described in this document. In step 602, software stylization may be performed as appropriate to narrow the distribution of the erased reactive dust of the erased memory unit. As a wiping process, the fruit saponin may be in a darker state than the necessary erasing state. The soft stylization may apply a small stylized pulse to move the erased memory unit. To a tighter threshold voltage distribution. In step 604, the resistance information of the data unit of each NAND string is determined. There are many different embodiments for performing step 604, and it can be determined that different information about different characteristics of the resistance is indicated. For example, step 〇4 may include direct measurement of resistance (absolute or relative value) or measurement of characteristics or information that may be used to determine information directly or indirectly about resistance (absolute or relative). Further details of some of the different embodiments are provided below. The invention described herein is not limited to any particular method of determining resistance information or 129892.doc • 23- 200901206 = any specific set of information on resistance characteristics. In an embodiment, the step of determining the resistance is performed by the controller or in other embodiments, and the step of determining the resistance is by a state machine or == or under the direction of a state machine or another component. ^: In step 606, the data memory unit is programmed with data (e.g., user data). For example, multiple data pages are programmed into memory cells connected to WL0 through WL63. In the step coffee, based on the steps

_中判定之電阻資訊而設定虛設記憶體單元之臨限電壓。在—些實施例中’設定虛設記憶體單元之臨限電壓可包括執行-或多個程式化操作。舉例而言，連接至机刖及/或WL—dl之記憶體單元可經受程式化，且程式化可使虛設記憶體單元為資料狀態〇至15中之任何者。或者，虛設記憶體單it可使其臨限電壓設定為若干類比位準中之任何者。改變虛設記憶體單元之臨限電壓改變nand串之電阻， Μ虛言更記憶體單元為NAND串之部分。增加虛設記憶體單元之臨限電壓增加财難串之電阻。減小虛設記憶體單元之限電屢減小NAND串之電阻。注意，可基於逐個NAND串（例如，基於逐個位元線）而執行步驟604，藉此，判定每一 NAND串之電阻資訊。因此，在一實施例中，可個別地設定虛設記憶體單元中之每一者的臨限電壓。藉由選擇性地程式化虛設字線上之記憶體單元’ NAND串之電阻可經個別地調諧以考量歸因於將資料程式化至各別nand串中的其個別電阻之改變。 129892.doc -24- 200901206 不必按所描繪之次序來執行圖9之步驟。舉例而言，可在步驟606之劎、之後或期間執行步驟及。在一些The threshold voltage of the dummy memory unit is set by the resistance information determined in _. The setting of the threshold voltage of the dummy memory unit in some embodiments may include performing - or a plurality of stylized operations. For example, a memory cell connected to the device and/or WL_dl can be subjected to stylization, and the stylization can cause the dummy memory cell to be any of the data states 1515. Alternatively, the dummy memory single it can have its threshold voltage set to any of a number of analog levels. Changing the threshold voltage of the dummy memory cell changes the resistance of the nand string, and the memory cell is part of the NAND string. Increasing the threshold voltage of the dummy memory unit increases the resistance of the string. Reducing the power-limiting of the dummy memory cell reduces the resistance of the NAND string. Note that step 604 can be performed on a NAND-by-NAND string (e.g., on a bit-by-bit line basis), whereby the resistance information for each NAND string is determined. Thus, in one embodiment, the threshold voltage of each of the dummy memory cells can be individually set. By selectively programming the memory cells of the dummy word lines, the resistance of the NAND strings can be individually tuned to account for the changes in their individual resistances attributed to the programming of the data into the respective nand strings. 129892.doc -24- 200901206 It is not necessary to perform the steps of Figure 9 in the order depicted. For example, the steps and steps can be performed after, after, or during step 606. In some

If況下在將使用者資料程式化至資料記憶體單元中之前，控制器知曉使用者資料；因此，可在步驟6〇6之前執行步驟604。舉例而言，控制器可在程式化之前缓衝資料。在另—實例中，控制器可初始將資料程式化至多個記 U體單it區塊t作為二進位資料（每—記憶體單元一個資料位元）。在儲存了足夠資料作為二進位資料後，接著將資料再程式化至一單一區塊中作為多位準(或多狀態)資料在將貝料程式化至單一區塊中作為多位準(或多狀態） k料之4，控制器能夠存取多個二進位資料區塊中之資 1在其他情況下，在將使用者資料程式化至資料記憶體單元中之4，控制态並不知曉使用者資料；因此，在步驟 6〇6之後執行步驟6〇4。在步驟6H)中’讀取資料記憶體單元，且將經讀取之資料提供至使用|。舉例而言，來自記憶體單元之資料由控制器提供至主機。因為如上所解釋程式化了虛設記憶體單兀’所以對於讀取資料之過程而言，歸因於程式化資料字線的電阻改變所產生之誤差減少了。一般而言，在讀取及驗證操作期間，將選定字線連接至電壓，扣疋用於母一讀取及驗證操作之電壓的位準，以便判定相關記憶體單元之臨限電壓是否已達到此位準。將未選定字線連接至一與選定字線之電壓不同的過驅動電壓 (被稱作lad)。通常選擇比可經程式化至資料記憶體單元 129892.doc -25· 200901206 的最大臨限電壓高的過驅動雷冤&。過驅動電壓與臨限電壓之間的差亦可被稱作過驅動。在將子線電壓施加至選定字線之後’量測記憶體單元之傳得導電流以判定是否回應於施加至字線的電壓而接通記愔辦极遇圯e體皁兀。若傳導電流經量測比特定值大’則假定記憶體單元接干凡楼通且施加至字線的電壓比記憶體單元之臨限電壓大。若傳導電流經量測不比特定值 tIf the user data is programmed into the data memory unit, the controller knows the user data; therefore, step 604 can be performed before step 6-6. For example, the controller can buffer the data before stylizing. In another example, the controller may initially program the data into a plurality of single-bit blocks t as binary data (one data bit per memory unit). After storing enough data as the binary data, the data is then reprogrammed into a single block as a multi-level (or multi-state) data in the stylized single-block as a multi-level (or Multi-state) k material 4, the controller can access the resources in multiple binary data blocks. In other cases, the user data is programmed into the data memory unit 4, the control state is not known. User data; therefore, step 6〇4 is performed after step 6〇6. The data memory unit is read in step 6H) and the read data is supplied to use |. For example, data from a memory unit is provided by the controller to the host. Since the dummy memory unit 程式 is programmed as explained above, the error due to the resistance change of the stylized data word line is reduced for the process of reading data. Generally, during the read and verify operations, the selected word line is connected to the voltage, and the level of the voltage for the mother-to-read and verify operation is deducted to determine whether the threshold voltage of the associated memory cell has been reached. This level. The unselected word line is connected to an overdrive voltage (called lad) that is different from the voltage of the selected word line. Overdrive thunder & is typically selected that is higher than the maximum threshold voltage that can be programmed to the data memory unit 129892.doc -25. 200901206. The difference between the overdrive voltage and the threshold voltage can also be referred to as overdrive. After the application of the sub-line voltage to the selected word line, the measured conductance of the memory cell is measured to determine whether or not the sputum saponin is turned on in response to the voltage applied to the word line. If the conduction current is measured to be larger than the specified value, then it is assumed that the memory unit is connected to the gate and the voltage applied to the word line is greater than the threshold voltage of the memory unit. If the conduction current is measured no more than a specific value t

大’則假定記憶體單元未接通且施加至字線的電壓不比記憶體單元之臨限電壓大。存在許多方式來在讀取或驗證操作期間量測記憶體單元之傳導電流。在一實例中’按記憶體單元對感測放大器中之專用電谷器放電或充電之速率來量測記憶體單元之傳導電流。在另-實例中’選定記憶體單元之傳導電流允許 (或不能允許）包括記憶體單元之NAND串對位元線上之電壓放電。在一時間週期之後量測位元線上之電荷以查看其是否已經放電。圖1 〇為描述用於程式化連接至一選定字線之記憶體單元之程式化過程的流程圖。可將許多不同程式化技術與本發月起使用。在一實施例中，圖10之過程由控制電路220 及/或在控制電路220之指導下（狀態機222提供控制，且功率控制226提供適當信號）及/或在控制器244之指導下執行。由於程式化過程可包括程式化多個頁，所以程式化過程可包括執行圖10之過程多次。圖10之過程可用以執行圖 9之步驟606及步驟608。主思’在一些實施例中（但並非所有）’自源極側至沒極 129892.doc 26 · 200901206 側程式化記憶體單元。舉例而言，看圖4，首先程式化字線WL0 ’接著程式化wli，接著程式化WL2等。在步驟724中，由控制器244發出一 ”資料載入''命令且將其輸入至狀態機222。在步驟720中，將指定頁位址之位址育料提供至解碼器電路。在步驟728中，輸入（多個）經定址頁之頁程式化資料以用於程式化。舉例而言，在一實施例中，可輸入528個位元組之資料。彼資料鎖存於適當暫存器/鎖存器中以用於選定位元線。在一些實施例中，該負料亦鎖存於第二暫存器中以備選定位元線用於驗證操作。在步驟730中，自控制器2料接收一 ”程式化”命令且將其提供至狀態機222。由程式化"命令觸發，使用一組施加至適當字線之脈衝將在步驟728中鎖存之資料程式化至由狀態機222控制之選定汜L'體單元内。在步驟732中，將程式化電壓信號(例如，該組脈衝）Vpgm初始化為初始量值（例如，約12 v或另一合適位準）’且將一由狀態機222維護之程式化計數器pc 初始化為0。纟步驟734中，㈣式化信號之脈衝外㈣施加至選定字線。在步驟736中，使用該組適當之目標位準驗證選定記憶體單元之資料狀態。若谓測到選定記憶體單元之臨限電壓已達到適當目標位準，則藉由升高其位元線電;i，鎖定該㈣體單元不受到關於圖1Q之其餘過程的程式化。若正經私式化之所有記憶體單元皆已達到其目標資料狀態（步驟 8)則程式化過程完成且成功。在步驟74q中報告,,通過” 129892.doc -27- 200901206 狀心/主忍，在步驟738之一些實施中，檢查至少預數：之記憶體單元是否已經驗證以已達到其目標狀態。此預疋數β目可小於所有記憶體單元之數目，藉此允許在所有。己隐體單7L已達到其適當驗證位準之前程式化過程停止。在讀取過㈣間，可使❹差校正來校正未經成功之記憶體單元。西若在步驟738巾判定並非所有記憶體單元皆已達到其目柘狀,t、則私式化過程繼續。在步驟750中，關於一程式化極限值而檢查程式化計數器PC。程式化極限值之一實例為20 ’然而，在各種實施中可使用其他值。若程式化計數益PC不小於程式化極限值，則在步驟766中判定未經成功知式化之δ己憶體單元的數目是否等於或小於—預定數目。若未經成功程式化之記憶體單元的數目等於或小於該預定數目，則用旗標將程式化過程表示為通過，且在步驟768 中報告通過，，之狀態。在許多情況下，在讀取過程期間可使用誤差校正來校正未經成功程式化之記憶體單元。然而，若未經成功程式化之記憶體單元的數目大於該預定數目則用旗‘將釭式化過程表示為未通過，且在步驟77〇 ^報σ未通過之狀態。若在步驟76〇中判定程式化計數器pc小於程式化極限值，則在步驟762中將下一個vpgm脈衝之量值增加步長（例如，0 2至〇 4伏步長），且遞增程式化計數器PC。在步驟762之後，過程返回至步驟734以施加下一個Vpgm脈衝。圖Π為描述判定資料非揮發性記憶體單元之電阻資訊 129892.doc -28· 200901206 (圖9之步驟604)之一過程之一實施例的流程圖。對於每一 NAND串而言，個別地（且在一些情況下同時）執行圖丨丨之過程。在步驟802中，考慮下一個資料記憶體單元。若此為第一次執行步驟802 ’則存取NAND串之第—資料記憶體單元（例如’連接至WL0之資料記憶體單元）。在步驟804中，系統表徵由當前正處於考慮下的nand串上之資料記憶體單元所經歷的電阻之改變。每—記慎體單元經歷相對於在彼記憶體單元之後經程式化之所有記憶體單元的電阻改變。舉例而言，連接至WL3之記憶體單元將經歷歸因於連接至WL4至WL63的記憶體單元之程式化的電阻改變。相對電阻改變將關於在程式化饥4至肌63上之記憶體單元之前與在程式化連接至WL4至wl63之記憶體單兀之後的比較。存在量測此電阻改變之許多方式。一方法為量測實際電阻值。另一實施例為基於經程式1至記憶體單元中的資料而估計電阻改變。亦可使用其他方法。圖11之實施例基於經程式化至記憶體單元中的資料而表徵電阻改變。藉由比齡錄紹4'儿 > 生卓程式化之貝際資料與資料之均勻分布且判定與該均勾分布之偏離，表徵電阻改變。當資料狀態經同等（或儘可能地接近同等）地表示時，存在資料之均勻分布。在於_财仙串±存在六十四個資料體單料狀態之-實例中，若存在資料之均；分則每一資料狀態在N娜串上將出現四次。步驟S04 將表徵經程式化之實際資料企次』丨 I丨不貝科與資料之均勻分布之間的異，且使用彼差異程式化虛設記憶體單元。 \29S92.doc •29· 200901206 可預先知曉資料之均勻分布對電阻之影響。工程師們可模擬或測試歸因於正經程式化至NAND串的資料之均勾分布之實際電阻改變。基於彼資訊，可調整讀取過程以考量與均勻分布之電阻改變。舉例而言，2006年6月i曰申請之美國專利申請案第 11/42 1，667號，'Verify Operatioll For Non-Large' assumes that the memory cell is not turned on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. There are many ways to measure the conduction current of a memory cell during a read or verify operation. In one example, the conduction current of the memory cell is measured by the rate at which the memory cell discharges or charges the dedicated battery in the sense amplifier. In another example, the conduction current of the selected memory cell allows (or does not allow) the voltage discharge on the NAND string-to-bit line including the memory cell. The charge on the bit line is measured after a period of time to see if it has been discharged. Figure 1 is a flow chart depicting the stylization process for staging memory cells connected to a selected word line. Many different stylization techniques can be used from this month. In one embodiment, the process of FIG. 10 is performed by control circuit 220 and/or under the direction of control circuit 220 (state machine 222 provides control and power control 226 provides appropriate signals) and/or is executed under the direction of controller 244 . Since the stylization process can include stylizing multiple pages, the stylization process can include performing the process of Figure 10 multiple times. The process of Figure 10 can be used to perform steps 606 and 608 of Figure 9. The main thinking 'in some embodiments (but not all) 'from the source side to the pole 129892.doc 26 · 200901206 side stylized memory unit. For example, looking at Figure 4, the programmatic word line WL0' is first programmed to wli, then WL2 is programmed. In step 724, a "data load" command is issued by controller 244 and input to state machine 222. In step 720, the address of the specified page address is provided to the decoder circuit. In 728, the paged programming data of the addressed page is input for programming. For example, in one embodiment, 528 bytes of data can be input. The data is latched in an appropriate temporary storage. In the device/latch for selecting a positioning element line. In some embodiments, the negative material is also latched in the second register to alternately locate the element line for verification operation. In step 730, The controller 2 receives a "stylized" command and provides it to the state machine 222. Triggered by the stylized " command, the data latched in step 728 is stylized using a set of pulses applied to the appropriate word line to The selected unit is controlled by state machine 222. In step 732, the programmed voltage signal (e.g., the set of pulses) Vpgm is initialized to an initial magnitude (e.g., about 12 v or another suitable level). 'And a stylized counter pc maintained by state machine 222 0. In step 734, the pulse of the (4)-formed signal is applied to the selected word line. In step 736, the data state of the selected memory cell is verified using the appropriate target level of the set. If the threshold voltage of the body unit has reached the appropriate target level, by raising its bit line power; i, locking the (four) body unit is not stylized with respect to the rest of the process of Figure 1Q. The memory unit has reached its target data state (step 8) and the stylization process is completed and successful. Reported in step 74q, through "129892.doc -27- 200901206 Heart/Master, some implementation at step 738 In the middle, check at least the pre-number: whether the memory unit has been verified to have reached its target state. This number of pre-numbers β can be less than the number of all memory cells, thereby allowing at all. The stylization process stops before the hidden 7L has reached its proper verification level. Between the readings (4), coma correction can be made to correct unsuccessful memory cells. In the step 738, Xi Ruo decides that not all memory units have reached their target state, and t, the privateization process continues. In step 750, the stylized counter PC is checked for a stylized limit value. An example of one of the stylized limits is 20 ' However, other values may be used in various implementations. If the stylized count benefit PC is not less than the stylized limit value, then in step 766 it is determined whether the number of unrecognized modified δ-resonant units is equal to or less than a predetermined number. If the number of memory cells that have not been successfully programmed is equal to or less than the predetermined number, the stylization process is flagged as a flag, and the status of the pass, is reported in step 768. In many cases, error correction can be used during the reading process to correct unsuccessfully programmed memory cells. However, if the number of memory cells that have not been successfully programmed is greater than the predetermined number, the flag is used to indicate that the process is not passed, and in step 77, the state in which σ has not passed is reported. If it is determined in step 76 that the stylized counter pc is less than the stylized limit value, then in step 762, the magnitude of the next vpgm pulse is increased by a step size (eg, 0 2 to 〇 4 volt steps), and the program is incremented. Counter PC. After step 762, the process returns to step 734 to apply the next Vpgm pulse. Figure is a flow diagram depicting one embodiment of one of the processes of determining resistance information for a non-volatile memory cell of a data non-volatile memory cell 129892.doc -28· 200901206 (step 604 of Figure 9). For each NAND string, the process of the map is performed individually (and in some cases simultaneously). In step 802, the next data memory unit is considered. If this is the first time step 802' is performed, then the first data memory unit of the NAND string (e.g., 'data memory unit connected to WL0') is accessed. In step 804, the system characterizes the change in resistance experienced by the data memory unit on the nand string currently under consideration. Each-care unit undergoes a change in resistance relative to all memory cells that are programmed after the memory unit. For example, a memory cell connected to WL3 will experience a stylized resistance change due to a memory cell connected to WL4 through WL63. The relative resistance change will be compared to the memory unit before stylizing the hungry 4 to the muscle 63 and after the stylized connection to the memory unit of WL4 to wl63. There are many ways to measure this resistance change. One method is to measure the actual resistance value. Another embodiment is to estimate the resistance change based on the data in the program 1 through the memory unit. Other methods can also be used. The embodiment of Figure 11 characterizes resistance changes based on data programmed into the memory cells. The resistance change is characterized by the uniform distribution of the data and data of the 4's > stylized stylized data and the deviation from the homogenous hook distribution. When the data status is expressed equally (or as close as possible), there is an even distribution of the data. In the case of _ 财仙串± there are sixty-four data items in the state of the material - in the example, if there is data; the value of each data will appear four times on the N Na string. Step S04 will characterize the difference between the stylized actual data and the uniform distribution of the data, and use the difference to program the dummy memory unit. \29S92.doc •29· 200901206 The influence of the uniform distribution of data on the resistance can be known in advance. Engineers can simulate or test the actual resistance change due to the sum of the data that is being programmed into the NAND string. Based on the information, the reading process can be adjusted to take into account the uniform distribution of resistance changes. For example, U.S. Patent Application Serial No. 11/42,667, filed June 2006, 'Verify Operatioll For Non-

Volatile Storage Using Different Voltages1’（其以引用的方式全部併入本文中）描述一種系統，該系統當執行—資料感測操作（包括在程式化非揮發性儲存元件期間的驗證操作）時，將第一電壓用於已經受程式化操作之未選定字線，及將第二電壓用於尚未經受程式化操作之未選定字線。此系統考畺在程式化期間的電阻改變且可經調譜以考量資料之均勻分布。亦可在讀取操作期間使用該技術。另一實例提供於2006年6月2日申請之美國專利申請案第 Π/421,871^-Data Pattern Sensitivity Compensation Using Different Voltage "中，其以引用的方式全部併入本文中。此申請案描繪一種系統，該系統當執行一資料感測操作 (包括在程式化非揮發性儲存元件期間的驗證操作）時，將第一電壓用於已經受程式化操作之未選定字線，將第二電壓用於尚未經受程式化操作之未選定字線，及將第三電壓用於尚未經受程式化操作且鄰近選定字線之未選定字線。亦可在讀取期間獨立地調整相鄰字線。此系統可經調諧以考量資料之均勻分布。亦可使用考量歸因於資料之均勻分布之電阻改變的其他技術。在步驟804中，系統判定與資料之均勻分布的偏離。對 _3〇· 129892.doc 200901206 於考慮中之資料記憶體單元而言’步驟8()4著眼於在彼記憶體單元之後經程式化之所有記憶體單元。舉例而言，若正考慮連接至WL3之記憶體單元，則步驟8〇4將包括著眼於連接至WL4至WL63之所有記憶體單元。系統可以許多不同方式表徵與均勻分布之偏離。一實例為將一數值指派至每一資料狀態；舉例而言，資料狀態〇指派有〇，資料狀態1指派有1 ’資料狀態2指派有2,資料狀態3指派有 3，……，資料狀態15指派有Μ。系統可合計實際資料之每一資料狀態的指派數且將其除以記憶體單元之數目。因此，將計算出一平均值。可將彼平均值與均勻分布之平均值比較。纟自實際平均值與均句分布之平均值的差為指示電阻特徵之資訊的一實例(其他實例包括實際電阻、相對電阻、本文中所描述之其他資料值以及其他）。步驟8〇8執行計算以判定在-NAND串上之H己憶體單元的㈣值，且在步驟806中儲存經判定之偏離值。在步驟8〇8中，判定在NAND串上是否存在待考慮之任何更多記憶體單元。若在NAND串上存在待考慮乂更多記憶體單元，則過程返回至步驟802且考慮下一個記憶體單元。因此，對於 NAND串上之母一 §己憶體單元而言，執行步驟至肋6之循環-：欠。在於NAND串上不存在待考慮之更多記憶體單元（步驟80S)之後，則在步驟81〇中識別最大偏離及最小偏離。在步驟812中’系統判定對最大偏離及最小偏離兩者之調整’使得最小偏離低於零改變，最大偏離高於零改變， 129892.doc -31 - 200901206 ::大偏離’、令改變之間的差最小化，且使最小 =最小化。在步驟814中，系統判定程式化虛 uk'體早π之臨限電屋’以便達成步驟812之調整。、主意’使最小及最大偏離相對於平均值關於零改變僅 =用之誤差減小準則的-實例。亦可使用其他誤差減小準則。 fVolatile Storage Using Different Voltages 1 ', which is incorporated herein by reference in its entirety, describes a system that, when performing a data sensing operation (including verification operations during staging non-volatile storage elements) A voltage is applied to the unselected word lines that have been programmed, and the second voltage is used to the unselected word lines that have not been subjected to the stylization operation. This system considers the change in resistance during stylization and can be tuned to take into account the uniform distribution of the data. This technique can also be used during read operations. Another example is provided in U.S. Patent Application Serial No. 4,421, 871, filed on Jun. This application describes a system for using a first voltage for unselected word lines that have been programmed, when performing a data sensing operation, including a verify operation during staging a non-volatile storage element. The second voltage is applied to the unselected word lines that have not been subjected to the stylization operation, and the third voltage is applied to the unselected word lines that have not been subjected to the stylization operation and are adjacent to the selected word line. Adjacent word lines can also be independently adjusted during reading. This system can be tuned to account for the even distribution of data. Other techniques that take into account resistance changes due to uniform distribution of data can also be used. In step 804, the system determines a deviation from the uniform distribution of the data. For _3〇· 129892.doc 200901206 for the data memory unit under consideration, step 8()4 looks at all memory units that are programmed after the memory unit. For example, if a memory cell connected to WL3 is being considered, then step 〇4 will include focusing on all of the memory cells connected to WL4 through WL63. The system can characterize deviations from uniform distribution in many different ways. An example is to assign a value to each data state; for example, the data status 〇 is assigned 〇, the data status 1 is assigned 1 'data status 2 is assigned 2, the data status 3 is assigned 3, ..., data status 15 is assigned. The system can total the number of assignments for each data state of the actual data and divide it by the number of memory cells. Therefore, an average value will be calculated. The average value can be compared to the average of the uniform distribution. The difference between the actual average and the average of the mean distribution is an example of information indicative of the resistance characteristics (other examples include actual resistance, relative resistance, other data values described herein, and others). Step 8〇8 performs a calculation to determine the (four) value of the H-remember cell on the -NAND string, and stores the determined offset value in step 806. In step 8〇8, it is determined whether there are any more memory cells to be considered on the NAND string. If there are more memory cells to consider on the NAND string, then the process returns to step 802 and considers the next memory cell. Therefore, for the parent-resonant unit on the NAND string, the loop to the rib 6 is performed - owed. After there are no more memory cells to be considered on the NAND string (step 80S), then the maximum and minimum offsets are identified in step 81. In step 812, 'the system determines the adjustment for both the maximum deviation and the minimum deviation' such that the minimum deviation is less than zero, and the maximum deviation is greater than zero, 129892.doc -31 - 200901206 :: large deviation ', between changes The difference is minimized and minimized = minimized. In step 814, the system determines that the stylized virtual uk' body is early π to limit the electric house' to achieve the adjustment of step 812. The idea is to make the minimum and maximum deviations relative to the average change with respect to zero only = the example of the error reduction criterion used. Other error reduction criteria can also be used. f

關於零改變而㈣最大偏離及最小偏離為之原因係因為零改變表示平均分布。因此，調整表示實際資料與資. 均勾分布之間的電阻差。藉由程式化虛設記憶體單元，可改變NAND串之電阻。田士甘从κ 因此，基於步驟812之調整而程式化虛設記憶體單元設法改變财啊之電阻，以移向具有均句分布之_串的電阻。如上所敍述，讀取過程經配備以考量歸因於資料之均勻分布的電阻改變。在實施例中，若NAND串具有等於零之最大偏離及最小偏離兩者，則該NAND串為均勾分布，且虛設記憶體單元（乳―d0及WL_dl)皆經設定為處於資料狀態7下。亦即，虛設記憶體單元之臨限電壓經升高，使得其處於對應於資料狀態7的臨限電壓分布中。若NAND串具有導致比均勻分布低之電阻的資料，則可藉由將虛設記憶體單元程式化I 比7高的資料狀態來增加NAND串之電阻。若ναν〇串具有大於均勻分布之電阻，則可藉由將虛設記憶體單元程式化至比資料狀態7低的狀態來降mNAND串之電阻。在—實施例中，虛設記憶體單元將僅經程式化至資料狀態〇、7及μ 中。在其他實施例中，記憶體單元可經程式化至資料狀態 129892.doc -32- 200901206 中之任何者中，冑此提供調諧nand串之電阻之方式的較多解析度。在又一實施例中’臨限電壓不必經程式化至— 資料狀態。相反’臨限電壓可為零與最大允許臨限電壓之間的任何類比值。在-實例中’最大允許臨限電壓至少比在讀取過程期間用於未選定字線上之過驅動電壓小2伏。在另一實施例中，並不使最小及最大偏離關於零居中， :可程式化虛設記憶體單元以使NAND串上之所有記憶體單70之偏離之平方的平均值最小化。或者，系統可設法使 NAND串中具有處於具有對整個vt分布之可忽略影響之電阻改變範圍外的電阻改變之記憶體單元之數目最小化。庄思，步驟8 1 4之結果可能需要比可能臨限值大（或低）的虛設臨限值。在此情況下，將（多個）虛設單元程式化至可能的最大（或最小）臨限電壓。圖12A至圖12D提供描述程式化資料記憶體單元及設定The reason for the zero change and (4) the maximum deviation and the minimum deviation is because the zero change represents the average distribution. Therefore, the adjustment represents the difference in resistance between the actual data and the capital distribution. The resistance of the NAND string can be changed by programming the dummy memory cells. Tian Shi Gan from κ Therefore, based on the adjustment of step 812, the stylized memory unit tries to change the resistance of the money to move to the resistance of the _ string with a uniform sentence distribution. As described above, the reading process is equipped to take into account the resistance change due to the uniform distribution of the data. In an embodiment, if the NAND string has both a maximum deviation and a minimum deviation of zero, the NAND string is uniformly distributed, and the dummy memory cells (milk - d0 and WL_dl) are all set to be in data state 7. That is, the threshold voltage of the dummy memory cell is raised such that it is in a threshold voltage distribution corresponding to the data state 7. If the NAND string has data that results in a lower resistance than the uniform distribution, the resistance of the NAND string can be increased by staging the dummy memory cell to a higher data state than 7. If the ναν〇 string has a resistance greater than a uniform distribution, the resistance of the mNAND string can be reduced by staging the dummy memory cell to a state lower than the data state 7. In the embodiment, the dummy memory cells will only be programmed into the data states 7, 7 and μ. In other embodiments, the memory unit can be programmed to any of the data states 129892.doc-32-200901206, which provides more resolution of the manner in which the resistance of the nand string is tuned. In yet another embodiment, the threshold voltage does not have to be programmed to a data state. Conversely, the threshold voltage can be any analogy between zero and the maximum allowable threshold voltage. In the - instance, the maximum allowable threshold voltage is at least 2 volts less than the overdrive voltage for the unselected word line during the read process. In another embodiment, the minimum and maximum deviations are not centered with respect to zero: the dummy memory cells can be programmed to minimize the average of the squares of the deviations of all memory banks 70 on the NAND string. Alternatively, the system can try to minimize the number of memory cells in the NAND string that have a resistance change outside of the range of resistance changes that have negligible effects on the overall vt distribution. Zhuang Si, the result of step 8 1 4 may require a dummy threshold that is larger (or lower) than the possible threshold. In this case, the dummy unit(s) are programmed to the maximum (or minimum) threshold voltage possible. 12A through 12D provide a description of a stylized data memory unit and settings

虛設記憶體單元之臨限電壓之次序的各種實施例。圖12A 提供包括在資料記憶體單元之後程式化虛設記憶體單元之一實例。在步驟850中，程式化所有資料記憶體單元。在步驟852中，在程式化資料記憶體單元之後，設定虛設記憶體單7G之臨限電壓。因為在程式化資料記憶體單元之後程式化虚設記憶體單元，所以可藉由著眼於記憶體單元中之貝際資料來執行圖11之過程。另一方面，亦可基於控制器已儲存於緩衝器中或其他區塊（如上所述）中之資料而執行圖11。圖12B描述僅使用每一 nAnD串之虛設記憶體單元中之 129892.doc -33- 200901206 一者的一實施例。在步驟86〇中， „ . 程式化所有育料記憶體早兀。在步驟862中，設定每—Na _ ^ AND串之—虛設記憶體單兀之臨限電壓。在一實施例φ，—本< 中—虛5又記憶體單元處於字線WL—cU上。在—些實施例中，可能存在許多虛設字線，然而’僅虛設字線之-子集用以影響電阻。在—些實施例中，可動態地進行哪一虛設字線用以影響電阻之判定。Various embodiments of the order of the threshold voltages of the dummy memory cells. Figure 12A provides an example of a programmatic dummy memory unit included after the data memory unit. In step 850, all data memory units are programmed. In step 852, the threshold voltage of the dummy memory card 7G is set after the stylized data memory unit. Since the dummy memory cells are programmed after the stylized data memory unit, the process of Fig. 11 can be performed by focusing on the interbay data in the memory cells. Alternatively, Figure 11 can be performed based on data that the controller has stored in the buffer or in other blocks (described above). Figure 12B depicts an embodiment of one of 129892.doc-33-200901206 in a dummy memory unit using only each nAnD string. In step 86, „. stylizes all the nurturing memories early. In step 862, the threshold voltage of each of the -Na _ ^ AND strings-dummy memory cells is set. In an embodiment φ, The <zhong-virtual 5 memory cell is on word line WL-cU. In some embodiments, there may be many dummy word lines, but 'only a subset of dummy word lines are used to affect the resistance. In some embodiments, which dummy word line can be dynamically performed to affect the determination of the resistance.

圖UC描述一實施例，其中（對於一 NAND串而言）在已程式化資料記憶體單元之一子集之後程式化—虛設記憶體單疋’且在程式化所有資料記憶體單元之後程式化另一虛設記憶體單元。在步驟請中，系統程式化前半部（或不同部分）字線（例如，WL〇至WL31)之資料記憶體單&。在步驟 8 72中。又定連接至WL—d0之（多個）虛設記憶體單元中之每 -者的臨限電壓。在步驟874令’程式化其餘資料記憶體單元（例如，對於WL32至WL63)。在步驟8?6中系統設定連接至W L—d 1之（多個）虛設記憶體單元之（多個）臨限電壓。在圖12C之過程之一變化中，控制器在執行步驟872的同時能夠存取所有字線之所有資料；因此，基於所有字線之資料而設定連接至WL_d〇之虚設記憶體單元。在另一實施例中，控制器（或其他相關實體）僅能夠存取在步驟87〇中已經程式化至資料記憶體單元中之資料。在後者情況下，基於連接至前半部（或不同部分）字線（例如，WL〇至wl31)2 資料記憶體單元之内容而設定連接至WL—d〇之虛設記憶體單。在步驟876中，系統基於所有字線之資料而設定連 129892.doc -34· 200901206 接至WL_dl之虛設記憶體單元之臨限電壓。此等變化可適用於圖11之過程及其他替代例。注意，由一虛設記憶體單元提供之電阻改變將影響在設定該虛設記憶體單元之臨限電壓之前程式化的彼等資料記憶體單元。圖12D提供在開始程式化資料記憶體單元之後且在完成所有資料記憶體單元之程式化之前程式化所有虛設記憶體單元之另一實施例。在步驟8 8 0中，程式化第一群字線之資料記憶體單元。在步驟882中，設定連接至WL_dO之虛設記憶體單元之臨限電壓。在步驟884中，程式化連接至第二群字線的記憶體單元。在步驟8 8 6中，設定連接至 WL—d 1之虛設記憶體單元之臨限電壓。在步驟8 8 8中，程式化連接至第三群字線的記憶體單元。在一實施例中，第一群字線包括WL0至WL21，第二群字線包括WL22至 WL42 ’且第三群字線包括Wl43至WL63。在其他實施例中’三個群包括不同成員。圖13提供判定資料記憶體單元之電阻資訊、程式化資料 s己憶體單元及基於電阻資訊而設定虛設記憶體單元之臨限電壓的另一實施例。在此實施例中，藉由處於高資料狀態下的記憶體單元之數目來估計NAND串之電阻改變。可將 NAND串分為三個群。第—群包括字線胃[〇至WL21，第二群包括WL22至WL42，且第三群包括WL43至WL63。在步驟902中’系統判定第二群記憶體單元中的高資料狀態之數目。假定狀態12至15為高資料狀態。因此，系統將計數第一群中具有儲存於資料狀態12至15下之資料的記憶體單 129892.doc •35- 200901206 元之數目。使高資料狀態與較高臨限電壓相關聯，其中較高臨限電壓對電阻具有較大影響。在步驟904中，系統將計數第三群中處於高資料狀態下的記憶體單元之數目。在步驟906中，用使用者資料程式化第一群記憶體單元。在步驟908中，將基於第二群及第三群資料記憶體單元中高資料狀態之數目而程式化連接至WL_dO之虛設記憶體單元。在一實施例中，將第二群及第三群中處於高電阻狀態下的記憶體單元之數目與對於均勻分布而言將處於高電阻狀恶下的記憶體單7L之數目比較。此偏離將用以將虛設記憶體單元之臨限電壓設定為資料狀態0、資料狀態7或資料狀態15。如上所述，藉由使用所有資料狀態或一類比值，可達成較大解析度。在步驟91〇中，程式化第二群記憶體單元。在步驟912中’基於第三群中處於高資料狀態下的記憶體單元之數目(如與單元之均勾分布比較)而程式化連Figure UC depicts an embodiment in which (for a NAND string) is programmed after a subset of the programmed data memory cells - a dummy memory block - and is stylized after all the data memory cells are programmed Another dummy memory unit. In the step, the system stylizes the data memory list & of the first half (or different parts) of the word line (for example, WL〇 to WL31). In step 8 72. It is also determined to be connected to the threshold voltage of each of the dummy memory cells(s) of WL_d0. At step 874, the remaining data memory cells are programmed (e.g., for WL32 through WL63). In steps 8-6, the system sets the threshold voltage(s) connected to the dummy memory unit(s) of W L-d 1 . In a variation of the process of Figure 12C, the controller can access all of the data for all word lines while performing step 872; therefore, the dummy memory cells connected to WL_d are set based on the data of all word lines. In another embodiment, the controller (or other related entity) can only access the data that has been programmed into the data memory unit in step 87. In the latter case, a dummy memory list connected to WL_d〇 is set based on the content of the data memory unit connected to the first half (or different portion) of the word line (e.g., WL〇 to wl31). In step 876, the system sets the threshold voltage of the 129892.doc -34.200901206 connected to the dummy memory unit of WL_dl based on the data of all word lines. These variations can be applied to the process of Figure 11 and other alternatives. Note that the resistance change provided by a dummy memory cell will affect their data memory cells that are programmed prior to setting the threshold voltage of the dummy memory cell. Figure 12D provides another embodiment of stylizing all dummy memory cells after starting the staging of the data memory unit and before completing the stylization of all data memory units. In step 880, the data memory cells of the first group of word lines are programmed. In step 882, the threshold voltage of the dummy memory cell connected to WL_dO is set. In step 884, the memory cells connected to the second group of word lines are stylized. In step 886, the threshold voltage of the dummy memory cell connected to WL_d1 is set. In step 888, the memory cells connected to the third group of word lines are programmed. In an embodiment, the first group of word lines includes WL0 through WL21, the second group of word lines includes WL22 through WL42', and the third group of word lines includes Wl43 through WL63. In other embodiments the 'three groups include different members. Figure 13 provides another embodiment of determining the resistance information of the data memory unit, the stylized data, and the threshold voltage of the dummy memory unit based on the resistance information. In this embodiment, the resistance change of the NAND string is estimated by the number of memory cells in a high data state. The NAND strings can be divided into three groups. The first group includes a word line stomach [〇 to WL21, the second group includes WL22 to WL42, and the third group includes WL43 to WL63. In step 902, the system determines the number of high data states in the second group of memory cells. It is assumed that states 12 to 15 are high data states. Therefore, the system will count the number of memory sheets 129892.doc • 35- 200901206 in the first group with data stored under data states 12-15. The high data state is associated with a higher threshold voltage, with a higher threshold voltage having a greater impact on the resistance. In step 904, the system will count the number of memory cells in the third group that are in the high data state. In step 906, the first group of memory cells is programmed with the user profile. In step 908, the dummy memory cells of WL_dO are programmatically coupled based on the number of high data states in the second and third group of data memory cells. In one embodiment, the number of memory cells in the high resistance state of the second and third groups is compared to the number of memory cells 7L that will be under high resistance for uniform distribution. This deviation will be used to set the threshold voltage of the dummy memory cell to data state 0, data state 7, or data state 15. As described above, a larger resolution can be achieved by using all data states or a class of ratios. In step 91, the second group of memory cells is programmed. In step 912, 'programming the number based on the number of memory cells in the third group in the high data state (as compared to the uniform hook distribution of the cells)

σ己憶體早元之數目而（在第— 將基於第—群中處於高狀態下的資料 (在第—群資料記憶體單元之後）程式 129892.doc -36· 200901206 化連接至WL_dO之虛設記憶體單元，將基於所有三個群中處於高狀態下的資料記憶體單元之數目而（在所有三個群之資料記憶體單元之後）程式化連接至WL—dl之虛設記憶體單元。 ίσ 忆忆体早 ( ( ( ( ( ( ( ( ( ( 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 The memory unit is programmatically connected to the dummy memory unit of the WL_dl based on the number of data memory cells in the high state of all three groups (after the data memory cells of all three groups).

圖14提供判定電阻資訊、程式化資料記憶體單元及設定虛設記憶體單元之臨限電壓的另一實施例。在步驟932 中，程式化資料記憶體單元。在步驟934中，系統計數處於高資料狀態下的資料記憶體單元之數目。在一實施例中，系統將考慮所有資料記憶體單元。在另一實施例中，系統僅考慮上部群之資料記憶體單元是否處於高資料狀態下。上部群之資料記憶體單元可為字線之頂部一半（例如，WL32至WL63)、字線之頂部三分之一或其他分群。在步驟936中，基於在步驟934中計數的記憶體單元之數目 (如與記憶體單tl之平均分布比較）而程式化虛設記憶體單 7G或者以其他方式設定虛設記憶體單元之臨限電壓。圖1 5提供判定電阻資訊、程式化資料記憶體單元及設定虛設記憶體單元之臨限電壓的另一實施例。在步驟96〇中，將資料程式化至所有資料記憶體單元中。在步驟中，系統執行NAND串之電阻資訊之實體量測。存在實體里測電阻4之多方式。舉例而言，為了量測NAnD串中的一或多個電晶體（集合A)之電阻，使其控制閘極電虔設定為比在讀取過程期間使用之常規過驅動電壓相對低。閘以對於NAND串上之所有其他電晶體（集合b)而纟，將控制極電壓設定為在讀取過程期間使用之常規過驅動電壓。 129892.doc -37- 200901206 此方式’集合A之電阻將支配整個nAND串之整體串聯電阻。藉由將位元線電壓設定為一些值且量測電流，系統可發現串聯電阻。一實施例描述於2006年12月29日申請的美國專利申請案第11/617,972號中，其以引用的方式全部併入本文中。在一替代例中’集合A可為整個NAND串。Figure 14 provides another embodiment of determining resistance information, stylizing data memory cells, and setting threshold voltages for dummy memory cells. In step 932, the data memory unit is programmed. In step 934, the system counts the number of data memory locations in the high data state. In one embodiment, the system will consider all data memory units. In another embodiment, the system only considers whether the data memory unit of the upper group is in a high data state. The data memory cells of the upper group can be the top half of the word line (e.g., WL32 to WL63), the top third of the word line, or other subgroups. In step 936, the dummy memory bank 7G is programmed or otherwise set based on the number of memory cells counted in step 934 (as compared to the average distribution of memory cells t1). . Figure 15 provides another embodiment of determining resistance information, stylizing data memory cells, and setting threshold voltages for dummy memory cells. In step 96, the data is stylized into all data memory units. In the step, the system performs an entity measurement of the resistance information of the NAND string. There are many ways to measure the resistance 4 in the entity. For example, to measure the resistance of one or more transistors (set A) in the NAnD string, its control gate power is set to be relatively lower than the conventional overdrive voltage used during the read process. Gates With all other transistors (set b) on the NAND string, the gate voltage is set to the conventional overdrive voltage used during the read process. 129892.doc -37- 200901206 This method 'the resistance of set A will dominate the overall series resistance of the entire nAND string. By setting the bit line voltage to some value and measuring the current, the system can find the series resistance. An embodiment is described in U.S. Patent Application Serial No. 11/617,972, filed on Dec. 29, 2006, which is incorporated herein by reference. In an alternative, 'set A' can be the entire NAND string.

在圖15之步驟964中，基於自步驟962之經量測之電阻而判定虛設記憶體單元之目標臨限電壓。舉例而言，實體量測可判定一特定NAND串為高電阻還是低電阻NAND串。若該NAND串為低電阻NAND串，則可將虛設記憶體單元程式化至資料狀態12。若該NAND串為高電阻nand串，則可將虛設記憶體單元程式化至資料狀態4。在步驟 t，基於在步驟964中判定之經判定之臨限電壓位準而程式化虛設記憶體單元。以上論述之所有實施例之—優點在於，當同時程式化連接至一制虛設字線之所有虛設記憶別地設定至不同狀態…，可個別地調譜每串。如上所述’在讀取或驗證操作期間，將未衫字線連接至通常經選擇為比可程式化至— _ 貞料6己憶體早兀之最大臨限电廢尚的過驅動電麼。尥駆動電壓與臨限電壓之間的姜被稱作過驅動。未選定 u . 厲體早兀之電阻為過驅動之非線性函數。討之，動之非線咸，㈣A 近零時’電阻對過驅動很敏 ^對於大過驅動而言，則相對地不敏感。因此，在一實施例中，用靠近零之過驅求麵作虛§又s己憶體單元。因 129892.doc -38- 200901206 二匕’可將虛設記憶體單元之過驅動電壓設定為比用於典型貧料記憶體單元之電麗低的電麼，使得過驅動電壓更靠近虛設記憶體單元之臨限電壓。在：實施例中，可將虛設記憶體單元程式化至與資料記憶體单元相比之較窄範圍的臨限電愿。舉例而言，虛設記憶體單元可具有設定於浮動閑極之電荷中性條件附近的臨限電麼’其中序動閘極之電荷中性條件為存在與電子一樣多的質子的條件。藉由使虛設記憶體單元臨限電塵之範圍在浮動問極之電荷令性條件附近居中，降低了資料保存及其他=性問題之影響。現在較易於定出虛設記憶體單元 …Τ门電阻(亦即’低過驅動)狀態’而並不招致高電荷夺動閘極之可靠性損失。在此實施例中，虛設記憶體翠元了具有較低過驅動電壓（如與f料記憶體單元比較）且視以 ΐ過程需要改變NAND串之電阻的方式而定，虛設記憶體设定為電荷中性條件、稍高於電荷中性條件或 :低於電荷中性條件(而非資料狀態0、7及15)之臨限電 I可將此組態與上述過程一起使用。已為說明及描述之日的、·，口出本發明之前述實施方式。JL 二不思欲為詳盡的或將本發明限於所揭示之精確形式。^ 按照上述教示作出蜂夕 T - ^夕t改及變化。選擇所述實施例係為了取好地解釋本菸日日门，之原理及其實際應用，從而使得熟習此項技術之其他去台t %田令， b -取好地將本發明用於各種實施例 ^ 且在適合於預期牲發明。希望各種修改下最好地利用本曰思附於本文之申請專利範圍定義本發明之 129892.doc -39- 200901206 範疇。【圖式簡單說明】圖1為NAND串之俯視圖。圖2為NAND串之等效電路圖。圖3為一非揮發性記憶體系統之方塊圖。圖4為描緣-記憶體陣列之—實施例的方塊圖。圖5為描繪一感測區塊之一實施例的方塊圖。圖6描繪臨限電壓分布之一實例集合。圖7描繪將資料編碼為與臨限電壓分布相關聯之一組資料狀邊的一實例。圖8彳田繪將育料編碼為與臨限電壓分布相關聯之一組資料狀態的一實例。圖9為描述操作非揮發性記憶體單元之—實施例的流程圖。圖1 〇為“述程式化非揮發性記憶體單元之過程之一實施例的流程圖。，圖11為描述敎資料_發性記《單元之電阻資訊之過程之一實施例的流程圖。圖至圖12D為描述程式化資料非揮發性記憶體單元及設定虛設非揮發性記憶體單元之臨限電壓之各種實施例的流程圖。圖為4田述判定資料非揮發性記憶體單元之電阻資訊、程式化資料非揮發性記憶體單元及設定虛設非揮發性記拷體單元之臨限電壓之過程之一實施例的流程圖。 129892.doc -40. 200901206 ,為為述列定資料非揮發性記憶體單元之電阻資訊、程弋化資料非揮發性記憶體單元及設定虛設非揮發性記憶體單元之臨限電壓之過程之一實施例的流程圖。圖15為描述判定資料非揮發性記憶體單元之電阻資訊、程式化資料非揮發性記憶體單元及設定虛設非揮發性記憶體單元之臨限電壓之過程之一實施例的流程圖。【主要元件符號說明】 100 電晶體 100CG 控制閘極 100FG 浮動閘極 102 電晶體 102CG 控制閘極 102FG 浮動閘極 104 電晶體 104CG 控制閘極 104FG 浮動閘極 106 電晶體 106CG 控制閘極 106FG 浮動閘極 120 選擇閘極 122 選擇閘極 126 位元線接觸 128 源極線 200 記憶體陣列 129892.doc -41 - 200901206 210 記憶體器件 212 έ己憶體晶粒或晶片 220 控制電路 222 狀態機/狀態機電路 224 解碼器/解碼器電路 226 功率控制模組/功率控制電路 230A 讀取/寫入電路 230B 讀取/寫入電路 232 線 234 線 240A 列解碼器/列解碼器電路 240B 列解碼器/行解碼器電路 242A 行解碼器/行解碼器電路 242B 行解碼器/行解碼器電路 244 控制器 300 感測區塊 420 資料匯流排 470 感測電路 472 匯流排 480 感測模組 482 位元線鎖存器 490 共同部分 492 處理器 493 輸入線 129892.doc -42- 200901206 494 資料鎖存器 496 I/O介面 SGD 汲極側選擇線 SGS 源極側選擇線 WLO ……WL63 字線 WL_dO 虛設字線 WL_dl 虛設字線In step 964 of Figure 15, the target threshold voltage of the dummy memory cell is determined based on the measured resistance from step 962. For example, physical measurements can determine whether a particular NAND string is a high resistance or a low resistance NAND string. If the NAND string is a low resistance NAND string, the dummy memory unit can be programmed to data state 12. If the NAND string is a high resistance nand string, the dummy memory cell can be programmed to data state 4. At step t, the dummy memory cells are programmed based on the determined threshold voltage levels determined in step 964. All of the above discussed embodiments - the advantage is that each of the strings can be individually tuned when all of the dummy memories that are simultaneously programmed to a dummy word line are set to different states. As described above, during the reading or verification operation, the unprinted word line is connected to the overdrive power that is usually selected to be the largest temporary power waste that can be programmed to be more than _ 6 6 . The ginger between the sway voltage and the threshold voltage is called overdrive. Not selected u. The resistance of the early body is a non-linear function of overdrive. Discuss, move the line is salty, (4) A near zero hour' resistance is very sensitive to overdrive ^ For large overdrive, it is relatively insensitive. Thus, in one embodiment, the near-zero overdrive surface is used as a dummy § s. 129892.doc -38- 200901206 匕' can set the overdrive voltage of the dummy memory cell to be lower than that of the typical poor memory cell, making the overdrive voltage closer to the dummy memory cell The threshold voltage. In an embodiment, the dummy memory unit can be stylized to a narrower range of marginal power than the data memory unit. For example, a dummy memory cell can have a threshold charge set near the charge neutral condition of the floating idle. The charge neutral condition of the sequence gate is a condition that there are as many protons as the electron. By tying the range of the dust cells of the dummy memory cells in the vicinity of the charge conditions of the floating cells, the effects of data storage and other problems are reduced. It is now easier to determine the dummy memory cell ... the gate resistance (i.e., the 'lower drive' state') without incurring the reliability loss of the high charge gate. In this embodiment, the dummy memory is set to have a lower overdrive voltage (as compared with the f memory memory cell) and the process of the NAND string is required to change the resistance of the NAND string. The charge neutral condition, slightly above the charge neutral condition or: the lower limit charge I below the charge neutral condition (instead of data states 0, 7 and 15) can be used with the above procedure. The foregoing embodiments of the present invention have been described for the purposes of illustration and description. JL is not intended to be exhaustive or to limit the invention to the precise form disclosed. ^ According to the above teachings, the bee eve T-^t t change and change. The embodiment is selected in order to explain the principle of the Japanese sun door, and the practical application thereof, so that other technologies familiar with the technology can be used, and the invention is applied to various kinds. Embodiments ^ are suitable for the intended invention. It is intended that the various patents are intended to best define the scope of the invention as defined in the 129892.doc-39-200901206. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view of a NAND string. Figure 2 is an equivalent circuit diagram of a NAND string. Figure 3 is a block diagram of a non-volatile memory system. 4 is a block diagram of an embodiment of a trace-memory array. Figure 5 is a block diagram depicting one embodiment of a sensing block. Figure 6 depicts a collection of examples of threshold voltage distributions. Figure 7 depicts an example of encoding data as a set of data edges associated with a threshold voltage distribution. Figure 8 shows an example of the status of a group of materials associated with a threshold voltage distribution. Figure 9 is a flow diagram depicting an embodiment of operating a non-volatile memory unit. Figure 1 is a flow diagram of one embodiment of a process for staging a non-volatile memory cell. Figure 11 is a flow chart depicting one embodiment of a process for the resistance information of a cell. Figure 12D is a flow chart depicting various embodiments of the stylized data non-volatile memory unit and the threshold voltage of the dummy non-volatile memory unit. Figure 4 is a non-volatile memory unit Flowchart of one embodiment of the process of resisting information, stylizing data non-volatile memory cells, and setting a threshold voltage of a dummy non-volatile copying unit. 129892.doc -40. 200901206, for the purpose of listing data Flowchart of one of the processes of the resistance information of the non-volatile memory unit, the non-volatile memory unit of the process, and the threshold voltage of the dummy non-volatile memory unit. FIG. 15 is a diagram for describing the non-volatile data. Flow of volatile memory cell resistance, stylized data non-volatile memory cells, and process of setting a threshold voltage of a dummy non-volatile memory cell Fig. [Main component symbol description] 100 transistor 100CG control gate 100FG floating gate 102 transistor 102CG control gate 102FG floating gate 104 transistor 104CG control gate 104FG floating gate 106 transistor 106CG control gate 106FG floating Gate 120 Select Gate 122 Select Gate 126 Bit Line Contact 128 Source Line 200 Memory Array 129892.doc -41 - 200901206 210 Memory Device 212 έ 体晶晶 or Chip 220 Control Circuit 222 State Machine / State machine circuit 224 decoder/decoder circuit 226 power control module/power control circuit 230A read/write circuit 230B read/write circuit 232 line 234 line 240A column decoder/column decoder circuit 240B column decoder /row decoder circuit 242A row decoder/row decoder circuit 242B row decoder/row decoder circuit 244 controller 300 sensing block 420 data bus 470 sensing circuit 472 bus 480 sensing module 482 bit Line Latch 490 Common Section 492 Processor 493 Input Line 129892.doc -42- 200901206 494 Data Latch 4 96 I/O interface SGD drain side select line SGS source side select line WLO ... WL63 word line WL_dO dummy word line WL_dl dummy word line

r I i 129892.doc -43 ·r I i 129892.doc -43 ·

Claims

200901206 申請專利範圍： 1. -種用於操作非揮發性儲存器之方法，其包含：判定指示非揮發性儲存次』仵之木合的一電阻特徵之貝ifl ’非揮發性儲存七一认干疋π亥巿口包括貢料非揮發性儲存几件及虛設非揮發性儲存元件；程式化该等資料非揮發性儲存元件；及基於該經判定之電阻資性儲存元件。心貝又疋或多個虛設非揮發 2 ·如請求項1之方法，其中：指不-電阻特徵之該資訊可包括絕對電阻、相對電阻、電阻改變、可用以划〜Μ+ "用以判-關於電阻之資訊的臨限電麼貝枓或可用以判定關於電阻之資訊的已储存資料.及指示-電阻特徵之該資訊可係關於所有該等資料非揮 ^性儲存π件或該等資料非揮發性儲存元件之一子隹 3·如請求項丨之方法，其中：千本。徵該設定-或多個虛設非揮發性健存元件改變該電阻特 4. 如請求項1之方法，其中：或多個虛設非揮發性儲存^改變非揮發性儲存7L件之該集合的一群電阻。 5. 如請求項1之方法，其中： =判定指示-電阻特徵之資訊包括判定經程式化之資料與一預定義資料分布的一偏離。 6. 如請求項1之方法，其中： 129892.doc 200901206 該設定一或多個虛設非揮發性儲存元件包括將一虛設非揮發性儲存元件之一臨限電壓調整至與―資料狀態相關聯的一臨限電壓範圍。 7. 如請求項1之方法，其中： ::定-或多個虛設非揮發性儲存元件包括將一虛設揮發性儲存元件之一臨限電壓調整至—類比值。 8 ·如清求項1之方法，立中今主丨6 一 . ”中μ W疋扣不—電阻特徵之資訊判定該等資料非揮發性儲存元件之至少—子集的電阻於—衫義改變的偏離，對於—給定資料非揮 ==件而言，該電阻改變係基於其他資料非揮發儲存7L件之前置及後置程式化；基於°亥判定之偏離而識別-最小偏離； “ ；X判疋之偏離而識別一最大偏離丨及二:-用於根據一誤差減小準則更改該最小偏離及該 :離的該等虛設非揮發性儲存元件甲之一或多者的條仵。 9·如請求項8之方法，其中·· 望—或多個虛設非揮發性儲存元件包括藉由將該來：整發性儲存元件中之該一或多者設定為該條件 δ°正軍發性儲存元件之該集合的電阻。 10. 如請求項8之方法，其中：該預定義改變係關於資料之—均 11. 如請求項丨之方法，其中： 129892.doc 200901206 -亥。又疋或多個虛設非揮發性儲存元件包括在完成資料非揮發性儲存元件之—第—子集之程式化之後且在完成所有資料非揮發性儲存元件之程式化之前，設定一第一虛設非揮發性儲存元件；及 °玄°又定或多個虛設非揮發性儲存元件進一步包括在完成所有資料非揮發性儲存元件之程式化之後設定一第二虛設非揮發性儲存元件。 12.如請求項1之方法，其中： 3亥叹疋-或多個虛設非揮發性儲存元件包括在完成資料非揮發性儲存元件仟之第一子集之程式化之後且在完成所有資料非揮發性儲存元件之程式化之前，設定一第一虛設非揮發性儲存元件；及該設定-或多個虛設非揮發性儲存元件進一步包括在完成資料非揮發性儲存元件之—第二子集之程式化之後 :在完成所有資料非揮發性儲存元件之程式化之前，設疋一第二虛設非揮發性儲存元件。 13 .如請求項1之方法，其中： =設定-或多個虛設非揮發性儲存元件包括在完成所有負料非揮發性儲存元件卞 < 程式化之後設定一第一虛設非揮發性儲存元件及一第二虛設非揮發性儲存元件。 14.如请求項1之方法，其中·· 該程式化包括驗證操作，該驗證操作將一第一過驅動電壓用於未選定資料非揮發性儲存元件，及將一第二過驅動電壓用於虛設資料非揮發性儲存元件，該第一過驅 129892.doc 200901206 動電壓比該第二過駆動電壓高；該設定一或多個虛設非揮發性儲存元件包括將用於該設定-或多個虛設非揮發性儲存元件之臨限電壓調整為處於在該等虛設非揮發性儲存元件之電冑中性附近的— 臨限電壓範圍内；及該方法包括讀取該等資料非揮發性儲存元件，該讀取包括將該第-過驅動電壓詩未選定諸非揮發性儲存元件’及將該第二過驅動電壓用於虛設資料非揮發性儲存元件。 15. -種經調適以用於執行如請求項！至丨*中任—項之的裝置。、 16, 一種非揮發性儲存器裝置，其包含：非揮發性儲存元件之一集合，;揮發性儲存 =括資料非揮發性儲存元件及虛設非揮發性儲存：一或多個管理電路，Α盥 ^ /、，、非揮發性儲存元件之該隼合通卜該—或多個管理電杲口之該隼厶之姓击疋知不非揮發性儲存元件之：集…群電阻特徵的資訊，該一或多個私式化該等資料非揮發性儲存之資訊而改變續算卢< 非⑼ 千藉由基於該經判定文“等虛设非揮發性儲存元件之一特性來調整非揮發性或夕者 17·如請求項16之非揮發性料器以之群電阻。電路藉…經程式化之資料與-預 ““布的―偏離來判定指示該群電阻特:之； I29892.doc 200901206 訊；及子^群電阻係關於料資料非揮發性儲存元件之至少— 1 8·如巧求項！ 6之非揮發性儲存器裝置，其中：多個虛設非揮發性儲存元件之-特性包 5夕個官理電路將一虛設非揮發臨限電>1調整至* H 赞注儲存兀件之- 圍。至與一貧料狀態相關聯的一臨限電壓範 19·如明求項丨6之非揮發性儲存器裝置，其中：該改變該-或多個虛設非揮發性儲存元件之一特性包括該#多個官理電路將一虛設非揮發性儲存元件之— 臨限電壓調整至一類比值。 20.如請求項16之非揮發性儲存器裝置，其中： / -或多個管理電路藉由判定該# f料非揮發性儲存疋件之至 > -子集的電阻改變相對於—預定義改變的偏離來判定指示—群電阻特徵之資訊，對於-給定資料非揮發性儲存元件而言，該電阻改變係基於其他資料非揮發性儲存元件之前置及後置程式化； δ亥一或多個官理電路基於該判定之偏離而識別一最小偏離及一最大偏離；及該一或多個官理電路判定一用於根據一誤差減小準則更改該最小偏離及該最大偏離的該等虛設非揮發性儲存元件中之一或多者的條件。 21 ·如晴求項2 〇之非揮發性儲存器裝置，其中： 129892.doc 200901206 該改變該一或多個虛設非揮發性儲存元件之一特性包括將一虛設非揮發性儲存元件之一臨限電壓調整至與= 條件相關聯的一臨限電壓範圍。 2 2.如凊求項2 0之非揮發性儲存器裝置，其中：該誤差減小準則包括使該最小偏離及該最大偏離相對於為料之一均勻分布關於—零改變而居中。 23. 如請求項20之非揮發性儲存器裝置，其中：該預定義改變係關於資料之一均勻分布。 24. 如請求項16之非揮發性儲存器裝置，其中：該改變該一或多個虛設非揮發性儲存元件之一特性包括在開始程式化該等資料非揮發性儲存元件之後且在完成該等資料非揮發性儲存元件之程式化之前，調整一第一虛設非揮發性儲存元件；及該改變該一或多個虛設非揮發性儲存元件之一特性進一步包括在完成該等資料非揮發性儲存元件之程式化之後調整一第二虛設非揮發性儲存元件。 2 5 ·如請求項1 6之非揮發性儲存器裝置，其中：該改變該一或多個虛設非揮發性儲存元件之一特性包括在完成該等資料非揮發性儲存元件之程式化之後調整一第一虛a又非揮發性儲存元件及一第二虛設非揮發性儲存元件。 26.如請求項1 6之非揮發性儲存器裝置，其進一步包含：資料字線，其連接至該等資料非揮發性儲存元件；及虛設字線，其連接至該等虛設非揮發性儲存元件，一 129892.doc 200901206 -虛設字線處於料資料字線之—第1，—第二虛設字線處於該等資料字線之一第二端，該改變該一或多個虛設非揮發性儲存元件之一特性包括在對該等資料字線執行了一或多個程式化過程之後執行對該第一虛設字線之一第一程式化過程及對該第二虛設字線之一第二程式化過程。 27. 如請求項16之非揮發性儲存器裝置，其中： f 邊-或多個管理電路藉由量測實際電阻資訊來判定指示一電阻特徵之資訊。 28. 如請求項16之非揮發性儲存器裝置，其中：一該-或多個管理電路藉由基於該等資料非揮發性儲存 7G件之至少-子集的f料狀態而估計對電阻之—影響來判定指示一電阻特徵之資訊。 29. 如請求項16之非揮發性儲存器裝置，其中：該-或多個管理電路使用用於未選定資料非揮發性儲存元件之—第—過驅動電壓及用於虛設資料非揮發性健存7G件之1二過驅動電|來讀取該等資料非揮發性儲存元件’該第一過驅動電壓比該第二過驅動電壓高；及該一或多個管理電路藉由將用於該一或多個虛設非揮發性儲存元件之臨限電_整為處於在該等虛設非揮發性儲存元件之電荷中性附近的—臨限電壓範圍内來改變該等虛設非揮發性儲存元件中之-或多者之-特性。 30.如請求項丨6之非揮發性儲存器裝置，其中：非揮發性儲存元件之該集合為一 NAND串上之财仙快閃記憶體器件。 129892.doc200901206 Patent Application Range: 1. A method for operating a non-volatile storage, comprising: determining a non-volatile storage period of the 』仵木一 if if if if if ' ' ' ' ' ' ' ' ' The dry 疋巿巿包括包括包括包括包括包括包括包括包括包括包括包括包括包括包括包括包括包括包括包括包括疋疋疋疋疋疋疋疋疋疋疋疋疋疋疋疋疋疋疋疋The method of claim 1 or the method of claim 1, wherein: the information of the non-resistance characteristic may include absolute resistance, relative resistance, resistance change, and may be used to draw ~ Μ + " Judgment - information about the resistance of the resistors or the stored data that can be used to determine the information about the resistance. And the indication-resistance characteristics of the information may be related to all such information non-volatile storage π pieces or One of the non-volatile storage elements of the data, such as the method of requesting items, among which: thousands. The setting is - or a plurality of dummy non-volatile storage elements are changed. The method of claim 1, wherein: or a plurality of dummy non-volatile storages ^ change a group of non-volatile storage 7L pieces of the set resistance. 5. The method of claim 1, wherein: = determining the indication-resistance characteristic information comprises determining a deviation of the stylized material from a predefined data distribution. 6. The method of claim 1, wherein: 129892.doc 200901206 the setting one or more dummy non-volatile storage elements includes adjusting a threshold voltage of a dummy non-volatile storage element to be associated with a "data state" A threshold voltage range. 7. The method of claim 1, wherein: :: or - a plurality of dummy non-volatile storage elements comprises adjusting a threshold voltage of a dummy volatile storage element to an analog value. 8 · If the method of claim 1 is used, Li Zhongjin is the main 丨6. ”中μ W疋扣—The information of the resistance characteristics determines the resistance of at least the subset of non-volatile storage elements of these data. The deviation of the change, for a given data non-swing == piece, the resistance change is based on other data non-volatile storage of 7L pieces of pre- and post-stylization; based on the deviation of the identification of the Haihai determination - the minimum deviation; "X deviation from the discriminating to identify a maximum deviation 丨 and two: - for modifying the minimum deviation according to an error reduction criterion and the strip of one or more of the dummy non-volatile storage elements opponent. 9. The method of claim 8, wherein - or - a plurality of dummy non-volatile storage elements comprises by setting the one or more of the all-round storage elements to the condition δ° The resistance of the set of hair storage elements. 10. The method of claim 8, wherein: the predefined change is related to the data - 11. The method of requesting the item, wherein: 129892.doc 200901206 - Hai. And a plurality of dummy non-volatile storage elements including a first dummy after completing the staging of the first subset of the non-volatile storage elements of the data and before completing the stylization of all of the non-volatile storage elements The non-volatile storage element; and the plurality of dummy non-volatile storage elements further includes setting a second dummy non-volatile storage element after completing the staging of all of the non-volatile storage elements. 12. The method of claim 1, wherein: 3 sighs- or a plurality of dummy non-volatile storage elements are included after completing the stylization of the first subset of data non-volatile storage elements and after completing all of the data Before the staging of the volatile storage element, setting a first dummy non-volatile storage element; and the setting - or the plurality of dummy non-volatile storage elements is further included in the second subset of the data non-volatile storage element After stylization: Set up a second dummy non-volatile storage element before completing the stylization of all non-volatile storage elements. 13. The method of claim 1, wherein: = setting - or a plurality of dummy non-volatile storage elements comprises setting a first dummy non-volatile storage element after completing all of the negative non-volatile storage elements < stylized And a second dummy non-volatile storage element. 14. The method of claim 1, wherein the stylization comprises a verify operation that uses a first overdrive voltage for the unselected data non-volatile storage component and a second overdrive voltage for the second overdrive voltage a dummy data non-volatile storage element, the first overdrive 129892.doc 200901206 dynamic voltage is higher than the second overdrive voltage; the setting one or more dummy non-volatile storage elements includes a setting for the one or more The threshold voltage of the dummy non-volatile storage element is adjusted to be within a threshold voltage range near the neutral of the virtual non-volatile storage element; and the method includes reading the non-volatile storage element of the data The reading includes using the first overdrive voltage poem to select non-volatile storage elements and using the second overdrive voltage for the dummy data non-volatile storage element. 15. - Adapted to perform as requested! As for the device of the *---------- 16. A non-volatile storage device comprising: a collection of non-volatile storage elements; a volatile storage = a non-volatile storage element and a dummy non-volatile storage: one or more management circuits,盥^ /,,, the combination of the non-volatile storage elements - or the management of the electrical outlets of the 隼厶疋疋疋疋疋疋疋疋疋疋 : : : : : : : 群群The one or more information that is privately stored in the non-volatile storage of the data changes the continuation of the continuation of the linguistics < non-(9) thousand by adjusting the non-characteristics based on the characteristics of the dummy non-volatile storage element Volatile or eve 17 • The non-volatile material of claim 16 is the resistance of the group. The circuit borrows ... the stylized data and the pre-""" deviation of the cloth to determine the resistance of the group: I29892 .doc 200901206 News; and subgroup resistance is at least about the material information non-volatile storage components - 1 8 · If you want to ask! 6 non-volatile storage device, where: a plurality of virtual non-volatile storage components - Feature Pack 5 The circuit adjusts a dummy non-volatile power limit >1 to *H. 赞兀兀临临临临临临临临临临临临临临临临临临临临临临临临临临临a volatile storage device, wherein: changing one of the characteristics of the one or more dummy non-volatile storage elements comprises: the plurality of government circuitry adjusting a threshold voltage of a dummy non-volatile storage element to a analogous value 20. The non-volatile memory device of claim 16, wherein: - or a plurality of management circuits determine by the <RTI ID=0.0># </ RTI> non-volatile storage element>-subset resistance change relative to - Deviation of the predefined change to determine the indication - the information of the group resistance characteristic, for a given data non-volatile storage element, the resistance change is based on other data non-volatile storage element pre- and post-stylization; δ One or more government circuits identify a minimum deviation and a maximum deviation based on the deviation of the determination; and the one or more government circuit determinations one for modifying the minimum deviation and the maximum deviation according to an error reduction criterion Such virtual The condition of one or more of the non-volatile storage elements. 21 · The non-volatile storage device of the second item, wherein: 129892.doc 200901206 The one or more dummy non-volatile storage elements are changed One characteristic includes adjusting a threshold voltage of a dummy non-volatile storage element to a threshold voltage range associated with the = condition. 2 2. A non-volatile memory device as claimed in claim 2, wherein: The error reduction criterion includes centering the minimum deviation and the maximum deviation with respect to one of the materials uniformly distributed with respect to - zero change. 23. The non-volatile memory device of claim 20, wherein: the predefined change system One of the data is evenly distributed. 24. The non-volatile storage device of claim 16, wherein: the changing one of the characteristics of the one or more dummy non-volatile storage elements comprises after starting to program the non-volatile storage elements of the data and after completing the Adjusting a first dummy non-volatile storage element prior to programming the non-volatile storage element; and changing the characteristic of the one or more dummy non-volatile storage elements further comprises non-volatile in completing the data A second dummy non-volatile storage element is adjusted after the staging of the storage element. The non-volatile memory device of claim 16, wherein: the changing one of the characteristics of the one or more dummy non-volatile storage elements comprises adjusting after completing the stylization of the non-volatile storage elements of the data A first virtual a non-volatile storage element and a second dummy non-volatile storage element. 26. The non-volatile storage device of claim 16, further comprising: a data word line coupled to the non-volatile storage element of the data; and a dummy word line coupled to the dummy non-volatile storage Component, a 129892.doc 200901206 - the dummy word line is in the material data word line - the first, - the second dummy word line is at the second end of one of the data word lines, the change of the one or more dummy non-volatile One of the characteristics of the storage element includes performing a first stylization process on the first dummy word line and a second one of the second dummy word line after performing one or more stylization processes on the data word line Stylized process. 27. The non-volatile memory device of claim 16, wherein: f-side or a plurality of management circuits determine information indicative of a resistance characteristic by measuring actual resistance information. 28. The non-volatile memory device of claim 16, wherein: the one or more management circuits estimate the resistance to the resistance by storing at least a subset of the 7G pieces based on the non-volatile storage of the data - Impact to determine information indicative of a resistance characteristic. 29. The non-volatile memory device of claim 16, wherein: the one or more management circuits use a first overdrive voltage for non-selected data non-volatile storage components and a non-volatile health for dummy data Storing a 1G overdrive device to read the data non-volatile storage component 'the first overdrive voltage is higher than the second overdrive voltage; and the one or more management circuits are used by The threshold of the one or more dummy non-volatile storage elements is changed to be within a threshold voltage range near the charge neutrality of the dummy non-volatile storage elements to change the dummy non-volatile storage elements In the - or more - the characteristics. 30. The non-volatile memory device of claim 6, wherein: the set of non-volatile storage elements is a wealthy flash memory device on a NAND string. 129892.doc