TW200849763A - Power transmission control device, power transmission device, electronic instrument, and non-contact power transmission system - Google Patents

Abstract

A power transmission control device provided in a power transmission device of a non-contact power transmission system includes a drive clock signal generation circuit that generates a drive clock signal that specifies a drive frequency of a primary coil, a driver control circuit that generates a driver control signal based on the drive clock signal and outputs the driver control signal to a transmission driver, a waveform adjusting circuit that outputs a waveform adjusting signal of an induced voltage signal of the primary coil, a pulse width detection circuit that receives the waveform adjusting signal and the drive clock signal and detects pulse width information relating to the waveform adjusting signal, and a control circuit that detects a change in secondary-side load based on the detected pulse width information.

Description

200849763 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種送電控制裝置、妒 _ ^ ^ q私且 迗冤裝置、電子機器 及無接點電力傳送系統等。 【先前技術】 近年來，利用電磁感應，即使無金屬部分之接點，仍可 傳送電力之無接點電力傳送（非接觸電力傳送）受到矚目，200849763 IX. Description of the Invention: [Technical Field] The present invention relates to a power transmission control device, a device, an electronic device, a contactless power transmission system, and the like. [Prior Art] In recent years, with electromagnetic induction, even without a metal part contact, the contactless power transmission (contactless power transmission) that can transmit power is attracting attention.

該無接點電力傳送之適用例，提出有行動電話及家庭用機 器（如電話機之子機）的充電等。 j接點電力傳送之先前技術如專利文獻1。該專利文獻i 係糟由所謂負載調制而實現從受電裴置(二次側)向送電裝 置（-次側）傳送資料。而後，送電裝置藉由比較器等檢測 久線圈之感應電壓，以判斷來自受電裝置之傳送資料係 「〇」或「1」。An application example of the contactless power transmission is to provide charging of a mobile phone and a home machine (such as a child of a telephone). The prior art of j-contact power transmission is as disclosed in Patent Document 1. This patent document i transmits data from the power receiving device (secondary side) to the power transmitting device (-second side) by so-called load modulation. Then, the power transmitting device detects the induced voltage of the long coil by a comparator or the like to determine whether the transmission data from the power receiving device is "〇" or "1".

^忒專利文獻1之先前技術，係藉由將感應電壓之 峰值電壓與特定之臨限值電壓比較，以檢測傳送資料。然 而’用於檢測電壓之判定的臨限值電壓亦因電源電壓及線 圈電感等之兀件常數變動而變動。因而有正確檢測二次側 之負載變動困難的問題。 [專利文獻1]日本特開2〇〇6_6〇9的號公報 【發明内容】 [發明所欲解決之問題] 藉由本發明之數個態樣’可提供可適當地檢測二次側之 負載文動的达電控制裝置、送電裝置、電子機器及無接點 128613.doc 200849763 電力傳送系統。 [解決問題之技術手段] 本發明係關於一種送電控制裝置，其設於使一次線圈與 二次線圈電磁性結合，從送電裝置對受電裝置傳送電力， 而對前述受電裝置之負載供給電力之無接點電力傳送系統 的前述送電裝置，且包含：驅動時脈產生電路，其產生規 疋削述一次線圈之驅動頻率的驅動時脈；驅動器控制電 路，其依據前述驅動時脈產生驅動器控制訊號，而對驅動 前述一次線圈之送電驅動器輪出；波形整形電路，其將前 述一次線圈之感應電壓訊號予以波形整形，而輸出波形整 形吼號；脈寬檢測電路，其接收前述波形整形訊號與前述 驅動時脈，而檢測前述波形整形訊號之脈寬資訊；及控制 電路，其依據檢測出之脈寬資訊，而檢測二次側之負載變 動。 本發明係脈寬檢測電路接收一次線圈之感應電壓訊號的 波形整形訊號，與規定一次線圈之驅動頻率（交流頻率）的 驅動時脈，而檢測脈寬資訊。而後，依據該脈寬資訊檢測 二次側之負載變動。藉此，即使不採用個別地檢測電壓及 電流，以其相位差作判定之方法，而將電壓波形予以簡單 之類比波形整形，仍可藉由數位電路處理而穩定地檢測二 次側之負載變動。因此，可以簡化之結構適當地檢測二次 側的負載變動。 此外，本發明亦可前述控制電路依據檢測出之脈寬資 訊，而檢測前述受電裝置藉由負載調制而傳送之資料。 128613.doc 200849763 藉此可依據脈寬資訊適當地檢測受電裝置傳送之資 料’而可實現與受電裝置之間高穩定性的資料轉送。 此外，本發明亦可前述脈寬檢測電路藉由計測脈究期 間，而檢測脈寬資訊’該脈寬期間係從前述驅動時脈從非 主動之電μ位準變成主動之㈣位準的第—點，至前述波 形整形訊號從主動之電壓位準變成非主動之電壓位準的第 二點之期間者。The prior art of Patent Document 1 detects the transmitted data by comparing the peak voltage of the induced voltage with a specific threshold voltage. However, the threshold voltage for determining the voltage is also varied by the variation of the component constant such as the power supply voltage and the coil inductance. Therefore, it is difficult to correctly detect the load variation on the secondary side. [Patent Document 1] Japanese Patent Laid-Open Publication No. Hei. No. Hei. No. Hei. No. 2-6 〇 的 【 【 【 【 【 【 【 发明 发明 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉Dynamic control device, power transmission device, electronic equipment and contactless 128613.doc 200849763 Power transmission system. [Technical means for solving the problem] The present invention relates to a power transmission control device that is provided to electromagnetically combine a primary coil and a secondary coil, and to transmit power from a power transmitting device to a power receiving device, and to supply power to a load of the power receiving device. The power transmitting device of the contact power transmission system includes: a driving clock generating circuit that generates a driving clock that regulates a driving frequency of the primary coil; and a driver control circuit that generates a driver control signal according to the driving clock. And driving the power transmission driver for driving the first coil; the waveform shaping circuit waveform shaping the induced voltage signal of the primary coil, and outputting a waveform shaping nick; the pulse width detecting circuit receiving the waveform shaping signal and the driving And detecting a pulse width information of the waveform shaping signal; and a control circuit detecting the load variation on the secondary side according to the detected pulse width information. According to the invention, the pulse width detecting circuit receives the waveform shaping signal of the induced voltage signal of the primary coil, and the driving clock of the driving frequency (AC frequency) of the primary coil, and detects the pulse width information. Then, the load variation on the secondary side is detected based on the pulse width information. Thereby, even if the voltage and current are individually detected, and the phase difference is used as the determination method, and the voltage waveform is simply shaped into a waveform, the load variation on the secondary side can be stably detected by the digital circuit processing. . Therefore, the structure of the simplification can appropriately detect the load fluctuation on the secondary side. Furthermore, in the present invention, the control circuit may detect the data transmitted by the power receiving device by load modulation based on the detected pulse width information. 128613.doc 200849763 Thereby, it is possible to appropriately detect the data transmitted by the power receiving device based on the pulse width information, and to realize high-speed data transfer with the power receiving device. In addition, in the present invention, the pulse width detecting circuit may detect the pulse width information by measuring the pulse period, and the pulse width period is changed from the inactive electric μ level to the active (four) level. - Point to the period during which the aforementioned waveform shaping signal changes from the active voltage level to the second point of the inactive voltage level.

藉此，僅藉由計測第一、第二點間之脈寬期間，即可檢 測脈寬資訊，可以簡化之結構檢測二次側之負載變動。 此外，本發明亦可前述脈寬檢測電路包含計數器，其在 前述脈寬期間進行計數值之增量或減量，並依據獲得之計 數值計測前述脈寬期間之長度。 藉此’可依據計數器數位性正確地計測脈寬期間。 此外，本發明亦可前述脈寬檢測電路包含賦能訊號產生 電路，、其接收前述波形整形訊號與前述驅動時脈，而產生 在别述脈寬期間成為主勤夕秘At % $ . 乃王動之賦此汛唬，前述計數器在前述 賦能訊號係主動時，進行計數值之增量或減量。 糟此’僅藉由產生賦能訊號’即可控制計數脈寬期間用 之計數處理，而可簡化處理。 此外’本發明亦可前述賦能訊號產生電路包含正反哭電 路’其將前述驅動時脈輪入至其時脈端子，將高電㈣電 源或低電位側電源之電壓輸入至其資料端子，於前述波形 整形訊號係主動時，進行重設或設定。Thereby, the pulse width information can be detected only by measuring the pulse width period between the first and second points, and the load variation on the secondary side can be simplified by the structure detection. Furthermore, in the present invention, the pulse width detecting circuit may include a counter that performs an increment or a decrement of the count value during the pulse width, and measures the length of the pulse width period based on the obtained count value. Thereby, the pulse width period can be accurately measured in accordance with the counter digitality. In addition, the pulse width detecting circuit of the present invention may further include an energizing signal generating circuit that receives the waveform shaping signal and the driving clock, and generates a master time at least during the pulse width. In this case, the counter performs increment or decrement of the count value when the energizing signal is active. In spite of this, the counting process for counting the pulse width period can be controlled only by generating the energizing signal, and the processing can be simplified. In addition, the present invention may also be characterized in that the energizing signal generating circuit includes a forward and reverse crying circuit that inputs the driving clock to the clock terminal and inputs the voltage of the high (four) power source or the low potential side power source to the data terminal thereof. Reset or set when the waveform shaping signal is active.

It此’可以僅設置正反哭雷政 反斋電路之間化的結構而實現賦能 128613.doc 200849763 訊號之產生。 此外，本發明亦可前述波形整形電路包含比較器，其將 一次線圈之感應電壓訊號輸入至其非反轉輸入端子，將賦 予之設定電壓輸入至其反轉輸入端子。 藉此，可藉由控制輸入比較器之反轉輸入端子的設定電 ^ 壓，而提高負載變動之檢測精度。此外，使用此種比較器 Η雖亦可此波形整形訊號之變化時點對驅動時脈之變化 日守點延遲，不過，藉由使用上述之正反器電路，因為在該 f 延遲期間亦進行計數處理，所以可獲得正確之計數值。 此外，本發明亦可前述脈寬檢測電路包含：計數值保持 電路，其保持來自前述計數器之計數值；及輸出電路，其 比較此次保持於前述計數值保持電路之計數值與前次保持 之计數值’而輸出大的一方之計數值。 藉此，可抑制因雜音等造成脈寬期間之變動，可實現穩 定之脈寬檢測。此外，亦可輕易地與振幅檢測方法組合。 〔此外，本發明亦可前述脈寬檢測電路包含：計數值保持 電路，其保持來自前述計數器之計數值；及輸出電路，其 輸出保持於前述計數值保持電路之數個計數值的平均值。 即使如此，仍可抑制因雜音等造成脈寬期間之變動，而 可實現穩定之脈寬檢測。 此外，本發明亦可包含··振幅檢測電路，其檢測前述一 -人線圈之感應電壓訊號的振幅資訊；A/D轉換電路，其進 行核測出之4述振幅資訊的A/D轉換；第一閂鎖電路，其 閂鎖來自前述A/D轉換電路之資料；及第二閂鎖電路，其 128613.doc 200849763 閃鎖來自前述脈寬檢測電路之資料；前述第二閃鎖電路在 與刖述第-閂鎖電路之閂鎖時點同步之時點，閂鎖來自前 述脈寬檢測電路之資料。 藉此，可在相同時點閂鎖藉由脈寬檢測而獲得之資料與 藉由振幅檢測而獲得之資料。藉此，可保持脈寬檢測與振 幅檢測間之電路互換性，而可簡化控制電路之程序處理及x 判斷處理。 此外，本發明係關於一 一項記載之送電控制裝置 而供給至前述一次線圈。 此外，本發明係關於一 裝置。 f 種送電裝置，其包含：上述任何 ’及送電部，其產生交流電壓， 種電子機器，其包含上述之送電 此外’本發明係關於—種無接點電力傳送系統，且包人 送電裝置與受電裝置，使—次線圈與二次線圈電磁^ 合，從财述送電裝置對前述受電裝置傳送電力，而對前述 受電裝置之負載供給電力’且前述受電裝置包含 部，其將前述二次線圈之感應電愿轉換成直流電壓；及 載調制部，其從前述受電裝置傳送資料至前述送電裳置 時，因應傳送資料而使負載可變地變化；前述送電裝置勺 含：驅動時脈產生電路’其產生規定前述一次線圈：驅： :員率的驅動時脈；驅動器控制電路，其依據前述 產生驅動器控制訊號，而對驅動前述—次線圈之送電键 ;輸出：波形整形電路，其將前述-次線圈之感應電壓訊 〜予以波形整形，而輸出波形整形訊號；m寬檢測電路， 128613.doc 200849763 其：收前述波形整形訊號與前述驅動時脈，而 形整形訊號之脈寬資訊；及控 呔波 n 制電路，其依據檢測出之脈 見《汛，而檢測二次側之負载變動。 本發明係關於一種送電控制裝置，其設於使一次線圈盘 -次線圈電磁性結合’從送電裝置對受電裝置傳送電力， 而對前述受電裝置之負載供給電力之無接點電力傳送系統 的刖述达電裝置，i包含：驅動時脈產生電路其產生規It can be used only to set the structure of the positive and negative crying Leizheng anti-fasting circuit to achieve the empowerment 128613.doc 200849763 signal generation. Furthermore, in the present invention, the waveform shaping circuit may include a comparator that inputs the induced voltage signal of the primary coil to its non-inverting input terminal, and inputs the given set voltage to its inverted input terminal. Thereby, the detection accuracy of the load variation can be improved by controlling the set voltage of the inverting input terminal of the input comparator. In addition, although the comparator is used, the change of the waveform shaping signal can also delay the change of the driving clock, but by using the above-mentioned flip-flop circuit, since the counting is also performed during the f-delay period. Processing, so you can get the correct count value. In addition, the pulse width detecting circuit of the present invention may further include: a count value holding circuit that holds a count value from the counter; and an output circuit that compares the count value held by the count value holding circuit and the previous hold. Count value ' and output the count value of the larger one. Thereby, fluctuations in the pulse width period due to noise or the like can be suppressed, and stable pulse width detection can be realized. In addition, it can be easily combined with the amplitude detection method. Further, in the present invention, the pulse width detecting circuit may include: a count value holding circuit that holds a count value from the counter; and an output circuit whose output is maintained at an average value of a plurality of count values of the count value holding circuit. Even in this case, it is possible to suppress fluctuations in the pulse width period due to noise or the like, and to realize stable pulse width detection. In addition, the present invention may further comprise: an amplitude detecting circuit for detecting amplitude information of the induced voltage signal of the one-person coil; and an A/D converting circuit for performing A/D conversion of the amplitude information detected by the core; a first latch circuit latching data from the A/D conversion circuit; and a second latch circuit having a 128613.doc 200849763 flash lock data from the pulse width detecting circuit; the second flash lock circuit being When the latch-time of the first latch circuit is synchronized, the latch is from the data of the pulse width detecting circuit. Thereby, the data obtained by the pulse width detection and the data obtained by the amplitude detection can be latched at the same time point. Thereby, the circuit interchangeability between the pulse width detection and the amplitude detection can be maintained, and the program processing and the x judgment processing of the control circuit can be simplified. Further, the present invention is supplied to the primary coil in accordance with the power transmission control device described in the first aspect. Furthermore, the invention relates to a device. And a power transmission device comprising: any of the above and a power transmission unit that generates an AC voltage, and the electronic device includes the power transmission described above. Further, the present invention relates to a contactless power transmission system, and the power transmission device and the power transmission device are The power receiving device electromagnetically couples the secondary coil and the secondary coil, and transmits power to the power receiving device from the power transmitting device, and supplies power to the load of the power receiving device, and the power receiving device includes a secondary coil. The induction power is converted into a DC voltage; and the load modulation unit variably changes the load when the data is transmitted from the power receiving device to the power transmission skirt; the power transmission device spoon includes: a drive clock generation circuit 'The production of the aforementioned primary coil: drive:: the drive rate of the rate; the driver control circuit, which generates the driver control signal according to the foregoing, and drives the power transmission key of the aforementioned secondary coil; the output: the waveform shaping circuit, which will - Inductive voltage signal of the secondary coil ~ waveform shaping, output waveform shaping signal; m width detection circuit, 128613 .doc 200849763: receiving the waveform shaping signal and the driving clock, and shaping the pulse width information of the signal; and controlling the c-wave circuit, according to the detected pulse, detecting the load on the secondary side change. The present invention relates to a power transmission control device which is provided in a contactless power transmission system in which a primary coil disk-secondary coil is electromagnetically coupled to transmit power to a power receiving device from a power transmitting device and supply power to a load of the power receiving device. The electrical device, i includes: a driving clock generating circuit

定前述一次線圈之驅動頻率的驅動時脈；驅動器控制電 路，其依據前述驅動時脈產生驅動器控制訊號，而對驅動 前述一次線圈之送電驅動器輸出；波形整形電路，其將前 述一次線圈之感應電壓訊號予以波形整形，而輸出波形整 形訊號；脈寬檢測電路，其接收前述波形整形訊號與前述 驅動時脈，而檢測前述波形整形訊號之脈寬資訊；及控制 電路’其依據檢測出之脈見貨訊’而控制前述送電控制裝 置。 本發明係關於一種送電裝置，其包含：上述之送電控制 裝置；及送電部，其產生交流電壓，而供給至前述一次線 圈。 本發明係關於一種電子機器，其包含上述之送電裝置。 本發明係關於一種無接點電力傳送系統，其包含送電裝 置與受電裝置，使一次線圈與二次線圈電磁性結合，從送 電裝置對受電裝置傳送電力，而對前述受電裝置之負載供 給電力；且前述送電裝置係上述之送電裝置。 【實施方式】 128613.doc 200849763 以下，詳細說明本發明適合之實施形態。另外，以下說 明之本實施形態並非不當地限定記載於申請專利範圍的本 發明之内容者’本實施形態說明之全部結構作為本發明之 解決手段，不限定為必須者。 1.電子機器 圖1 (A)顯示適用本實施形態之無接點電力傳送方法的電 子機器之例。1個電子機器之充電器500(托架（cradle))包含 送電裝置10。此外，1個電子機器之行動電話51〇包含受電 裝置40。此外，行動電話5 1 0包含：LCD等之顯示部5 i 2、 以按鈕等構成之操作部514、麥克風516(聲音輸入部）、喇 °八518(聲音輸出部）及天線520。 充電器500中經由AC轉接器502供給電力，該電力藉由 無接點電力傳送，而從送電裝置1〇送電至受電裝置4〇。藉 此，將行動電話510之電池充電，可使行動電話51〇内之裝 置動作。 另外’適用本實施形態之電子機器不限定於行動電話 510。如可適用於手錶、無繩（cordless)電話機、刮鬍刀、 電動牙刷、手腕電腦（wrist computer)、掌上終端機、攜帶 式資訊終端或是電動腳踏車等各種電子機器。 如模式地顯示於圖1(B)，自送電裝置1〇向受電裝置4〇之 電力傳送，係藉由使設於送電裝置10側之一次線圈L1 (送 電線圈）與設於受電裝置40側之二次線圈L2(受電線圈）電磁 性結合’形成電力傳送變壓器（transformer)而實現。藉此 可以非接觸傳送電力。 128613.doc -12- 200849763 2·送電裝置、受電裝置 圖2顯示本貫施形態之送電裝置丨〇、送電控制裝置π、 文電裹置40及受電控制裝置5〇之結構例。圖i(A)之充電器 500等的送電側之電子機器至少包含圖2之送電裝置1〇。此 外，行動電話510等之受電側的電子機器至少包含受電裝 . 置4〇與負載90(主要負载）。而後，藉由圖2之結構，實現使 ‘ 一次線圈1^1與二次線圈L2電磁性結合，而自送電裝置1〇對 文電裝置40傳送電力，並從受電裝置4〇之電壓輸出節點 Γ NB7對貞載9G供給電力（電壓VOUT)的無接點電力傳送（非 接觸電力傳送）系統。 运電裝置10(送電模組、一次模組）可包含··一次線圈 L1、送電部12、電壓檢測電路14、顯示部16及送電控制裝 置20。另外，送電裝置1〇及送電控制裝置2〇不限定於圖: 之結構’而可實施省略其構成要素之一部分(如顯示部、a driving clock for determining a driving frequency of the first coil; a driver control circuit for generating a driver control signal according to the driving pulse to drive a power transmission driver output of the first coil; and a waveform shaping circuit for inducing a voltage of the first coil The signal is waveform shaped, and the output waveform shaping signal; the pulse width detecting circuit receives the waveform shaping signal and the driving clock, and detects the pulse width information of the waveform shaping signal; and the control circuit is based on the detected pulse The cargo message 'controls the aforementioned power transmission control device. The present invention relates to a power transmission device comprising: the power transmission control device described above; and a power transmission unit that generates an alternating current voltage and supplies the power to the primary coil. The present invention relates to an electronic device comprising the above-described power transmitting device. The present invention relates to a contactless power transmission system including a power transmitting device and a power receiving device for electromagnetically coupling a primary coil and a secondary coil, and transmitting power from the power transmitting device to the power receiving device, and supplying power to a load of the power receiving device; Further, the power transmitting device is the power transmitting device described above. [Embodiment] 128613.doc 200849763 Hereinafter, a preferred embodiment of the present invention will be described. In addition, the present embodiment of the present invention is not limited to the scope of the present invention described in the claims. The entire configuration described in the present embodiment is not limited thereto. 1. Electronic Apparatus Fig. 1 (A) shows an example of an electronic apparatus to which the contactless power transmission method of the present embodiment is applied. A charger 500 (cradle) of an electronic device includes a power transmitting device 10. Further, the mobile phone 51A of one electronic device includes the power receiving device 40. Further, the mobile phone 510 includes a display unit 5 i such as an LCD, an operation unit 514 composed of a button or the like, a microphone 516 (sound input unit), a karaoke 518 (sound output unit), and an antenna 520. The charger 500 supplies electric power via the AC adapter 502, and the electric power is transmitted from the power transmitting device 1 to the power receiving device 4A by the contactless power transmission. By this, the battery of the mobile phone 510 is charged, and the device in the mobile phone 51 can be operated. Further, the electronic device to which the present embodiment is applied is not limited to the mobile phone 510. For example, it can be applied to watches, cordless phones, razors, electric toothbrushes, wrist computers, handheld terminals, portable information terminals or electric bicycles. As shown in FIG. 1(B), the power transmission from the power transmitting device 1 to the power receiving device 4 is performed by the primary coil L1 (power transmitting coil) provided on the power transmitting device 10 side and the power receiving device 40 side. The secondary coil L2 (receiving coil) is electromagnetically coupled to form a power transfer transformer. This allows non-contact transmission of power. 128613.doc -12- 200849763 2. Power transmission device and power receiving device Fig. 2 shows a configuration example of the power transmitting device 丨〇, the power transmission control device π, the power supply package 40, and the power receiving control device 5 of the present embodiment. The electronic device on the power transmitting side of the charger 500 or the like of Fig. i(A) includes at least the power transmitting device 1 of Fig. 2. Further, the electronic device on the power receiving side of the mobile phone 510 or the like includes at least a power receiving device and a load 90 (main load). Then, by the structure of FIG. 2, the primary coil 1^1 and the secondary coil L2 are electromagnetically coupled, and the self-power transmitting device 1 transmits power to the electrical device 40, and the voltage output node from the power receiving device 4 NB NB7 is a contactless power transmission (contactless power transmission) system that supplies power (voltage VOUT) to 9G. The power transmission device 10 (power transmission module, primary module) may include a primary coil L1, a power transmission unit 12, a voltage detection circuit 14, a display unit 16, and a power transmission control device 20. Further, the power transmitting device 1A and the power transmission control device 2 are not limited to the configuration of the figure: and a part of the constituent elements (such as the display unit,

L 電麼檢測電路），或追加其他構成要素，或是變更連接關 係荨之各種改良。 运電部12於電力傳送時產生特定頻率之交流電壓，於資 料轉达時’因應貧料產生頻率不同之交流電壓，而供給至 -次線圈L1。具體而言，如圖3(A)所示，如對受電裝置糾 :送資料「V」情況下’產生頻率fl之交流電壓，於傳送 貝枓「〇」情況下’產生頻率f2之交流電壓。該送電部 :包含驅動-次線圈L1之一端的第—送電驅動器、驅動一 次線圈L1之另—端的第二送電驅動器、及與-次線圈L1_ 起構成共振電路之至少1個電容器。 128613.doc -13- 200849763 而後，送電部12包含之第一、第二送電驅動器如分別係 藉由電力MOS電晶體構成之反相電路（緩衝電路），且藉由 送電控制裝置20之驅動器控制電路26控制。 一次線圈L1 (送電側線圈）與二次線圈L2(受電側線圈）電 磁結合，而形成電力傳送用變壓器。如需要傳送電力時， 如圖1(A)、圖1(b)所示，在充電器500之上放置行動電話 5 1 〇 ’形成一次線圈l 1之磁束通過二次線圈乙2之狀態。另 外’不需要傳送電力時，物理性分離充電器5〇〇與行動電 話51〇’而形成一次線圈L1之磁束不通過二次線圈L2之狀 態。 電壓私測電路14係檢測一次線圈l 1之感應電壓的電路， 如包含··電阻RA1、RA2，及設於RA1與RA2之連接節點 NA3與GND(廣義而言，係低電位側電源）之間的二極體 DA1 〇 該電壓檢測電路14作為一次線圈L1之線圈端電壓訊號的 半波整流電路之功能。而後，藉由將—次線圈以之線圈端 電壓以電阻RA1、RA2分壓而獲得之訊號pHIN(感應電壓 Λ唬、半波整流訊號）輸入送電控制裝置之波形整形電 路 亦即電阻RA1、RA2構成電壓分割電路（電阻分割 電路）’而;k其電壓分割節點ΝΑ3輸出訊號ρΗΐΝ。 頌示邛1 6係使用顏色及影像等顯示無接點電力傳送系統 之各種狀態（電力傳送中、ID認證等）者，如藉由led及 LCD等來實現。 送電控制裝置20係進行送電裝置1()之各種控制的裝置， 128613.doc 200849763 可藉由積體電路裝置（IC)等來實現。該送電控制裝置2〇可 包含：控制電路22(送電侧）、振盪電路24、驅動時脈產生 電路25、驅動器控制電路26、波形整形電路^及脈寬檢測 電路33。 控制電路22(控制部）係進行送電裝置丨〇及送電控制裝置 20之控制者，如可藉由閘極陣列及微電腦等來實現。具體 而言，控制電路22係進行電力傳送、負載檢測、頻率調 制、雜質檢測或裝卸檢測等時需要的各種程序控制及判定 處理。 振盪電路24如藉由水晶振盪電路而構成，產生一次側之 時脈。驅動時脈產生電路25產生規定驅動頻率之驅動時 脈。而後，驅動器控制電路26依據該驅動時脈及來自控制 電路22之頻率設定訊號等，產生希望頻率之控制訊號，並 輸出至送電部12之第一、第二送電驅動器，以控制第一、 第二送電驅動器。 波形整形電路32將一次線圈L1之感應電壓訊號PHIN(線 圈端電壓）予以波形整形，而輸出波形整形訊號。具體而 言，如訊號PHIN超過賦予之臨限值電壓時，輸出形成主 動（如Η位準）之方形波（矩形波）的波形整形訊號。 脈I檢測電路3 3檢測一次線圈l 1之感應電壓訊號phin 的脈I資訊（線圈端電壓波形為賦予之設定電壓以上的脈 寬期間）。具體而言，係接收來自波形整形電路32之波形 整形訊號與來自驅動時脈產生電路25之驅動時脈，藉由檢 測波形整形訊號之脈寬資訊，而檢測感應電壓訊號ρΗΙΝ 128613.doc 200849763 之脈寬資訊。 控制電路22依據脈寬檢測電路33檢測出之脈 士 制送電控制裝置20。如依據脈寬資訊檢測二次側 ： 置40側）之負載變動（負載之高低）。具體而言，進行資^ (負載）檢測、雜質（金屬）檢測、裝卸（取出）檢測等。枓 感應電壓訊號之脈寬資訊的脈寬期間係因應二次側之負卩’、 變動而變化。控制電路22依據藉由該脈寬期間（藉由計= 脈寬期間而獲得之計數值）檢測二次側之負載變動。1 此，如圖3(B)所示，受電裝置40之負載調制部46藉由負^ 調制而傳送資料時，可檢測該傳送資料。 受電裝置40(受電模組、二次模組）可包含：二次線圈 L2、受電部42、負載調制部46、饋電控制部48及受電控制 裝置50。另外，受電裝置4〇及受電控制裝置5〇不限定於圖 2之結構，可實施省略其構成要素之一部分，或是追加其 他之構成要素，或是變更連接關係等之各種改良。 受電部42將二次線圈L2之交流的感應電壓轉換成直流電 壓。該轉換藉由受電部42包含之整流電路43來進行。該整 流電路43包含二極體DB1〜DB4。二極體DB1設於二次線圈 L2之一端的節點NB1與直流電壓VDC的產生節點NB3之 間，DB2設於節點NB3與二次線圈L2之另一端的節點>^2 之間，DB3設於節點NB2與VSS之節點NB4之間，DB4設於 節點NB4與NB1之間。 受電部42之電阻RBI、RB2設於節點NB1與NB4之間。而 後，將節點NB1、NB4間之電壓藉由電阻RBI、RB2予以分 128613.doc -16- 200849763 壓而獲得之訊號CCMPI輸入受電控制裝置50之頻率檢測電 路60 〇 受電部42之電容器CB1及電阻RB4、RB5設於直流電壓 VDC之節點NB3與VSS的節點NB4之間。而後，將節點 NB3、NB4間之電壓藉由電阻RB4、RB5予以分壓而獲得之 訊號ADIN輸入受電控制裝置5 0之位置檢測電路5 6。L electric detection circuit), or add other components, or change the connection between the various improvements. The power transmission unit 12 generates an AC voltage of a specific frequency at the time of power transmission, and supplies it to the secondary coil L1 in response to the AC voltage having a different frequency due to the lean material. Specifically, as shown in FIG. 3(A), if the power receiving device is corrected: when the data "V" is sent, the AC voltage of the frequency fl is generated, and in the case of the transmission "枓", the AC voltage of the frequency f2 is generated. . The power transmission unit includes a first power transmission driver including one end of the drive-secondary coil L1, a second power transmission driver that drives the other end of the primary coil L1, and at least one capacitor that constitutes a resonance circuit with the secondary coil L1_. 128613.doc -13- 200849763 Then, the first and second power transmitting drivers included in the power transmitting unit 12 are respectively inverted circuits (snubber circuits) constituted by power MOS transistors, and are controlled by the driver of the power transmitting control device 20 Circuit 26 controls. The primary coil L1 (power transmitting side coil) is electromagnetically coupled to the secondary coil L2 (power receiving side coil) to form a power transmission transformer. When it is necessary to transmit power, as shown in Fig. 1(A) and Fig. 1(b), a mobile phone 5 1 〇 ' is placed on the charger 500 to form a state in which the magnetic flux of the primary coil l 1 passes through the secondary coil B 2 . Further, when it is not necessary to transmit power, the charger 5〇〇 and the mobile phone 51〇' are physically separated to form a state in which the magnetic flux of the primary coil L1 does not pass through the secondary coil L2. The voltage private test circuit 14 is a circuit for detecting the induced voltage of the primary coil l1, and includes the resistors RA1 and RA2, and the connection nodes NA3 and GND (generally, the low potential side power supply) provided at RA1 and RA2. The intermediate diode DA1 〇 the voltage detecting circuit 14 functions as a half-wave rectifying circuit of the coil terminal voltage signal of the primary coil L1. Then, the signal pHIN (induction voltage Λ唬, half-wave rectified signal) obtained by dividing the coil voltage of the primary coil by the resistance of the coils R1 and RA2 is input to the waveform shaping circuit of the power transmission control device, that is, the resistors RA1 and RA2. A voltage dividing circuit (resistor dividing circuit) is formed; and k its voltage dividing node ΝΑ3 outputs a signal ρΗΐΝ.邛1 6 is a display of various states (power transmission, ID authentication, etc.) of the contactless power transmission system using color, video, etc., by LED, LCD, etc. The power transmission control device 20 is a device that performs various controls of the power transmission device 1 (), and can be realized by an integrated circuit device (IC) or the like. The power transmission control device 2A includes a control circuit 22 (power transmission side), an oscillation circuit 24, a drive clock generation circuit 25, a driver control circuit 26, a waveform shaping circuit, and a pulse width detecting circuit 33. The control circuit 22 (control unit) is a controller of the power transmitting device 丨〇 and the power transmission control device 20, and can be realized by a gate array, a microcomputer, or the like. Specifically, the control circuit 22 performs various program control and determination processes required for power transmission, load detection, frequency modulation, impurity detection, or detachment detection. The oscillation circuit 24 is constituted by a crystal oscillation circuit, and generates a clock on the primary side. The drive clock generating circuit 25 generates a drive clock for specifying the drive frequency. Then, the driver control circuit 26 generates a control signal of a desired frequency according to the driving clock and the frequency setting signal from the control circuit 22, and outputs the control signal to the first and second power transmitting drivers of the power transmitting unit 12 to control the first and the second Two power transmission drivers. The waveform shaping circuit 32 waveform-shapes the induced voltage signal PHIN (the coil end voltage) of the primary coil L1 to output a waveform shaping signal. Specifically, if the signal PHIN exceeds the threshold voltage given, the waveform shaping signal of the square wave (rectangular wave) forming the active (e.g., Η level) is output. The pulse I detecting circuit 3 3 detects the pulse I information of the induced voltage signal phin of the primary coil l1 (the coil terminal voltage waveform is a pulse width period equal to or higher than the set voltage). Specifically, the waveform shaping signal from the waveform shaping circuit 32 and the driving clock from the driving clock generating circuit 25 are received, and the pulse width information of the waveform shaping signal is detected to detect the induced voltage signal ρΗΙΝ 128613.doc 200849763 Pulse width information. The control circuit 22 is based on the pulse transmission control device 20 detected by the pulse width detecting circuit 33. For example, according to the pulse width information, the load on the secondary side (40 side) is monitored (load level). Specifically, the detection of the load (load), the detection of impurities (metal), the detection of loading and unloading (extraction), and the like are performed.脉 The pulse width period of the pulse width information of the induced voltage signal changes in response to the negative 卩' and fluctuation of the secondary side. The control circuit 22 detects the load fluctuation on the secondary side in accordance with the pulse width period (the count value obtained by counting the pulse width period). 1. As shown in Fig. 3(B), when the load modulation unit 46 of the power receiving device 40 transmits data by negative modulation, the transmission data can be detected. The power receiving device 40 (power receiving module, secondary module) may include a secondary coil L2, a power receiving unit 42, a load modulation unit 46, a power feeding control unit 48, and a power receiving control device 50. Further, the power receiving device 4A and the power receiving control device 5A are not limited to the configuration of Fig. 2, and various modifications may be made to omit one of the constituent elements, or to add other constituent elements, or to change the connection relationship. The power receiving unit 42 converts the induced voltage of the alternating current of the secondary coil L2 into a direct current voltage. This conversion is performed by the rectifier circuit 43 included in the power receiving unit 42. The rectifying circuit 43 includes diodes DB1 to DB4. The diode DB1 is disposed between the node NB1 at one end of the secondary coil L2 and the generating node NB3 of the DC voltage VDC, and DB2 is disposed between the node NB3 and the node at the other end of the secondary coil L2 > Between node NB2 and node NB4 of VSS, DB4 is provided between nodes NB4 and NB1. The resistors RBI and RB2 of the power receiving unit 42 are provided between the nodes NB1 and NB4. Then, the voltage between the nodes NB1 and NB4 is divided by the resistors RBI and RB2 by a voltage of 128613.doc -16-200849763. The signal CCMPI is input to the frequency detecting circuit 60 of the power receiving control device 50, and the capacitor CB1 and the resistor of the power receiving unit 42 are received. RB4 and RB5 are provided between the node NB3 of the DC voltage VDC and the node NB4 of the VSS. Then, the signal ADIN is input to the position detecting circuit 56 of the power receiving control device 50 by dividing the voltage between the nodes NB3 and NB4 by the resistors RB4 and RB5.

ϋ 負載調制部46進行負載調制處理。具體而言，從受電裝 置40傳送希望之資料至送電裝置1〇時，因應傳送資料，使 負載調制部46(二次側）之負載可變地變化，如圖3(B)所示 地使一次線圈L1之感應電壓的訊號波形變化。為此，負載 調制部46包含串聯地設於節點NB3、NB4之間的電阻 RB3、及電晶體丁扪⑺型之CM〇s電晶體）。該電晶體丁扪 精由來自受電控制裝置5〇之控制電路52的訊號p3Q實施接 〔、斷開控制。而後，接通、斷開控制電晶體，進行 負載調制時，饋電控制部48之電晶體ΤΒι、tb2斷開，而 形成負載90不電性連接於受電裝置4〇之狀態。 如圖3(B)所示，為了傳送資料 」μ 一-人取成低 負載（阻抗大）情況下，訊號P3Q形成[位準，電晶體τβ3斷 開。藉此，負載調制部46之負載形成大致無限大(益負 載）。另外，為了傳送資料「！」而將二次側形成高負載（阻 抗小）情況下，訊號P3Q形成Η位準，而電晶體τβ3接通。 藉此’負載調制部46之負載形成電阻刪（高負載）。 饋電控制部48控制對負載9Q之電力的饋電。調 整以整流電路43轉換而獲得之直流電請C的電壓位準調 128613.doc -17- 200849763 產生電源電壓VD5(如5 V)。受電控制裝置5〇如供給該電源 電塵VD5而動作。 ' 電晶體ΤΒ2(Ρ型之CM0S電晶體）藉由來自受電控制裝置 50之控制電路52的訊號p1q而控制。具體而言，I電晶體 TB2於ID認證完成（確立），進行通常之電力傳送情況下接 通，而於負載調制時等斷開。负载 The load modulation unit 46 performs load modulation processing. Specifically, when the desired information is transmitted from the power receiving device 40 to the power transmitting device 1 , the load of the load modulation unit 46 (secondary side) is variably changed in response to the transfer of the data, as shown in FIG. 3(B). The signal waveform of the induced voltage of the primary coil L1 changes. Therefore, the load modulation unit 46 includes a resistor RB3 provided in series between the nodes NB3 and NB4, and a CM〇s transistor of a transistor type (7). The transistor Dc is controlled by the signal p3Q from the control circuit 52 of the power receiving control device 5, and is disconnected. Then, when the control transistor is turned on and off, and the load modulation is performed, the transistors ΤΒ1, tb2 of the feed control unit 48 are turned off, and the load 90 is not electrically connected to the power receiving device 4''. As shown in Fig. 3(B), in order to transmit data "μ一-人为为low load (high impedance), the signal P3Q forms [level, and the transistor τβ3 is turned off. Thereby, the load of the load modulation unit 46 is formed to be substantially infinite (benefit). Further, in the case where the secondary side is formed with a high load (small impedance) in order to transmit the data "!", the signal P3Q forms a Η level, and the transistor τβ3 is turned on. Thereby, the load of the load modulation unit 46 forms a resistor (high load). The feed control unit 48 controls the feeding of the electric power to the load 9Q. Adjust the voltage level obtained by converting the rectifier circuit 43 to the voltage level of the C. 128613.doc -17- 200849763 Generate the power supply voltage VD5 (such as 5 V). The power receiving control device 5 operates by supplying the power source dust VD5, for example. The transistor ΤΒ 2 (the CMOS type CMOS transistor) is controlled by the signal p1q from the control circuit 52 of the power receiving control device 50. Specifically, the I transistor TB2 is completed (established) after ID authentication, and is turned on in the case of normal power transmission, and is turned off during load modulation or the like.

電晶體TB1(P型之CM0S電晶體）藉自來自輪出保證電路 54的訊號P4Q而控制。具體而言，於出認證完成，進行通 常之電力傳送情況下接通。另外，檢測Ac轉接器之連 接，於電源電塵VD5比受電控制裝置5〇(控制電路Μ)之動 作下限電壓小時等斷開。 受電控制裝置50係進行受電裝置4〇之各種控制的裝置， :藉㈣體電路裝置（IC)等來實現。該受電控制裝置辦 藉由從二次線圈L2之感應電壓產生的電源電壓VD5而動 作。此夕卜，受電控制裝置50可包含：控制電路52(受電 側）、輸出保證電路54、位置檢測電路56、振蘯電路以、 頻率檢測電路6 0及滿充電檢測電路6 2。 控制電路52(控制部）係進行受電裝置4〇及受電控制裝置 5〇之控制者，如可藉由閘極陣列及微電腦等來實現。具體 而言J控制電路52係進行ID認證、位置檢測、頻率檢測、 負載周fj或滿充電檢測等時需要的各種程序控制及判定處 理。 _輸出保證電路54係保證低電壓時（〇 v時）之受電裝置⑽的 '之電路，且防止電流自電壓輸出節點NB7向受電裝置 128613.doc 200849763 40側逆流。 位置檢測電路56監視相當於二次線圈L2之感應電壓波形 的訊號ADIN之波形，判斷一次線圈L1與二次線圈L2之位 置關係是否適當。具體而言，係將訊號ADIN以比較器轉 換成二值或A/D轉換，以判定位準，來判斷位置關係是否 適當。 振盈電路58如精由CR振盈電路而構成，並產生二次側 之時脈。頻率檢測電路60檢測訊號CCMPI之頻率（fi、The transistor TB1 (P-type CMOS transistor) is controlled by the signal P4Q from the turn-off guarantee circuit 54. Specifically, it is turned on when normal authentication is completed and normal power transmission is performed. Further, the connection of the Ac adapter is detected, and the power supply dust VD5 is disconnected from the lower limit voltage of the power receiving control device 5 (control circuit 小时). The power receiving control device 50 is a device that performs various types of control of the power receiving device 4, and is realized by a (four) body circuit device (IC) or the like. The power receiving control device operates by the power source voltage VD5 generated from the induced voltage of the secondary coil L2. Further, the power receiving control device 50 may include a control circuit 52 (power receiving side), an output ensuring circuit 54, a position detecting circuit 56, a vibrating circuit, a frequency detecting circuit 60, and a full charge detecting circuit 62. The control circuit 52 (control unit) is a controller of the power receiving device 4A and the power receiving control device 5, and can be realized by a gate array, a microcomputer, or the like. Specifically, the J control circuit 52 performs various program control and determination processes required for ID authentication, position detection, frequency detection, load cycle fj, or full charge detection. The output assurance circuit 54 is a circuit for ensuring the power receiving device (10) at a low voltage (〇v), and prevents current from flowing back from the voltage output node NB7 to the power receiving device 128613.doc 200849763 40 side. The position detecting circuit 56 monitors the waveform of the signal ADIN corresponding to the induced voltage waveform of the secondary coil L2, and judges whether or not the positional relationship between the primary coil L1 and the secondary coil L2 is appropriate. Specifically, the signal ADIN is converted to a binary or A/D conversion by a comparator to determine the level to determine whether the positional relationship is appropriate. The oscillating circuit 58 is constructed by a CR oscillating circuit and produces a secondary side clock. The frequency detecting circuit 60 detects the frequency of the signal CCMPI (fi,

f2)，如圖3(A)所示地判斷來自送電裝置ι〇之傳送資料為 「1」或「0」。 滿充電檢測電路62(充電檢測電路）係檢測負载9〇之電池 94(二次電池）是否達到滿充電狀態（充電狀態）的電路。 負載90包含進行電池94之充電控制等的充電控制裝置 92。該充電控制裝置92(充電控制可藉由積體電路裝置 等來實現。另外，亦可如智慧型電池，使電池94本身具備 充電控制裝置92之功能。 其次，就送電側與受電側之動作的概要，使用圖4之流 程圖作說明。送電側於投人電源而電力接通時（步驟si)， 進行位置檢測用之暫時性雷六值技,丰_ c^ ι 句了丨王电力傳达（步驟S2)。藉由該電力F2) As shown in Fig. 3(A), it is judged that the transmission data from the power transmitting device is "1" or "0". The full charge detecting circuit 62 (charge detecting circuit) is a circuit that detects whether or not the battery 94 (secondary battery) of the load 9 is in a fully charged state (charged state). The load 90 includes a charge control device 92 that performs charging control of the battery 94 and the like. The charging control device 92 (charge control can be realized by an integrated circuit device or the like. Alternatively, the smart battery can be used to provide the battery 94 itself with the function of the charging control device 92. Next, the operation of the power transmitting side and the power receiving side The outline of the diagram is illustrated by the flow chart of Fig. 4. When the power transmission side is powered by the power source and the power is turned on (step si), the temporary lightning value of the position detection is performed, and the _ c^ ι sentence Communicate (step S2). With the power

傳送，受電側之電源電壓卜显 ... . A 电l上幵，解除文電控制裝置5 0之重 設（步驟S11)。如此，受雷相，丨收_ & ^ 又冤側將訊號P1Q設定成H位準，並 將訊號Ρ 4 Q没定成局阻抗妝能〆丰 机狀您（步驟S12)。藉此，電晶體 TB2、TB 1均斷開，而遮斯盘备 W，、員载90間之電性連接。Transmission, the power supply voltage on the power receiving side is displayed. A is turned on, and the reset of the text control device 50 is released (step S11). In this way, by the ray phase, the _ & ^ 冤 side sets the signal P1Q to the H level, and the signal Ρ 4 Q is not determined to be a local impedance makeup 〆 机 ( ( (step S12). Thereby, the transistors TB2 and TB1 are all disconnected, and the shims are prepared, and the members are electrically connected by 90.

其次，受電側使用位詈；、、B、丨+ A 仏叫電路56判斷一次線圈L1與二 128613.doc 200849763 -人線圈L2之位置關係是否適當（步驟s丨3)。而後，於位置 關係適當情況下，受電側開始出之認證處理，並將認證訊 框傳送至送電側（步驟S14)。具體而言，係藉由圖3(b)中說 明之負載調制，來傳送認證訊框之資料。 送電側接收認證訊框時，進行出是否一致等之判斷處理 (V驟S3)。而後，在允許ID認證之情況下，將允許訊框傳 达至受電側（步驟S4)。具體而言，係藉由圖3(A)中說明之 頻率調制來傳送資料。 叉電側接收允許訊框，其内容為οκ情況下，將開始無 接點電力傳送用之開始訊框傳送至送電側（步驟si5、、 S16)。另外’送電側接收開始訊框，於其内容為〇κ情況 下，開始通常之電力傳送（步驟S5、S6)。而後，受電側將 訊號P1Q、P4Q設定成L位準（步驟S17：^藉此，因為電晶 體TB2、TB1均接通，所以可對負載9〇傳送電力，而開始 對負載供給電力（VOUT之輸出）（步驟S18)。 3·脈寬檢測 圖5顯示本實施形態之送電控制裝置2〇的具體結構例。 另外，本實施形態之送電控制裝置20不限定於圖5之結 構了實把省略其構成要素之一部分（如閃鎖電路、電壓 檢測電路、波形整形電路），或是追加其他構成要素等的 各種改良。 圖5中，一次線圈L1之電感及構成共振電路之電容器的 電各值變動，或電源電壓等變動時，感應電壓訊號PHIN 之峰值電壓（振幅）亦變動。因此，僅藉由檢測訊號PHIN之 128613.doc -20- 200849763 峰值電壓的方法，可能無法實現負載變動之正確的檢測。 因此’圖5係藉由進行感應電壓訊號pHIN之脈寬資訊的檢 測，來檢測負載變動。 波形整形電路32將一次線圈！^之感應電壓訊號pHIN(線 圈端電壓）予以波形整形，而輸出波形整形訊號WFQ。具 體而言’如訊號PHIN超過賦予之臨限值電壓時，輸出形 成主動（如Η位準）之方形波（矩形波）的波形整形訊號WFQ。 驅動時脈產生電路25產生規定一次線圈L1之驅動頻率的 驅動時脈DRCK。具體而言，將振盪電路24所產生之基準 時脈CLK予以分頻，而產生驅動時脈drck。一次線圈L1 中供給該驅動時脈DRCK之驅動頻率的交流電壓。 驅動器控制電路26依據驅動時脈DRCK產生驅動器控制 δΤΙ號，並輸出至驅動一次線圈l 1之送電部12的送電驅動器 (第一、第二送電驅動器）。此時，係以貫穿電流不流入構 成送電驅動裔之反相電路之方式，並以輸入反相電路之Ρ 型電晶體的閘極之訊號與輸入Ν型電晶體的閘極之訊號彼 此形成不重疊之訊號的方式，產生驅動器控制訊號。 脈寬檢測電路3 3檢測一次線圈l 1之感應電壓訊號phin 的脈寬資訊。具體而言，係接收來自波形整形電路3 2之波 形整形訊號WFQ與來自驅動時脈產生電路25之驅動時脈 DRCK(驅動裔控制亂號）’藉由檢測波形整形訊號wfq之 脈寬資訊，而檢測感應電壓訊號PHIN之脈寬資訊。 更具體而言’脈寬檢測電路33藉由計測驅動時脈 DRCK(驅動控制訊號）從非主動之電壓位準（如l位準）變成 128613.doc -21 - 200849763 主動之電壓位準（如Η位準）的第一點（如上昇邊緣。開始驅 動點），至波形整形訊號WFQ從主動之電壓位準（如η位準） 變成非主動之電壓位準（如L位準）的第二點（如下降邊緣。 波形整形訊號之結束點）之期間的脈寬期間，來檢測脈寬 資訊。如計測藉由驅動時脈DRCK之電壓變化而感應的電 壓訊號PHIN為賦予之臨限值電壓以上的脈寬期間。而 後，計測波形整形訊號WFQ(感應電壓訊號）之脈寬對驅動 日寸脈DRCK之脈寬的大小。此時之脈寬期間的計測如使用 基準時脈CLK進行。而後，脈寬檢測電路33計測結果之資 料PWQ閂鎖於閂鎖電路34。具體而言，脈寬檢測電路33藉 由基準時脈CLK，使用進行計數值之增量（或減量）的計數 裔，計測脈寬期間，並將其計測結果之資料PWQ閂鎖於閂 鎖電路34。 控制電路22依據脈寬檢測電路33檢測出之脈寬資訊，檢 測二次側（受電裝置40側）之負載變動（負載之高低）。具體 而言，控制電路22係依據脈寬檢測電路33檢測出之脈寬資 訊，進行受電裝置40藉由負載調制而傳送之資料的檢測。 或是，亦可進行雜質檢測及裝卸檢測等之過載狀態的檢 測。 圖6(A)、圖6(B)顯示一次線圈L1之線圈端電壓波形的測 定結果。圖6(A)、圖6(B)分別係受電側之負載電流為15〇 mA、3 00 mA時的電壓波形。負載電流愈大（愈是高負 載），線圈端電壓為賦予之設定電壓VR以上的脈寬期間 TPW愈短。因此，藉由計測該脈寬期間TPW，可判斷受電 128613.doc »22- 200849763 裝置40之負載調制部46的負載高低，並可判斷來自受電側 之傳送資料係「0」或是「i」。如圖3(B)所示，規定為低 負載時係「〇」，高負載時係「i」。此種情況下，脈寬期間 TPW比賦予之基準脈寬期間長時，為低負載，所以可判斷 為「〇」，脈寬期間短時為高負冑，所以可判斷為。Next, the power receiving side uses the position 詈;, B, 丨 + A 仏 电路 circuit 56 to determine whether the positional relationship between the primary coil L1 and the two 128613.doc 200849763 - the human coil L2 is appropriate (step s 丨 3). Then, when the positional relationship is appropriate, the power receiving side starts the authentication process, and the authentication frame is transmitted to the power transmitting side (step S14). Specifically, the data of the authentication frame is transmitted by the load modulation described in Fig. 3(b). When the power transmitting side receives the authentication frame, it performs determination processing such as whether or not it is consistent (V step S3). Then, in the case where ID authentication is permitted, the permission frame is transmitted to the power receiving side (step S4). Specifically, the data is transmitted by the frequency modulation explained in Fig. 3(A). When the fork side receives the permission frame and the content is οκ, the start frame for starting the contactless power transmission is transmitted to the power transmission side (steps si5, S16). Further, the power transmission side receives the start frame, and when the content is 〇 κ, the normal power transmission is started (steps S5 and S6). Then, the power receiving side sets the signals P1Q and P4Q to the L level (step S17: ^, since the transistors TB2, TB1 are both turned on, the power can be transmitted to the load 9 ,, and the power supply to the load is started (VOUT (Output) (Step S18). 3. Pulse Width Detection FIG. 5 shows a specific configuration example of the power transmission control device 2A of the present embodiment. The power transmission control device 20 of the present embodiment is not limited to the configuration of FIG. One of the constituent elements (such as a flash lock circuit, a voltage detecting circuit, a waveform shaping circuit), or various other modifications, etc. In Fig. 5, the inductance of the primary coil L1 and the electrical values of the capacitors constituting the resonant circuit When the fluctuation, or the power supply voltage changes, the peak voltage (amplitude) of the induced voltage signal PHIN also changes. Therefore, the load fluctuation may not be correct only by detecting the peak voltage of the signal PHIN 128613.doc -20- 200849763. Therefore, Fig. 5 detects the load variation by detecting the pulse width information of the induced voltage signal pHIN. The waveform shaping circuit 32 will perform the primary coil. !^ The induced voltage signal pHIN (coil terminal voltage) is waveform shaped, and the output waveform shaping signal WFQ. Specifically, if the signal PHIN exceeds the threshold voltage given, the output forms an active (such as the Η level) square. The waveform shaping signal WFQ of the wave (rectangular wave). The driving clock generating circuit 25 generates a driving clock DRCK that defines the driving frequency of the primary coil L1. Specifically, the reference clock CLK generated by the oscillation circuit 24 is divided. The driving clock drck is generated. The AC voltage of the driving frequency of the driving clock DRCK is supplied to the primary coil L1. The driver control circuit 26 generates the driver control δ ΤΙ according to the driving clock DRCK, and outputs it to the power transmitting unit that drives the primary coil l1. 12 power transmission driver (first and second power transmission driver). At this time, the through-current does not flow into the inverter circuit constituting the power transmission driver, and the signal of the gate of the NMOS transistor of the input inverter circuit is used. The driver control signal is generated in such a manner that the signals of the gates of the input 电-type transistors form a non-overlapping signal with each other. The pulse width detecting circuit 3 3 detects The pulse width information of the induced voltage signal phin of the secondary coil l1. Specifically, the waveform shaping signal WFQ from the waveform shaping circuit 32 and the driving clock DRCK from the driving clock generating circuit 25 are received. The pulse width information of the induced voltage signal PHIN is detected by detecting the pulse width information of the waveform shaping signal wfq. More specifically, the pulse width detecting circuit 33 is inactive by measuring the driving clock DRCK (drive control signal). The voltage level (such as the 1-level) becomes 128613.doc -21 - 200849763 The first point of the active voltage level (such as the Η level) (such as the rising edge). Start driving point), until the waveform shaping signal WFQ changes from the active voltage level (such as η level) to the second point of the inactive voltage level (such as the L level) (such as the falling edge. The end point of the waveform shaping signal) During the pulse width period, the pulse width information is detected. For example, the voltage signal PHIN induced by the voltage change of the driving clock DRCK is measured as a pulse width period equal to or higher than the threshold voltage. Then, the pulse width of the waveform shaping signal WFQ (inductive voltage signal) is measured to drive the pulse width of the day pulse DRCK. The measurement during the pulse width at this time is performed using the reference clock CLK. Then, the data PWQ of the measurement result of the pulse width detecting circuit 33 is latched to the latch circuit 34. Specifically, the pulse width detecting circuit 33 measures the pulse width period by using the count clock of the increment (or decrement) of the count value by the reference clock CLK, and latches the data PWQ of the measurement result to the latch circuit. 34. The control circuit 22 detects the load fluctuation (the level of the load) on the secondary side (the power receiving device 40 side) based on the pulse width information detected by the pulse width detecting circuit 33. Specifically, the control circuit 22 detects the data transmitted by the power receiving device 40 by load modulation based on the pulse width information detected by the pulse width detecting circuit 33. Alternatively, it is possible to perform an overload state detection such as impurity detection and loading and unloading detection. Fig. 6(A) and Fig. 6(B) show the measurement results of the coil end voltage waveform of the primary coil L1. 6(A) and 6(B) show voltage waveforms when the load current on the power receiving side is 15 mA and 300 mA, respectively. The larger the load current (the higher the load), the shorter the TPW during the pulse width of the coil terminal voltage given the set voltage VR or higher. Therefore, by measuring the pulse width period TPW, it is possible to determine the load level of the load modulation unit 46 of the power receiving unit 128613.doc »22-200849763, and determine whether the transmission data from the power receiving side is "0" or "i". . As shown in Fig. 3(B), it is defined as "〇" for low load and "i" for high load. In this case, when the pulse width period TPW is longer than the reference pulse width period given, the load is judged as "〇", and the pulse width period is high and negative when it is short.

圖7模式顯*·驅動時脈DRCK(驅動控制訊號）與線圈端電 壓波形之關係。驅動時脈DRCK在時點t2l為H位準（主 動），在時點t22為L位準（非主動）。另外，線圈端電壓在驅 動時脈DRCK為Η位準的時點t21急遽地上昇，其後下降。 而後，如圖7所示，受電側之負載愈低，線圈端電壓之下 降愈緩慢。因@ ’受電側之負載愈低，線圈端電壓（感應 電壓訊號）為賦予之設定電壓以上的脈寬期間愈長。因 此，藉由計測該脈寬期間，可判斷受電侧之負載係低負 載、中負載、高負載或過載之哪一個。 另外’計測脈寬期間用之設定電壓VR(如〇 v以上之電 壓。N型電晶體之臨限值電壓以上的電壓），只須適切選擇 負載變動之檢測精度為最佳的電壓來設定即可。 圖8(A)顯示無負載時一次側之等價電路，圖8(B)顯示有 負載時之等價電路。如圖8(A)所示，無負載時，藉由電容 C、一次側之洩漏電感L11及結合電感Μ而形成串聯共振電 路。因此’如圖8(C)之Β1所示，無負載時之共振特性形成 Q值南之陡峭（sharp)特性。另外，有負載情況下，加上二 次側之洩漏電感L12及二次側之負載的電阻。因此如圖 8(B)所示’有負載時之共振頻率fr2、fr3比無負載時之共 128613.doc -23- 200849763 振頻率frl大。此外，藉由電阻 振特性形成Q值低的緩和特性。再^響_有負載時之共 大)變成高負載⑽小)，共振頻率提二者從低負載⑽ 圈之驅動頻率(DRCK的頻率）。 。，/、振頻率接近線 如此’共振頻率接近驅動頻率 示，逐漸可看出共振波形之正 之低負載時帽波形，驅動波皮 之正弦波具支配性。反之，如圖 形，共振波形之正弦波者比^ 皮 社果公… ㈣波形之方形波具支配性。 :果，愈疋尚負載，線圈端電應為設定電 兔期™愈短。因此，藉由計測該脈寬期間TP%: 簡化之結構判斷受電側之負載的變動（高低）。 如亦有以負載之相位特性判斷受電側之負载變動的方 法。此處’所謂負載之相位特性，係指電壓、電流相位差 ，，不過，該方法有電路結構複雜，而導致高成本化的問 題0 、對於此，本實施形態之脈寬檢測方法，因為係利用電壓 波形’可以簡單之波形整形電路與計數電路（計數器)作為 數位資料來處理，所以具有可簡化電路結構之優點。此 外，還具有容易實現與使用t壓波形檢測負載變動之振幅 檢測方法組合的優點。 圖9顯示本實施形態之送電控制裝置2〇的具體結構例。 圖9係波形整形電路32包含：串聯連接於VDD(高電位側電 源）與GND間之電阻RC1及N型電晶體TC1、與反相電路 128613.doc -24- 200849763 INVC。在電晶體TC1之閘極中輸入來自電壓檢測電路14之 訊號PHIN。而後，訊號PHIN&電晶體TC1之臨限值電壓 咼時，因為TC1接通，節點NC1之電壓形成L位準，所以波 形整形訊號WFQ形成η位準。另外，訊號pHIN比臨限值電 壓低時，波形整形訊號WFQ形成L位準。 脈九檢測電路33包含計數器122。該計數器122在脈寬期 間進行計數值之增量（或減量），並依據獲得之計數值計測 脈寬期間之長度。此時，計數器122如依據基準時脈cLK 進行計數值之計數處理。 更具體而言，脈寬檢測電路33包含賦能訊號產生電路 120。該賦能訊號產生電路ι2〇接收波形整形訊號WFQ與驅 動時脈DRCK，在脈寬期間產生成為主動之賦能訊號 ENQ。而後，計數器122於賦能訊號ENQ係主動（如H位準） 時，進行計數值之增量（或減量）。 該賦能訊號產生電路120可藉由在其時脈端子上輸入驅 動時脈DRCK，在其資料端子上輸入VDD(廣義而言，為高 電位側電源）的電壓，於波形整形訊號WFQ係非主動仏位 準）時重設之正反器電路吓^而構成。藉由該正反器電路 FFC1 ’於波形整形訊號WFq形成主動（H位準）後，驅動時 脈DRCK形成主動（H位準）時，其輸出訊號之賦能訊號ENq 形成主動（Η位準）。其後，於波形整形訊號WFq形成非主 動（L位準）時重設正反器電路FFC1，其輸出訊號之賦能訊 號ENQ形成非主動（L位準）。因此，計數器122藉由以基準 柃脈CLK計數賦能訊號ENQ為主動之期間，可計測脈寬期 128613.doc -25- 200849763 間。 另外，亦可藉由在其時脈端子上輸入驅動時脈drck， 在其資料端子上連接GND(低電位側電源），於波形整形訊 號WFQ係非主動時設定的正反器電路來構成賦能訊號產生 電路120。此種情況下’只須將正反器電路之輸出訊號的 • 反轉訊號作為賦能訊號ENQ而輸入計數器122即可。 • 計數值保持電路丨24保持來自計數器122之計數值 CNT(脈寬資訊）。而後，將保持之計數值的資料ltq2輸出 f 至輸出電路126。 輸出電路126(濾波器電路、雜訊除去電路）接收被計數 值保持電路124保持之計數值的資料LTQ2，而輸出資料 PWQ。該輸出電路126如可包含比較此次保持於計數值保 持電路124之計數值與前次保持之計數值，而輸出大的一 方之計數值的比較電路130。藉此，可自輸出電路126保持 最大值之計數值而輸出。如此，可抑制因雜音等造成脈寬 期間之k動，而可實現穩定之脈寬檢測。此外，亦可輕易 ‘ 地與振幅檢測方法組合。 圖1〇顯示說明圖9之電路動作用的訊號波形例。在時點 t31波形整形訊形成H位準時，解除正反器電路 FFC1之重设。而後，在時點t32，於驅動時脈drck形成η 位準時，在其上昇邊緣，VDD之電壓被引進正反器電路 FFC1，藉此，賦能訊號ENQ&I^i準變成η位準。結果計 數器122開始計數處理，並使用基準時脈clk計測脈寬 間 TPW。 / 128613.doc -26- 200849763 其次’在時點t33，波形整形訊號WFQ形成L位準時，重 設正反器電路FFC1，賦能訊號ENQ從Η位準變成L位準。 藉此，計數器122之計數處理結束。而後，藉由該計數處 理而獲得之計數值成為表示脈寬期間Tpw之計測結果。 同樣地，圖10係藉由在時點t34，波形整形訊號WFq形 成Η位準，在時點t35，賦能訊號ENQ形成H位準，而開始 。十數處理。其後，藉由在時點t36，波形整形訊號WFQ及 fFigure 7 shows the relationship between the drive mode DRCK (drive control signal) and the coil end voltage waveform. The driving clock DRCK is at the H level (active) at the time point t2l, and is at the L level (inactive) at the time point t22. Further, the coil terminal voltage rises sharply at the time point t21 when the driving clock DRCK is at the Η level, and then falls. Then, as shown in Fig. 7, the lower the load on the power receiving side, the slower the drop under the coil terminal voltage. The lower the load on the power receiving side of @ ’, the longer the coil terminal voltage (inductive voltage signal) is the pulse width period above the set voltage. Therefore, by measuring the pulse width period, it can be determined which of the load on the power receiving side is low load, medium load, high load, or overload. In addition, the voltage VR (for voltages above 〇v and voltages above the threshold voltage of the N-type transistor) for measuring the pulse width period is only required to be appropriately selected to select the voltage with the highest detection accuracy of the load variation. can. Fig. 8(A) shows the equivalent circuit on the primary side when no load is applied, and Fig. 8(B) shows the equivalent circuit when there is load. As shown in Fig. 8(A), when there is no load, the series resonance circuit is formed by the capacitor C, the leakage inductance L11 on the primary side, and the combined inductance Μ. Therefore, as shown in Fig. 8(C), the resonance characteristic at the time of no load forms a sharp characteristic of the south value of the Q value. In addition, in the case of a load, the leakage inductance L12 on the secondary side and the resistance on the secondary side are added. Therefore, as shown in Fig. 8(B), the resonance frequencies fr2 and fr3 at the time of load are larger than the vibration frequency frl of 128613.doc -23-200849763 when there is no load. Further, the relaxation characteristics of the Q value are formed by the resistance characteristics. Then, when the load is large, it becomes a high load (10) small, and the resonance frequency is raised from the drive frequency of the low load (10) circle (the frequency of DRCK). . , /, the vibration frequency is close to the line. Therefore, the resonance frequency is close to the driving frequency. It can be seen that the positive waveform of the resonant waveform has a low load-loaded hat waveform, and the sine wave of the driving wave is dominant. On the contrary, as shown in the figure, the sine wave of the resonance waveform is better than that of the skin. (4) The square wave of the waveform is dominant. : If the load is still more, the coil end should be set to the shorter the rabbit period. Therefore, by measuring the pulse width period TP%: the simplified structure determines the fluctuation (high and low) of the load on the power receiving side. There is also a method of determining the load variation on the power receiving side based on the phase characteristics of the load. Here, the phase characteristic of the load refers to the voltage and current phase difference. However, this method has a complicated circuit structure and causes a problem of high cost. For this, the pulse width detecting method of the present embodiment is The voltage waveform 'can be simply processed by a waveform shaping circuit and a counting circuit (counter) as digital data, so that it has the advantage of simplifying the circuit structure. In addition, it has the advantage of being easily combined with an amplitude detecting method that detects a load variation using a t-voltage waveform. Fig. 9 shows a specific configuration example of the power transmission control device 2A of the present embodiment. Fig. 9 is a waveform shaping circuit 32 including a resistor RC1 and an N-type transistor TC1 connected in series between VDD (high-potential side power source) and GND, and an inverter circuit 128613.doc -24-200849763 INVC. A signal PHIN from the voltage detecting circuit 14 is input to the gate of the transistor TC1. Then, when the threshold voltage of the signal PHIN & TC1 is 咼, since the voltage of the node NC1 forms the L level because TC1 is turned on, the waveform shaping signal WFQ forms the η level. In addition, when the signal pHIN is lower than the threshold voltage, the waveform shaping signal WFQ forms an L level. The pulse nine detection circuit 33 includes a counter 122. The counter 122 increments (or decrements) the count value during the pulse width and measures the length of the pulse width period based on the obtained count value. At this time, the counter 122 performs the counting process of the count value according to the reference clock cLK. More specifically, the pulse width detecting circuit 33 includes an energizing signal generating circuit 120. The enable signal generating circuit ι2 receives the waveform shaping signal WFQ and the driving clock DRCK, and generates an active enabling signal ENQ during the pulse width. Then, the counter 122 performs an increment (or decrement) of the count value when the enable signal ENQ is active (such as the H level). The enable signal generating circuit 120 can input a voltage of VDD (broadly speaking, a high-potential side power supply) at its data terminal by inputting a driving clock DRCK at its clock terminal, and the waveform shaping signal WFQ is not The active flip-flop circuit is reset when the flip-flop circuit is reset. After the flip-flop circuit FFC1' forms an active (H level) on the waveform shaping signal WFq, when the driving clock DRCK forms an active (H level), the output signal ENq of the output signal forms an active (positive level). ). Thereafter, the flip-flop circuit FFC1 is reset when the waveform shaping signal WFq forms a non-active (L level), and the output signal ENQ of the output signal forms an inactive (L level). Therefore, the counter 122 can measure the pulse width period 128613.doc -25 - 200849763 by taking the reference pulse CLK count enable signal ENQ as the active period. In addition, by inputting the driving clock drck to the clock terminal, GND (low potential side power supply) is connected to the data terminal, and the flip-flop circuit is set when the waveform shaping signal WFQ is inactive. The signal generation circuit 120 can be used. In this case, it is only necessary to input the inverted signal of the output signal of the flip-flop circuit as the enable signal ENQ into the counter 122. • The count value holding circuit 丨 24 holds the count value CNT (pulse width information) from the counter 122. Then, the data ltq2 of the held count value is output f to the output circuit 126. The output circuit 126 (filter circuit, noise removing circuit) receives the data LTQ2 of the count value held by the count value holding circuit 124, and outputs the data PWQ. The output circuit 126 may include a comparison circuit 130 that compares the count value held by the count value holding circuit 124 with the count value held last time, and outputs a larger one. Thereby, the output value can be outputted from the output circuit 126 while maintaining the maximum value. In this way, it is possible to suppress the k-motion during the pulse width period due to noise or the like, and to realize stable pulse width detection. In addition, it can be easily combined with the amplitude detection method. Fig. 1A shows an example of a signal waveform for explaining the operation of the circuit of Fig. 9. At the time point t31, the waveform shaping signal forms the H level, and the reset of the flip-flop circuit FFC1 is released. Then, at time t32, when the driving clock drck forms an n-level, at its rising edge, the voltage of VDD is introduced into the flip-flop circuit FFC1, whereby the energizing signal ENQ&I^i becomes quasi-n-level. The result counter 122 starts counting processing and measures the pulse width TPW using the reference clock clk. / 128613.doc -26- 200849763 Next, at time point t33, when the waveform shaping signal WFQ forms the L level, the flip-flop circuit FFC1 is reset, and the enable signal ENQ changes from the Η level to the L level. Thereby, the counting process of the counter 122 ends. Then, the count value obtained by the counting process becomes a measurement result indicating the pulse width period Tpw. Similarly, Fig. 10 is formed by the waveform shaping signal WFq at the time point t34, and at the time t35, the energizing signal ENQ forms the H level and starts. Ten processing. Thereafter, by shaping the waveforms WFQ and f at time t36

賦能訊號ENQ形成位準，而結束計數處理。而後，藉由該 計數處理而獲得之計數值成為表示脈寬期間丁pW2計測結 果0 而後，如圖10所示，受電側係低負載情況下，因為脈寬 期間TPW變長，所以計數值亦變大。另外，受電侧係高負 載情況下，因為脈寬期間TPW變短，所以計數值亦變小。 因此，控制電路22可依據此等計數值之大小來判斷受電側 之負載高低。 另外，波形整形電路32之結構不限定於圖9之結構。如 圖11(A)所tf，亦可藉由在其非反轉輸入端子（第一端子）上 輸入訊號PHIN，在其反韓齡人嫂上/给 你八汉轉翰入鳊子（弟二端子）上輸入設定 電壓VR的比較器CPC 1而構成浊报敕r币& 叩傅欣，反形整形電路32。因為使用 此種比較器CPC1時，可任咅妯坰敕 < —系 j 1士思地凋整设定電壓VR，所以可 提高負載變動之檢測精度。 此外’賦能訊號產生電路1 2 〇夕彡士 4致 电塔12ϋ之結構不限定於圖9之結 構。如圖11 (Β)所示，亦可葬由尤甘 力J糟由在其第一輸入端子上輸入 驅動時脈DRCK，在JL笫-於人各山7 ，、弟一輸入鈿子上輪入波形整形訊號 128613.doc -27- 200849763 WFQ之AND電路ANC1而構成賦能訊號產生電路12〇。 但是，波形整形電路32採用圖11(A)之結構情況下，賦 能訊號產生電路120須為圖9之結構。如圖12顯示波形整形 電路32係圖11 (A)之結構時的訊號波形例。採用使用比較 器CPC1之波形整形電路32時，如圖12所示，有時波形整 形訊號WFQ之上昇邊緣對驅動時脈drcK之上昇邊緣（時點 t32、t3 5)延遲。如輸入比較器cpci之設定電壓vr提高 時，該延遲變大。而波形整形訊號WFQ之上昇邊緣延遲情 況下，使用圖11(B)之AND電路ANC1構成賦能訊號產生電 路120時，賦能訊號ENQ之脈寬期間Tpw比實際短。結果 藉由計數處理而獲得之計數值不正確。 就這一點，於賦能訊號產生電路12〇採用圖9之結構時， 口為波形整形成號WFQ之上昇邊緣延遲時，賦能訊號ENq 在時點t32、t35亦上昇，所以脈寬期間Tpw不縮短，而可 獲得正確之計數值。 此外，輸出電路126之結構亦不限定於圖9之結構。如圖 13所示，亦可藉由求出保持於計數值保持電路1之數個 計數值（如此次之計數值與前次之計數值）的平均值（移動平 均）之平均化電路132而構成輸出電路126。使用此種平均 化電路132時，於計數值中重疊雜音成分時，亦可將其除 去，而可實現穩定之脈寬檢測。此外，亦可輕易地與振幅 檢測方法組合。 4·改良例 圖Η顯示本實施形態之改良例。該改良例係除了檢測感 128613.doc -28- 200849763 應電壓訊號之脈寬外，亦進行振幅檢測。圖丨4與圖5不同 之處為追加·振幅檢測電路28、A/D轉換電路29及閃鎖電 路30等。另外，改良例之結構不限定於圖14，如亦可省略 A/D轉換電路29及閂鎖電路3〇、34等之構成要素，如亦可 取代A/D轉換電路29，而設置比較峰值電壓與臨限值電壓 • 之數個比較器。 振幅檢測電路28檢測相當於一次線圈L1之一端感應電壓 的感應電壓訊號PHIN之振幅資訊（峰值電壓、振幅電壓、 ( 有效電壓）’而檢測受電側之負載變動。藉此，可進行雜 貝檢測、裝卸檢測及資料檢測等。另外，亦可使用峰值電 壓來判斷受電側之負載提高或降低，亦可使用峰值電壓以 外之物理量（振幅電壓、有效電壓）作判斷。 A/D轉換電路29在從振幅檢測電路28檢測之電壓（峰值電 壓）超過暫行規定電壓（暫行臨限值電壓）的時點經過賦予之 期間的轉換時點，進行檢測電壓之A/D轉換，求出基準臨 限值電壓之數位資料。而後，控制電路22使用基準臨限值The enable signal ENQ forms a level and ends the counting process. Then, the count value obtained by the counting process becomes the pulse width period □pW2 measurement result 0, and then, as shown in FIG. 10, when the power receiving side is under a low load, since the pulse width period TPW becomes long, the count value is also Become bigger. In addition, in the case of a high load on the power receiving side, since the pulse width TPW becomes shorter, the count value also becomes smaller. Therefore, the control circuit 22 can determine the level of the load on the power receiving side based on the magnitude of the count values. Further, the configuration of the waveform shaping circuit 32 is not limited to the configuration of FIG. As shown in Fig. 11(A), the signal PHIN can also be input on its non-inverting input terminal (first terminal), and it can be turned on in the anti-Korean age. The comparator CPC 1 of the set voltage VR is input to the two terminals to form a turbidity 敕r coin & 叩 Fu Xin, a reverse shaping circuit 32. Since the comparator CPC1 is used, it is possible to reduce the set voltage VR by using the <-system j1, so that the detection accuracy of the load variation can be improved. Further, the configuration of the 'energized signal generating circuit 1 2' is not limited to the structure of Fig. 9. As shown in Figure 11 (Β), it can also be buried by Eugene J. by driving the drive clock DRCK on its first input terminal, in JL笫-Yu Renshan 7, and the first input of the dice The waveform shaping signal 128613.doc -27- 200849763 WFQ AND circuit ANC1 constitutes an enable signal generating circuit 12A. However, in the case where the waveform shaping circuit 32 is constructed as shown in Fig. 11(A), the enable signal generating circuit 120 must be the structure of Fig. 9. Fig. 12 shows an example of a signal waveform when the waveform shaping circuit 32 is the configuration of Fig. 11(A). When the waveform shaping circuit 32 using the comparator CPC1 is used, as shown in Fig. 12, the rising edge of the waveform shaping signal WFQ may be delayed by the rising edge (time point t32, t3 5) of the driving clock drcK. When the set voltage vr of the input comparator cpci is increased, the delay becomes large. When the rising edge of the waveform shaping signal WFQ is delayed, the pulse width period Tpw of the energizing signal ENQ is shorter than the actual value when the AND circuit ANC1 of Fig. 11(B) is used to constitute the energizing signal generating circuit 120. As a result, the count value obtained by the counting process is incorrect. In this regard, when the enabling signal generating circuit 12 is configured as shown in FIG. 9, when the port is delayed by the rising edge of the waveform forming number WFQ, the energizing signal ENq also rises at the time points t32 and t35, so the pulse width period Tpw is not Shorten and get the correct count value. Further, the configuration of the output circuit 126 is not limited to the configuration of FIG. As shown in FIG. 13, the averaging circuit 132 of the average value (moving average) of the count values held by the count value holding circuit 1 (the next count value and the previous count value) can be obtained. The output circuit 126 is constructed. When such an averaging circuit 132 is used, when the noise component is superimposed on the count value, it can be removed, and stable pulse width detection can be realized. In addition, it can be easily combined with the amplitude detection method. 4. Improved Example A modified example of the present embodiment is shown. In the modified example, in addition to detecting the pulse width of the voltage signal 128613.doc -28- 200849763, amplitude detection is also performed. The difference between Fig. 4 and Fig. 5 is the addition/amplitude detecting circuit 28, the A/D conversion circuit 29, the flash lock circuit 30, and the like. Further, the configuration of the modified example is not limited to FIG. 14, and the constituent elements of the A/D conversion circuit 29 and the latch circuits 3A, 34, and the like may be omitted, and the comparative peak may be set instead of the A/D conversion circuit 29, for example. Voltage and threshold voltage • Several comparators. The amplitude detecting circuit 28 detects the amplitude information (peak voltage, amplitude voltage, (effective voltage)' of the induced voltage signal PHIN corresponding to the induced voltage at one end of the primary coil L1, and detects the load variation on the power receiving side. It is also possible to use the peak voltage to determine whether the load on the power receiving side is increased or decreased, or to use a physical quantity other than the peak voltage (amplitude voltage, effective voltage) for judgment. The A/D conversion circuit 29 When the voltage (peak voltage) detected by the amplitude detecting circuit 28 exceeds the temporary predetermined voltage (temporary threshold voltage), the A/D conversion of the detected voltage is performed at the point of transition of the period during which the voltage is applied, and the reference threshold voltage is obtained. Digital data. Then, control circuit 22 uses the reference threshold

| "I ' 電壓之數位資料進行雜質檢測、裝卸檢測及資料檢測之至 少1個。 • 具體而言，控制電路22從檢測電壓超過暫行規定電壓 • (SIGH0)的時點’開始使用計數器1 〇2之計數處理，a/d轉 換電路29在依據該計數器1 〇2之計數值所設定的轉換時點 進行A/D轉換。更具體而言，振幅檢測電路2 §藉由將一次 線圈L1之感應電壓訊號（半波整流訊號）之峰值電壓保持於 保持節點，以檢測振幅資訊之峰值電壓。而後，控制電路 128613.doc •29- 200849763 22在從峰值電壓超過暫行規定電壓的時點，經過第一期間 之重设時點（重設期間），進行將保持節點之電荷放電於低 電位側電源的重設控制。A/D轉換電路29在從重設時點經 過第二期間之轉換時點，進行峰值電壓之A/D轉換，以求 出基準臨限值電壓（SIGHV)之數位資料。 • 如振幅檢測電路28檢測訊號PHIN之振幅資訊情況下， —人線圈L1之電感及構成共振電路之電容器的電容值變 動，或電源電壓等變動時，振幅檢測電路28之檢測電壓 f) (峰值電壓、振幅電壓、有效電壓）亦變動。因此，雜質檢 測、裝卸檢測及資料檢測之判定用的基準臨限值電壓（判 定電壓）係固定值時，可能無法實現正確之檢測。 因此，圖14係設置A/D轉換電路29，而採用在從暫行之 規定電壓（規格電壓）經過賦予之期間的時點進行A/D轉 換，而自動修正檢測判定用之基準臨限值電壓的方法。 具體而言，設定圖15所示之暫行規定電壓SIGH〇。該暫 行規定電壓SIGH0係圖2之受電裝置40的負載調制部邨之 丨 負載係無負載（TB3斷開）時的峰值電壓（廣義而言，為檢測 電壓），與係有負載（TB3接通）時之峰值電壓間的電壓，如 -係SIGH0=2.5 V。另外，亦可藉由暫存器可變地設定暫行 規定電壓SIGH0。 A/D轉換電路29在從感應電壓訊號PHIN之峰值電壓（訊 號PHQ)超過暫行規定電壓SIGH0之時點u經過賦予之期間 丁P的轉換時點t2，進行峰值電壓之a/d轉換。而後，求出 基準臨限值電壓SIGHV的數位資料ADQ而輸出。閂鎖電路 128613.doc -30- 200849763 3〇問鎖該資料ADQ。控制電路22使用閃鎖之資料 雜質檢測、裝卸檢測或資料檢測。亦即，檢測放置於充： 器之-次線圈上的雜質(二次線圈以外之金屬），或是檢例 放置於充電器上之行動電話等之電子機器的裝卸(取幻， 或是檢測受電裝置40藉由負載調制而傳送之資料的「〇 、 「1 I。 、 」、| "I' The digital data of the voltage is at least one for impurity detection, loading and unloading detection and data detection. • Specifically, the control circuit 22 starts counting processing using the counter 1 〇 2 from the time point when the detected voltage exceeds the provisional predetermined voltage • (SIGH0), and the a/d conversion circuit 29 is set according to the count value of the counter 1 〇 2 A/D conversion is performed at the time of conversion. More specifically, the amplitude detecting circuit 2 § detects the peak voltage of the amplitude information by holding the peak voltage of the induced voltage signal (half-wave rectified signal) of the primary coil L1 at the holding node. Then, the control circuit 128613.doc • 29- 200849763 22 performs discharging of the charge of the holding node to the low-potential side power source at the time point when the peak voltage exceeds the provisional predetermined voltage and after the reset period of the first period (reset period). Reset control. The A/D conversion circuit 29 performs A/D conversion of the peak voltage at the point of transition from the reset period to the second period to obtain digital data of the reference threshold voltage (SIGHV). • When the amplitude detection circuit 28 detects the amplitude information of the signal PHIN, the detection voltage f) (peak value) of the amplitude detection circuit 28 when the inductance of the human coil L1 and the capacitance of the capacitor constituting the resonance circuit fluctuate, or when the power supply voltage or the like fluctuates. The voltage, amplitude voltage, and effective voltage also vary. Therefore, when the reference threshold voltage (determination voltage) used for the determination of impurity detection, handling detection, and data detection is a fixed value, correct detection may not be possible. Therefore, in Fig. 14, the A/D conversion circuit 29 is provided, and the reference threshold voltage for the detection determination is automatically corrected by performing A/D conversion at the time when the provisional predetermined voltage (specification voltage) is supplied. method. Specifically, the provisional predetermined voltage SIGH 所示 shown in FIG. 15 is set. The provisional predetermined voltage SIGH0 is the peak voltage (in a broad sense, the detection voltage) when the load modulation unit of the power receiving device 40 of the power receiving device 40 of FIG. 2 has no load (TB3 is turned off), and the load is tied (TB3 is turned on). The voltage between the peak voltages, such as - SIGH0 = 2.5 V. Alternatively, the temporary regulation voltage SIGH0 may be variably set by the register. The A/D conversion circuit 29 performs the a/d conversion of the peak voltage at the point t2 at which the period u of the induced voltage signal PHIN exceeds the provisional predetermined voltage SIGH0 when the peak value (signal PHQ) of the induced voltage signal PHIN exceeds the temporary predetermined voltage SIGH0. Then, the digital data ADQ of the reference threshold voltage SIGHV is obtained and output. Latch circuit 128613.doc -30- 200849763 3 锁Lock the information ADQ. The control circuit 22 uses the flash lock data for impurity detection, handling detection or data detection. That is, detecting the impurities placed on the secondary coil of the charging device (metal other than the secondary coil), or the loading and unloading of the electronic device such as a mobile phone placed on the charger (detection, or detection) "〇, "1 I. , ," of the data transmitted by the power receiving device 40 by load modulation

如在圖15之時點t0，受電側之負載調制部牝的電晶體 TB3接通、，或是從無負載（負載不連接）變成有負載（負載連 接）時，感應電壓訊號PHIN的峰值電壓上昇。圖15係嗖定 檢測此種峰值電壓之上昇用的暫行規定電-sigh〇(暫 臨限值電壓）。該暫行規定電壓81<311〇於受電側為無負載情 況下，係並未超過之電壓，峰值電壓超過81(}]^〇情況下， 可判斷為受電側確實地連接有負載。因此，在從該時點u 經過充分之斯間TP，於峰值電壓之位準穩定的時點t2，進 行A/D轉換，求出基準臨限值電壓SIGHV。具體而言，控 制電路22攸超過暫行規定電壓§igh〇之時點11，使用計數 器102開始計數處理（計數值之增量或減量）。而後，以在依 據計數器1 02之計數值而設定的轉換時點t2進行a/d轉換之 方式’控制A/D轉換電路29，來求出基準臨限值電壓 SIGHV。 而後，控制電路22依據該基準臨限值電進行雜 質檢測、裝卸檢測或資料檢測。具體而言，藉由對基準臨 限值電壓SIGHV減去或加上雜質檢測、裝卸檢測或資料檢 測用之參數電壓，而獲得雜質檢測用、裝卸檢測用或資料 128613.doc •31· 200849763 檢測用之臨限值電壓。而後，依據此等臨限值電壓，進行 雜質檢測、裝卸檢測及資料檢測之至少1個。 圖1 6顯示求出資料檢測用、過載檢測用、雜質檢測用、 裝卸檢測用之臨限值電壓VSIGH、VOVER、VMETAL、 VLEAVE用的臨限值表1〇〇之例。控制電路22使用該臨限值 • 表 100 求出 VSIGH、VOVER、VMETAL 及 VLEAVE。如資 料檢測用之臨限值電壓VSIGH藉由對基準臨限值電壓 SIGHV減去資料檢測用之參數電壓PV1而求出。同樣地， O VOVER藉由對SIGHV加上過載檢測用之參數電壓PV2而求 出，VMETAL藉由對SIGHV加上雜質檢測用之參數電壓 PV3而求出，VLEAVE藉由對SIGHV減去裝卸檢測用之參 數電壓PV4而求出。 另外，本實施形態係首先進行過載檢測，於檢測出過載 時，進行電壓檢測電路14之電壓分割節點的切換控制，並 進行雜質檢測、裝卸檢測。此時參數電壓PV1、PV2、 PV3、PV4如可設定成 0·3 V、0.8 V、0.8 V、0.1 V。如 ’ SIGHV= 3.0 V情況下，VSIGH= 3·0-0·3=2·7 V，資料檢測 用之臨限值電壓VSIGH形成基準臨限值電壓SIGHV(3.0 V) 與暫行規定電壓SIGH0(2.5 V)間之電壓。 . 藉由以上之振幅檢測方法，於線圈之電感及電容器之電 容值及電源電壓變動時，因應其變動，基準臨限值電壓 SIGHV亦變化，藉由SIGHV而求出之雜質檢測用、裝卸檢 測用、資料檢測用的臨限值電壓VMETAL、VLEAVE、 VSIGH亦變化。亦即，因應依元件變動等而變化之基準臨 128613.doc -32· 200849763 來自動修正臨限值電壓νΜΕΤΑ£、At time t0 in Fig. 15, when the transistor TB3 of the load modulation unit 受 on the power receiving side is turned on, or when the load (load connection) is changed from no load (load is not connected), the peak voltage of the induced voltage signal PHIN rises. . Figure 15 shows the provisional regulation power-sigh〇 (temporary limit voltage) for detecting the rise of this peak voltage. The temporary regulation voltage 81 < 311 is a voltage that does not exceed the load on the power receiving side, and if the peak voltage exceeds 81 (}), it can be determined that the load is reliably connected to the power receiving side. From this point u, after a sufficient inter-band TP, A/D conversion is performed at a time point t2 at which the level of the peak voltage is stable, and the reference threshold voltage SIGHV is obtained. Specifically, the control circuit 22 exceeds the provisional regulation voltage § At time 11 of igh, the counter 102 is used to start counting processing (increment or decrement of the count value), and then a/d conversion is performed in a manner of a/d conversion at the conversion time point t2 set according to the counter value of the counter 102. The reference threshold voltage SIGHV is obtained by the D conversion circuit 29. Then, the control circuit 22 electrically performs impurity detection, detachment detection, or data detection based on the reference threshold. Specifically, by using the reference threshold voltage SIGHV Subtract or add the parameter voltage for impurity detection, loading and unloading detection or data detection, and obtain the threshold voltage for detection, loading and unloading detection or data 128613.doc •31· 200849763 After that, at least one of impurity detection, loading and unloading detection, and data detection is performed based on the threshold voltages. Fig. 16 shows the threshold voltage for data detection, overload detection, impurity detection, and loading and unloading detection. Examples of threshold values for VSIGH, VOVER, VMETAL, and VLEAVE are shown in Table 1. The control circuit 22 uses the threshold value • Table 100 to find VSIGH, VOVER, VMETAL, and VLEAVE. For data detection threshold voltage VSIGH This is obtained by subtracting the parameter voltage PV1 for data detection from the reference threshold voltage SIGHV. Similarly, O VOVER is obtained by adding the parameter voltage PV2 for overload detection to SIGHV, and VMETAL is added by SIGHV. The parameter voltage PV3 for impurity detection is obtained, and VLEAVE is obtained by subtracting the parameter voltage PV4 for detachment detection from SIGHV. In addition, in the present embodiment, overload detection is first performed, and voltage detection is performed when an overload is detected. The switching control of the voltage division node of the circuit 14 performs impurity detection and loading and unloading detection. At this time, the parameter voltages PV1, PV2, PV3, and PV4 can be set to 0·3 V, 0.8 V, 0.8 V, and 0.1 V. In the case of SIGHV=3.0 V, VSIGH=3·0-0·3=2·7 V, the threshold voltage VSIGH for data detection forms the reference threshold voltage SIGHV (3.0 V) and the interim regulated voltage SIGH0 (2.5 V). Voltage between the two. According to the amplitude detection method described above, when the inductance of the coil, the capacitance of the capacitor, and the power supply voltage fluctuate, the reference threshold voltage SIGHV also changes, and the impurity is obtained by SIGHV. The threshold voltages VMETAL, VLEAVE, and VSIGH for detection, loading and unloading, and data detection also change. That is, the threshold voltage νΜΕΤΑ£ is automatically corrected in accordance with the change of the component, etc., 128613.doc -32· 200849763.

限值電壓SIGHV VLEAVE、VSIGH。藉此，可自動地吸收元件變動，而可 實現穩定之檢測動作。此外，基準臨限值電堡SIGHV之 A/D轉換，係在使用SIGH()確實地檢測出受電側之負載從 無負載變成有負載的時點tl，經過充分之期間叮的時點u 進2 °因A，可防止檢測出錯誤之基準臨限值電壓 的情形’而可實現無錯誤檢測之穩定的檢測動作。 主另外，在二次線圈L2靠近-次線圈L1之過程及設有雜質 f月況下，有時峰值電壓超過暫行規定電壓。但是， 此種f月況下’因為其以後之負載調制的程序與預先規定之 程序不一致，所以成為10認證錯誤，因為須再起動，所以 不致發生問題。Limit voltages SIGHV VLEAVE, VSIGH. Thereby, the component variation can be automatically absorbed, and a stable detection operation can be realized. In addition, the A/D conversion of the reference phage SIGHV is based on the fact that SIGH() is used to reliably detect the time at which the load on the power receiving side changes from no load to load, and the time point u is 2 ° after a sufficient period of time. Because A can prevent the detection of the erroneous reference threshold voltage condition, a stable detection operation without error detection can be realized. In addition, in the process in which the secondary coil L2 is close to the secondary coil L1 and the presence of the impurity f, the peak voltage may exceed the provisional predetermined voltage. However, in this case, the program for load modulation in the future is inconsistent with the pre-specified program, so it becomes a 10 authentication error, and it is necessary to restart, so that no problem occurs.

，此外，圖15係顯示振幅檢測電路28之檢測電壓係峰值電 壓的情況例，不過，振幅資訊不限定於峰值電壓，只須為 表不感應電壓訊號之振幅大小的物理量即可。如振幅資訊 亦可為表示感應電壓訊號之電力的有效電壓，亦可為感應 電麼訊號之振幅電壓本身。 圖17顯示振幅檢測電路28、A/D轉換電路29之詳細結構 例。圖17中，振幅檢測電路28包含：運算放大器〇pAi、 〇pA2、保持電容器CA1及重設用之N型的電晶體TAi。運 开放大為OPA1在其非反轉輸入端子上輸入訊號pHIN，在 /、反轉輸入鳊子上連接運算放大器〇PA2之輸出節點。 保持電各斋C A1及重設用電晶體ΤΑ 1設於運算放大器〇pA i 之輸出節點的峰值電壓之保持節點NA4與GND(低電位側 128613.doc -33- 200849763 電源）之間。運算放大器0PA2在其非反轉輪入端子上連接 保持節點NA4，在其反轉輸入端子上連接〇pA2的輸出節點 NA5,而構成電壓輸出器連接的運算放大器。另外，亦可 在運异放大器OPA2之後段進一步設置電壓輸出器連接的 運算放大器。 藉由圖17之運算放大器0PA1、〇PA2、保持電容器cAl 及重設用電晶體TA1而構成峰值保持電路（峰值檢測電 路）。亦即，來自電壓檢測電路14之檢測訊號pmN的峰值 電壓保持於保持節點NA4，該保持之峰值電壓的訊號藉由 電壓輸出器連接之運算放大器0PA2實施阻抗轉換，並輸 出至節點NA5。 重设用電晶體TA1在重設期間接通，將保持節點Na4之 電荷放電於GND側。亦即，運算放大器〇pA1僅係在保持 電容器CA1中貯存電荷’而無法將電荷放電於gnd側之類 型的運异放大|§。因而，雖可追隨訊號pHiN之峰值電壓 的上昇，但是無法追隨峰值電壓的下降。此外，因為設於 運算放大器OPA1之輸出部的電荷貯存用之p型的電晶體中 存在漏電流，所以該P型電晶體斷開情況下，於經過長時 間後，保持節點NA4之電壓亦上昇。目而，需要定期地重 設保持節點NA4之電壓。基於以上之理由，圖厂中在保持 節點NA4上設有重設用之電晶體TAl。 如本貝施形悲係受電側從送電側之交流電壓檢測（抽出） 時脈，並與該時脈同步進行負載調制。因&，受電側之負 載調制與送電侧之時脈同步地進行，所以送電側可唯—地 128613.doc -34- 200849763 瞭解X電側之負載調制的時點。因此，控制電路Μ特定受 電側之負載調制之負載的切換時點，在包含特定之切換時 點之重a又期間’進行將保持節點NA4之電荷放電於gnD側 的重設控制。藉此，採用無法追隨峰值電壓之下降類型的 運异放大器OPA1情況下，亦可實現適當之峰值保持動 • 作。此外，在等待峰值電壓超過暫行規定電壓SIGH0的待 • 機模式時，藉由定期地重設保持節點ΝΛ4之電壓，可防止 因運异放大器OPA1之P型電晶體之漏電流造成保持電壓之 〇 上昇。 圖18顯示說明振幅檢測電路28之動作用的訊號波形例。 如圖18所示，訊號PHIN為藉由半波整流電路之電壓檢測 電路14而半波整流的訊號。運算放大器〇pA1之輸出訊號 OPQ在訊號PHIN之脈衝發生期間，其電壓上昇，在脈衝不 發生期間，其電壓被保持電容器CA1保持而維持。而後， 運算放大器OPA2之輸出訊號PHq平滑地追隨訊號pHIN之 峰值。 f A/D轉換電路29包含：抽樣保持電路丨丨〇、比較器 CPA 1、逐次比較暫存器丨丨2、D/A轉換電路丨丨4。抽樣保持 電路110抽樣訊號PHq而保持。比較器cpA1比較來自d/a 轉換電路114之D/A轉換後的類比訊號DAQ與來自抽樣保持 電路110之抽樣保持訊號SHQ。逐次比較暫存器112(逐次比 較控制電路）儲存比較器CPA1之輸出訊號cqi的資料。d/a 轉換電路114將來自逐次比較暫存器112之如8位元的數位 資料SAQ予以d/A轉換後，輸出類比訊號DAq。 128613.doc -35- 200849763 該逐次比較型之A/D轉換電路29由比較器cpAi比較僅 MSB(最上p白位元）為「！」時之D/A轉換後的訊號dAq與輸 入訊號SHQ(PHQ)。而後只要訊號SHQ之電壓大時，msb 仍為「lj，小時則MSB為「〇」。而後，A/D轉換電路29就 以後之下階位元亦同樣地逐次進行比較處理。而後，將最 後獲得之數位資料ADQ輸出至閂鎖電路3〇。另外，A/D轉 換電路29不限於圖17之結構，如亦可為不同電路結構之 逐次比較型A/D轉換電路，亦可為追隨比較型、並列比較 型、雙重積分型等之A/D轉換電路。 圖19顯π說日月圖i7之電路動作用的訊號波形例。在時點 til，重設訊號RST形成L位準（非主動），解除重設時，峰 值電壓之汛唬PHQ稍微上昇。在其後之時點t丨2，受電側 (二次側）從無負載變成有負載時，峰值電壓進一步上昇， 在時點tl3，超過暫行規定電壓81(}11〇時，計數器1〇2開始 計數動作。而後，在經過期間TP1(如1〇4 CLK)的重設時點 tl4，紕號RST形成Η位準（主動），電晶體TA1接通，保持節 點NA4之電荷放電於GND側。藉此，峰值電壓暫時下降。 而後，經過重設期間TP2(如32 CLK)，而到達時點tl5時， 因為受電側仍然有負載，所以峰值電壓再度上昇。其後， 在經過期間TP3(如32 CLK)的轉換時點tl6，A/D轉換電路 29開始A/D轉換，求出基準臨限值電壓SIGHVi數位資 料。而後，在經過期間TP4(如64 CLK)的時點tl7，閂鎖訊 號LAT1形成Η位準（主動），基準臨限值電壓SIGHv之數位 資料被閂鎖電路30閂鎖。 128613.doc -36 - 200849763 如此，圖19係在從峰值電壓（pHQ)超過暫行規定電壓 SIGH:的時點’經過第_期間⑺之重設時點w，進行將 保持即點NA4之電荷放電於低電位側電源的重設控制。而 後，在攸重設時點tl4經過第二期間（τρ2+τρ3)的轉換時點 U6’進行峰值電壓之A/D轉換，而求出基準臨限值電壓 SIGHV之數位資料。 亦即’從超過暫行規定電壓SIGH0起，經過期間τρι 後，設置重設期間TP2，暫時重設保持節點NA4之電壓。 而後，於期間TP3中等待振幅檢測電路28(峰值保持電路） 之輸出穩定，其後，起動A/D轉換電路29，進行a/d轉 換。藉此，因為重設保持節點NA4之電壓，可於峰值電壓 穩疋後進行A/D轉換，所以可提高基準臨限值電壓SIGHv 之檢測精度。 5 ·脈寬檢測與振幅檢測之併用 採用圖14之結構時，可藉由併用脈寬檢測與振幅檢測， 而提高負載變動之檢測精度。 具體而言’控制電路22係依據脈寬檢測電路33檢測出之 脈寬資訊，進行受電裝置40藉由負載調制而傳送之資料的 檢測。另外，依據振幅檢測電路28檢測出之振幅資訊，進 行雜質檢測及裝卸檢測之至少一方。 更具體而言，控制電路22依據以脈寬檢測電路3 3檢測， 而閂鎖於閂鎖電路34之脈寬期間的資料PWq(脈寬資訊）， 進行資料檢測。另外，使用藉由振幅檢測電路28、A/d轉 換電路2 9求出’而閂鎖於閂鎖電路3 〇之基準臨限值電壓的 128613.doc -37- 200849763 數位資料進行雜質檢測及裝卸檢測之至少一方。如求出圖 1 6中說明之雜質檢測用、裝卸檢測用的臨限值電壓，來進 行雜質檢測及裝卸檢測。 如在圖1 9之時點117中，振幅檢測用之第一閂鎖電路3 〇 藉由閂鎖訊號LAT1閂鎖來自A/D轉換電路29之資料 ADQ(如基準臨限值電壓之資料）。此外，脈寬檢測用之第 二閂鎖電路34藉由閂鎖訊號LAT2閂鎖來自脈寬檢測電路 33之資料PWQ(脈寬期間之資料）。此時第二閂鎖電路34在 ”第閂鎖電路30之閂鎖時點同步的時點，閂鎖來自脈寬 松測電路33之資料。具體而言，第一、第二閂鎖電路川、 34藉由相同時點之閂鎖訊號LAT1、LAT2閂鎖資料。 如此，可在相同時點閂鎖藉由脈寬檢測而獲得之資料與 藉由振幅檢測而獲得之資料，並輸入控制電路22。藉此， 可保持脈寬檢測與振幅檢測間之電路互換性，並可簡化控 制電路22之程序處理及判斷處理。 如圖9係藉由輸出電路126之比較電路13〇，與振幅檢測 電路28中保持峰值電壓同樣地，即使來自脈寬檢測電路^ 之輸出資料PWQ(計數值）仍可始終保持最大值。因此，可 維持與振幅檢測電路28、A/D轉換電路29間之電路互換， 以謀求系統結構及程序之簡化。 _⑷顯示«之變化特性’圖卿）顯示振幅之變化 1寺！。圖20(A)之橫軸係受電側之負載電流量，縱軸為計 “ 122之β十數值（脈見期間）。另外，圖20(B)之橫軸係受 電側之負載電流量’縱軸為線圈端電廢之振幅(峰值電 128613.doc -38- 200849763 壓）。 圖20(A)之脈寬變化特性係如E1所示，負載電流量小， 而為低負載情況下，計數值對負載電流量之變化的變化率 大，靈敏度高。另外，如E2所示，負載電流量大，而為高 負載情況下，計數值對負載電流量之變化的變化率小，靈 敏度低。其理由係因與正常之線圈結合時，藉由結合度之 限制，隨著負載加重，負載-相位特性中之相位旋轉飽 和〇Further, Fig. 15 shows an example of the case where the detected voltage peak voltage of the amplitude detecting circuit 28 is used. However, the amplitude information is not limited to the peak voltage, and it is only necessary to indicate the physical quantity of the amplitude of the induced voltage signal. For example, the amplitude information can also be the effective voltage representing the power of the induced voltage signal, or the amplitude voltage itself of the induced signal. Fig. 17 shows a detailed configuration example of the amplitude detecting circuit 28 and the A/D converting circuit 29. In Fig. 17, the amplitude detecting circuit 28 includes operational amplifiers 〇pAi, 〇pA2, a holding capacitor CA1, and an N-type transistor TAi for resetting. The OPA1 inputs the signal pHIN to its non-inverting input terminal, and connects the output node of the operational amplifier 〇PA2 to the / and inverted input dice. The holding circuit C A1 and the reset transistor ΤΑ 1 are provided between the holding node NA4 of the output node of the operational amplifier 〇pA i and the GND (low potential side 128613.doc -33 - 200849763 power supply). The operational amplifier 0PA2 is connected to the non-inverting wheel-in terminal to hold the node NA4, and its inverting input terminal is connected to the output node NA5 of the 〇pA2 to constitute an operational amplifier to which the voltage output is connected. Alternatively, an operational amplifier to which the voltage output device is connected may be further provided in the subsequent stage of the operational amplifier OPA2. The peak hold circuit (peak detecting circuit) is constituted by the operational amplifiers 0PA1, 〇PA2, the holding capacitor cAl, and the reset transistor TA1 of Fig. 17 . That is, the peak voltage of the detection signal pmN from the voltage detecting circuit 14 is held at the holding node NA4, and the signal of the held peak voltage is impedance-converted by the operational amplifier 0PA2 connected to the voltage output, and output to the node NA5. The reset transistor TA1 is turned on during the reset period, and discharges the charge of the holding node Na4 to the GND side. That is, the operational amplifier 〇pA1 is only a type of polarization amplification in which the charge is stored in the holding capacitor CA1 and the charge cannot be discharged to the gnd side. Therefore, although the peak voltage of the signal pHiN can be increased, the peak voltage cannot be followed. In addition, since there is a leakage current in the p-type transistor for storing the charge in the output portion of the operational amplifier OPA1, the voltage of the node NA4 is also increased after a long period of time after the P-type transistor is turned off. . Therefore, it is necessary to periodically reset the voltage of the holding node NA4. For the above reasons, the resetting transistor TA1 is provided on the holding node NA4 in the drawing factory. For example, according to Benbesch, the power receiving side detects (extracts) the clock from the AC voltage on the power transmitting side, and performs load modulation in synchronization with the clock. Since &, the load modulation on the power receiving side is synchronized with the clock on the power transmitting side, the power transmitting side can be used only to understand the timing of the load modulation on the X power side 128613.doc -34- 200849763. Therefore, the control circuit 切换 the switching timing of the load modulation of the specific power receiving side, and the reset control for discharging the electric charge of the holding node NA4 to the gnD side is performed at the weight a and the period including the specific switching timing. In this case, an appropriate peak hold operation can be realized in the case of the OPA1, which is a type of the amplifier that cannot follow the drop type of the peak voltage. In addition, by waiting for the voltage of the holding node ΝΛ4 to be periodically reset while waiting for the peak voltage to exceed the standby voltage SIGH0, the holding voltage can be prevented from being caused by the leakage current of the P-type transistor of the OPA1. rise. Fig. 18 shows an example of a signal waveform for explaining the operation of the amplitude detecting circuit 28. As shown in Fig. 18, the signal PHIN is a half-wave rectified signal by the voltage detecting circuit 14 of the half-wave rectifying circuit. The output signal of the operational amplifier 〇pA1 OPQ rises during the pulse of the signal PHIN, and its voltage is maintained by the holding capacitor CA1 while the pulse is not occurring. Then, the output signal PHq of the operational amplifier OPA2 smoothly follows the peak of the signal pHIN. The f A/D conversion circuit 29 includes a sample hold circuit 丨丨〇, a comparator CPA 1, a successive comparison register 丨丨2, and a D/A conversion circuit 丨丨4. The sample and hold circuit 110 samples the signal PHq and holds it. The comparator cpA1 compares the D/A converted analog signal DAQ from the d/a conversion circuit 114 with the sample hold signal SHQ from the sample and hold circuit 110. The compare register 112 (sequential comparison control circuit) stores the data of the output signal cqi of the comparator CPA1 one by one. The d/a conversion circuit 114 d/A converts the digital data SAQ of the 8-bit element from the successive comparison register 112, and outputs the analog signal DAq. 128613.doc -35- 200849763 The successive comparison type A/D conversion circuit 29 compares the D/A converted signal dAq and the input signal SHQ when only the MSB (the uppermost white bit) is "!" by the comparator cpAi. (PHQ). Then, as long as the voltage of the signal SHQ is large, the msb is still "lj, and the MSB is "〇". Then, the A/D conversion circuit 29 successively performs comparison processing on the subsequent lower order bits. Then, the digital data ADQ finally obtained is output to the latch circuit 3A. In addition, the A/D conversion circuit 29 is not limited to the structure of FIG. 17, and may be a successive comparison type A/D conversion circuit of different circuit configurations, or may be a follow-up comparison type, parallel comparison type, double integral type, etc. D conversion circuit. Fig. 19 shows an example of a signal waveform for the circuit operation of the sun and moon diagram i7. At the time point til, the reset signal RST forms an L level (inactive), and when the reset is released, the peak voltage 汛唬PHQ rises slightly. At the time point t丨2, when the power receiving side (secondary side) changes from no load to load, the peak voltage further rises. At the time point t13, when the temporary predetermined voltage 81 (}11〇 is exceeded, the counter 1〇2 starts counting. Then, during the reset of the period TP1 (such as 1〇4 CLK), the point tl4, the apostrophe RST forms the Η level (active), the transistor TA1 is turned on, and the charge of the node NA4 is discharged to the GND side. The peak voltage temporarily drops. Then, after resetting the period TP2 (such as 32 CLK) and reaching the time point t15, since the power receiving side still has a load, the peak voltage rises again. Thereafter, during the elapse of the period TP3 (such as 32 CLK) At the conversion time point t16, the A/D conversion circuit 29 starts A/D conversion to obtain the reference threshold voltage SIGHVi digital data. Then, at the time point t17 of the period TP4 (e.g., 64 CLK), the latch signal LAT1 forms a clamp. Quasi (active), the digital data of the reference threshold voltage SIGHv is latched by the latch circuit 30. 128613.doc -36 - 200849763 Thus, Fig. 19 is at the time point when the peak voltage (pHQ) exceeds the provisional regulated voltage SIGH: Point w after the reset of the _ period (7) Performing reset control for discharging the electric charge of the point NA4 to the low-potential side power supply. Then, at the time of the resetting, the point T14 is subjected to the A/D conversion of the peak voltage at the point U6' of the second period (τρ2+τρ3). The digital data of the reference threshold voltage SIGHV is obtained. That is, the reset period TP2 is set after the period τρι is exceeded from the temporary regulation voltage SIGH0, and the voltage of the holding node NA4 is temporarily reset. Then, in the period TP3 The output of the amplitude detecting circuit 28 (peak holding circuit) is stabilized, and then the A/D converting circuit 29 is activated to perform a/d conversion. Thereby, since the voltage of the holding node NA4 is reset, the peak voltage can be stabilized. A/D conversion is performed, so the detection accuracy of the reference threshold voltage SIGHv can be improved. 5 · When the pulse width detection and the amplitude detection are used in combination with the structure of Fig. 14, the load can be increased by using the pulse width detection and the amplitude detection together. Specifically, the control circuit 22 detects the data transmitted by the power receiving device 40 by load modulation based on the pulse width information detected by the pulse width detecting circuit 33. Further, at least one of impurity detection and detachment detection is performed based on the amplitude information detected by the amplitude detecting circuit 28. More specifically, the control circuit 22 is latched by the latch circuit 34 in accordance with the detection by the pulse width detecting circuit 33. The data PWq (pulse width information) during the pulse width period is used for data detection. Further, the reference threshold value latched to the latch circuit 3 求出 is obtained by using the amplitude detecting circuit 28 and the A/d conversion circuit 29. Voltage 128613.doc -37- 200849763 Digital data for at least one of impurity detection and handling detection. For example, the threshold voltage for impurity detection and handling detection described in Fig. 16 is obtained to perform impurity detection and detachment detection. As in the time point 117 of Fig. 19, the first latch circuit 3 for amplitude detection latches the data ADQ (such as the reference threshold voltage data) from the A/D conversion circuit 29 by the latch signal LAT1. Further, the second latch circuit 34 for pulse width detection latches the data PWQ (data during the pulse width period) from the pulse width detecting circuit 33 by the latch signal LAT2. At this time, the second latch circuit 34 latches the data from the pulse loosening circuit 33 at the point when the latching timing of the latch circuit 30 is synchronized. Specifically, the first and second latch circuits, 34 The data is latched by the latch signals LAT1, LAT2 at the same time. Thus, the data obtained by the pulse width detection and the data obtained by the amplitude detection can be latched at the same time point and input to the control circuit 22. The circuit interchangeability between the pulse width detection and the amplitude detection can be maintained, and the program processing and the judgment processing of the control circuit 22 can be simplified. As shown in FIG. 9, the comparison circuit 13 of the output circuit 126 is held in the amplitude detection circuit 28. Similarly to the peak voltage, even if the output data PWQ (count value) from the pulse width detecting circuit can always maintain the maximum value, the circuit interchange between the amplitude detecting circuit 28 and the A/D converting circuit 29 can be maintained. The simplification of the system structure and program. _(4) shows the change characteristic of «the qing" shows the change of amplitude 1 temple! The horizontal axis of Fig. 20(A) is the load current of the power receiving side, and the vertical axis is the β of the 122 Numerical value See period). Further, the horizontal axis of Fig. 20(B) is the amount of load current on the power receiving side, and the vertical axis is the amplitude of the coil end electrical waste (peak voltage 128613.doc -38 - 200849763). The pulse width variation characteristic of Fig. 20(A) is as shown by E1, the load current amount is small, and in the case of low load, the rate of change of the count value to the change of the load current amount is large, and the sensitivity is high. In addition, as shown in E2, the amount of load current is large, and in the case of high load, the rate of change of the count value to the change of the amount of load current is small, and the sensitivity is low. The reason is that when combined with a normal coil, the phase rotation in the load-phase characteristic is saturated as the load is increased due to the limitation of the degree of bonding.

另外’圖20(B)之振幅變化特性係如F1所示，於低負載 情況下，線圈端電壓對負載電流量之變化的變化率小，靈 敏度低。另外，如F2所示，於高負載情況下，計數值對負 載電流量之變化的變化率大，靈敏度高。 如此，脈寬檢測在低負載區域者之檢測靈敏度比高負載 區域高。另外，振幅檢測在高負載區域者之檢測靈敏度比 低負載區域高。因&，在低負載區域負載變動情況下，須 :用脈寬檢測來判斷負載之高低，在高負載區域負載變動 情況下，須使用振幅檢測來判斷負載之高低。如此，藉由 在低負載區域與高負载區域分開使用檢财式，可有^檢 測負載變動。 具體而言，如檢測藉由負 在較低負載之區域負载變動 載調制所傳送之資料的檢測 測出之脈寬資訊來進行。另 過载狀態情況下，在高負载 栽調制而傳送之資料情況下， 。因此，就受電裝置40藉由負 ，須依據以脈寬檢測電路3 3檢 外，雜質檢測及裝卸檢測等之 區域須靈敏度高，就雜質檢測 128613.doc -39- 200849763 及裝卸檢測，須依據振幅檢測電路28檢測出之振幅資訊來 進订。藉此’可以高靈敏度效率佳地實現資料檢測、雜質 檢測及裝卸檢測等。 另外’依狀況亦可依據振幅檢測電路2 8檢測出之振幅資 訊進行資料檢測，或是依據脈寬檢測電路33檢測出之脈寬 貧訊進行雜質檢測及裝卸檢測等之過載檢測。如資料檢測 時’在高負載區域負載變動情況下，係依據振幅資訊進行 貝料檢測’或是兼用振幅資訊與脈寬資訊進行資料檢測。 另外，電源之供給能力低，藉由過載而電源電壓降低之系 統等情況下，係依據脈寬資訊進行雜質檢測及裝卸檢測， 或是兼用脈寬資訊與振幅資訊進行雜質檢測及裝卸檢測。 如圖21顯示雜質尺寸與脈寬檢測之計數值的關係。G1係 正吊負載時之變化特性。G2係並非雜質之正常負載時，在 一次側（受電裝置）觀察之計數界限值的收斂橫軸線。如⑺ 之變化特性’計數值為G2之計數界限值以下情況下，可判 斷為雜質。亦即，因為G3係無法藉由振幅檢測而檢測之雜 質的變化特性，且在與線圈之間進行估計外之結合，藉由 正常之負載（G1)無法獲得之相位旋轉，而觀察小之計數 值’所以可判斷為雜質。藉由將該圖2丨之檢測方法與振幅 檢測組合，可進行更具智能之檢測處理。 另外’如上述，係就本實施形態詳細作說明，不過熟悉 本技術之業者應可輕易瞭解，從本發明之創新事項及效果 可作許多實體性不脫離的改良。因此，此種改良例均係包 含於本發明之範圍者。如在說明書或圖式中，至少曾與更 128613.doc -40 - 200849763 土例之全部組合亦包含於本發明之範圍。此外，送電控制 衣置、达電装置、f電控制裝置、受電裝置之結構與動 作、脈寬檢測方法、振幅檢測方法亦不限定於本實施形態 中說明者，而可實施各種改良。 κ義或同義之不同用語(低電位側電源、冑電位側電源、 ^電壓、電子機器等）一起記載之用語（GNd、vdd、峰 =電I、仃動電話與充電器等），在說明書或圖式之任何 ΙΜ立均可替換成其不同之用語。此外，本實施形態及改Further, the amplitude variation characteristic of Fig. 20(B) is as shown by F1, and the rate of change in the coil terminal voltage to the change in the load current amount is small at a low load, and the sensitivity is low. In addition, as shown by F2, under high load conditions, the rate of change of the count value to the amount of load current is large and the sensitivity is high. Thus, the detection sensitivity of the pulse width detection in the low load region is higher than that in the high load region. In addition, the detection sensitivity of the amplitude detection in the high load region is higher than that in the low load region. When &, in the case of load fluctuation in the low load region, it is necessary to use the pulse width detection to judge the level of the load. In the case of load fluctuation in the high load region, the amplitude detection must be used to determine the level of the load. Thus, by using the checkout type separately from the low load area and the high load area, the load fluctuation can be detected. Specifically, the detection is performed by detecting the pulse width information measured by the detection of the data transmitted by the load variation modulation in the region of the lower load. In the case of an overload condition, in the case of data transmitted with high load modulation. Therefore, in the case where the power receiving device 40 is negative, it must be based on the pulse width detecting circuit 33, and the area of the impurity detecting and loading and unloading detection must have high sensitivity, and the impurity detection 128613.doc -39-200849763 and the loading and unloading detection are subject to The amplitude detection circuit 28 detects the amplitude information to subscribe. In this way, data detection, impurity detection, and loading and unloading detection can be realized with high sensitivity and efficiency. Further, depending on the situation, the amplitude detection may be performed based on the amplitude information detected by the amplitude detecting circuit 28, or the overload detection may be performed based on the pulse width detection detected by the pulse width detecting circuit 33 for impurity detection and loading and unloading detection. For example, when the data is detected, 'the load is changed according to the amplitude information in the case of load change in the high load region' or the amplitude information and the pulse width information are used for data detection. In addition, when the power supply capability is low, and the power supply voltage is reduced by overload, the impurity detection and loading and unloading detection are performed based on the pulse width information, or the pulse width information and the amplitude information are used for impurity detection and loading and unloading detection. The relationship between the impurity size and the count value of the pulse width detection is shown in FIG. The G1 is a change in the load when the load is being lifted. When G2 is not a normal load of impurities, the convergence horizontal axis of the count limit value observed on the primary side (power receiving device). If the variation characteristic of (7) is less than the count limit value of G2, it can be judged as an impurity. That is, since the G3 system cannot detect the change characteristic of the impurity by the amplitude detection, and combines the estimation with the coil, the phase rotation which cannot be obtained by the normal load (G1) is observed. The value 'is judged to be an impurity. By combining the detection method of Fig. 2 with the amplitude detection, a more intelligent detection process can be performed. Further, as described above, the present embodiment will be described in detail, but those skilled in the art should be able to easily understand that many innovations and effects of the present invention can be improved without departing from the scope of the invention. Accordingly, such modifications are intended to be included within the scope of the invention. In the specification or the drawings, all combinations of at least 128613.doc -40 - 200849763 are also included in the scope of the present invention. Further, the power transmission control clothing, the power transmission device, the f electric control device, the configuration and operation of the power receiving device, the pulse width detecting method, and the amplitude detecting method are not limited to those described in the embodiment, and various improvements can be made. κ 义 or synonymous terms (low potential side power supply, zeta potential side power supply, ^ voltage, electronic equipment, etc.) together with the words (GNd, vdd, peak = electric I, mobile phone and charger, etc.), in the manual Or any of the figures can be replaced with different terms. In addition, this embodiment and the modification

【圖式簡單說明】 圖UA)、圖1(b)係無接點電力傳送之說明圖。 圖2係本實施形態之送電裝置、送電控制裝置、受電裝 置、受電控制裝置的結構例。 圖3(A)、圖3(B)係藉由頻率調制、負載調制而轉送資料 之說明圖。 圖4係就送電側與受電側之動作概要作說明用之流程 圖0 圖5係本實施形態之送電控制裝置的結構例。 圖6(A)、圖6(B)係顯示線圈端電壓波形之測定結果圖。 圖7係顯示驅動時脈與線圈端電壓波形之關係的模式 圖0 圖8(A)〜圖8(C)係無負載時、有負載時之等價電路及共 振特性圖。 圖9係送電控制裝置之具體的結構例。 圖10係說明本實施形態之動作用的訊號波形例。 128613.doc 200849763 圖11(A)、圖11(B)係波形整形電路、賦能訊號產生電路 之結構例。 圖12係說明本實施形態之動作用的訊號波形例。 圖13係輸出電路之結構例。 圖14係本實施形態之改良例的結構例。 圖15係說明改良例之動作用的訊號波形例。 圖16係臨限值表之例。 圖17係改良例之具體結構例。 圖18係說明振幅檢測電路之動作用的訊號波形例。 圖19係說明改良例之動作用的訊號波形例。 圖2〇(A)、圖20(B)係脈寬變化、振幅變化之特性圖。 圖21係顯示雜質尺寸與脈寬檢測之計數值的關係之特性 【主要元件符號說明】 L1 一次線圈 L2 二次線圈 10 送電裝置 12 送電部 14 電壓檢測電路 16 顯示部 20 送電控制裝置 22 控制電路（送電侧） 24 振盪電路 25 驅動時脈產生電路 128613.doc -42- 200849763 Γ 26 驅動器控制電路 28 振幅檢測電路 29 A/D轉換電路 30 閂鎖電路 32 波形整形電路 33 脈寬檢測電路 34 閂鎖電路 40 受電裝置 42 受電部 43 整流電路 46 負載調制部 48 饋電控制部 50 受電控制裝置 52 控制電路（受電側） 54 輸出保證電路 56 位置檢測電路 58 振盈電路 60 頻率檢測電路 62 滿充電檢測電路 90 負載 92 充電控制裝置 94 電池 100 臨限值表 102 計數器 128613.doc -43- 200849763 110 抽樣保持電路 112 逐次比較暫存器 114 D/A轉換電路 120 賦能訊號產生電路 122 計數器 124 計數值保持電路 126 輸出電路 130 比較電路 f 1 128613.doc -44-[Simplified description of the drawings] Figure UA) and Figure 1(b) are explanatory diagrams of contactless power transmission. Fig. 2 shows an example of the configuration of a power transmitting device, a power transmission control device, a power receiving device, and a power receiving control device according to the present embodiment. 3(A) and 3(B) are explanatory diagrams of data transfer by frequency modulation and load modulation. Fig. 4 is a flow chart for explaining the operation of the power transmitting side and the power receiving side. Fig. 0 Fig. 5 is a configuration example of the power transmission control device of the embodiment. 6(A) and 6(B) are graphs showing measurement results of voltage waveforms at the coil ends. Fig. 7 is a diagram showing the relationship between the driving clock and the coil terminal voltage waveform. Fig. 0 Fig. 8(A) to Fig. 8(C) are diagrams showing the equivalent circuit and the resonance characteristic when there is no load. Fig. 9 is a view showing a specific configuration example of the power transmission control device. Fig. 10 is a view showing an example of a signal waveform for the operation of the embodiment. 128613.doc 200849763 Fig. 11(A) and Fig. 11(B) show a configuration example of a waveform shaping circuit and an energization signal generating circuit. Fig. 12 is a view showing an example of a signal waveform for the operation of the embodiment. Fig. 13 is a diagram showing an example of the configuration of an output circuit. Fig. 14 is a view showing a configuration example of a modified example of the embodiment. Fig. 15 is a view showing an example of a signal waveform for explaining the operation of the modified example. Figure 16 is an example of a threshold table. Fig. 17 is a specific structural example of a modified example. Fig. 18 is a view showing an example of a signal waveform for operating the amplitude detecting circuit. Fig. 19 is a view showing an example of a signal waveform for explaining the operation of the modified example. Fig. 2A(A) and Fig. 20(B) are characteristic diagrams showing changes in pulse width and amplitude. Fig. 21 is a graph showing the relationship between the impurity size and the count value of the pulse width detection. [Main element symbol description] L1 primary coil L2 secondary coil 10 power transmitting device 12 power transmitting portion 14 voltage detecting circuit 16 display portion 20 power transmitting control device 22 control circuit (Power transmission side) 24 Oscillation circuit 25 Driving clock generation circuit 128613.doc -42- 200849763 Γ 26 Driver control circuit 28 Amplitude detection circuit 29 A/D conversion circuit 30 Latch circuit 32 Wave shaping circuit 33 Pulse width detection circuit 34 Latch Lock circuit 40 Power receiving device 42 Power receiving unit 43 Rectifier circuit 46 Load modulation unit 48 Feed control unit 50 Power receiving control device 52 Control circuit (power receiving side) 54 Output guarantee circuit 56 Position detecting circuit 58 Vibration circuit 60 Frequency detecting circuit 62 Fully charged Detection circuit 90 Load 92 Charge control device 94 Battery 100 Threshold table 102 Counter 128613.doc -43- 200849763 110 Sample hold circuit 112 Successive compare register 114 D/A conversion circuit 120 Enable signal generation circuit 122 Counter 124 The value holding circuit 126 outputs electricity The comparison circuit 130 f 1 128613.doc -44-

Claims (1)

200849763 十、申請專利範圍·· !.一種送電控制裝置，其特徵為··其設於使一次線圈與二 次線圈電磁性結合，從送電裝置對受電裝置傳送電力， 而對則述X電裝置之負載供給電力之無接點電力傳送系 統的前述送電裝置，且包含： μ 驅動時脈產生電路，其產生規定前述一次線圈之驅動 頻率的驅動時脈； 驅動器控制電路，其依據前述驅動時脈產生驅動器控 制訊號，而對驅動前述-次線圈之送電驅動器輸出； 波形整形電路，其將前述一次線圈之感應電壓訊號予 以波形整形，而輸出波形整形訊號； 脈寬檢測電路，其接收前述波形整形訊號與前述驅動 時脈而檢測前述波形整形訊號之脈寬資訊；及 控制電路，其依據檢測出之脈寬資訊，而檢測二次側 之負載變動。 2.如請求们之送電控制裝置，其中前述控制電路依據檢 測出之脈寬資訊’而檢測前述受電裝置藉由負載調制而 傳送之資料。 3 士口 士主屯百 ^ 〉、1或2之送電控制裝置，其中前述脈寬檢測電路 =由冲測脈I期間，而檢測脈寬資訊，該脈寬期間係從 ^區動時脈從非主t之電壓位準變成主動t電壓位準 的第 點’至前述波形整形訊號從主動之電壓位準變成 非主動之電壓位準的第三點之期間者。 4.如請求項3夕^ 、<适電控制裝置，其中前述脈寬檢測電路包 128613.doc 5· Γ (; 前述脈寬 值 200849763 2計數器，其在前述脈寬期間進行計數值之增量或減 重，並依據獲得之計數值計測前述脈寬期間之長度。 如請求項4之送電控制裝置’其中前述脈寬檢測電路包 3賦月“號產生電路’其接收前述波形整形訊號與前述 驅動時脈，而產生在前述脈寬期間成為主動之賦能訊 號， 前述計數器在前述賦能訊號係主動時，進行計數值之 增量或減量。 6.如請求項5之送電控制裝置’其中前述賦能訊號產生電 路包3^反器電路’其將前述驅動時脈輸人至其時脈端 子：將高電位側電源或低電位側電源之電壓輸入至其資 料端子’於前述波形整形訊號係主動時’進行重設 定。 。 ':請=6之送電控制褒置，其中前述波形整形電路包 含比較器 '其將一:欠線圈之感應、電壓tfl號輸入至其非反 轉輸入端子，將賦+夕机中蕾厭 肘賦予之认疋電壓輸入至其反轉輸入端 子0 8.如請求項4至7中任一項之送電控制裝置，其中 檢測電路包含： 。十數值保持電路，其保持來自前述計數器之計數 值；及 ▲輸出電路’其比較此次保持於前述計數值保持電路之 计數值與刖次保持之計數值，而輪出大的一方之計數 128613.doc 200849763 9.如睛求項4至7中任一項之 、k電控制裝置，其中前述脈寬 檢測電路包含： 計數值保持電路，其保持來自前述計 值；及 輸出電路，其輸出保持於 计數值的平均值。 10·如請求項1至9中任一 數器之計數 前述計數值保持電路之數個 、之适電控制裝置，其中包含： 振幅檢測電路，其檢測命 一…_ 、1迷一次線圈之感應電壓訊號 的振幅資訊； A/D轉換電路，其進行檢 測出之前述振幅資訊的a/D轉 換； 第一閂鎖電路，其 料；及 弟二閂鎖電路，其閂錯水 料； 鎖來自别述脈寬檢測電路之資 門鎖來自前述A/D轉換電路之資 •前述第二問鎖電路在與前述第一閃鎖電路之 同步=時點，問鎖來自前述脈寬檢測電路之資料。、 11 · 一種送電裝置，其特徵為包含·· 請求項1至10中任一項之送電控制裝置’·及 送電部，其產生交流電麼，而供給 12. 一種電子機器’其特徵為：包含請求項u之送電:置圏： 13. ^無接點電力傳❹統，其特徵為··包含送 受電裝置，使-次線圈與二次線圈電磁…： 送電裝置對前述受電裝置# …口從前述 置傳达電力’而對前述受電裝置 128613.doc 200849763 之負載供給電力， 且前述受電裝置包含： 叉電部’其將前述二次線圈之感應電壓轉換成直流電 壓；及 負載調制部，其從前述受電裝置傳送資料至前述送電 裝置時’因應傳送資料而使負載可變地變化； 前述送電裝置包含： 驅動時脈產生電路，其產生規定前述一次線圈之驅動 頻率的驅動時脈； •驅動器控制電路，其依據前述驅動時脈產生驅動器控 制訊號’而對驅動前述一次線圈之送電驅動器輸出； 波形整形電路，其將前述一次線圈之感應電壓訊號予 以波形整形，而輸出波形整形訊號； 脈寬檢測電路，其接收前述波形整形訊號與前述驅動 時脈，而檢測前述波形整形訊號之脈寬資訊；及 控制電路，其依據檢測出之脈寬資訊，而檢測二次側 之負載變動。 14. 一種送電控制裝置，其特徵為：其設於使—次線圈與二 次線圈電磁性結合，從送電裝置對受電裝置傳送電力， 而對前述受電裝置之負载供給電力之無接‘點電力傳送车 統的前述送電裝置，且包含： μ 驅動日卞脈產生電路，其彦决 屋生規疋刖述一次線圈之驅 頻率的驅動時脈； 128613.doc 200849763 制訊號’而對驅動前述一次線圈之送電驅動器輸出； 波形整形電路，其將前述一次線圈之感應電壓訊號予 以波形整形，而輸出波形整形訊號； 脈寬檢測電路’其接收前述波形整形訊號與前述驅動 時脈’而檢測前述波形整形訊號之脈寬資訊；及 控制電路，其依據檢測出之脈寬資訊，而控制前述送 電控制裝置。 15. ί' 16· 17. 一種送電裝置，其特徵為包含： 請求項14之送電控制裝置；及 G電邛其產生父流電壓，而供給至前述一次線圈。 一種電子機器，其特徵為：包含請求項15之送電裝置。 :種無接點電力傳送系統，其特徵為：包含送電裝置與 :”置使-入線圈與二次線圈電磁性結合，從送電 裝置對受電裝置傳送電力，而對前述受電裝置之負載供 給電力； 、/、 且前述送電裝置係請求項15之送電裝置。 128613.doc200849763 X. Patent application scope: A power transmission control device is characterized in that it is provided such that a primary coil and a secondary coil are electromagnetically coupled, and power is transmitted from a power transmitting device to a power receiving device, and an X-electric device is described. The power transmitting device of the contactless power transmission system that supplies power to the load includes: a driving pulse generation circuit that generates a driving clock that defines a driving frequency of the primary coil; and a driver control circuit that drives the clock according to the driving pulse Generating a driver control signal to drive the output of the power transmission driver of the aforementioned secondary coil; a waveform shaping circuit that waveform-shapes the induced voltage signal of the primary coil to output a waveform shaping signal; and a pulse width detecting circuit that receives the waveform shaping And detecting the pulse width information of the waveform shaping signal by the signal and the driving clock; and the control circuit detecting the load variation of the secondary side according to the detected pulse width information. 2. The power transmission control device of the request, wherein the control circuit detects the data transmitted by the power receiving device by load modulation based on the detected pulse width information'. 3 Shishishi main 屯 ^, 1 or 2 power transmission control device, wherein the aforementioned pulse width detection circuit = during the pulse detection period I, and detects the pulse width information, the pulse width period is from the ^ area dynamic clock The voltage level of the non-master t becomes the first point of the active t voltage level' to the third point of the waveform shaping signal from the active voltage level to the third point of the inactive voltage level. 4. The request item 3, < suitable electric control device, wherein the pulse width detecting circuit package 128613.doc 5 · Γ (; the aforementioned pulse width value 200849763 2 counter, which increases the count value during the aforementioned pulse width The amount or the weight is reduced, and the length of the pulse width period is measured according to the obtained count value. The power transmission control device of claim 4, wherein the pulse width detecting circuit package 3 is configured to receive the waveform shaping signal and The driving pulse generates an active enabling signal during the pulse width period, and the counter performs an increment or a decrement of the counting value when the energizing signal is active. 6. The power transmission control device of claim 5 Wherein the energization signal generating circuit package 3 is configured to input the driving clock to its clock terminal: input the voltage of the high potential side power source or the low potential side power source to its data terminal 'in the foregoing waveform shaping When the signal is active, 'reset the setting.' ': Please ==6 power transmission control device, wherein the aforementioned waveform shaping circuit includes a comparator' which will be one: the induction of the under-coil, Pressing the tfl number to the non-inverting input terminal, and inputting the put voltage given by the bud in the singer to the reverse input terminal 0. 8. The power transmission control device according to any one of claims 4 to 7. Wherein the detection circuit comprises: a ten-value hold circuit that holds the count value from the counter; and a ▲ output circuit that compares the count value held by the count value hold circuit with the count value held one time, and the wheel The k-electric control device according to any one of the items 4 to 7, wherein the pulse width detecting circuit comprises: a count value holding circuit that holds the value from the foregoing; And an output circuit whose output is maintained at an average value of the count value. 10. A device for counting the number of the count value holding circuits as recited in any one of claims 1 to 9, which comprises: an amplitude detecting circuit , the detection of the first ... _, 1 fan amplitude signal of the induced voltage signal; A / D conversion circuit, which performs the a/D conversion of the amplitude information detected; The lock circuit, the material thereof; and the second latch circuit, which latches the wrong material; the lock from the other pulse width detecting circuit is from the A/D conversion circuit; the second second lock circuit is in the foregoing Synchronization of the first flash lock circuit = time point, the lock is from the data of the pulse width detecting circuit. 11 A power transmitting device characterized by comprising: the power transmission control device of any one of claims 1 to 10 and Power transmission unit, which generates AC power, and supplies 12. An electronic device' is characterized by: power transmission including request item u: setting: 13. ^ contactless power transmission system, characterized by ···including power transmission and receiving device The secondary-coil and the secondary coil are electromagnetically...the power transmitting device supplies power to the load of the power receiving device 128613.doc 200849763 to the power receiving device from the above-mentioned power receiving device, and the power receiving device includes: a portion that converts the induced voltage of the secondary coil into a DC voltage, and a load modulation unit that causes the load to be transmitted in response to transmission of data from the power receiving device to the power transmitting device The power transmitting device includes: a driving clock generating circuit that generates a driving clock that defines a driving frequency of the primary coil; and a driver control circuit that drives the aforementioned one according to the driving pulse generating driver control signal a power transmission driver output of the coil; a waveform shaping circuit that waveform-shapes the induced voltage signal of the primary coil to output a waveform shaping signal; and a pulse width detecting circuit that receives the waveform shaping signal and the driving clock, and detects the waveform The pulse width information of the shaped signal; and the control circuit detects the load variation on the secondary side based on the detected pulse width information. A power transmission control device, characterized in that it is provided by electromagnetically coupling a secondary coil and a secondary coil, and transmitting power from the power transmitting device to the power receiving device, and supplying power to the load of the power receiving device The power transmitting device of the transmission system includes: μ driving the day pulse generating circuit, and the driving clock of the driving frequency of the primary coil is recited by the fan; 128613.doc 200849763 system signal 'and driving the foregoing one time a power transmission driver output of the coil; a waveform shaping circuit that waveform-shapes the induced voltage signal of the primary coil to output a waveform shaping signal; and a pulse width detecting circuit that receives the waveform shaping signal and the driving clock to detect the waveform The pulse width information of the shaping signal; and the control circuit, which controls the power transmission control device according to the detected pulse width information. 15. A power transmitting device, comprising: the power transmission control device of claim 14; and the G power generating the parental voltage to be supplied to the primary coil. An electronic machine characterized by comprising a power transmitting device of claim 15. A contactless power transmission system characterized by comprising: a power transmitting device; and: "activating-into-coil and a secondary coil are electromagnetically coupled, and power is transmitted from the power transmitting device to the power receiving device, and power is supplied to the load of the power receiving device. ; /, and the aforementioned power transmitting device is the power transmitting device of claim 15. 128613.doc