TW200849511A - Tape type semiconductor package with improved thermal dissipation - Google Patents

Tape type semiconductor package with improved thermal dissipation Download PDF

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Publication number
TW200849511A
TW200849511A TW96120413A TW96120413A TW200849511A TW 200849511 A TW200849511 A TW 200849511A TW 96120413 A TW96120413 A TW 96120413A TW 96120413 A TW96120413 A TW 96120413A TW 200849511 A TW200849511 A TW 200849511A
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TW
Taiwan
Prior art keywords
tape
flexible
semiconductor package
dissipating resin
package structure
Prior art date
Application number
TW96120413A
Other languages
Chinese (zh)
Inventor
Tsung-Lung Chen
Kuei-Yu Lai
Original Assignee
Chipmos Technologies Inc
Chipmos Technologies Bermuda
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Application filed by Chipmos Technologies Inc, Chipmos Technologies Bermuda filed Critical Chipmos Technologies Inc
Priority to TW96120413A priority Critical patent/TW200849511A/en
Publication of TW200849511A publication Critical patent/TW200849511A/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

Disclosed is a tape type semiconductor package with improved thermal dissipation. The semiconductor package mainly comprises a flexible substrate, a chip and a flexible radiator resin. The chip is disposed inside a chip-mounting region of the substrate and electrically connected with a plurality of leads of the substrate. The active surface of the chip faces the substrate. The flexible radiator resin is formed on the substrate and thermally coupled to at least the sides of the chip to increase heat dissipating area of the chip but not to affect the product' s flexibility.

Description

200849511 九、發明說明: 【發明所屬之技術領域】 本發明係有關於一種捲帶式半導體封裝構造,特別係有 關於一種增進散熱效益之捲帶式半導體封裝構造。 【先前技術】 捲帶式半導體封裝構造,例如薄膜覆晶封裝構造(c〇F package, Chip-On-Film package)與捲帶承載封裝構造(TCp, f, CarHer Package),具有可撓曲性與薄化的優點,目前可 ' 運用於顯示器㈣IC之封裝 '然而隨著積體轉製程的演 進,基板之端子間隙越來越小,晶片尺寸亦越來越小。故晶 片工作時,熱能集中在越小的空間内,導致晶片溫度越來越 高。這種容易積熱的現象會導致晶片無法正常運作,亦會引 起金屬遷移(migration)導致耐用度不佳的問題。 如第!圖所示,習知捲帶式半導體封裝構造1〇〇主要是 以一可撓性基板110作為晶片載體,該可撓性基板丨1〇具有 Ο 上表面ill與下表面1丨2,並具有複數個引腳113。一 晶片120係設置於該可撓性基板11〇之上表面m並以其凸 塊12 1電性連接至該些引腳i i 3。另,以點塗形成之一封裝 膠體130形成於該晶片120與該可撓性基板ιι〇之間,但顯 露該晶片120之背面122以及該可撓性基板ug之挽曲部 位。隨著該晶片120之尺寸越來越小與積體電路密集化,晶 片的集熱問題將更顯重要。習知捲帶式半導體封裝構造ι〇〇 在接合與運作時,發現該晶片12〇高達攝氏一百多度,會有 熱當或產品損毀之虞。 5 200849511 【發明内容】 本發明之主要目的係在於提供一種增進散熱效益之 捲帶式半導體封裝構造,藉由可撓性散熱樹脂熱耦合至 晶片之配置方式,增加晶片之導熱面積並且保持捲帶 式產品之可撓曲性,有效降低晶片工作時所產生之熱 能,以增加其工作壽命。 本發明的目的及解決其技術問題是採用以下技術 方案來實現的。依據本發明,一種增進散熱效益之捲帶 式半導體封裝構造係主要包含一可撓性基板、一晶片以 及至少一可撓性散熱樹脂。該可撓性基板係具有一上 表面與一下表面,該上表面係‘界定有一晶片設置區, 該可撓性基板係具有複數個引腳。該晶片係設置於該 可撓性基板之該晶片設置區内並電性連接至該些引 腳,該 片係具有一主動面、 一背面以及複數個側面, 其中該主動面係朝向該可撓性基板。該可撓性散熱樹 ϋ 脂係形成於該可撓性基板之該上表面並至少熱耦合至 片之該些側面 /本發明的目的及解決其技術問題還可採用以下技 術措施進一步實現。 在前述的捲帶式半導體封裝構造中, 該可撓性散熱樹脂 之該背面。 之厚度係可不低於該晶片之該背面。 在前述的捲帶式半導體封裝構造中BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tape and tape type semiconductor package structure, and more particularly to a tape and tape type semiconductor package structure which improves heat dissipation efficiency. [Prior Art] Tape and Reel Semiconductor Package Structure, such as chip-on-film package (c〇F package, Chip-On-Film package) and tape-and-container package structure (TCp, f, CarHer Package), with flexibility With the advantages of thinning, it can be used in the display (IV) IC package. However, with the evolution of the integrated process, the terminal gap of the substrate is getting smaller and smaller, and the chip size is getting smaller and smaller. Therefore, when the wafer is in operation, the heat is concentrated in a smaller space, resulting in an increase in the temperature of the wafer. This tendency to accumulate heat can cause the wafer to malfunction and cause metal durability to cause poor durability. As the first! As shown, the conventional tape-and-reel semiconductor package structure 1 is mainly a flexible substrate 110 having a top surface ill and a lower surface 1 丨 2 and having a top surface ill and a lower surface 1 丨 2 A plurality of pins 113. A wafer 120 is disposed on the upper surface m of the flexible substrate 11A and electrically connected to the pins i i 3 by the bumps 12 1 . Further, one of the encapsulants 130 formed by dot coating is formed between the wafer 120 and the flexible substrate, but the back surface 122 of the wafer 120 and the curved portion of the flexible substrate ug are exposed. As the size of the wafer 120 becomes smaller and the integrated circuit is denser, the heat collecting problem of the wafer will become more important. Conventional Tape and Reel Semiconductor Package Structure ι〇〇 When bonded and operated, it was found that the wafer 12 was as high as one hundred degrees Celsius, and there was a risk of heat or product damage. 5 200849511 SUMMARY OF THE INVENTION The main object of the present invention is to provide a tape-and-reel semiconductor package structure that enhances heat dissipation benefits, by thermally coupling a flexible heat-dissipating resin to a wafer, increasing the heat-conducting area of the wafer and maintaining the tape. The flexibility of the product effectively reduces the heat generated by the wafer during operation to increase its working life. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. According to the present invention, a tape-and-reel package structure for improving heat dissipation benefits mainly includes a flexible substrate, a wafer, and at least one flexible heat-dissipating resin. The flexible substrate has an upper surface and a lower surface that defines a wafer mounting region having a plurality of pins. The chip is disposed in the wafer mounting region of the flexible substrate and electrically connected to the pins, the film has an active surface, a back surface and a plurality of sides, wherein the active surface is oriented toward the flexible Substrate. The flexible heat-dissipating resin is formed on the upper surface of the flexible substrate and is at least thermally coupled to the sides of the sheet. The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures. In the above-described tape-and-reel semiconductor package structure, the back surface of the flexible heat-dissipating resin. The thickness can be no less than the back side of the wafer. In the aforementioned tape and reel type semiconductor package construction

述的捲帶式半導體封裝構造中 該可撓性散熱樹脂 可另包含一封裝膠 6 200849511 體,其係形成於該晶片與該可撓性基板之間。 在前述的捲帶式半導體封裝構造中,該可撓性散熱樹脂 之導熱係數與可撓性皆可高於該封裝膠體。 在前述的捲帶式半導體封梦糂、皮Α 土 守篮对裝構造中,該可撓性散熱樹脂 係可包覆該封裝膠體。 在前述的捲帶式半導體封梦椹、 子蒞对忒構造中,該可撓性基板之晶 片設置區係可為一裳置孔,兮继 1札4封裝膠體更形成於該裝置孔 内0 該可撓性散熱樹脂 該可撓性散熱樹脂 該可撓性散熱樹脂 該可撓性基板係可 在前述的捲帶式半導體封襞構造中 係具有大於1.0 w/mk之導熱係數。 在前述的捲帶式半導體封裝構造中 係具有介於30至300Mpa之折曲強度c 在前述的捲帶式半導體封裝構造中 係可為點塗膠體或膠片。 在前述的捲帶式半導體封裝構造中 ϋ 具有-防銲層’並且該防銲層與該可撓性散熱樹脂::覆蓋 該些引腳之複數個外引腳。 在月〗述的捲帶式半導體封# ★甚、生士 Ή體封裝構造中’該可撓性散熱樹脂 係可附著於該防銲層。 在前述的捲帶式半導體封裝構造中,可另包含—第二可 :性散熱樹脂’其係圖案化形成於該可撓性基板之該上表面 在遺晶片設置區之外之區域。 在刖述的捲帶式半導體射奘错 谢mi 中,該第二可撓性散熱 ^知係可為矩陣或梳形。 7 200849511 在前述的捲帶式半導體封裝構造中,可另包含一第二可 換性散熱樹脂,其係形成於該可撓性基板之該下表面。 在則述的捲帶式半導體封裝構造中,該第二可撓性散熱 樹脂係可對應於該可撓性散熱樹脂之下方。 【實施方式】 依據本發明之第一具體實施例,如第2及3圖所 示,揭示一種增進散熱效益之捲帶式半導體封裝構造200, 其係主要包含一可撓性基板2 1 0、一晶片2 2 0以及一第 I : 一可撓性散熱樹脂2 3 0。該可撓性基板2 1 0係具有一 上表面211與一下表面212,該上表面211係界定有一 晶片設置區2 1 3,以供該晶片2 2 0之設置。該可撓性 基板2 1 0並具有複數個引腳2 1 4,其一端延伸至該晶 片設置區21 3内,另一端往外形成一外露之外引腳 2 1 5。在本實施例中,該可撓性基板2 1 0係為薄膜覆晶 封裝載膜(COF film),兩側可設有等間距之鏈齒孔。該可撓 U 性基板210係可具有一防銲層216,其係具有一開孔,用以 界定該晶片設置區2 1 3。而該些引腳2 1 4係位於該可撓 性基板2 1 0之該上表面2 1 1。 該晶片220係設置於該可撓性基板2 1 0之該晶片設 置區213内並電性連接至該些引腳214。該晶片220 係具有一主動面 221、一背面 222以及複數個側面 223,其中該主動面221係朝向該可撓性基板210。在 本實施例中,該主動面221上設有複數個凸塊224, 如金凸塊或其它導電凸塊,其係為該晶片220内部積 8 200849511 體電路之外接端。而該晶片220係可為顯示器驅動晶 片或其它特殊應用積體電路(ASIC)。可利用熱壓合使 該些凸塊224電性連接至該些引腳214之内端。 該第一可撓性散熱樹脂23 0係形成於該可挽性某 板210之該上表面211並至少熱耦合至該晶片22〇之 該些側面223 ’用以擴大該晶片220之散熱面積。在 本實施例中,該第一可撓性散熱樹脂23〇之厚度係可不低 f, 於該晶片220之該背面222,故該第一可撓性散熱樹脂230 係可更熱耦合至該晶片220之該背面222。依材料特性而 έ ’該第一可撓性散熱樹脂230應具有大於ί ο w/mk之導 熱係數(thermal conductivity)以及介於30至3OOMpa之折曲 強度(又可稱為抗張彈性,tensiie eiasticity),例如導熱 石夕膠,可Θ含有散熱粒子。較佳地,該第一可挽性散熱樹脂 230之導熱係數係接近該晶片22〇之導熱係數(約2 3 W/mk),可為熱塑性或熱固性。依形成方法而言,該第一可 〇 撓性散熱樹脂230係可為點塗膠體,可沿用既有的捲帶封裝 設備之點膠機與烘烤爐,或亦可為一膠片,用以黏貼方式形 成於該可撓性基板21〇上。依形成位置而言,該第一可撓 性散熱樹脂230係可貼附於該防銲層2 i 6。 較佳地,再如第2圖所示,該捲帶式半導體封裝構造2〇〇 係可另包含一封裝膠體240,其係形成於該晶片220與該可 撓性基板21G之間’如包覆該些凸塊以。然該第_可捷性 政熱樹月曰230之導熱係數與可撓性皆應高於該封裝膠體 240,以維持產品的撓曲性。在本實施例中,該第—可繞性 9 200849511 散熱樹脂230係可包覆該封裝膠體24〇。 此外’再如第2圖所示’該捲帶式半導體封裝構造2〇〇 係可另包含一第二可撓性散熱樹脂250,其係形成於該可撓 性基板210之該下表面212,藉以擴大散熱面積與提供另一 政熱面。在本實施例中,該第二可撓性散熱樹脂25〇係可對 應於該第一可撓性散熱樹脂23〇之下方。該第二可撓性散熱 樹脂250之材料特性與形成方法係可與該第一可撓性散熱樹 脂230相同。In the tape and reel type semiconductor package structure, the flexible heat dissipating resin may further comprise an encapsulant 6 200849511 formed between the wafer and the flexible substrate. In the above-described tape-and-reel semiconductor package structure, the flexible heat-dissipating resin may have a higher thermal conductivity and flexibility than the package. In the above-described tape-and-reel type semiconductor enveloping and skin-containing basket-attaching structure, the flexible heat-dissipating resin can coat the encapsulant. In the above-described tape-and-reel type semiconductor enveloping device, the wafer setting area of the flexible substrate may be a skirting hole, and the 兮继1 扎4 encapsulation colloid is further formed in the device hole. The flexible heat dissipating resin, the flexible heat dissipating resin, and the flexible heat dissipating resin. The flexible substrate may have a thermal conductivity of more than 1.0 w/mk in the tape-wound semiconductor sealing structure. The above-described tape-and-reel semiconductor package structure has a flexural strength c of 30 to 300 MPa. In the above-described tape-and-reel semiconductor package structure, it may be a dot-coated colloid or film. In the above-described tape-and-reel semiconductor package structure, ϋ has a solder mask layer and the solder resist layer and the flexible heat-dissipating resin: cover a plurality of outer leads of the pins. In the tape-type semiconductor package described in the month, the flexible heat-dissipating resin can be attached to the solder resist layer. In the above-described tape-and-reel semiconductor package structure, a second heat-dissipating resin may be further formed in a region in which the upper surface of the flexible substrate is outside the wafer-disposed region. In the reeling of the tape-type semiconductor shot 奘 mi, the second flexible heat dissipation can be a matrix or a comb shape. 7 200849511 In the tape and reel type semiconductor package structure described above, a second variable heat dissipating resin may be further formed on the lower surface of the flexible substrate. In the tape-and-reel semiconductor package structure described above, the second flexible heat-dissipating resin may correspond to the lower side of the flexible heat-dissipating resin. [Embodiment] According to a first embodiment of the present invention, as shown in FIGS. 2 and 3, a tape-type semiconductor package structure 200 for improving heat dissipation benefits is disclosed, which mainly includes a flexible substrate 210. A wafer 2 2 0 and an I: a flexible heat-dissipating resin 2 300. The flexible substrate 210 has an upper surface 211 and a lower surface 212. The upper surface 211 defines a wafer mounting region 2 1 3 for the wafer 220. The flexible substrate 2 10 has a plurality of pins 2 1 4 , one end of which extends into the wafer setting region 21 3 , and the other end forms an exposed outer pin 2 15 . In this embodiment, the flexible substrate 210 is a film-on-film package film (COF film), and both sides may be provided with equally spaced sprocket holes. The flexible U substrate 210 can have a solder mask layer 216 having an opening for defining the wafer setting region 2 1 3 . The pins 2 14 are located on the upper surface 2 1 1 of the flexible substrate 2 1 0. The wafer 220 is disposed in the wafer setting region 213 of the flexible substrate 210 and electrically connected to the pins 214. The wafer 220 has an active surface 221, a back surface 222, and a plurality of side surfaces 223, wherein the active surface 221 faces the flexible substrate 210. In this embodiment, the active surface 221 is provided with a plurality of bumps 224, such as gold bumps or other conductive bumps, which are external ends of the internal circuit of the wafer 220. The wafer 220 can be a display drive chip or other special application integrated circuit (ASIC). The bumps 224 can be electrically connected to the inner ends of the pins 214 by thermal pressing. The first flexible heat dissipating resin 205 is formed on the upper surface 211 of the slab 210 and is at least thermally coupled to the side surfaces 223' of the wafer 22 to expand the heat dissipation area of the wafer 220. In this embodiment, the thickness of the first flexible heat dissipating resin 23 is not lower than f on the back surface 222 of the wafer 220, so the first flexible heat dissipating resin 230 can be more thermally coupled to the wafer. The back side 222 of 220. Depending on the material properties, the first flexible heat-dissipating resin 230 should have a thermal conductivity greater than ίο/mk and a flexural strength of 30 to 300 MPa (also known as tensile elasticity, tensiie). Eiasticity), such as heat-transfer stone, can contain heat-dissipating particles. Preferably, the thermal conductivity of the first chargeable heat-dissipating resin 230 is close to the thermal conductivity (about 23 W/mk) of the wafer 22, and may be thermoplastic or thermosetting. According to the forming method, the first flexible heat dissipating resin 230 can be a point coating gel, can be used in a conventional tape winding device and a baking machine, or can be a film for A pasting method is formed on the flexible substrate 21A. The first flexible heat dissipating resin 230 can be attached to the solder resist layer 2 i 6 depending on the formation position. Preferably, as shown in FIG. 2, the tape-and-reel package structure 2 can further include an encapsulant 240 formed between the wafer 220 and the flexible substrate 21G. Cover the bumps. However, the thermal conductivity and flexibility of the first thermal conductivity month 230 should be higher than the encapsulation colloid 240 to maintain the flexibility of the product. In the present embodiment, the first rewindability 9 200849511 heat dissipating resin 230 can coat the encapsulant 24 〇. In addition, as shown in FIG. 2, the tape-and-reel package structure 2 can further include a second flexible heat-dissipating resin 250 formed on the lower surface 212 of the flexible substrate 210. In order to expand the heat dissipation area and provide another political surface. In this embodiment, the second flexible heat dissipating resin 25 can be disposed below the first flexible heat dissipating resin 23A. The material properties and formation method of the second flexible heat-dissipating resin 250 can be the same as that of the first flexible heat-dissipating resin 230.

因此,該捲帶式半導體封裝構造2〇〇係藉由該第一可撓 性散熱樹脂2 3 0熱耦合至該晶片2 2 〇之配置方式,有 效增加該晶片220之導熱面積並且保持捲帶式產品之可 撓曲性,有效降低晶片220工作時所產生之熱能,以增 加其工作壽命。 在本發明之第二具體實施例中,如第4及5圖所 示,揭示另一種增進散熱效益之捲帶式半導體封裝構造 300,其係主要包含一可撓性基板31〇、一 θ 曰曰月3 20以 及一第一可撓性散熱樹脂3 3 0,主要元件係與第一具 體實施例相同。該可撓性基板3 1 0之上表面3丨丨係界 定有一晶片設置區3 1 3。該可撓性基板3丨〇係具有複 數個引腳3 1 4,其一端往外形成一外露之外引腳3丨5。 一封裝膠體340係可形成於該晶片320鱼兮7 t 一孩可撓性基板 31〇之間。當該可換性基板31〇係為薄膜覆晶封裝載膜 (COF film),該晶片設置區3 1 3係由一防鋥s, 、 I 3 1 6之開孔 所界定。當該可挽性基板3 1 0係為捲帶承载封穿 200849511 tape),該晶片設置區313係可為一裝置孔(device h〇le),一 封裝膠體更形成於該裝置孔内(圖未纟會出 該晶片320係設置於該可撓性基板3 j 〇之該晶片設 置區313内並以其凸塊324電性連接至該些引腳314。 该晶片3 2 0係具有一主動面3 2 i、一背面3 2 2以及複 數個側面3 2 3,其中該主動面3 2丨係朝向該可撓性基 板 3 1 0。Therefore, the tape-type semiconductor package structure 2 is configured to thermally increase the heat-conducting area of the wafer 220 and maintain the tape by the thermal coupling of the first flexible heat-dissipating resin 230 to the wafer 2 2 〇. The flexibility of the product effectively reduces the thermal energy generated by the wafer 220 during operation to increase its working life. In a second embodiment of the present invention, as shown in FIGS. 4 and 5, another tape-and-reel package structure 300 for improving heat dissipation benefits is disclosed, which mainly includes a flexible substrate 31〇, a θ 曰The main component is the same as the first embodiment in the month of the first month and the first flexible heat dissipating resin 303. The upper surface 3 of the flexible substrate 310 is bounded by a wafer setting region 3 1 3 . The flexible substrate 3 has a plurality of pins 3 1 4, one end of which forms an exposed external pin 3丨5. An encapsulant 340 can be formed between the wafer 320 and the flexible substrate 31〇. When the replaceable substrate 31 is a film-on-film package (COF film), the wafer set region 3 1 3 is defined by an opening of the anti-sputum s, I 3 16 . When the switchable substrate 310 is a tape carrier-sealing seal (200849511 tape), the wafer setting region 313 can be a device hole, and an encapsulant is formed in the device hole (FIG. The chip 320 is disposed in the wafer mounting region 313 of the flexible substrate 3 j 并 and is electrically connected to the pins 314 by bumps 324. The wafer 3 2 0 has an active The surface 3 2 i, a back surface 3 2 2 and a plurality of side surfaces 3 2 3 , wherein the active surface 32 2 is oriented toward the flexible substrate 3 10 .

該第一可撓性散熱樹脂33〇係形成於該可撓性基 板310之该上表面311並熱耦合至該晶片32〇之該些 側面323。在本實施例中,該第一可撓性散熱樹脂33〇 係不覆盍該晶片320之背面322,同樣具有擴大該晶 片320散熱面積之功效。 此外,該捲帶式半導體封裝構造3〇〇係可另包含一第二 可換性散熱樹脂350,其係圖案化形成於該可撓性基板3 1〇 之忒上表面311在豸曰曰片设置區313之外之區域。如第$圖 所示’該第二可撓性散熱樹脂35Q係可為梳形,用以增加該 可撓性基板310之散熱面積。 本發明之第三具體實施例係說明第二可撓性散熱樹 脂可以有不同的形狀變化。如第6圖所示,—種捲帶式半導 體封裝構造之主要元件,例如可撓性基板3im 32〇、 第一可撓性散熱樹脂330,係與第二具體實施例相同,故 相同其中’該捲帶式半導體封裝構造另包含一 層圖案化之第一可撓性散熱樹脂35〇,,其係形成於該可挽性 基板310之上表面並為矩陣配置。 11 200849511 Γ, c 以上所述,僅H .^ , 疋本發明的較佳實施例而已,並非對本發明作任何形々 卫开支丁 式上的限制,雖然本發明已營 施例揭露如上 U已以杈佳實、 並非用以限定本發明,权h勃籴 本項技術者,在不胺齡4 任何熱悉 作的任何簡單修杜欲 fe圍内’所 少、等效性變化與修飾,皆、、& 1 0 i 發明的技術範圍内。 自涵盍於本 【圖式簡單說明】 習知捲帶式半導體封裝構造之截面示意圖。 :::發明之第一具體實施例,一種增進散熱效益 捲帶式半導體封裝構造之截面示意圖。 依據本發明之第-具體實施例,該捲帶式半導體封 裝構造之頂面示意圖。 依據本發明之第二具體實施例,另一種增進散熱效 盈之捲帶式半導體封裝構造之截面示意圖。 依據本發明之第二具體實施例,該捲帶式半導體封 裝構造之頂面示意圖。 依據本發明之第三具體實施例,另一種捲帶式半導 體封裝構造之頂面示意圖。 【主要元件符號說明】 100捲帶式半導體封装構造 π 〇可撓性基板 111上表面 113引腳 120晶片 121凸塊 130封裝膠體 第第 圖圖 第3圖 第4圖 第5圖 第6圖 11 2下表面 122背面 12 200849511 200捲帶式半導體封裝構造 210可撓性基板 211上表面 213晶片設置區 214引腳 216防銲層 212下表面 215外引腳The first flexible heat dissipating resin 33 is formed on the upper surface 311 of the flexible substrate 310 and thermally coupled to the side surfaces 323 of the wafer 32. In this embodiment, the first flexible heat dissipating resin 33 does not cover the back surface 322 of the wafer 320, and has the same effect of expanding the heat dissipating area of the wafer 320. In addition, the tape-type semiconductor package structure 3 can further include a second replaceable heat-dissipating resin 350, which is patterned on the upper surface 311 of the flexible substrate 3 1 . An area other than the area 313 is set. As shown in Fig. $, the second flexible heat dissipating resin 35Q may be comb-shaped to increase the heat dissipating area of the flexible substrate 310. A third embodiment of the invention illustrates that the second flexible heat dissipating resin can have different shape changes. As shown in FIG. 6, the main components of the tape-wound type semiconductor package structure, such as the flexible substrate 3im 32〇 and the first flexible heat-dissipating resin 330, are the same as those of the second embodiment, so that the same The tape-and-reel semiconductor package structure further includes a patterned first flexible heat-dissipating resin 35 形成 formed on the upper surface of the tractable substrate 310 and arranged in a matrix. 11 200849511 Γ, c As described above, only H.^, the preferred embodiment of the present invention, is not intended to impose any limitation on the invention, although the present invention has been disclosed as In order to limit the invention, it is not intended to limit the invention, and the person who is the subject of this technology, in any of the simple ages, is not known to have any simplifications, equivalence changes and modifications. All of them are within the technical scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS [Simplified illustration of the drawings] A schematic cross-sectional view of a conventional tape and reel type semiconductor package structure. ::: The first embodiment of the invention, a cross-sectional schematic view of a ribbon-type semiconductor package structure that enhances heat dissipation benefits. In accordance with a first embodiment of the present invention, a top plan view of the tape-and-reel semiconductor package construction. According to a second embodiment of the present invention, another schematic cross-sectional view of a ribbon-type semiconductor package structure for improving heat dissipation is provided. In accordance with a second embodiment of the present invention, a top plan view of the tape-and-reel semiconductor package construction is shown. Another top view of a tape and reel package structure in accordance with a third embodiment of the present invention. [Description of main component symbols] 100-volume tape semiconductor package structure π 〇Flexible substrate 111 Upper surface 113 Pin 120 Wafer 121 Bump 130 Package colloids Fig. 3Fig. 4 Fig. 5 Fig. 6 Fig. 11 2 lower surface 122 back surface 12 200849511 200 tape-type semiconductor package structure 210 flexible substrate 211 upper surface 213 wafer setting area 214 pin 216 solder resist layer 212 lower surface 215 outer pin

220晶片 221主動面 223側面 224凸塊 230第一可撓性散熱樹脂 240封裝膠體 250第二可撓性散熱樹脂 300捲帶式半導體封裝構造 3 1 0可撓性基板 3 11上表面 313晶片設置區 314引腳 3 1 6防鲜層 320晶片 321主動面 222背面 312下表面 3 15外引腳 322背面 323側面 324凸塊220 wafer 221 active surface 223 side 224 bump 230 first flexible heat dissipating resin 240 encapsulant 250 second flexible heat dissipating resin 300 tape reel type semiconductor package structure 3 1 0 flexible substrate 3 11 upper surface 313 wafer setting Area 314 Pin 3 1 6 Anti-fresh layer 320 Wafer 321 Active surface 222 Back 312 Lower surface 3 15 Outer pin 322 Back 323 Side 324 Bump

330第一可撓性散熱樹脂 340封裝膠體 350第二可撓性散熱樹脂 350’第二可撓性散熱樹脂 13330 first flexible heat dissipating resin 340 encapsulant 350 second flexible heat dissipating resin 350' second flexible heat dissipating resin 13

Claims (1)

200849511 十、申請專利範圍: 1 種增進散熱效益之捲帶式半導體封裝構造,包含: 一可撓性基板,其係具有一上表面與一下表面,該上表 面係界定有一晶片設置區,該可撓性基板係具有複數個 引腳; 曰曰片’其係設置於該可撓性基板之該晶片設置區内並 電性連接至該些引腳,該晶片係具有一主動面、一背面 以及複數個側面,其中該主動面係朝向該可撓性基板; 以及 一第一可撓性散熱樹脂,其係形成於該可撓性基板之該 上表面並至少熱耦合至該晶片之該些側面。 2、 如申請專利範圍第1項所述之增進散熱效益之捲帶式半 導體封裝構造,其中該第一可撓性散熱樹脂之厚度係不 低於該晶片之該背面。 3、 如申請專利範圍第2項所述之增進散熱效益之捲帶式半 〇 導體封裳構造,其中該第一可撓性散熱樹脂係更熱耦合 至該晶片之該背面。 4、 如申請專利範圍第1項所述之增進散熱效益之捲帶式半 導體封裝構造,另包含一封裝膠體,其係形成於該晶片 與該可撓性基板之間。 5、 如申請專利範圍第4項所述之增進散熱效益之捲帶式半 導體封裝構造,其中該第一可撓性散熱樹脂之導熱係數 與可撓性皆高於該封裝膠體。 6、 如申請專利範圍第5項所述之增進散熱效益之捲帶式半 14 200849511 導體封裳構造,其中該第一可撓性散熱樹脂係包覆該封 裝膠體。 7、 如申請專利範圍第5項所述之增進散熱效益之捲帶式半 導體封裝構造,其中該可撓性基板之晶片設置區係為一 裝置孔’該封裝膠體更形成於該裝置孔内。 8、 如申請專利範圍第1項所述之增進散熱效益之捲帶式半 導體封裴構造,其中該第一可撓性散熱樹脂係具有大於 1·〇 W/mk之導熱係數。 9、 如申請專利範圍第1項所述之增進散熱效益之捲帶式半 導體封裝構造,其中該第一可撓性散熱樹脂係具有介於 30至30〇Mpa之折曲強度。 10 =如申請專利範圍第丨項所述之增進散熱效益之捲帶式 半導體封裝構造,其中該第—可撓性散熱樹脂係為點塗 膠體或是膠片。 11 "如申睛專利範圍第1項所述之增進散熱效益之捲帶式 半導體封裝構造,其中該可撓性基板係具有一防銲層, 並且该防銲層與該第一可撓性散熱樹脂皆不覆蓋該些引 腳之複數個外引腳。 12 \如申明專利範圍第u項所述之增進散熱效益之捲帶式 半導體封裝構造’其中該第_可撓性散熱樹脂係附著於 該防銲層。 一如申叫專利範圍第i項所述之增進散熱效益之捲帶式 半導體封裝構造’另包含一第二可撓性散熱樹脂,其係 圖案化形成於該可撓性基板之該上表面在言亥晶片設置區 15 200849511 之外之區域β 4,如申·。月專利範圍帛13項所述之增進散熱效益之捲帶式 半導體封|構造’其中該第二可撓性散熱樹脂係為矩陣 或梳形。 ^如申明專利範圍第1項所述之增進散熱效益之捲帶式 半導體封裝構造,另包含一第二可撓性散熱樹脂,其係 形成於該可撓性基板之該下表面。 Γ 16 _如申叫專利乾圍第15項所述之增進散熱效益之捲帶式 半導體封裝構造,其中該第二可撓性散熱樹脂係對應於 該第一可撓性散熱樹脂之下方。 16200849511 X. Patent Application Range: A tape-and-reel semiconductor package structure for improving heat dissipation benefits, comprising: a flexible substrate having an upper surface and a lower surface, the upper surface defining a wafer setting area, The flexible substrate has a plurality of pins; the cymbal sheet is disposed in the wafer mounting region of the flexible substrate and electrically connected to the pins, the wafer has an active surface, a back surface, and a plurality of sides, wherein the active surface faces the flexible substrate; and a first flexible heat dissipating resin formed on the upper surface of the flexible substrate and thermally coupled to at least the sides of the substrate . 2. The tape-and-reel semiconductor package structure of claim 1, wherein the first flexible heat-dissipating resin has a thickness not less than the back surface of the wafer. 3. A tape-and-reel type semi-conductor sealing structure as disclosed in claim 2, wherein the first flexible heat dissipating resin is more thermally coupled to the back side of the wafer. 4. A tape-and-reel semiconductor package structure for improving heat dissipation according to claim 1 of the patent application, further comprising an encapsulant formed between the wafer and the flexible substrate. 5. The tape-type semiconductor package structure of claim 4, wherein the first flexible heat-dissipating resin has a higher thermal conductivity and flexibility than the package. 6. A tape-wound half-heating structure according to claim 5, wherein the first flexible heat-dissipating resin coats the packaged colloid. 7. The tape-type semiconductor package structure of claim 5, wherein the wafer mounting area of the flexible substrate is a device hole. The encapsulant is further formed in the device hole. 8. The tape-type semiconductor sealing structure for improving heat dissipation according to claim 1, wherein the first flexible heat-dissipating resin has a thermal conductivity greater than 1·〇 W/mk. 9. The tape-and-reel semiconductor package structure of claim 1, wherein the first flexible heat-dissipating resin has a flexural strength of between 30 and 30 MPa. 10 = A tape-and-reel semiconductor package structure for improving heat dissipation as described in the scope of the patent application, wherein the first flexible heat-dissipating resin is a dot-coating film or a film. The tape-type semiconductor package structure of claim 1 , wherein the flexible substrate has a solder resist layer, and the solder resist layer and the first flexible layer The heat-dissipating resin does not cover the plurality of external pins of the pins. 12] A tape-and-reel type semiconductor package structure in which the heat dissipation benefit is improved as described in the above-mentioned patent scope, wherein the first flexible heat-dissipating resin is adhered to the solder resist layer. The tape-and-reel semiconductor package structure as described in claim i of the patent scope includes a second flexible heat-dissipating resin patterned on the upper surface of the flexible substrate. Yanhai wafer setting area 15 outside the 200849511 area β 4, such as Shen·. The tape-type semiconductor package|structure in which the heat-dissipating benefit is described in the above-mentioned patent scope 其中13, wherein the second flexible heat-dissipating resin is a matrix or a comb shape. The tape-type semiconductor package structure for improving heat dissipation according to claim 1, further comprising a second flexible heat-dissipating resin formed on the lower surface of the flexible substrate. The tape-type semiconductor package structure for improving heat dissipation according to claim 15, wherein the second flexible heat-dissipating resin corresponds to the lower side of the first flexible heat-dissipating resin. 16
TW96120413A 2007-06-06 2007-06-06 Tape type semiconductor package with improved thermal dissipation TW200849511A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI575682B (en) * 2015-04-02 2017-03-21 南茂科技股份有限公司 Chip package structure and stacked chip package structure
TWI618205B (en) * 2015-05-22 2018-03-11 南茂科技股份有限公司 Chip on film package and heat dissipation method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI575682B (en) * 2015-04-02 2017-03-21 南茂科技股份有限公司 Chip package structure and stacked chip package structure
TWI618205B (en) * 2015-05-22 2018-03-11 南茂科技股份有限公司 Chip on film package and heat dissipation method thereof

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