TW200849247A - Method for operating non-volatile storage and non-volatile storage system - Google Patents

Method for operating non-volatile storage and non-volatile storage system Download PDF

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TW200849247A
TW200849247A TW097105962A TW97105962A TW200849247A TW 200849247 A TW200849247 A TW 200849247A TW 097105962 A TW097105962 A TW 097105962A TW 97105962 A TW97105962 A TW 97105962A TW 200849247 A TW200849247 A TW 200849247A
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Taiwan
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volatile storage
stylization
pulse
storage elements
program
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TW097105962A
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Chinese (zh)
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TWI374446B (en
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Nima Mokhlesi
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Sandisk Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)

Abstract

After erasing a plurality of non-volatile storage elements, a soft programming process is performed to tighten the erase threshold distribution for the non-volatile storage elements. During the soft programming process, the system identifies the number of programming pulses needed for a first set of the non-volatile storage elements to complete the soft programming and the number of programming pulses needed for the all but a last set of non-volatile storage elements to complete soft programming. These two numbers are used to characterize the threshold distribution of the non-volatile storage elements. This characterization of the threshold distribution and the program pulse step size are used to limit the number of verify pulses used during subsequent programming.

Description

200849247 九、發明說明： 【發明所屬之技術領域】 本發明係關於非揮發性儲存器之技術。 本申請案主張Nima Mokhlesi於2007年2月20曰申請之臨 時專利申請案第 60/890,832號 ’’Diagonal Sequence Write’f2 權利，該案之全文以引用的方式併入本文中。 本專利申請與下列申請案參考交互參照，並且該等案之 全文以引用的方式併入本文中：發明人Nima Mokhlesi於 與本申請案同日申請之美國專利申請案第_ (代 理人檔案號碼第SAND-0123 7US0號）標題為"Multiple Pass Write Sequence For Non，Volatile Storage";發明人Nima Mokhlesi於與本申請案同日申請之美國專利申請案 第_ (代理人檔案號碼第SAND-01237US2號） 標題為 ’’Non-Volatile Storage Apparatus With Multiple Pass Write Sequence” ；發明人Nima Mokhlesi於與本申請案同曰 申請之美國專利申請案第_ (代理人檔案號碼 第 SAND-01239US0 號）標題為"Variable Initial Program Voltage Magnitude For Non-Volatile Storage” ；發明人Nima Mokhlesi於與本申請案同日申請之美國專利申請案 第_— (代理人檔案號碼第SAND-01239US1號） 標題為"Non-Volatile Storage Apparatus With Variable Initial Program Voltage Magnitude” ；及發明人 Nima Mokhlesi於與本申請案同日申請之美國專利申請案 第_ (代理人檔案號碼第SAND-01240US1號） 128993.doc 200849247 榇題為 Non-Volaule Storage Apparatus With Dynamic200849247 IX. INSTRUCTIONS: TECHNICAL FIELD OF THE INVENTION The present invention relates to the technology of non-volatile storage. The present application claims the benefit of the instant patent application Serial No. 60/890,832, the entire disclosure of which is incorporated herein by reference. This patent application is hereby incorporated by reference in its entirety by reference in its entirety in the the the the the the the the the the the the the the the the the the the the the SAND-0123 No. 7US0) titled "Multiple Pass Write Sequence For Non, Volatile Storage"; Inventor Nima Mokhlesi, US Patent Application No. _ (Attorney Docket No. SAND-01237US2) filed on the same day as this application The title is ''Non-Volatile Storage Apparatus With Multiple Pass Write Sequence'; and the inventor's U.S. Patent Application No. _ (Attorney Docket No. SAND-01239US0), filed concurrently with the present application, is entitled " Variable Initial Program Voltage Magnitude For Non-Volatile Storage; Inventor Nima Mokhlesi, U.S. Patent Application No. _- (Attorney Docket No. SAND-01239US1), filed on the same day as the present application, titled "Non-Volatile Storage Apparatus With Variable Initial Program Voltage Magnitude"; and inventor Nima U.S. Patent Application No. s. (Attorney Docket No. SAND-01240US1) filed by Mokhlesi on the same day as this application. 128993.doc 200849247 Title: Non-Volaule Storage Apparatus With Dynamic

Verify Based on Threshold Voltage Distribution** 〇 【先前技術】 半導體記憶體已愈來愈普遍地用於各種電子裝置中。例 如，蜂巢式電話、數位相機、個人數位助理、行動計算裝 置非行動计异裝置或其他裝置中使用非揮發性半導體記 憶體。電可擦除可程式化唯讀記憶體（EEpR〇M)及快閃記 憶體係最受歡迎的非揮發性半導體記憶體。 EEPROM及快閃記憶體兩者皆採用一位於一半導體基板 中之通道區上方並與該通道區絕緣之浮動閘極。浮動閘極 及通道區位於源極區與汲極區之間。一控制閘極設定於該 浮動閘極上方，並與該浮動閘極絕緣。電晶體的臨限電壓 文控於浮動閘極上所保持的電荷量。亦即，在電晶體接通 以容許其源極與汲極之間導通之前所必須施加至控制閘極 的最小電壓量係受控於浮動閘極上的電荷位準。 當程式化諸如一 NAND快閃記憶體裝置等EEpR〇M或快 閃a己丨思體裝置時，通常對該控制閘極施加一程式電壓且將 位元線接地。來自通道之電子被注入至該浮動閘極中。當 電子積聚於在浮動閘極中時，該浮動閘極變成帶負電荷且 記憶體單元的臨限電壓升高，從而使該記憶體單元處於一 已程式化狀態。可在以下專利案中發現更多關於程式化之 資訊：名稱為"Source Side Self Boosting Technique forVerify Based on Threshold Voltage Distribution** 〇 [Prior Art] Semiconductor memory has become more and more popular in various electronic devices. For example, non-volatile semiconductor memory is used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile devices, or other devices. Electrically erasable programmable read-only memory (EEpR〇M) and flash memory system are the most popular non-volatile semiconductor memory. Both EEPROM and flash memory employ a floating gate that is over and insulated from the channel region in a semiconductor substrate. The floating gate and channel region are located between the source region and the drain region. A control gate is disposed above the floating gate and insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge held on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to allow conduction between its source and drain is controlled by the level of charge on the floating gate. When programming an EEpR 〇M or flash a 丨 丨 等 device such as a NAND flash memory device, a program voltage is typically applied to the control gate and the bit line is grounded. Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell rises, thereby causing the memory cell to be in a programmed state. More stylized information can be found in the following patents: Name "Source Side Self Boosting Technique for

Non-Volaile Memory” 之美國專利案 6,859,397 ;名稱為 ’’Detecting Over Programmed Memory” 之美國專利案 128993.doc 200849247 6,917,542； ^^-Programming Non-V〇latile Memory- 之美國專利案6,888,758，所有列舉之三個專利案之全文皆 以引用方式併入本文中。US Patent No. 6,859,397 to Non-Volaile Memory; US Patent No. 128993.doc 200849247 6,917,542, entitled "'Detecting Over Programmed Memory"; US Patent No. 6,888,758 to Programming Non-V〇latile Memory-, all cited The entire contents of the three patents are incorporated herein by reference.

在諸多情形下，程式電麼作為—系列脈衝(稱為程式化 脈衝)施加至控制閘極，其中該等脈衝之量值在每一脈衝 處皆會增加。在程式化脈衝之間’實施一組一個或多個驗 也作業以確定正被程式化之（多個）記憶體單元是否已達到 其目標位準。若—記㈣單元已制其目標位準，則停止 對該記憶體單元之程式化。若—記憶體單元還未達到其目 標位準，則對該記憶體單元繼續進行程式化。 一某些EEPROM及快閃記憶體裝置具有一用來儲存兩個電 荷範圍之浮動閘極，且因此記憶體單元可在兩種狀態（一 =擦除狀態與—已程式化狀態）之間進行程式化/擦除。有 寸將此〖夬閃§己憶體裝置稱為二元記憶體裝置。 夕狀‘悲“己憶體裝置通過識別由禁用範圍分離之多個不 同的有效臨限電壓分佈(或資料狀態)使每個記憶體單元儲 存多個資料位元。每一個不同的臨限電壓分佈均對應該記 憶體裝置中所編碼之資料位元組之—預定值。例如，一儲 存兩個資料位元之記憶體單元使用四個有效的臨限電壓分 佈。-儲存三”料位元之記㈣單元使^财效臨限 電壓分佈。 奴者母個，己憶體單元之資料位元數目（且目&，有效臨 限電壓分佈之數目)增加，-記憶體裝置之資料容量增 加。然而，程式化所需之時間亦增加，，有效臨限電 128993.doc 200849247 壓分佈之數目越大’在程式_之間所f线證作業之數 目越大。❹者通常殘望料其電子裝置儲存資料。例 如，數位相機之使用者不期望在照相之間拖延。 由於記憶體裝置之每個記憶體單元儲存更多的資料位 凡，故增加了對合理程式速度之需要。 【發明内容】In many cases, the program is applied as a series of pulses (called programmed pulses) to the control gate, where the magnitude of the pulses increases at each pulse. A set of one or more tests are performed between the stylized pulses to determine if the memory unit(s) being programmed have reached their target level. If the (4) unit has made its target level, the stylization of the memory unit is stopped. If the memory unit has not reached its target level, the memory unit continues to be programmed. A certain EEPROM and flash memory device has a floating gate for storing two charge ranges, and thus the memory cell can be operated between two states (one = erased state and - programmed state) Stylized/erased. In this case, the device is called a binary memory device. The singular "sorrowful" memory device stores a plurality of data bits for each memory cell by identifying a plurality of different effective threshold voltage distributions (or data states) separated by the disabled range. Each of the different threshold voltages The distribution corresponds to a predetermined value of the data byte encoded in the memory device. For example, a memory cell storing two data bits uses four effective threshold voltage distributions. The note (4) unit makes the financial effect limit voltage distribution. The slave's mother, the number of data bits (and the number of effective threshold voltage distributions) of the memory unit increased, and the data capacity of the memory device increased. However, the time required for stylization has also increased, and the effective limit of power is 128993.doc 200849247 The greater the number of pressure distributions, the greater the number of f-line certificates between programs. The latter usually expects to store data in their electronic devices. For example, users of digital cameras do not expect to delay between photographs. Since each memory unit of the memory device stores more data bits, the need for a reasonable program speed is increased. [Summary of the Invention]

本發明揭示-種限制程式脈衝之間的驗證作業量以提高 程式化速度之方法。 -個實施例包含對複數個非揮發性儲存元件實施一第一 程式化過程及在該第-程式化過程後對該等非揮發性儲存 兀件實施一第二程式化過程。該第二程式化過程包含至少 部分地基於該第一程式化過程之一組驗證作業。 。一個實施例包含對複數個非揮發性儲存元件實施一第一 私式化過程。該第-程式化過程包含向該等非揮發性儲存 兀件施加程式化脈衝。該方法進—步包括在㈣—程式化 過程期間識別所需用來達成—第—結果之第—程式脈衝， 識別一所需用來達成該第一程式化過程之第二結果之第二 程式脈衝，及在該第-程式化過程後對該等非揮發性料 =件實施-第二程式化過程。該第：程式化過程在程式脈 厂之間使用驗證脈衝。基於該第一程式脈 脈衝限制該等驗證脈衝。 弟一以 —個實施例包含擦除複數個非揮發性儲存元件，軟程式 化與擦除相關聯之非揮發性儲存元#，識別一肖第一組完 成该軟程式化之-個或多個非揮發性儲存元件相關聯之第 128993.doc 200849247 一程式脈衝，識別一與第二組完成該軟程式化之一個或多 個非揮發性儲存元件相關聯之第二程式脈衝，及程式化該 等非揮發性儲存元件。該程式化過程包含基於第—數目之 耘式化脈衝與第二數目之程式化脈衝實施驗證作業。 一個實例性實施案包含一組非揮發性儲存元件及與該組 非揮發性儲存元件連通之一個或多個管理電路。該一個或 多個管理電路實施以上所述方法。 【實施方式】 一快閃記憶體系統之實例使用NAND結構，其包括夾在 兩個選擇閘極之間以串聯形式佈置之多個電晶體。該等串 聯電晶體及選擇閘極稱作一 NAND串。圖1為顯示一個 N AND串之俯視圖。圖2為其一等效電路。圖中所繪示 之NAND串包含夾於第一（或汲極側）選擇閘極1與第二 (或源極側）選擇閘極122之間的四個串聯電晶體1 〇〇、1 、 104及106。選擇閘極120經由位元線觸點126將該NAND串 連接至一位元線。選擇閘極122將該NAND串連接至源極線 128。藉由對選擇線SGD施加合適電壓來控制選擇閘極 12 0。藉由對選擇線s G S施加合適電壓來控制選擇閘極 122。電晶體1〇〇、1〇2、1〇4及106中之每一者皆具有一控 制閘極及一浮動閘極。例如，電晶體1 00具有控制閘極 100CG及浮動閘極l〇〇FG。電晶體102包含控制閘極102CG 及一浮動閘極102FG。電晶體104包含控制閘極i〇4CG及浮 動閘極104FG。電晶體106包含一控制閘極1 〇6CG及一浮動 閘極106FG。控制閘極100CG連接至字線WL3，控制閘極 128993.doc 200849247 102CG連接至字線WL2，控制閘極i〇4CG連接至字線 WL1 ’且控制閘極1 〇6CG連接至字線WL0。 應庄思，雖然圖1及圖2顯示NAND串中之四個記憶體單 元，但使用四個電晶體僅係作為一實例。一NAND串可具 有少於四個之記憶體單元或多於四個之記憶體單元。例 如，某些NAND串會包含8個記憶體單元、16個記憶體單 元、32個記憶體單元、64個記憶體單元、ι28個記憶體單 元等。本文中之論述並非將一 NAND串中的記憶體單元侷 限於任何特定數目。 一使用一 NAND結構之快閃記憶體系統之典型架構將包 含若干個NAND串。每一 NAND串藉由受選擇線SGS控制之 源極選擇閘極連接至源極線，且藉由受選擇線SGD控制之 汲極選擇閘極連接至與其相關聯之位元線。每一位元線及 經由一位元線觸點連接至該位元線之相應Nand串構成記 憶體單元陣列的行。位元線由多個NAND串共享。通常， 位元線在該等NAND串之上沿一與字線垂直之方向佈置且 連接至一個或多個感測放大器。 每一記憶體單元皆能儲存模擬資料或數位資料。當儲存 一個數位資料位元時，將記憶體單元之可能的臨限電壓範 圍劃分為兩個範圍並賦值邏輯資料” 1"及"q”。在一 nand 類型快閃記憶體之一實例中，在擦除記憶體單元之後臨限 電壓為負並定義為邏輯”丨”。在程式化之後臨限電壓為正 並定義為邏輯”〇”。當臨限電壓為負並通過向控制閘極施 加0伏來嘗試讀取時，記憶體單元將導通以指示儲存邏輯 128993.doc -10- 200849247 1。而當臨限電壓為正且通過向控制閘極施加〇伏來嘗試讀 取作業時，記憶體單元將不會導通，此指示儲存邏輯0。The present invention discloses a method of limiting the amount of verification work between program pulses to increase the speed of programming. An embodiment includes performing a first stylization process on a plurality of non-volatile storage elements and performing a second stylization process on the non-volatile storage elements after the first stylization process. The second stylization process includes verifying the job based at least in part on the first stylized process. . One embodiment includes performing a first privateization process on a plurality of non-volatile storage elements. The first stylization process includes applying a stylized pulse to the non-volatile storage elements. The method further includes identifying, during the (four)-stylization process, a first program pulse required to achieve the -first result, identifying a second program required to achieve the second result of the first stylization process Pulses, and after the first stylization process, perform a second stylization process on the non-volatile materials. This: stylization process uses a verify pulse between the programmers. The verify pulses are limited based on the first program pulse. In one embodiment, the method includes erasing a plurality of non-volatile storage elements, and soft-programming and erasing the non-volatile storage elements #, identifying a first group to complete the soft-programming one or more A program pulse associated with a non-volatile storage element, 128993.doc 200849247, identifying a second program pulse associated with a second set of one or more non-volatile storage elements that complete the soft programming, and stylizing These non-volatile storage elements. The stylization process involves performing a verification operation based on the first number of mashed pulses and the second number of stylized pulses. An exemplary embodiment includes a set of non-volatile storage elements and one or more management circuits in communication with the set of non-volatile storage elements. The one or more management circuits implement the methods described above. [Embodiment] An example of a flash memory system uses a NAND structure including a plurality of transistors arranged in series between two selected gates. The series transistors and select gates are referred to as a NAND string. Figure 1 is a top view showing an N AND string. Figure 2 is an equivalent circuit. The NAND string shown in the figure includes four series transistors 1 〇〇, 1 sandwiched between the first (or drain side) selection gate 1 and the second (or source side) selection gate 122. 104 and 106. Select gate 120 connects the NAND string to a bit line via bit line contact 126. Select gate 122 connects the NAND string to source line 128. The selection gate 120 is controlled by applying a suitable voltage to the selection line SGD. The selection gate 122 is controlled by applying a suitable voltage to the selection line s G S . Each of the transistors 1〇〇, 1〇2, 1〇4, and 106 has a control gate and a floating gate. For example, the transistor 100 has a control gate 100CG and a floating gate 10F. The transistor 102 includes a control gate 102CG and a floating gate 102FG. The transistor 104 includes a control gate i〇4CG and a floating gate 104FG. The transistor 106 includes a control gate 1 〇 6CG and a floating gate 106FG. The control gate 100CG is connected to the word line WL3, the control gate 128993.doc 200849247 102CG is connected to the word line WL2, the control gate i〇4CG is connected to the word line WL1' and the control gate 1 〇6CG is connected to the word line WL0. In view of the fact that although Figures 1 and 2 show four memory cells in a NAND string, the use of four transistors is only an example. A NAND string can have fewer than four memory cells or more than four memory cells. For example, some NAND strings will contain 8 memory cells, 16 memory cells, 32 memory cells, 64 memory cells, ι28 memory cells, and the like. The discussion herein does not limit the memory cells in a NAND string to any particular number. A typical architecture for a flash memory system using a NAND structure would include several NAND strings. Each NAND string is coupled to the source line by a source select gate controlled by the select line SGS, and is connected to the bit line associated therewith by a drain select gate controlled by the select line SGD. Each bit line and a corresponding Nand string connected to the bit line via a bit line contact form a row of the memory cell array. The bit lines are shared by multiple NAND strings. Typically, the bit lines are arranged above the NAND strings in a direction perpendicular to the word lines and to one or more sense amplifiers. Each memory unit can store analog data or digital data. When storing a digit data bit, divide the possible threshold voltage range of the memory unit into two ranges and assign the logical data "1" and "q". In one example of a nand type flash memory, the threshold voltage is negative after the erase of the memory cell and is defined as a logical "丨". After stylization, the threshold voltage is positive and defined as a logical "〇". When the threshold voltage is negative and a read is attempted by applying 0 volts to the control gate, the memory cell will turn on to indicate the storage logic 128993.doc -10- 200849247 1 . When the threshold voltage is positive and a read operation is attempted by applying a stagnation to the control gate, the memory cell will not turn on, and this indication stores a logic zero.

在儲存多個資料位準之情形下，將可能的臨限電壓範圍 劃分成資料位準之數目。例如，若儲存四個位準之資訊 (兩個資料位元），則將有四個被賦予資料值” 11 ”、” 10 ”、 ’’〇1”及”〇〇”之臨限電壓範圍。在一nand類型記憶體之— 個貝例中，在一擦除作業之後臨限電壓為負並被定義為 11 。正臨限電壓用於資料狀態”1〇”、，，〇1 "及，，〇〇，，。若儲 存八個貝汛位準（或狀態）（例如，三個資料位元），將有八 個被賦予資料值 ”〇〇〇，，、”001”、”010”、"〇n”、、 101 、”110”及” lu ”之臨限電壓範圍。 权式化到圮憶體單元内之資料與記憶體單元臨限電壓位 準之間的具體關係取決於針對記憶體單元採用之資料編碼 方案i例如，美國專利案第6,222,762號及美國專利申請公 開案弟2004/0255090號(此二者之全文皆以引用方式併入本 ^)。闡述了針對多狀態快閃記憶體單元之各種資料編碼 ^在果^例中，使用一格雷（Gray)碼賦值方案將資 該等臨限電壓讀若—浮動閘極之臨限電 ^。曰决二偏移至其相鄰物理狀態時，則僅會影響一個位 • 一 μ ^例中，資料編碼方案可針對不同字線變 化’資料編碼方幸 一 1 〃了隧守間受化，或者隨機字線之資料位 隨機化以減少資料型樣靈敏度及甚至對記憶體 在下列美國專利/專利申請案 中提供有NAND類型快閃記 128993.doc 200849247 憶體及其作業之相關實例，所有該等美國專利/專利申請 案均以引用的方式併人本文中：美國專利第5,57Q，315號； 美國專利第5,774,397號；美國專利第6,〇46,935號；美國專 . 利第6,456,528號；及美國專利申請案第us 2〇〇3/〇〇〇2348 唬。本文中之論述亦適用於除NAND之外之其他類型快閃 記憶體以及其他類型之非揮發性記憶體。 除了 NAND快閃記憶體之外，亦可使用其他類型之非揮 () 發性儲存裝置。例如，本發明亦可使用一所謂的TANOS結In the case of storing multiple data levels, the possible threshold voltage range is divided into the number of data levels. For example, if you store four levels of information (two data bits), there will be four threshold voltage ranges that are assigned the data values "11", "10", "'〇1", and "〇〇". In a case of nand type memory, the threshold voltage is negative after an erase operation and is defined as 11. The positive threshold voltage is used for the data state "1〇",,,〇1 " And, 〇〇,,. If you store eight beta levels (or status) (for example, three data bits), eight will be given the data value "〇〇〇,,," 001"," The threshold voltage range of 010”, "〇n”, 101, “110” and “lu”. The specific relationship between the weighted data in the memory unit and the threshold voltage level of the memory unit Depending on the data encoding scheme employed for the memory unit, for example, U.S. Patent No. 6,222,762 and U.S. Patent Application Serial No. 2004/0255090, the entireties of each of which are hereby incorporated by reference. Multi-state flash memory unit various data encoding ^ In the case of the case, use a gray (Gray) code assignment scheme will read the threshold voltage if the floating gate is limited to the power of the floating gate. When the offset is shifted to its adjacent physical state, it will only affect one bit. The data coding scheme can be changed for different word lines. 'The data coding method is fortunately. The data is randomized to reduce the data type sensitivity and even the memory in the following US patents/patents. Examples of NAND type flashes 128993.doc 200849247 and related operations are provided in the application, all of which are incorporated herein by reference: U.S. Patent No. 5,57Q,315 U.S. Patent No. 5,774,397; U.S. Patent No. 6, 〇46, 935; U.S. Patent No. 6,456, 528; and U.S. Patent Application Serial No. 2 〇〇 3/ 〇〇〇 2 348 。. Other types of flash memory other than NAND and other types of non-volatile memory. In addition to NAND flash memory, other types of non-volatile memory devices can be used. For example, the present invention can also Junction with a so-called TANOS

構（由在一矽基板上之TaN_A12〇3-SiN_si〇2堆疊層構成）， 該TANOS結構基本上係一使用氮化物層（代替浮動閘極）陷 獲電荷之記憶體單元。適用於快閃EEpR〇M系統之另一種 類型之§己憶體單元採用一非導電性介電材料取代一導電性 浮動閘極來以一非揮發方式儲存電荷。此一記憶體單元闡 述於一篇由Chan等人所著之文章，，一種真正的單一電晶體 氧化物-氮化物-氧化物EEpR〇M裝置"（a True single· C/ Transistor Oxide-Nitride-Oxide EEPROM Device)(IEEEThe structure (consisting of a stacked layer of TaN_A12〇3-SiN_si〇2 on a substrate) is basically a memory cell in which a charge is trapped using a nitride layer (instead of a floating gate). Another type of CMOS memory cell suitable for flash EEpR 〇M systems uses a non-conductive dielectric material in place of a conductive floating gate to store charge in a non-volatile manner. This memory unit is described in an article by Chan et al., A true single transistor oxide-nitride-oxide EEpR〇M device" (a True single· C/ Transistor Oxide-Nitride -Oxide EEPROM Device) (IEEE

Electron Device Letters，第 EDL-8卷，No. 3，1987年 3 月， 第93-95頁）中。一由氧化矽、氮化矽及氧化矽（，，〇n〇”）形 ' 成的二層式電介質夾於一導電性控制閘極與記憶體單元通 • 道上方的一半導電性基板之一表面之間。藉由將電子自記 憶體單兀通道注入至氮化物内來程式化記憶體單元，其中 電子被陷獲並儲存於一有限區域中。然後，所儲存之電荷 以一可伯測方式改變記憶體單元通道之一部分之臨限電 壓。藉由將熱電洞注入至氮化物内擦除記憶體單元。亦參 128993.doc -12- 200849247Electron Device Letters, Vol. EDL-8, No. 3, March 1987, pp. 93-95). A two-layer dielectric formed of yttrium oxide, tantalum nitride, and yttrium oxide (ie, 〇n〇) is sandwiched between a conductive control gate and a half of a conductive substrate above the memory cell via Between the surfaces, the memory cells are programmed by injecting electrons from the memory channel into the nitride, where the electrons are trapped and stored in a limited area. Then, the stored charge is measured in a measurable manner. The mode changes the threshold voltage of a portion of the memory cell channel by injecting a thermal hole into the nitride to erase the memory cell. See also 128993.doc -12- 200849247

見由Nozaki等人所著的”具有用於半導體磁盤應用的 MONOS記憶體單元的一 l-Mb EEPROM(A 1-Mb EEPROM with MONOS Memory Cell f〇r Semiconductor DiskSee an l-Mb EEPROM with a MONOS memory cell for semiconductor disk applications by Nozaki et al. (A 1-Mb EEPROM with MONOS Memory Cell f〇r Semiconductor Disk

GG

Aipp\icaXion、、（IEEE Journal of Solid-State Circuits，第 26 卷，No· 4，1991年4月，第497-501頁）中，該文章描述了 一種呈***式閘極組態之類似記憶體單元，其中一經摻雜 之多晶矽閘極沿記憶體單元通道之一部分延伸從而形成一 單獨選擇電晶體。以上兩個文章之全文皆以引用方式併入 本文中。在William D· Brown及J〇e E. Brewer所編輯之Aipp\icaXion, (IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, April 1991, pp. 497-501), this article describes a similar memory in a split gate configuration. The body unit, wherein a doped polysilicon gate extends partially along one of the memory cell channels to form a single select transistor. The entire contents of both of the above articles are incorporated herein by reference. Edited by William D. Brown and J〇e E. Brewer

"Nonvolatile Semiconductor Memory Technology”（IEEE"Nonvolatile Semiconductor Memory Technology" (IEEE

Press，1998)第1.2節中所提及之程式化技術在該節中亦被 描述為適用於介電質電荷陷獲裝置，該文章以引用方式併 入本文中。亦可使用其他類型之記憶體裝置。 圖3繪示一可包含一個或多個記憶體晶粒或晶片212之非 揮發性儲存裝置210。記憶體晶粒212包含一記憶體單元陣 列200(兩維或二維）、控制電路22〇及讀取/寫入電路boa及 230B。在一實施例中，各外圍電路對記憶陣列2〇〇之存取 係以一對稱形式在該陣列之對置側實施，以便將每側的存 取線及私路之饴度減半。讀取/寫入電路及包含 :個：測塊300，料感測塊允許並行讀取或程式化一記 ^體:兀頁。記憶陣列1〇〇可經由列解碼器2_及2_由 字線尋址且可經由行解碼器242^ 242b由位元線尋址。 在一典型實施例中，-控制器244與_個或多個記憶體晶 粒-樣包含於同一記憶體裝置21咖口，一可擦除儲 128993.doc -13- 200849247 存卡或包）中。命令與資料經由線232在主機與控制器244 之間及經由線234在控制器與一個或多個記憶體晶粒212之 間傳輸。一實施案可包含多個晶片21 2。 控制電路220與讀取/寫入電路23 0A及230B協作以對記憶 陣列200實施記憶作業。控制電路22〇包含一狀態機222、 一晶片上位址解碼器224及一功率控制模組226。狀態機 222¼供A ’丨思作業之晶片位準控制。晶片上位址解碼器224 在主機或一記憶體控制器所用硬體位址與解碼器24〇a、 240B、242A及242B所用硬體位址之間提供一位址介面。 在記憶作業期間，功率控制模組226控制提供至字線及位 兀線之功率和電壓。在一實施例中，功率控制模組226包 含一個或多個能產生大於電源電壓之電壓之電荷幫浦。 在貝施例中，控制電路220、功率控制電路226、解碼 器電路224、狀態機電路222、解碼器電路242八、解碼器電 路242B、解碼态電路24〇A、解碼器電路、讀取/寫入 電路230A、5買取/寫入電路2则及/或控制器⑽之一組合 或任何組合可稱為一個或多個管理電路。 圖憎示記憶體單元陣列2〇〇之一實例性結構。在_實施 例中，將記憶體單元陣列劃分為M個記憶體單元區塊。、通 常對於快閃EEPR0M系統來說’區塊即為擦除單位。亦 :，母個區塊含有被一起擦除之最小數目之記憶體單元。 =區㈣常被劃分為若干個頁。頁係—程式化單位。在 5己f思體早元之一列中诵當絲左 , 通书儲存一個或多個資料頁。-頁能 儲存一個或多個區段。一個 〒又I 3使用者貧料及開銷資 128993.doc -14- 200849247 料。開銷資料通常包含依據該區段之使用者資料計算得出 一部分在資料The stylization techniques mentioned in Section 1.2 of Press, 1998) are also described in this section as being applicable to dielectric charge trapping devices, which is incorporated herein by reference. Other types of memory devices can also be used. 3 illustrates a non-volatile storage device 210 that may include one or more memory dies or wafers 212. The memory die 212 includes a memory cell array 200 (two-dimensional or two-dimensional), a control circuit 22A, and read/write circuits boa and 230B. In one embodiment, the access of each peripheral circuit to the memory array 2 is implemented in a symmetrical form on the opposite side of the array to halve the access line and the private path of each side. The read/write circuit includes: a block 300, and the material sensing block allows parallel reading or programming of a body: a page. Memory arrays 1 can be addressed by word lines via column decoders 2_ and 2_ and can be addressed by bit lines via row decoders 242^242b. In an exemplary embodiment, the controller 244 and the one or more memory dies are included in the same memory device 21, an erasable storage 128993.doc -13 - 200849247 card or package) in. Commands and data are transmitted between the host and controller 244 via line 232 and between the controller and one or more memory dies 212 via line 234. An embodiment can include a plurality of wafers 21 2 . Control circuit 220 cooperates with read/write circuits 230A and 230B to perform a memory job on memory array 200. Control circuit 22 includes a state machine 222, an on-chip address decoder 224, and a power control module 226. The state machine 2221⁄4 is used for wafer level control of A's thinking operations. The on-chip address decoder 224 provides an address interface between the hardware address used by the host or a memory controller and the hardware address used by the decoders 24A, 240B, 242A, and 242B. During a memory operation, power control module 226 controls the power and voltage supplied to the word lines and bit lines. In one embodiment, power control module 226 includes one or more charge pumps capable of generating a voltage greater than the supply voltage. In the example of the embodiment, the control circuit 220, the power control circuit 226, the decoder circuit 224, the state machine circuit 222, the decoder circuit 242, the decoder circuit 242B, the decoding state circuit 24A, the decoder circuit, the read/ The combination or combination of one of the write circuits 230A, 5 the buy/write circuit 2 and/or the controller (10) may be referred to as one or more management circuits. The figure shows an exemplary structure of the memory cell array 2〇〇. In the embodiment, the memory cell array is divided into M memory cell blocks. Usually, for a flash EEPROM system, the block is the erase unit. Also: The parent block contains the smallest number of memory cells that are erased together. = Area (4) is often divided into several pages. Page system - stylized unit. In the column of 5 sf, you can store one or more data pages. - The page can store one or more sections. A 〒 and I 3 users of poor materials and expenses 128993.doc -14- 200849247 material. The overhead data usually contains a portion of the data calculated based on the user data of the segment.

( 至多達32個、64個、128個或更多個頁不等。亦可使用不 之一個糾錯碼（ECC)。控制器（以下所述）之一 正被程式化於陣列内時計算ECC，且亦在從陣 時校驗ECC。另一選擇為，將ECC及/或i 同大小之區塊及佈置。 在另一實施例中，將位元線劃分為奇數位元線與偶數位 元線。在一奇數/偶數位元線架構中，在一個時刻程式化 〉'口 一共同子線且連接至該等奇數位元線之記憶體單元，而 在另一時刻程式化沿一共同字線且連接至偶數位元線之記 憶體單元。 圖4顯不e己憶陣列2 0 0之區塊i之更多詳細内容。區塊i包 Q 含X+1個位元線及X+1個NAND串。區塊丨亦包含64個資料 字線（WL0-WL63)、2個虛擬字線（WL—d0及WL dl)、一汲 極側選擇線（SGD)及一源極側選擇線（SGS)。每一 NAND串 ， 之一端經由一汲極選擇閘極（連接至選擇線SGD)連接至一 / 對應位元線，且另一端經由一源極選擇閘極（連接至選擇 線SGS)連接至源極線。由於存在64個資料字線及兩個虛擬 字線，故每一 NAND串包含64個資料記憶體單元及兩個虛 擬記憶體單元。在其他實施例中，NAND串可具有多於或 少於64個資料記憶體單元及兩個虛擬記憶體單元。資料記 128993.doc -15- 200849247 憶體單元能儲存使用者或系統資料。通常，虛擬記憶體單 元不用於儲存使用者或系統資料。一些實施例不包含虛擬 記憶體單元。 圖5係一劃分為一核心部分（稱為一感測模組48〇)及一共 同部分490之個別感測塊3〇〇之方塊圖。在一實施例中，針 對母位元線存在一單獨的感測模組480，且針對一組多 個感測模組480存在一個共同部分49〇。在一實例中，一感 測塊包含一共同部分490及8個感測模組48〇。一組感測模 組中之每-者將經由一資料匯流排472與相關聯之共同部 刀連通更夕洋細内容，參考美國專利申請公開案 厕船侧7,該公開案之全文以引用方式併入本文中。 感測模組48〇包括確定—所連接位元線中之傳導電流係 在一預定臨限位準之上或之下之感測電路47〇。纟一些實 施例中’感測模組480包含一電路，其通常被稱為一感測 放大器。感測模組48〇亦包含—位元線鎖存器術，其用來 設定所連接位元線上之電壓狀態。例如，鎖存在位元線鎖 =器482中之一預定狀態會導致把所連接位元線拉至一指 定程式禁止之狀態（例如Vdd)。 共同部分490包括一處理器492、一組資料鎖存器494及 -箱合於該組資料鎖存器494與資料匯流排咖間之ι/〇介 面帽。處理器492實施計算。例如，其功能之_係確定儲 存在所感測記憶體單元巾之資料並將所確定的資料儲存入 該組資料鎖存器中。在一讀取作業期間，該組資料鎖存哭 494用於儲存由處理器所確定的資料位元。在―程式: 128993.doc 200849247 業期間，其亦用於儲存由資料匯流排42〇導入的資料位 元。經導入資料位元表示欲程式化於記憶體内之寫入資 料。卯介面496在資料鎖存器例與資料匯流排42〇之間提 供一介面。(Up to 32, 64, 128 or more pages. You can also use one of the error correction codes (ECC). One of the controllers (described below) is being programmed into the array) ECC, and also verify ECC in the slave time. Another option is to block and arrange ECC and / or i of the same size. In another embodiment, the bit line is divided into odd bit lines and even A bit line. In an odd/even bit line architecture, a common sub-line is programmed at one time and connected to the memory cells of the odd bit lines, and at another time stylized along a A common word line and connected to the memory unit of the even bit line. Figure 4 shows more details of the block i of the array 2 0 0. Block i package Q contains X+1 bit lines and X+1 NAND strings. The block 丨 also includes 64 data word lines (WL0-WL63), 2 dummy word lines (WL_d0 and WL dl), a drain side select line (SGD), and a source. Side select line (SGS). One end of each NAND string is connected to one/corresponding bit line via a drain select gate (connected to select line SGD), and the other end is selected via a source The gate (connected to select line SGS) is connected to the source line. Since there are 64 data word lines and two dummy word lines, each NAND string contains 64 data memory cells and two virtual memory cells. In other embodiments, the NAND string may have more or less than 64 data memory cells and two virtual memory cells. Data 128993.doc -15- 200849247 The memory cell can store user or system data. The virtual memory unit is not used to store user or system data. Some embodiments do not include a virtual memory unit. Figure 5 is an individual divided into a core portion (referred to as a sensing module 48A) and a common portion 490. A block diagram of the sense block 3A. In one embodiment, there is a separate sense module 480 for the parent bit line and a common portion 49〇 for a set of multiple sense modules 480. In one example, a sensing block includes a common portion 490 and eight sensing modules 48. Each of the sensing modules will be connected to the associated common knife via a data bus 472. Xiyang fine content, refer to the US special The disclosure of the disclosure of the vessel side 7 is incorporated herein by reference in its entirety. The sensing module 48 includes determining that the conducted current in the connected bit line is above a predetermined threshold level or The sensing circuit 47 is below. In some embodiments, the sensing module 480 includes a circuit, which is generally referred to as a sensing amplifier. The sensing module 48〇 also includes a bit line latch. It is used to set the voltage state on the connected bit line. For example, latching a predetermined state in the bit line lock = 482 will cause the connected bit line to be pulled to a specified program disabled state (for example, Vdd). . The common portion 490 includes a processor 492, a set of data latches 494, and an ι/〇 interface cap that is housed between the set of data latches 494 and the data bus. Processor 492 performs the calculations. For example, its function is to determine the data stored in the sensed memory unit and store the determined data in the set of data latches. During a read job, the set of data latches cry 494 is used to store the data bits determined by the processor. During the program: 128993.doc 200849247, it is also used to store the data bits imported by the data bus 42. The imported data bits indicate the writing information to be programmed into the memory. The interface 496 provides an interface between the data latch instance and the data bus 42.

在讀取或感測期間，由一狀態機222來控制系統作業， 該狀態機控制向已定址記憶體單元提供不同的控制間極電 壓。在狀態機逐步調節對應於記憶體所支援的各種記憶體 狀態之各種預定義控制閘極電壓時，感測模組48〇可在該 等電壓之一者處跳閘且從感測模組48〇經由匯流排Ο]向處 理器492提供-輸出。此時，處理器梢通過考慮感測模組 的跳閘事件及關於狀態機經由輸人線493所施加控制間極 電C之資溪來確疋所彳亍記憶體狀態。然後處理器々Μ計算 記憶體狀態之二進制編碼並將所得資料位㈣存於資料鎖 存& 494中。在該核心部分之另一實施例中，位元線鎖存 為482有兩個用途：作為一用於鎖存感測模組48〇之輸出之 鎖存Is、及亦作為一如上所述之位元線鎖存器二者。 預期某些實施案會包含多個處理器492。在一實施例 中，每一處理器492將包含一輸出線（在圖5中未繪示出）以 使π亥等輸出線之每一者皆線，，或"連接在一起。在一些實施 m 、、泉在連接至線’’或”線之前發生反轉。此組態使 /寻月b在私式驗證過程中快速確定程式化過程何時完成，此 乃因接納線或”線之狀態機能確定正被程式化之所有位元 y寸達到所而位準。例如，當每一位元已達到其所需位準 才針對彼位元之一邏輯零將發送至線，，或，，線（或反轉一資 128993.doc -17- 200849247 :測，通之實施例中’狀態機可能(:二v:::) 需要讀取線"或，，線八次’或者向處理 、a 1 積:關聯位元線之結果—需讀 在程式或驗證期間，將來自資料匯流排420欲程式化之 貝科儲存於該組資料鎖存器494中。由狀態機控制之程式 作業包括將一系列程式化電麼脈衝（具有增加的量值）施加 至所疋址記憶體單元之㈣㈣上。每m脈衝後跟 :驗證過程以確定該記憶體單元是否已程式化為所需狀 悲。處理器492相對於所需記憶體狀態來監控被驗證之記 ，體狀態。當二者—致時’處理器492將設定位元線鎖存 益482，則吏該位元線被拉至一指定程式禁止之狀態。此 禁止耦合至該位元線之記憶體單元進一步程式化，即使在 程式化脈衝施加在其控制閘極上時。在其他實施例中，處 理器首先裝載位元線鎖存器482且在驗證過程中感測電路 將位元線鎖存器設定為一禁止值。 資料鎖存器堆g 494含有一對應於感測模組之資料鎖存 益堆璺。在一實施例中，每個感測模組48〇有3-5(或其他數 目）個資料鎖存器。在一實施例中，該等鎖存器各自為一 位元。在某些實施案中（但不要求），將該等資料鎖存器實 施為一移位暫存器以使儲存於其中之並行資料轉換成用於 資料匯流排420之串行資料，且反之亦然。在一較佳實施 128993.doc -18- 200849247 例中’可將對應於由m個記憶體單元構成之讀取/寫入 之所有資料鎖存器鏈接在一起以形成一移位暫存器塊，以 使：資料區塊可通過串行傳送來輸入或輸出。特定而言， 對σ貝取/寫人模組庫進行調配，以使其資料鎖存器組中之 每一者依序將資料移入或移出資料匯流排，仿佛其係一用 於整體讀取/寫入區塊之移位暫存器之一部分一般。 可在以下專利中發現關於讀取作業及感測放大器之額外 資訊：（1)在2004年3月25日公佈的美國專利申請公開案第 2004/0057287號，’’Non-Volatile Memory And Method WithDuring reading or sensing, system operation is controlled by a state machine 222 that provides different control inter-electrode voltages to the addressed memory cells. When the state machine gradually adjusts various predefined control gate voltages corresponding to the various memory states supported by the memory, the sensing module 48 can trip at one of the voltages and from the sensing module 48. The output is output to the processor 492 via the bus. At this time, the processor tip determines the state of the memory by considering the trip event of the sensing module and the sigma of the control inter-electrode C applied by the state machine via the input line 493. The processor then computes the binary code of the memory state and stores the resulting data bits (4) in data lock & 494. In another embodiment of the core portion, the bit line latch 482 has two uses: as a latch Is for latching the output of the sense module 48, and also as described above. Both bit line latches. It is contemplated that certain implementations will include multiple processors 492. In one embodiment, each processor 492 will include an output line (not shown in Figure 5) such that each of the output lines, such as πHai, is wired, or " connected together. In some implementations, the spring is reversed before it is connected to the line '' or 'line.) This configuration enables /finding b to quickly determine when the stylization process is completed during the private verification process, due to the acceptance line or "" The state machine of the line determines that all bits that are being programmed are at the desired level. For example, when each bit has reached its required level, one of the logical zeros for one of the bits will be sent to the line, or, the line (or reversed the amount of 128993.doc -17-200849247: test, pass In the embodiment, the 'state machine may (: two v:::) need to read the line " or, the line eight times 'or to the processing, a 1 product: the result of the associated bit line - need to read in the program or verify During the period, the Beko from the data bus 420 to be programmed is stored in the data latch 494. The program operation controlled by the state machine includes applying a series of stylized pulses (with an increased magnitude) to (4) (4) of the address memory unit. Each m pulse is followed by a verification process to determine whether the memory cell has been programmed to the desired state. The processor 492 monitors the verified record with respect to the desired memory state. , the body state. When the two - the processor 492 will set the bit line latch benefit 482, then the bit line is pulled to a state that is prohibited by the specified program. This prohibits the memory coupled to the bit line The body unit is further stylized even after the stylized pulse is applied to its control gate In other embodiments, the processor first loads the bit line latch 482 and the sense circuit sets the bit line latch to a disable value during verification. The data latch stack g 494 contains a Corresponding to the data latching stack of the sensing module. In one embodiment, each sensing module 48 has 3-5 (or other number) of data latches. In an embodiment, the The latches are each a bit. In some embodiments (but not required), the data latches are implemented as a shift register to convert parallel data stored therein for use in data. The serial data of bus 420, and vice versa. In a preferred embodiment 128993.doc -18-200849247, all data corresponding to read/write consisting of m memory cells can be latched. The devices are linked together to form a shift register block so that the data block can be input or output through serial transfer. In particular, the σ Becker/Writer module library is configured to make its data Each of the latch groups sequentially moves data into or out of the data bus, as if it were A portion of the shift register for the overall read/write block is generally available. Additional information on read operations and sense amplifiers can be found in the following patents: (1) published on March 25, 2004 U.S. Patent Application Publication No. 2004/0057287, ''Non-Volatile Memory And Method With

Reduced Source Line Bias Errors”；（2)在 2004年 ό月 l〇 日公 佈的美國專利申請公開案第2004/0109357號"Non-Volatile Memory And Method with Improved Sensing" ; (3)美國專利 申請公開案第20050169082號；（4)在2005年4月5日申請的 由 Jian Chen 發明、名稱為"Compensating f〇r Coupling During Read Operations of Non-Volatile Memory”之美國專 利公開案2006/0221692 ;及（5)在2005年12月28日中請、發 明人為 Siu Lung Chan 及 Raul-Adrian Cernea、名為 ’’Reference Sense Amplifier For Non-Volatile Memory1’之美 國專利申請案第11/321，953號。所有以上剛剛列出的5個專 利文件之全文皆以引用方式併入本文中。 在一成功程式化過程（具有驗證過程）結束時，記憶體單 元的臨限電壓應在臨限電壓的一個或多個分佈内（對於經 程式化之記憶體單元而言），或視情況在臨限電壓的一個 分佈内（對於經擦除的記憶體單元而言）。圖6繪示當每一記 128993.doc -19- 200849247 憶體單元皆儲存四個資料位元時，對應於記憶體單元陣列 之資料狀態之實例性臨限電壓分佈。然而，在另一實施例 中母個°己憶體單元可使用多於或少於四個資料位元。圖 6顯示對應於資料狀態〇_丨5之丨6個臨限電壓分佈。在一實 施例中，處於狀態0之臨限電壓為負且處於狀態1-15之臨 ^ 限電壓為正。 在貝料狀恶(M5之每一者之間者係用於自記憶體單元讀 ( 取資料之讀取參考電壓。例如，圖6顯示資料狀態〇與i之 間的％取參考電壓Vrl，及資料狀態丨與2之間的。藉由 測試一指定記憶體單元之臨限電壓在相應讀取參考電壓之 上或之下，系統能確定該記憶體單元處於何種狀態。 驗證參考電壓在每一資料狀態〇_15之下限處或其附近。 例如，圖6顯示狀態1之又¥1及狀態22Vv2。當將記憶體單 兀程式化為一指定狀態時，該系統將測試彼等記憶體單元 是否具有一大於或等於驗證參考電壓之臨限電壓。 U 圖7繪示另一實施例，其中對應於資料狀態（M5之臨限 電壓分佈可部分重疊，此乃因ECC可處理一定比例之發生 錯誤之記憶體單元。 亦應注意，當使用通過源極之本體效應或本體偏壓來將 •’ 負臨限電壓偏移至可量測正電壓範圍時，Vt轴可能會偏離 施加至該控制閘極之實際電壓。應注意之另一點是，與所 繪示之16種狀態之相等間隔/寬度相反，各種狀態可具有 不同的寬度/間隔以適應對保持損失之不同程度感受性。 在一些實施例中，狀態〇及/或丨5寬於其他狀態。 128993.doc -20- 200849247 圖6(或圖7)中之每一資料狀態 應狀態之記憶體單元中的資料位元: 於儲存在程式化為相 \其=將，料值賦予每一資料狀態μ之一實例。在 該四個頁稱為第—下部頁、第_上=子於四個不同頁中。 四頂部頁。圖叫示每一二:上：頁、第三高部頁及第 料。在-實施例中，對每一頁分別：：之每-頁中的資 ,门士 只刀別私式化。在另一實施例 '程式化一記憶體單元的所有四個資料位元。 之^1—表格’其提供將資料值❹每-資料狀態(M5 只例ffi| 8中之貝料值採用_格雷碼賦值方 =料狀態之間僅改變-個位元。若-記憶體單… 限電塵太低或太高’此佈置可減少錯誤位元之數目。 圖10係-描繪-操作非揮發性記憶體單元之實施例之流(2) U.S. Patent Application Publication No. 2004/0109357 "Non-Volatile Memory And Method with Improved Sensing"; (3) US Patent Application Disclosure, published on January 31, 2004 U.S. Patent No. 20050169082; (4) U.S. Patent Publication No. 2006/0221692, filed on Jan. 5, 2005, by the name of "Compensating f〇r Coupling During Read Operations of Non-Volatile Memory; (5) On December 28, 2005, the inventor was Siu Lung Chan and Raul-Adrian Cernea, and U.S. Patent Application Serial No. 11/321,953, entitled ''Reference Sense Amplifier For Non-Volatile Memory 1'. All of the above five patent documents just listed above are incorporated herein by reference. At the end of a successful stylization process (with a verification process), the threshold voltage of the memory cell should be within one or more distributions of the threshold voltage (for a stylized memory cell), or as appropriate Within a distribution of threshold voltages (for erased memory cells). Figure 6 illustrates an exemplary threshold voltage distribution corresponding to the data state of the memory cell array when each of the 128993.doc -19-200849247 memory cells stores four data bits. However, in another embodiment more than or less than four data bits may be used for the parent cell. Figure 6 shows the six threshold voltage distributions corresponding to the data state 〇_丨5. In one embodiment, the threshold voltage in state 0 is negative and the voltage in the state 1-15 is positive. In the case of shellfish (between each of M5 is used to read from the memory unit (read the reference voltage of the data. For example, Figure 6 shows the data between the state 〇 and i take the reference voltage Vrl, And the data state between 丨 and 2. By testing the threshold voltage of a specified memory cell above or below the corresponding read reference voltage, the system can determine what state the memory cell is in. Verify that the reference voltage is For each data state 〇 _ 15 at or near the lower limit. For example, Figure 6 shows state 1 again and 1 state 22Vv2. When the memory unit is programmed into a specified state, the system will test their memory. Whether the body unit has a threshold voltage greater than or equal to the verification reference voltage. U Figure 7 illustrates another embodiment in which the threshold voltage distribution corresponding to the data state (M5 can be partially overlapped, because the ECC can handle a certain ratio The memory unit in which the error occurred. It should also be noted that when using the source effect of the source or the body bias to shift the negative threshold voltage to the measurable positive voltage range, the Vt axis may deviate from being applied to The control gate The actual voltage of the pole. It should be noted that the other states may have different widths/intervals to accommodate different degrees of susceptibility to sustain loss, as opposed to the equal spacing/width of the 16 states illustrated. In the state, the state 〇 and / or 丨 5 is wider than the other states. 128993.doc -20- 200849247 The data bit in the memory unit of each data state in Figure 6 (or Figure 7): stored in the program The phase is given to the instance, and the material value is assigned to one instance of each data state μ. The four pages are called the first-lower page, the first _upper=the child is in four different pages. Show each two: upper: page, third high page and material. In the embodiment, for each page:: each of the pages, the door is only private. An embodiment 'programs all four data bits of a memory unit. ^1 - Table' provides a data value ❹ per-data state (M5 only ffi| 8 in the shell value is _ Gray code Assignment side = only change one bit between material states. If - memory single... limit the electric dust is too low or too high 'this arrangement can be reduced Error bit number 10 of FIG line - is depicted - the operation of non-volatile memory cell embodiment of Example ilk

程圖。在諸多實施宰中 士 p ntJ 木t δ己憶體早兀於程式化之前被擦除 (以區塊為單位或以其他為單位)。在一實施例中，藉由在 源極線及位元線浮動之同時將卜井提升至-擦除電壓（例如 20伏）且持續一足夠長時間並將一所選區塊之字線接地來 ㈣記憶體單元（見步驟卿）。由於電容性耗合，未選擇之 予線位$、線、選擇線及源極亦提升至佔擦&電壓顯著分 數之值。由此將一強電場施加至所選記憶體單元的隨道氧 化物層上，且當浮動閘極之電子發射至基板側時，所選記 體單7L之貧料通常藉由一 F〇wler_N〇rdheim穿隧機制擦 除。當電子自浮動閘極傳送至p_井區時，一所選記憶體單 兀之臨限電壓降低。可對整個記憶陣列、一區塊、或另一 128993.doc -21 · 200849247 記憶體單元單位實施擦除。在 可如太# 士 π Τ陈°己體早元區塊之後， 本文中所述程式化各個記憶體單元。 在步驟502中，視需要實施軟 I#輩开 式化以縮小經擦除記憶 體早兀之經擦除臨限電壓分佈。 於搲W 某些圮憶體單元可能會由 於“除過程之緣故而處於一較 ^勺人〇 平乂所而為沬的擦除狀態。軟程 式化包έ鈿加程式化脈衝以將 厭狡紅s 仏除5己憶體單元之臨限電 壓移動至一較緊密臨限電壓 电 pe叮叙^ 刀师在母一程式化脈衝之 ^1以—驗證作業以確定記憶體單元是否在適合的經 ^㈣㈣壓分佈内。在軟程式化過程結束之前不再需要 =化之記憶體單元可藉由提升對應位元線被鎖定以不 進仃進一步軟程式化。驗證電壓 ,IL ^ i J暴於特定實施案而變 。此項技術中已知曉軟程式化。 J在吴國專利6,661，71 1 中务現更多關於軟程式化之資 ^ ^ ^ 貝Λ该專利以引用方式併入 ::思不要求以-特定方案來實施軟程式化。雖 ，“人程式化可與一擦除過程聯合實施，但軟程 可在程式化時實施。 在步驟504中，接收對一程式資料之請求。可自一主機 ^他裝置接收該請求。在步驟502與5〇4之間緣示一虛線 以和不-不可預知之時間量，且某些潛在的中間任務（包 含其他程式化作業）可在步驟502與5〇4之間實施。 在步驟506中，蕪出/由田 々占 曰由使用一多遍程式化過程將資料程式 化於忑體單兀中從而將記憶體單元從經擦除臨限電壓分 布矛式化為U有政資料狀態相關聯之任一臨限電壓分佈。 下文將提供步驟506之更多詳細内容。 I28993.doc -22- 200849247 在步驟508中，讀取資料記憶體單元且向使用者提供所 讀取的資料。例如，藉由控制器向主機提供來自記情體單 元之資料。在步驟506與508之間繪示一虛線以指示一不可 預知之時間量且某些潛在的中間任務可在步驟5〇6與5〇8之 間實施。在某些情形下，可能從未讀取資料。圖1〇中之過 程係在控制器244及/或控制電路220指示下由控制器2料及/ 或控制電路220實施。Cheng Tu. In many implementations, the slaughter p ntJ wood t δ hexamed body is erased (in blocks or in other units) before being stylized. In one embodiment, the well is raised to an erase voltage (eg, 20 volts) while the source line and the bit line are floating, and continues for a sufficient time to ground the word line of a selected block. (4) Memory unit (see step Qing). Due to the capacitive fit, the unselected line positions $, lines, select lines, and sources are also raised to the value of the significant & voltage significant fraction. Thereby, a strong electric field is applied to the channel oxide layer of the selected memory cell, and when the electrons of the floating gate are emitted to the substrate side, the poor material of the selected bank 7L is usually by a F〇wler_N The 〇rdheim tunneling mechanism erases. When the electrons are transferred from the floating gate to the p_well region, the threshold voltage of a selected memory cell decreases. Erasing can be performed on the entire memory array, a block, or another 128993.doc -21 · 200849247 memory cell unit. The individual memory cells are stylized as described herein after being able to be as if they were too. In step 502, the soft-initialization is performed as needed to reduce the erased threshold voltage distribution of the erased memory.于搲W Some memory units may be erased due to “because of the process.” The soft stylized package adds stylized pulses to distaste. The red s 仏 5 5 己 己 己 己 己 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临Within the pressure distribution of ^(4)(4). The memory unit that is no longer needed before the end of the soft stylization process can be locked by lifting the corresponding bit line to further soften the program. Verify voltage, IL ^ i J storm It has been changed in the specific implementation. Soft stylization is known in this technology. J is more concerned with soft stylization in Wu Guofang 6,661,71 1 ^ ^ ^ BEI This patent is incorporated by reference: : Thinking does not require software-implementation with a specific scheme. Although "personalization can be implemented in conjunction with an erasure process, the soft-process can be implemented at the time of stylization. In step 504, a request for a program material is received. The request can be received from a host device. A dashed line between steps 502 and 5〇4 indicates a non-unpredictable amount of time, and some potential intermediate tasks (including other stylized jobs) may be implemented between steps 502 and 5〇4. In step 506, the data is stylized from the erased threshold voltage distribution to the U-policy by using a multi-pass stylization process to program the data into the body unit. Any threshold voltage distribution associated with the data state. More details of step 506 are provided below. I28993.doc -22- 200849247 In step 508, the data memory unit is read and the user is provided with the read data. For example, the controller provides the host with information from the ticker unit. A dashed line is drawn between steps 506 and 508 to indicate an unpredictable amount of time and some potential intermediate tasks can be implemented between steps 5〇6 and 5〇8. In some cases, the data may never be read. The process of Figure 1 is implemented by controller 2 and/or control circuit 220 as directed by controller 244 and/or control circuit 220.

通常，在讀取及驗證作業過程中，所選字線連接至一電 壓-針對每一讀取及驗證作業規定該電壓之位準（例如， Vrl或Vvl)，以便確定相關記憶體單元之一臨限電壓是否 已達到此位準。未選擇字線連接至一不同於所選字線之電 壓之超驅動電壓(稱為Vread)。通常，將該超驅動電壓選擇 為高於能被程式化至一資料記憶體單元之最大臨限電壓。 超驅動電壓與臨限電壓之間的差亦可稱為超驅動。在向所 選字線施加字線電壓之後，量測記憶體單元中之傳導電泣 以碟定該記龍單元是㈣應於絲至該字線之電壓而= 通。若經量測該傳導電流大於一特定 口口 —疋值則涊為該記憶體 料且絲至該字狀於記㈣單元之臨限電 壓。若經量測該傳導電流不大於兮 — …土、# ^ L不大於㈣疋值，則認為記憶體 早兀未¥通且施加至該字線之電壓不大於記憶 限電壓。 干兀d 讀Γ驗證作業過程中，可藉由諸多方式量測一記 ^早70中之傳導電流。在-實例中，藉由記憶體單元對 感測放大器中一糞用堂六w 4 Α 早 對 -中專用電谷盗之放電率或充電率來量測一記 128993.doc -23- 200849247 fe體單元中之傳導電流。在另一實例中，所選記憶體單元 之傳導電流允許（或未能允許）包含該記憶體單元之NAND 串對位元線釋放一電壓。一段時間之後量測該位元線上之 電壓以瞭解其是否已被放電。關於讀取資料之更多詳細内 谷可在美國專利公開案2006/0221683中發現，此公開案之 全文以引用方式併入本文中。 圖11A-D描繪一種四遍程式化過程，其用於將資料程式 ^於儲存四個資料位元（如在圖6或圖7中所繪示）之記憶體 單疋中。在程式化之前，將一區塊中之所有記憶體單元擦 除為一經擦除臨限電壓分佈（見圖1〇中之步驟5〇〇)。例如， θ 1A 員示處於經擦除臨限電壓分佈E之記憶體單元區 八匕貝施例中，經擦除臨限電壓分佈Ε高於〇伏，或部分地 高於〇伏。可藉由提升源極電壓及藉此誘導一欲提升臨限 電壓而不改變浮動閘極上之電子數目之逆向本體偏壓來將Typically, during a read and verify operation, the selected word line is connected to a voltage - the level of the voltage (eg, Vrl or Vvl) is specified for each read and verify operation to determine one of the associated memory cells Whether the threshold voltage has reached this level. The unselected word line is connected to an overdrive voltage (called Vread) that is different from the voltage of the selected word line. Typically, the overdrive voltage is selected to be higher than the maximum threshold voltage that can be programmed into a data memory unit. The difference between the overdrive voltage and the threshold voltage can also be referred to as superdrive. After applying the word line voltage to the selected word line, the conduction sob in the memory cell is measured to determine that the cell is (4) the voltage from the wire to the word line = pass. If the measured conduction current is greater than a specific mouth-value, then the memory is the memory and the wire is drawn to the threshold voltage of the unit (4). If the measured conduction current is not greater than 兮 - soil, # ^ L is not greater than (4) 疋 value, it is considered that the memory is not rushed and the voltage applied to the word line is not greater than the memory limit voltage. During the dry test, the conduction current can be measured in a number of ways. In the example, the memory unit measures a discharge rate or a charge rate of a squatter in the sense amplifier, and the discharge rate or the charge rate is used to measure 128993.doc -23- 200849247 fe Conducted current in the body unit. In another example, the conduction current of the selected memory cell allows (or fails to allow) the NAND string containing the memory cell to release a voltage to the bit line. After a period of time, the voltage on the bit line is measured to see if it has been discharged. Further details regarding the reading of the data are found in U.S. Patent Publication No. 2006/0221683, the entire disclosure of which is incorporated herein by reference. Figures 11A-D depict a four-pass stylization process for storing data in a memory unit that stores four data bits (as shown in Figure 6 or Figure 7). Before programming, all memory cells in a block are erased to an erased threshold voltage distribution (see step 5 in Figure 1). For example, the θ 1A member is in the memory cell region of the erased threshold voltage distribution E. The erased threshold voltage distribution Ε is higher than the stagnation, or partially higher than the stagnation. By raising the source voltage and thereby inducing a reverse body bias that does not change the number of electrons on the floating gate without increasing the threshold voltage

負臨限電壓分佈移入正電壓區中。此藉由施加逆向本體偏 壓來改變臨限電壓歸因於衆所周知的本體效應現象。在大 多數NAND記憶體之上下文中，ρ井構成該體。為了簡化 圖’圖UA至11D中之Vt軸相對於實際發生偏移以使 所有VT看上去為正。實際中，可藉由使用逆向本體偏壓 來提升该等VT使其大於〇來讀取負竹，且可在不提升本體 偏壓之情形下來讀取正ντ’在此情形下，最大正ντ將為 大約4 V且未高到如該等圖中之經偏㈣軸所反映…或 6 V以上。 128993.doc -24- 200849247 在圖11B中繪不了第一遍程式化。在第一程式化脈衝過 程中，彼等最終將被程式化為資料狀態〇至7之記憶體單元 將被程式為一低於狀態0之臨限電壓分佈之低電壓分佈。 例如，圖1 1B顯示將彼等記憶體單元程式化為中間臨限電 壓分佈LM01。最終將被程式化為資料狀態8至15之記憶體 單元群組將被程式化為一中間臨限電壓分佈（在圖丨1β上標 示為LM02)。在一實施例中，臨限電壓分mLM〇2f大於資 料狀悲7之臨限電壓。在此第一遍之程式化脈衝之間，執 行兩個驗證作業：一個針對LM01且一個針對LM02。因 此’在程式脈衝之間，將使用兩個驗證脈衝。從該程式過 程開始直到至少一個記憶體單元達到LM01(此時，該系統 將使用兩個驗證脈衝）可僅使用一個驗證脈衝（僅用於 LM01)。在其他實施例中，第一遍程式化可程式化為兩個 以上臨限電壓分佈。在一實施例中，資料經擦除為狀態〇 且最終將被程式化為資料狀態8至15之記憶體單元將被程 式化為一中間臨限電壓分佈，而最終將被程式化為資料狀 態0至7之記憶體單元將仍處於狀態〇。在另一實施例中， LM01可稍微與經擦除之臨限電壓分佈e重疊，此乃因ECC 能處理一定百分比的發生錯誤之記憶體單元。因此，該遍 程式化可在已驗證除了 K個位元之外的所有位元時結束， 其中K為一可由ECC校正之數目。 在圖1 1C中繪示了第二遍程式化。彼等將被程式化為資 料狀態0至3之記憶體單元將自LM〇丨程式化為臨限電壓分 佈LM11。例如，圖11C顯示臨限電壓分佈lM〇丨（虛線）及 128993.doc -25- 200849247 LM11(實線）。最終將被程式化為資料狀態3至7之記憶體單 兀將自LM01程式化為中間臨限電壓分佈LM12。最終將被 程式化為資料狀態8至1 1之記憶體單元將自L_2程式化為 中間臨限電壓分佈LM13。》皮等最終將被程式化為資料狀 恶12至15之記憶體單元將自乙“们程式化為中間臨限電壓 为佈LM14。在第二遍程式化期間，在程式化脈衝之間需 要執行多達四個驗證作業··一個針對LMU之驗證作業， 一個針對LM12之驗證作業，一個針對]^1^13之驗證作業， 及一個針對LMU之驗證作業。因此，在每一程式化脈衝 之間，將存在多達四個驗證脈衝。在一些實施例中，可藉 由使用-種確定何時可由於沒有記憶體單元接近—特定目 標而省略某些驗證脈衝之智慧方案來減少驗證脈衝之數 目。可使用各種方案。關於有效驗證方案之更多資訊可參 見美國專利7,073，1()3中，該專利之全文以引用方式倂入本 文中由於ECC可處理_定百分比的發生錯誤之記憶體單 元故在另實轭例中，LM11可與LM12重疊，且LM13可 舁LM14重噎。另外，LM12可與LM01或LM02重疊，且 LM14可與1^02重®。因此，該遍程式化可在已驗證除了 κ個位元之外的所有位元時結束，其中κ為一可由ecc校正 之數目。 在圖D中、、、曰示了第二遍程式化。彼等最終將被程式化 為資料狀態0與1之記憶體單元將自LM11程式化為中間臨 限電壓/刀佈LM21。彼等將被程式化為資料狀態2與3之記 體單兀將自LM11程式化為中間臨限電壓分佈LM22。彼 128993.doc -26- 200849247 專將被程式化為資料狀態4與5之記憶體單元將自LM 1 2程 式化為中間臨限電壓分佈LM23。彼等將被程式化為資料 狀恶6與7之記憶體單元將自lm 12程式化為中間臨限電壓 分佈LM24。彼等將被程式化為資料狀態8與9之記憶體單 凡將自LM13程式化為中間臨限電壓分佈lm25。彼等將被 程式化為資料狀態⑺與丨丨之記憶體單元將自LM13程式化 為中間臨限電壓分佈LM26。彼等將被程式化為資料狀態 12與13之δ己憶體單元將自lm 14程式化為中間臨限電壓分 佈LM27。彼等將被程式化為資料狀態14與15之記憶體單 元將自LM14程式化為中間臨限電壓分佈lm28。由於ECC 可處理一定百分比的發生錯誤之記憶體單元，故在另一實 施例中，相鄰LM2x分佈可彼此重疊（例如，LM26可與 LM25重疊）。另外，LM2x*佈亦可與謹丨乂分佈重疊（例 如，LM26可與LM13重疊）。因此，此遍程式化可在已驗證 除了 K個位元之外的所有位元時結束，其中κ為一可由 校正之數目。 在圖11E中繪示了第四遍程式化。在第四遍程式化中， 將被私式化為資料狀態〇之記憶體單元將自LM2 1程式化為 資料狀態0。將被程式化為資料狀態丨之記憶體單元將自 LM2 1程式化為資料狀態丨。將被程式化為資料狀態2之記 憶體單元將自LM22程式化為資料狀態2。將被程式化為資 料狀態3之記憶體單元將自LM22程式化為資料狀態3。將 被程式化為資料狀態4之記憶體單元將自LM23程式化為資 料狀態4。將被程式化為資料狀態5之記憶體單元將自 128993.doc -27- 200849247 LM23程式化為資料狀態5。將被程式化為資料狀態6之記 憶體單兀將自LM24程式化為資料狀態6。將被程式化為資 料狀怨7之纪憶體單元將自LM24程式化為資料狀態7。將 被程式化為貧料狀態8之記憶體單元將自LM25程式化為資 料狀悲8。將被程式化為資料狀態9之記憶體單元將自 LM25程式化為貧料狀態9。將被程式化為資料狀態丨〇之記 憶體單兀將自LM26程式化為資料狀態丨〇。將被程式化為 貧料狀態11之記憶體單元將自LM26程式化為資料狀態 11。將被程式化為資料狀態12之記憶體單元將自程 式化為資料狀態12。將被程式化為資料狀態13之記憶體單 元將自LM27程式化為資料狀態13。將被程式化為資料狀 態14之記憶體單元將自LM28程式化為資料狀態14。將被 程式化為資料狀態15之記憶體單元將自LM28程式化為資 料狀態15。如以上對圖7所論述，另一實施例包含重疊= 資料狀怨（M5。其他實施例可包含彼此重疊之中間[Μ狀 態，特別在直到整個區塊經歷完整個程式化序列時，資料 之二進制形式仍然存在。 / 在一實施例中，當接收一程式化資料之請求時，該請求 伴隨有所有四頁的資料以便在一字線上之所有記憶體^元 可程式化為資料狀態0至15之任意一者。在該情形下，基 於所接收之資料實施圖丨丨A-D中之四遍程式化。 在另一實施例中，一記憶體系統一次可接收少於所有四 個頁。在該情形下，可最初將記憶體單元寫作二進制弋憒 體單元’其中每一資料頁被寫入不同 128993.doc -28- 200849247 除成為經擦除狀態且將一個眘枓Α 一 個貝枓位兀程式化入記憶體單元 中以使某些記憶體單元仍處於娘橄 处於、、、工擦除狀態（狀態1)且某些記 體単兀處於經程式化狀態（狀態〇)。當接收一第一記情頁 時，將彼資料以二進制模式寫入一 ^ , 弟一 §己體単元區塊 中。當接收第二資料頁時，將彼 一 攸貝才+寫入一第二記憶體單 凡區塊中。當接收第三資料頁時 ^ τ 將彼貝枓頁以二進制形 式寫入一第三記憶體單元區塊中。 ^ τ 田接收第四資料頁時， 將彼資料以二進制形式寫入—楚 ^ 、 、 八馬入弟四記憶體單元區塊中。一 旦寫入所有四個區塊，則系始 j糸統可糟由使用圖11A-D之四遍 程式化過程對每一記憶體單元 ^ 私式化四個賢料位元來將所 有四個區塊重寫入一個區塊中。 在另一實施例中，一頁一百士宜 貝地寫入一個二進制區塊直到 寫完該區塊。然後，一頁一百士宜 貝地寫入另一個二進制區塊直 到亦寫完該區塊。隨德，以你a 一 凡丨通佼以與則兩個區塊相同之方式寫入 一第三個二進制區塊及-第四個二進㈣塊。當四個完成 Ο 的二進制區塊可用日夺，則將該等四個區塊中之資料壓縮並 以每個記憶體單元4個位元 ' 、❿式冩入區塊中。在一實施 例中’首先將該等二進龍塊中之資料發送至其中實施二 進制ECC解碼之控制器日日日片，且隨後除了實施資料置亂之 外’實施適合每記憶體單元 u i0禋狀恶之另一類型ECC解 碼，且將新資料發回至用於 冷人馬入母5己憶體早凡4種狀態 之區塊之記憶體晶片。 圖12係-流程圖’其騎—用於程式化連接至—已選擇 字線之記憶體單元之程式化過程。諸多不同程式化技術可 128993.doc -29. 200849247 用於本發明。在一實施例中，由控制電路22〇及/或在控制 電路220指示下（狀態機222提供控制且功率控制226提供合 適信號）及/或在控制器244之指示下實施圖1〇中之過程。: —實施例中，圖12中之過程用來對連接至(例如，藉由其 控制閘極）一字線之記憶體單元實施圖ua_e中之四遍程式 化過程中之一遍。 在步驟624中，由控制器244發佈—，，資料載人"命令，並 將此命令輸入狀態機22h在步驟626中，向解碼器電路提 供指示頁位址之位址資料。在步驟628 輸入一頁程式資料以供程式化。例如，在—實施例= 入528個貧料字組。將彼資料鎖存在所選位元線之合適的 暫存器/鎖存器中。在一些實施例中，亦可將資料鎖存於The negative threshold voltage distribution is shifted into the positive voltage region. This change of the threshold voltage by applying a reverse bulk bias is attributed to the well-known bulk effect phenomenon. In the context of most NAND memory, the p well constitutes the body. To simplify the Vt axis in the graphs UA to 11D, the offset is relative to the actual one so that all VTs appear positive. In practice, the negative radii can be read by using the reverse body bias to raise the VT to be larger than 〇, and the positive ντ′ can be read without raising the body bias. In this case, the maximum positive ντ It will be approximately 4 V and not as high as reflected by the biased (four) axis in the figures... or 6 V or more. 128993.doc -24- 200849247 The first pass stylization is not depicted in Figure 11B. During the first stylized pulse, the memory cells that will eventually be programmed into data states 〇 to 7 will be programmed to a low voltage distribution below the threshold voltage distribution of state 0. For example, Figure 11B shows the stylization of their memory cells to the intermediate threshold voltage distribution LM01. The group of memory cells that will eventually be programmed into data states 8 through 15 will be programmed into an intermediate threshold voltage distribution (labeled LM02 on Figure 1β). In one embodiment, the threshold voltage fraction mLM 〇 2f is greater than the threshold voltage of the data sorrow. Between the stylized pulses of the first pass, two verification jobs are performed: one for LM01 and one for LM02. Therefore, between the program pulses, two verify pulses will be used. From the beginning of the program process until at least one memory unit reaches LM01 (in which case the system will use two verify pulses), only one verify pulse can be used (for LM01 only). In other embodiments, the first pass stylization can be programmed into more than two threshold voltage distributions. In one embodiment, the memory cells that are erased to state and eventually programmed into data states 8 through 15 will be programmed into an intermediate threshold voltage distribution that will eventually be programmed into a data state. The memory cells from 0 to 7 will remain in the state 〇. In another embodiment, LM01 may overlap slightly with the erased threshold voltage distribution e because ECC can handle a certain percentage of memory cells that have failed. Thus, the programming can end when all bits except K bits have been verified, where K is a number that can be corrected by ECC. The second pass stylization is depicted in Figure 1 1C. The memory cells that will be programmed into data states 0 through 3 will be programmed from LM〇丨 to the threshold voltage distribution LM11. For example, Figure 11C shows the threshold voltage distribution lM〇丨 (dashed line) and 128993.doc -25-200849247 LM11 (solid line). The memory file that will eventually be programmed into data states 3 through 7 will be programmed from LM01 to the intermediate threshold voltage distribution LM12. The memory cells that will eventually be programmed into data states 8 through 1 will be programmed from L_2 to the intermediate threshold voltage distribution LM13. The skin units that will eventually be stylized as data-like murmurs 12 to 15 will be programmed from B to the intermediate threshold voltage for the cloth LM14. During the second pass of the stylization, between the stylized pulses is required. Perform up to four verification jobs • One verification job for LMU, one verification job for LM12, one verification job for ^1^13, and one verification job for LMU. Therefore, in each stylized pulse There will be up to four verification pulses between them. In some embodiments, the verification pulse can be reduced by using a smart scheme that determines when certain verification pulses can be omitted due to no memory unit approaching - a particular target. A number of schemes are available. Various information on an effective verification scheme can be found in U.S. Patent No. 7,073,1 (3), the entire disclosure of which is hereby incorporated by reference inco In the case of another solid yoke, the LM11 can overlap with the LM12, and the LM13 can be overlapped with the LM14. In addition, the LM12 can overlap with the LM01 or LM02, and the LM14 can be combined with the 1^02®. Therefore, the pass Stylization can end when all bits except κ bits have been verified, where κ is the number that can be corrected by ecc. In Figure D, the second pass is programmed, and they will eventually The memory cells that are programmed into data states 0 and 1 will be programmed from LM11 to intermediate threshold voltage/knife LM21. They will be programmed into data states 2 and 3 will be stylized from LM11. For the intermediate threshold voltage distribution LM22. He 128993.doc -26- 200849247 The memory unit that will be programmed into data states 4 and 5 will be programmed from LM 1 2 to the intermediate threshold voltage distribution LM23. They will be The memory cells that are stylized as data-like evils 6 and 7 will be programmed from lm 12 to the intermediate threshold voltage distribution LM24. They will be programmed into data states 8 and 9 and the memory will be programmed from LM13 to The intermediate threshold voltage distribution is lm25. They will be programmed into data states (7) and the memory cells will be programmed from LM13 to the intermediate threshold voltage distribution LM26. They will be programmed into data states 12 and 13 The δ-resonant unit will be programmed from lm 14 to the intermediate threshold voltage LM27. The memory cells that will be programmed into data states 14 and 15 will be programmed from LM14 to the intermediate threshold voltage distribution lm28. Since ECC can handle a certain percentage of memory cells that have errors, in another implementation In the example, the adjacent LM2x distributions may overlap each other (for example, the LM26 may overlap with the LM25). In addition, the LM2x* cloth may overlap with the 丨乂 丨乂 distribution (for example, the LM26 may overlap with the LM 13). Therefore, this programming can be programmed. Ends when all bits except K bits have been verified, where κ is the number that can be corrected. The fourth pass stylization is depicted in Figure 11E. In the fourth pass stylization, the memory unit that will be privateized to the data state will be programmed from LM2 1 to data state 0. The memory unit that will be programmed into the data state will be programmed from LM2 1 to the data state. The memory unit that will be programmed into data state 2 will be programmed from LM22 to data state 2. The memory unit that will be programmed into data state 3 will be programmed from LM22 to data state 3. The memory unit that will be programmed into data state 4 will be programmed from LM23 to data state 4. The memory unit that will be programmed into data state 5 will be programmed into data state 5 from 128993.doc -27- 200849247 LM23. The memory unit that will be programmed into data state 6 will be programmed from LM24 to data state 6. The unit that will be stylized as a material complaint will be programmed from LM24 to data state 7. The memory unit that will be programmed into a lean state 8 will be programmed from LM25 to a data-like sorrow. The memory unit that will be programmed into data state 9 will be programmed from LM25 to lean state 9. The stylized file will be stylized as a data state and will be programmed from the LM26 to a data state. The memory unit that will be programmed into the lean state 11 will be programmed from the LM26 to the data state 11 . The memory unit that will be programmed into data state 12 will be self-programmed to data state 12. The memory unit that will be programmed into data state 13 will be programmed from LM27 to data state 13. The memory unit that will be programmed into data state 14 will be programmed from LM28 to data state 14. The memory unit that will be programmed into data state 15 will be programmed from LM28 to data state 15. As discussed above with respect to Figure 7, another embodiment includes overlap = data grievances (M5. Other embodiments may include intermediates that overlap each other [Μ state, especially until the entire block experiences a complete stylized sequence, data The binary form still exists. / In one embodiment, when receiving a request for stylized data, the request is accompanied by all four pages of data so that all of the memory elements on a word line can be programmed into data state 0 to Any of the following: In this case, the four-pass stylization in the map AD is implemented based on the received data. In another embodiment, a memory system can receive less than all four pages at a time. In this case, the memory unit can be initially written as a binary unit, where each data page is written to a different 128993.doc -28-200849247, except that it is erased and will be a cautious one. Stylized into the memory unit so that some memory cells are still in the state of being in the state of being erased (state 1) and some of the records are in a stylized state (state 〇). In the first note page, the data is written in binary mode in a binary mode. When receiving the second data page, the other data is written into a second memory. In the single block, when the third data page is received, ^ τ writes the page of the Bieber into a third memory unit block in binary form. ^ τ When receiving the fourth data page, the data is in binary. Formal writing—Chu^, , and 八马in the four-memory unit block. Once all four blocks are written, it is possible to use the four-pass stylization process of Figure 11A-D for each A memory unit ^ privately digitizes four resources to rewrite all four blocks into one block. In another embodiment, one page is written to a binary block. Until the block is written. Then, one page of one hundred words is written to another binary block until the block is also written. With the German, you can use the same two blocks. In the same way, write a third binary block and - the fourth binary (four) block. When the four completed 二进制 binary If the block is available, the data in the four blocks is compressed and entered into the block by 4 bits in each memory unit. In an embodiment, 'the first two are entered. The data in the block is sent to the controller day and day chip in which the binary ECC decoding is implemented, and then another type of ECC decoding suitable for each memory unit is implemented except for the data scrambling. The new data is sent back to the memory chip used for the block of the 4 states of the cold man. Figure 12 is a flow chart 'the ride' is used to programmatically connect to the selected word line. The stylization process of memory cells. A number of different stylization techniques can be used in the present invention 128993.doc -29. 200849247. In one embodiment, the control circuit 22 is and/or indicated by the control circuit 220 (the state machine 222 provides control and the power control 226 provides a suitable signal) and/or is implemented under the direction of the controller 244. process. In the embodiment, the process of Figure 12 is used to implement one of the four pass programming operations in Figure ua_e for a memory cell connected to a word line (e.g., by its control gate). In step 624, the controller 244 issues a data manned " command and inputs the command to the state machine 22h in step 626 to provide the decoder circuit with the address data indicating the page address. At step 628, a page of program data is entered for stylization. For example, in the embodiment = 528 poor plots. The data is latched in the appropriate register/latch of the selected bit line. In some embodiments, the data can also be latched in

所選位元線之第二暫存器内以供用於驗證作業。在步驟 63〇中，自控制器244接收一"程式化”命令並提供給狀態機 如。由”程式化"命令觸發後，使用—組施加至合適字線 之脈衝將在步驟628中鎖存的資料程式化人由狀態機222控 制之所選記憶體單元中^：舟驟 早Y在步驟732中，由狀態機222維護 的程式計數器PC初始化為〇。 在—些實施例中’至少—個多遍程式化子集包含識別一 與獲取-相應料㈣程之特u果㈣聯之程式脈衝及 使用該經_之程式脈衝來調節非揮發㈣存元件之隨後 私式化過程之程式化。在一實例中’系統將識別可使第一 記憶體單元達到其目標之程式脈衝。在另一實例中，*** 將識別使第一N個記憶體單元達到其目標之程式脈衝，其 128993.doc -30- 200849247 中N為一少於可由ECC校正之锊嘩旦夕鉍曰 仅止之錯决里之數量。已識別之拙The second register of the selected bit line is used for verification work. In step 63, a "stylized" command is received from controller 244 and provided to the state machine. After being triggered by the "stylized" command, the pulse applied to the appropriate word line using the set will be in step 628. The latched data stylized person is selected by the state machine 222 in the selected memory unit. The boat is prematurely Y. In step 732, the program counter PC maintained by the state machine 222 is initialized to 〇. In some embodiments, 'at least one multi-pass stylized subset includes a program pulse that identifies a special-element (four) process of the acquisition-corresponding material (four) and uses the program pulse to adjust the non-volatile (four) memory component. The subsequent stylization of the private process. In one example, the system will identify a program pulse that causes the first memory unit to reach its target. In another example, the system will identify a program pulse that causes the first N memory cells to reach their target, and the N in 128993.doc -30- 200849247 is less than the one that can be corrected by the ECC. The number of mistakes. Recognized

脈衝將具有一量值。為一 ^ / ) JU 里值在一實施例中，隨後一遍程式化 一脈衝量值將設定為盘ρ Μ ^ 、 疋馮ν、已硪別脈衝之Ϊ值相同。例如，若 第遍私式化之第四個程式脈衝導致使第一記憶體單元 到其目標且該第四個程式 、 ,u狂八脈衝之篁值為14伏，則第二遍程 =化之第-程式脈衝量值將被設定為14伏。以此方式，^ -遍程式化中所觀察的行為可影響隨後—遍程式化。The pulse will have a magnitude. For a ^ / ) JU value in an embodiment, the subsequent one-stroke pulse value will be set to the same value of the disc ρ Μ ^, 疋 von ν, the discriminating pulse. For example, if the fourth program pulse of the first privateization causes the first memory unit to reach its target and the fourth program, the value of the u mad eight pulse is 14 volts, then the second pass = The first-program pulse value will be set to 14 volts. In this way, the behavior observed in the programming can affect subsequent-pass programming.

在其他實施例中’可實施其他變體。例如，可基於前— 遍中已識別脈衝來設㈣後—遍之第—脈衝，但不用使直 量值精確地相等。 〃 另卜$ 遍权式化中之程式脈衝可與一不同於第一記 憶體單元(或多個)達到其目標之事件相關聯。例如，可在 °己隐體單it達到—中間位準或其他狀態時識別—程式化 脈衝。 因此’當開始-遍新程式化時，系統將存取識別與達成 預定特定結果相關聯之前—遍程式化中之程式脈衝的資訊 (步驟634)。系統將自—暫存器一快閃記憶體單元或其他 非揮發性儲存裝置中讀取識別脈衝之資訊。在-實施例 中，對一個多遍程式化過程之第一遍不實施步驟634，並 端視裝置特徵將第一程式化脈衝之初始量值設定為1〇_17 伏之標稱值。 在步驟636中，基於自前一遍程式化中所識別並在步驟 634中讀取的脈衝來設定程式化信號Vpgm之第一程式脈衝 量值。在步驟640中，將程式信號Vpgm之一個脈衝施加至 128993.doc -31 - 200849247 所選字線。 在步驟⑷中’制適合的目標位準集合來驗證所選吃 憶體早兀之資料狀態。^經偵測—所選記憶體單元之臨限 電壓已達到合適目標位準，_由提升該記憶體單元之位 :線電壓將該記憶體單元封鎖^再針對_之剩餘過程 實施進一步程式化。亦可使用其它封鎖技術。 若在該遍程式化期間經第一次偵測，經程式化之第一 N(其中N可為i或更多）個記憶體單元已達到其目標資料狀 態，則在步驟644中，將關於此程式脈衝之資訊儲存（步驟 646)於一諸如快閃記憶體單元或暫存器等非揮發性儲存裝 置中。此脈衝將用來設定下一遍程式化之第一脈衝量值。 在另一實施例中，藉由確定N個記憶體單元是否由於其已 達到目標狀態而自非封鎖變為封鎖以不進行進一步程式化 來實施步驟644。在一些實施例中，不對以下記憶體單元 r施步驟644之分析：自LM01程式化為LM1 1、自LM02程 式化為LM13、自LM11程式化為LM21、自LM12程式化為 23、自[M13程式化為LM25及自LM14程式化為LM27之記 憶體單元。在一實施例中，對於多遍程式化過程之最後一 遍不實施步驟644及646。 在步驟646之後，該過程繼續到步驟648。若當前脈衝在 該遍程式化期間並非第一次使經程式化的第一 N個記憶體 單元達到其目標資料狀態，則該過程會不經實施步驟646 而繼續到步驟648。 若所有經程式化記憶體單元皆已達到其目標資料狀態 128993.doc .32- 200849247 (步驟648)，則該程式化過程完成並成功。在步驟65〇處報 告”通過（pASS)m主意，在步驟648之某些實施案 中’校驗是否至少一預定數目的記憶體單元已經驗證為達 到其目標狀態。此預定數目可小於所有記憶體單元之數 目，因此允許在所有記憶體單元達到其適合驗證位準之前 停止程式化過程。未成功程式化之記憶料元可在讀取過 程期間使用錯誤校正來校正。 右在步驟648中確定並非所有記憶體單元已經達到其目 標狀態，則繼續該程式化過程。在步驟66〇中，對照一程 式限值來校驗程式計數器Pc。程式限值之一實例為2〇;然 而在各種實施案中可使用其他值。若程式計數器pc不小 於程式限值’則在步驟666中確定未成功程式化之記憶體 單元數目是否等於或小於一預定數目。若未成功程式化之 記憶體單元數目等於或小於該預定數目，則該程式化過程 標記為通過並在步驟668處報告通過（pAss)狀態。在諸多 情形下，未成功程式化之記憶體單元可在讀取過程中使用 糾錯過程來校正。然而，若未成功程式化之記憶體單元數 目大於該預定數目’則此程式化過程標記為失敗並在步驟 670中報σ失敗（FAIL)狀悲、。若在步驟66〇中確定程式計數 器pc小於程式限值，則在步驟662中，下—vpgm脈衝之量 值增加一步長且程式計數器Pc之計數增加。在步驟662之 後，此過程循環回至步驟640以施加下一 Vpgm脈衝。 程式化信號VPgm之程式脈衝具有以一步長增加之漸增 量值。在-實施例中’該步長為f數以使每_遍程式化中 128993.doc -33- 200849247 之每-脈衝自其前-脈衝增加相同步長，在另一實施例 中’每-遍程式化（或多遍程式化之子集）將採用一不同步 長（見步驟652)。例如，第一遍程式化將具有一 〇·4伏的步 長，第二遍程式化將具有一〇·7伏的步長，第三遍 將具有-G.35伏的步長，且第四遍程式化將具有伏 的步長。亦可使用其它值。Other variations may be implemented in other embodiments. For example, the (-)th-pass-first pulse can be set based on the identified pulses in the previous-pass, but the magnitudes are not necessarily equal.程式 Another program pulse in the weighting process can be associated with an event different from the first memory unit (or multiple) reaching its goal. For example, a stylized pulse can be identified when the hidden unit is reached - the intermediate level or other state. Thus, when a new programming is initiated, the system will access information identifying the program pulses in the previous programming associated with the achievement of the predetermined specific result (step 634). The system reads the information of the identification pulse from the scratchpad-flash memory unit or other non-volatile storage device. In an embodiment, step 634 is not implemented for the first pass of a multi-pass stylization process, and the end device feature sets the initial magnitude of the first stylized pulse to a nominal value of 1 〇 17 volts. In step 636, the first program pulse magnitude of the stylized signal Vpgm is set based on the pulse identified from the previous programming and read in step 634. In step 640, a pulse of the program signal Vpgm is applied to the selected word line of 128993.doc -31 - 200849247. In step (4), a suitable set of target levels is made to verify the status of the data of the selected memory. ^Detected - the threshold voltage of the selected memory unit has reached the appropriate target level, _ by raising the position of the memory unit: the line voltage blocks the memory unit and further stylizes the remaining process of _ . Other blocking techniques can also be used. If the first N (where N can be i or more) memory cells have reached their target data state after the first detection during the programming period, then in step 644, The information of the program pulse is stored (step 646) in a non-volatile storage device such as a flash memory unit or a scratchpad. This pulse will be used to set the first pulsed value for the next pass. In another embodiment, step 644 is implemented by determining whether the N memory cells have changed from non-blocking to blocking because they have reached the target state without further stylization. In some embodiments, the following memory cell r is not analyzed in step 644: from LM01 to LM1 1, from LM02 to LM13, from LM11 to LM21, from LM12 to 23, from [M13 Stylized as LM25 and from LM14 to LM27 memory unit. In one embodiment, steps 644 and 646 are not implemented for the last pass of the multi-pass stylization process. After step 646, the process continues to step 648. If the current pulse does not cause the programmed first N memory cells to reach their target data state for the first time during the programming, then the process proceeds to step 648 without performing step 646. If all of the stylized memory units have reached their target data status 128993.doc .32- 200849247 (step 648), the stylization process is complete and successful. At step 65, the report "pass (pASS)m idea, in some embodiments of step 648, 'checks if at least a predetermined number of memory cells have been verified to reach their target state. This predetermined number can be less than all memories. The number of body units, thus allowing the stylization process to be stopped before all memory cells reach their appropriate verification level. Unsuccessfully programmed memory cells can be corrected using error correction during the reading process. Right in step 648 Not all memory cells have reached their target state, then the stylization process continues. In step 66, the program counter Pc is checked against a program limit. One example of the program limit is 2〇; however, in various implementations Other values may be used in the case. If the program counter pc is not less than the program limit', then in step 666, it is determined whether the number of unsuccessfully programmed memory cells is equal to or less than a predetermined number. If the number of memory cells is not successfully programmed Equal to or less than the predetermined number, the stylization process is marked as passing and reporting the pass (pAss) state at step 668. In many cases, unsuccessfully programmed memory cells can be corrected using an error correction process during the reading process. However, if the number of memory cells that have not been successfully programmed is greater than the predetermined number, then the stylization process is marked as failed. And in step 670, the sigma failure (FAIL) is reported. If it is determined in step 66 that the program counter pc is less than the program limit, then in step 662, the magnitude of the lower-vpgm pulse is increased by one step and the program counter Pc. The count is incremented. After step 662, the process loops back to step 640 to apply the next Vpgm pulse. The programmed pulse of the stylized signal VPgm has an incremental value that increases in one step. In the embodiment, the step is The f-number is such that each pulse of 128993.doc -33- 200849247 is synchronized from its pre-pulse increment in each stylized, in another embodiment 'per-pass stylization (or multi-pass stylization) The subset will be unsynchronized (see step 652). For example, the first pass will have a step size of 4 volts, and the second pass will have a step size of 〇7 volts. Three passes will have a step of -G.35 volts And having a fourth time programmable volt step size. Other values may also be used.

在一替代實施例中，僅在第一遍程式化期間實施步驟 644與步驟646。因此，隨後三遍程式化將使用一基於該第 一遍程式化之第一程式脈衝量值。 針對每一遍程式化實施一次圖12中的過程。在其中有Μ 個字線且每個字線實施四遍程式化之情形下，針對每一區 塊可執行4x64次圖12中的過程。 圖12Α顯示具有一組程式脈衝68〇之程式化電壓信號 Vpgm之一實例，該等程式脈衝之量值以一步長增加。該 步長繪示為線684與線686之間的空間。驗證脈衝（例如， 驗證脈衝682)在程式脈衝之間。圖12A顯示可用於區分四 個資料狀態的三個驗證脈衝。僅繪示三個脈衝以使此圖易 頃。在一使用十六個資料狀態之實施例中，在程式脈衝之 間可能有多達15個驗證脈衝。再返回觀察圖12，步驟64〇 包含施加一程式脈衝68〇而步驟642包含施加一組驗證脈衝 (例如’多達十五個之一組脈衝）682。 圖13描繪用於在一記憶體區塊之不同字線上程式化不同 遍程式化的次序。例如，圖13將初始作業識別為在字線 WL0上實施第一遍（圖丨1B)，隨後在字線WL1上實施第一 128993.doc -34- 200849247 遍，隨後在字線WL0上實施第二遍（圖uc)，隨後在字線 WL2上實施第一遍，隨後在字線WL1上實施第二遍，隨後 在子線WL0上實施第三遍（圖丨1D)，隨後在字線WL3上實 轭第一遍，···隨後在字線WL63上實施第四遍（圖iiE)。由 圖13繪示的多遍程式化序列稱為對角序列過程，此乃因該 順序沿圖13中圖表的對角進行。在其他實施例中，亦可使 用其他序列。 在一實施例中，每一遍可對應一資料頁。例如，觀察圖 8及圖1 1B，若下部頁接收資料丨則將記憶體單元程式化為 LM01，且若下部頁接收資料〇則將記憶體單元程式化為 LM02。因此，在第一遍程式化之後，可基於記憶體單元 之g品限電壓處於LM01還是LM02來讀取下部頁資料為j還 是為〇。第二遍程式化可與上部資料頁之程式化相關。例 如，觀察圖8及圖11C，若第二上部資料頁為資料丨，則將 a己fe?體單元程式化為LM1 1或者LM13。若上部資料頁為資 料〇 ’則將記憶體單元程式化為LM12或LM14。藉由測試 記憶體單元的臨限電壓在哪一臨限電壓分佈内，可讀取第 二資料頁以及第一資料頁。第三遍程式化可對應於程式化 高部資料頁。例如，將為資料1的高部頁資料儲存於 LM21、LM23、LM25 及 LM27中。資料〇將儲存 kLM22、 LM24、LM26或LM28中。第四遍可對應於將頂部資料頁程 式化為合適貧料狀態。 圖14為一流程圖，其描繪在使用軟程式化結果來調節多 遍程式化之替代實施例中操作非揮發性記憶體之過程。在 128993.doc -35- 200849247 步驟700中，擦除一記憶體 &卜 平凡^塊。在步驟702中，實施 軟私式化。軟程式化過程可包 、 12iftr 1匕3貫施經某些稍微改動之圖 I2過私。不需要實施步驟63 予广 4且步驟636通常會將初始脈衝 電屋設定於某個標稱值（例 W祝於裝置特徵而定設定 在10伏與17伏之間）。當州固 圯f思體早兀由於已達到經擦除 ⑽體單元之合適目標臨限電壓分佈而被封鎖不再進行軟 程式化時’在圖12之步驟646中枝左祖从处 娜046中儲存對彼等程式化脈衝之 識別。可將識別程式脈衝之資訊儲存於一暫存器 閃記憶體單元中。在步驟704中，接收一程式資料請求。、 在步驟702與704之間存在一声綞 甘此- 虛線，，、4曰示在一段時間之間 可實施中間步驟。在一此者 隹二錢鈿例中，可在未接收一程式化 貧料請求之情形下程式化資料。在步驟中，使用圖 11A-时的多遍程式化過程（或另—多遍程式化過程）將資 料程式化於偏離經擦除臨限電壓分佈之記憶體單元中。在 圖14中之每一遍程式化φ | 、不式化中，基於在步驟7〇2之軟程式化過 私中所觀察的仃為設定第一程式脈衝的量值。在步驟· 中’自記憶體單元讀取資料。在一實施例中，如在圖… 所繪示’聯合擦除記憶體單元實施軟程式化。在其他實施 例中’软知式化可與程式化（例如，回應於一程式化請求） 聯合實施。 圖15提供-實施圖14中的步驟7〇6之流程圖的實例。圖 15中的步驟824·832與圖12中的步驟㈣收相同。在步驟 834中U讀取在圖14中的步驟中儲存的來自該遍軟 程式化之程式脈衝識別。在步驟836中，基於在步驟中 128993.doc -36 - 200849247 ό賣取的經識別脈衝設定程式化信號vpgm之第一程式脈衝 量值。在一實施例中，將當前遍程式化之第一程式脈衝量 值設定為與在步驟834中讀取的脈衝量值相同。因此，在 步驟834中讀取的資訊可包含量值資訊、脈衝數目資訊（根 據該資訊可計算出量值）或可用來確定合適量值之其他資 訊。在步驟840中，將程式脈衝施加至所選字線以實施程 式化。在步驟842中，驗證沿所選字線之記憶體單元。若 所有或一預訂數目之記憶體單元通過該驗證（步驟844)，則 在步驟846中該過程完成且成功（狀態=通過）。若未驗證所 有或足夠數目之記憶體單元，則在步驟86〇中確定程式計 數裔是否低於一預定限值。若低於該預定限值，則在步驟 862中將程式#號Vpgm的電壓量值增加一步長且程式計數 器亦增加。如以上所述，該步長可基於正在實施哪遍程式 化而變化。在步驟862之後，該過程循環回至步驟84〇且施 加下一個程式脈衝。若在步驟86〇中確定程式計數器大於 預定限值且未成功程式化之記憶體單元數目小於一預定數 目（步驟866)，則在步驟868中該過程成功完成（狀態=通 過）。否則，若未成功程式化之記憶體單元數目不小於或 等於該預定數目（步驟866)，則在步驟87〇中該過程失敗。 針對每一遍程式化實施一次圖15中的過程。在一其中有 64個字線及每個字線實施四遍程式化之情形下，針對每一 區塊可實施4x64次圖15中的過程。 圖16提供一另一實施例之流程圖，該實施例使用軟程式 化過程來確定一遍單獨程式化過程的程式化信號的初始量 128993.doc -37- 200849247 ^ =驟m中，擦除一記憶體單元區塊。在步驟m 、讀％式化且系統儲存與當_記憶體單元驗證為 臨限電壓分佈時相關聯之程式脈衝識別。如以上所 論述，端視裝置建置而定，N可等於卜2、…。圖16中之 步驟：與圖14之步驟702相同。在步驟884中，接收一程 ，化：料之凊求。在步驟886中’使用一遍單獨程式化過 =將^貝料程式化人自經擦除臨限電壓分佈變為任—資料狀In an alternate embodiment, steps 644 and 646 are implemented only during the first pass of stylization. Therefore, the subsequent three-pass stylization will use a first program pulse magnitude based on the first pass. The process in Figure 12 is implemented once for each pass of stylization. In the case where there are 字 word lines and each word line is programmed four times, the process in Figure 12 can be performed 4x64 times for each block. Figure 12A shows an example of a stylized voltage signal Vpgm having a set of program pulses 68, the magnitude of which is increased by one step. This step is depicted as the space between line 684 and line 686. A verify pulse (eg, verify pulse 682) is between the program pulses. Figure 12A shows three verify pulses that can be used to distinguish four data states. Only three pulses are shown to make this diagram easy. In an embodiment using sixteen data states, there may be up to 15 verify pulses between program pulses. Returning to Fig. 12, step 64A includes applying a program pulse 68 and step 642 includes applying a set of verify pulses (e.g., 'up to fifteen sets of pulses 682'). Figure 13 depicts the order in which different programming passes are programmed for different word lines on a memory block. For example, FIG. 13 identifies the initial job as implementing the first pass on word line WL0 (FIG. 1B), then implementing the first 128993.doc -34-200849247 pass on word line WL1, followed by implementation on word line WL0. Two passes (Fig. uc), followed by a first pass on word line WL2, followed by a second pass on word line WL1, followed by a third pass on sub-line WL0 (Fig. 1D), followed by word line WL3 The first pass of the upper solid yoke, then the fourth pass is performed on the word line WL63 (Fig. iiE). The multi-pass stylized sequence illustrated by Figure 13 is referred to as a diagonal sequence process, as this sequence proceeds diagonally along the graph of Figure 13. In other embodiments, other sequences may also be used. In an embodiment, each pass may correspond to a data page. For example, look at Figure 8 and Figure 1B. If the lower page receives data, the memory unit is programmed to LM01, and if the lower page receives data, the memory unit is programmed to LM02. Therefore, after the first pass is programmed, the lower page data can be read as j or 基于 based on whether the voltage limit voltage of the memory cell is at LM01 or LM02. The second pass can be related to the stylization of the upper data page. For example, if FIG. 8 and FIG. 11C are observed, if the second upper data page is data, the a-fe body unit is programmed into LM1 1 or LM13. If the upper data page is 〇 ’, the memory unit is programmed into LM12 or LM14. The second data page and the first data page can be read by testing in which threshold voltage distribution the threshold voltage of the memory cell is within. The third pass can be programmed to correspond to the stylized high profile page. For example, the high page data for the data 1 is stored in the LM21, LM23, LM25, and LM27. The data will be stored in the kLM22, LM24, LM26 or LM28. The fourth pass may correspond to programming the top data page to a suitable lean state. Figure 14 is a flow chart depicting the process of operating a non-volatile memory in an alternate embodiment of using a soft stylization result to adjust a multi-pass stylization. In step 128, 128993.doc -35- 200849247, a memory & In step 702, soft privateization is implemented. The soft stylization process can be packaged, 12iftr 1 匕 3 through some slightly modified map I2 private. Step 63 is not required to be implemented and step 636 typically sets the initial pulse house to a nominal value (eg, between 10 volts and 17 volts depending on device characteristics). When the state's 圯 圯 思 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 046 046 046 046 046 046 046 046 046 046 046 046 046 046 046 046 046 046 046 046 046 046 The storage identifies the identification of their stylized pulses. The information of the identification program pulse can be stored in a scratchpad flash memory unit. In step 704, a program data request is received. Between the steps 702 and 704, there is a 缍 此 - 虚线 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - In this case, in the case of the second money, the data can be stylized without receiving a stylized poor request. In the step, the multi-pass stylization process (or another multi-pass stylization process) of Figure 11A- is used to program the data into memory cells that deviate from the erased threshold voltage distribution. In each of the stylized φ | and the irregularizations in Fig. 14, the magnitude of the first program pulse is set based on the 观察 observed in the soft stylization of step 7〇2. Read the data from the memory unit in step ·. In one embodiment, the associative erase memory unit is implemented as shown in the figure. In other embodiments, 'software can be implemented in conjunction with stylization (e.g., in response to a stylized request). Figure 15 provides an example of a flow chart for implementing steps 7〇6 of Figure 14. Step 824·832 in Fig. 15 is the same as step (4) in Fig. 12. In step 834, U reads the program pulse identification from the software program stored in the step of Fig. 14. In step 836, the first program pulse value of the stylized signal vpgm is set based on the identified pulse in the step 128993.doc -36 - 200849247. In one embodiment, the first program pulse magnitude currently programmed is set to be the same as the pulse magnitude read in step 834. Thus, the information read in step 834 can include magnitude information, pulse number information (which can be calculated based on the information), or other information that can be used to determine the appropriate amount. In step 840, a program pulse is applied to the selected word line for implementation. In step 842, the memory cells along the selected word line are verified. If all or a predetermined number of memory units pass the verification (step 844), then in step 846 the process is completed and successful (status = pass). If all or a sufficient number of memory cells have not been verified, then in step 86, it is determined if the program count is below a predetermined limit. If it is lower than the predetermined limit, the voltage value of the program ##Vpgm is increased by one step and the program counter is also increased in step 862. As mentioned above, this step size can vary based on which programming is being implemented. After step 862, the process loops back to step 84 and the next program pulse is applied. If it is determined in step 86 that the program counter is greater than the predetermined limit and the number of unsynchronized memory cells is less than a predetermined number (step 866), then the process is successfully completed (status = pass) in step 868. Otherwise, if the number of memory cells that have not been successfully programmed is not less than or equal to the predetermined number (step 866), then the process fails in step 87. The process in Figure 15 is implemented once for each pass of stylization. In the case where there are 64 word lines and each word line is four-pass programmed, 4x64 times the process of Figure 15 can be implemented for each block. Figure 16 provides a flow diagram of another embodiment that uses a soft stylization process to determine the initial amount of a stylized signal for a single stylized process. 128993.doc -37 - 200849247 ^ = m, erase one Memory unit block. At step m, the read % is programmed and the system stores the program pulse identification associated with when the memory cell is verified as a threshold voltage distribution. As discussed above, depending on the configuration of the end view device, N can be equal to b, 2. The steps in Fig. 16 are the same as step 702 of Fig. 14. In step 884, a request is received to determine the request. In step 886, 'use a single stylized version of the ^ beveled stylized person from the erased threshold voltage distribution into any - data

態之記憶體單元中。在步驟m中，讀取記憶體單元並向 一使用者提供資料。 在貝^例中，藉由針對每一字線執行一次圖丄$中的過 程來實施步驟886。亦即，對每一字線實施一遍。在一實 施例中驟880將記憶體單元程式化為經擦除臨限電壓 刀佈E且步驟886將記憶體單元自經擦除臨限電壓分佈e程 式化為資料狀態』至15中之任—者。在另—實施例中，步 驟880將圮憶體單元擦除為資料狀態〇且步驟將所有記 隐體單元或一冗憶體單元子集自資料狀態〇程式化為資料 狀態1至1 5中之任一者。 圖17為一流程圖，其描繪一使用軟程式化過程來改變程 式化過程之驗證部分來操作記憶體單元的過程之實施例。 在步驟902中，擦除一記憶體單元區塊。在步驟9〇4中，實 施一軟程式化過程。在一實施例中，可將記憶體單元擦除 為經擦除臨限電壓分佈E。在其他實施例中，記憶體單元 可擦除為資料狀態0。在軟程式化過程中，系統將識別第N 個（其中N專於1或更大）纟災驗正為適宜經擦除臨限電壓分佈 128993.doc -38- 200849247In the memory unit. In step m, the memory unit is read and provided to a user. In the example, step 886 is implemented by performing a process in map $ for each word line. That is, each word line is implemented once. In one embodiment, step 880 programs the memory cell into an erased threshold voltage knife E and step 886 programs the memory cell from the erased threshold voltage distribution e to a data state to 15 -By. In another embodiment, step 880 erases the memory unit to a data state and the step stylizes all of the secret unit or a subset of the memory unit from the data state to data states 1 through 15. Either. Figure 17 is a flow chart depicting an embodiment of a process for using a soft stylization process to change the verification portion of a programming process to operate a memory cell. In step 902, a memory cell block is erased. In step 9〇4, a soft stylization process is implemented. In one embodiment, the memory cells can be erased to an erased threshold voltage distribution E. In other embodiments, the memory unit can be erased to data state 0. During the soft stylization process, the system will identify the Nth (where N is dedicated to 1 or greater) disaster detection is suitable for the erased threshold voltage distribution 128993.doc -38- 200849247

之記憶體單元的程式化脈衝。系統亦將識別何時驗證完除 了 P個記憶體單元之外(其中p等於〇或更大)之戶斤有記憶體 單元。可基於ECC及/或裝置特徵來選擇N值與？值。藉由 瞭解以上論述之兩個脈衝，可估計記憶體單元之正常^臨 限電麼分佈。例如’若N等於2’ p等於8，且步長為4:: 則=常態臨限電壓分佈為（8·2) χ .4=24伏。此資訊可用來 確定在每-程式脈衝之後所需的驗證作#數目。例如，儘 管有16個資料狀態，但驗證作f之數目可減少至每一程式 脈衝(2.4+0.3)/0.3 5=8個驗證。前幾個及後幾個 至可具有少於8次之驗證作業。在以上等式中，叫= 式雜訊邊限且0 · 3 5表示一個實例性實施案之狀態到狀態臨 限電壓分離係數。 在步驟906中，將兩個經識別的程式脈衝儲存於非揮發 性儲存器中(例如，暫存器、快閃記憶體單元等）。在步驟 9〇6中，系統基於如以上論述之兩個經識別脈衝來計算臨 限電壓分佈之-近似值。在步驟91〇中，系統將基於以上 所論述的臨限電壓分佈之近似值及步長來計算並儲存所需 的驗證脈衝之最大數目。在步驟912中，接收一程式化資 料之請求。在步驟910與步驟912之間的虛線指示一不可預 測之時間量且可在步驟91〇與912之間實施中間作業。在步 驟914中，使用一遍單獨程式化過程將資料程式化於記憶 體單凡中。在另一實施例中，步驟914可包含實施多遍程 式化過程。在步驟91 6中，自記憶體單元中讀取資料並向 使用者或主機報告。 128993.doc -39· 200849247 可使用圖15之過程來執行步驟914 ;然而，當實施一遍 早獨程式化過程時，每一遍的步長不改變。更確切地說， 其保持為一基於裝置特徵所確定的恆定值（例如，〇.1_〇4 • 伏）。在一實施例中，圖Η之過程亦可包含如以上所論述 基於軟程式化來設定初始程式脈衝之量值。在一實施例 ， 巾’按照自最靠近源極線之字線開始並向位元線觸點工作 之次序來程式化字線；例如，自WL〇處開始且在處 (' 結束。因此，在一遍單獨程式化過程中將實施64次圖15: 過程，每個字線一次。 圖18為當使用圖15之過程來執行圖17之步驟914時，執 行圖15之步驟842的過程的一實施例。圖18之過程執行以 下概念··僅使用一有限脈衝集合進行驗證，其中該有限集 合（可能）小於總集合。對於如以上針對圖17所述之實例， 在程式脈衝之間僅使用不超過8個驗證脈衝而不是所有b 個驗證脈衝。然而，所施加之8個驗證脈衝之集合基於記 . 憶、體單元之正常態臨限電壓分佈與程式化過程之當^狀態 而隨時間變化。-旦系統瞭解記憶體單元之正常態臨限; 壓刀佈寬度，系統就會估計該正常態臨限電壓沿圖6坐標 ‘ 圖之分佈。 v 圖17之步驟910計算驗證脈衝之最大數目。此確定驗證 脈衝集合之最大寬度。例如，若驗證脈衝之最大數目為 8，則二18中所預期之驗證脈衝集合包含多達_驗證脈 衝。隨著程式化過程的繼續（經過圖15之各種叠代），該驗 證脈衝集合將移動以使不同的驗證脈衝成為該集合之一部 128993.doc -40- 200849247 分。例如，該集合可以冑包含一資料狀態〇之驗證脈衝開 始。最後，使该集合增大以使其包含資料狀態0至資料狀 態7之驗證脈衝，隨後使該集合移動以使其包含資料狀能1 至8之驗證脈衝，然後是資料狀態2至9等等。 在圖18的步驟928中，基於驗證脈衝之最大數目且基於 在當前程式化過程中任一記憶體單元能達到之最高資:狀 態來識別驗證集合。在圖18中，任—記龍單元所達到之 最咼貧料狀態稱為狀態X。該驗證脈衝集合將包含所需用 來驗證-高於所達到之最高資料狀態之狀態之驗證脈^及 用於低於該狀態之狀態之驗證脈衝，但不大於已確定之驗 證脈衝之最大數目。在圖18中，—高於所達成之最高資料 狀態之狀態稱為狀態X+1。例如，若程式化過程剛剛開 X所達成之最高資料狀態可為狀態E，故該驗證脈衝集 合會僅包含一狀態〇之驗證脈衝。若記憶體單元僅達到狀 且已確定之驗證脈衝之最大數目為8，則該驗證脈衝集 口會包含狀態0-6之驗證脈衝。若程式化過程進行了大部 記憶體單元已經達到狀態7，且已確定之驗證脈衝之 最大數目為8，則該驗證脈衝集合會包含狀態8]之驗證脈 ，。若記憶體單元已經達到狀㈣且已確定之驗證脈衝之 取大數目為8 ’則該驗證脈衝集合會包含狀態4] i之驗證 脈衝。若記憶體單元已達㈣態13且已確定之驗證脈衝之 最大數目為8 ’則該驗證脈衝集合將包含狀態7_14之驗證 脈衝。 在步驟930中，將在步驟928中所識別的該驗證脈衝集合 128993.doc -41 - 200849247 之最低驗證脈衝施加至所選字線。將該一個脈衝之量值設 定為相應資料狀態之驗證位準。在一些實施例中，一資料 狀態之驗證位準等於該資料狀態之最低臨限電壓（見例 如，圖6中狀態1之Vvl)。在步驟932中，感測程式脈衝結 果。亦即，確定所關注記憶體單元（或多個記憶體單元）是 否已導通或未導通。在步驟934中，將感測結果與每一記 憶體單兀之資料相比較。若欲將記憶體單元程式化為剛剛 驗證之目標位準且其已達到該位準，則在步驟93 6中，藉 由提升該記憶體單元之位元線電壓來封鎖該記憶體單元。 在步驟938中，確定該驗證脈衝集合内是否仍有還未施加 之驗證脈衝。若沒有，則在步驟942中，確定是否該等記 憶體單元之任-者已達到狀態χ+1。若有，則更新最高狀 態（狀態X)之指示且圖18之過程完成（亦完成圖15中的步驟 842)。若該驗證脈衝集合中仍有較多還未施加之驗證脈衝 (步驟938) ’則在步驟940中施加下一個最高驗證脈衝，且 該過程循環回至步驟932。例如，當在步驟中所識別之 该驗證脈衝集合包含狀態2_1〇之驗證脈衝時，將實施8次 圖18之循環（步驟932-938)。 在程式化資料之德，由於I认μ + ^ 於基於儲存在毗鄰浮動間極 電荷的電㈣合，料在浮動閘極上之視在電荷發 移。此浮動閑極到浮動閉極之搞合現象閣述於美國專利 :鄭9中，此專利之全文以引用方式併入本文中： 到一目標浮動閉極之浮動閉極可包含位於同—位元線上； 相鄰浮動閘極、位於同一孛綠…+ &線上的 门子線上的相鄰浮動閘極、或與目 128993.doc -42- 200849247 標浮動閘極成對角之浮動閘極（此乃因該等閘極既在-相 鄰位元線上又在一相鄰字線上）。 此浮動閘極到浮自閘極之麵纟j見象最明顯地發生於在不 同時候被程式化的毗鄰記憶體單元集合之間。例如，以一 纟第-記憶體單元浮動閘極上對應於一資料集合之電荷準 、：立來程，化該記憶體單元。隨後，以-在一個或多個毗鄰 • 1己憶體單元之浮動閘極上對應第二資料集合之電荷位準來 r 冑式化該-個或多個毗鄰記憶體單元。在程式化一個或多 卜 ㈣鄰記憶體單^之後，自第—記憶體單元讀取的電荷位 準似乎不同於所程式化的電荷位準，此乃因贼鄰記憶體單 元上之電荷效應耦合至該第一記憶體單元。與毗鄰記憶體 單元之耦合可使所讀取視在電荷位準偏移一足夠量從而導 致對所儲存資料之錯誤讀取。 一種解決浮動閘極耦合問題之嘗試可發現於由犯咖Stylized pulses of the memory unit. The system will also identify when the user has verified that the memory cells have been removed (where p is equal to 〇 or greater). Can I choose N values based on ECC and/or device characteristics? value. By understanding the two pulses discussed above, it is possible to estimate the normal distribution of the memory cells. For example, 'If N is equal to 2' p is equal to 8, and the step size is 4:: then = normal threshold voltage distribution is (8·2) χ .4 = 24 volts. This information can be used to determine the number of verifications required after each program pulse. For example, although there are 16 data states, the number of verifications f can be reduced to each program pulse (2.4 + 0.3) / 0.3 5 = 8 verifications. The first few and the last few can have less than 8 verification jobs. In the above equation, the = noise margin is called and 0 · 3 5 represents the state of the example embodiment to the state threshold voltage separation factor. In step 906, the two identified program pulses are stored in a non-volatile memory (e.g., a scratchpad, flash memory unit, etc.). In step 9.6, the system calculates an approximation of the threshold voltage distribution based on the two identified pulses as discussed above. In step 91, the system will calculate and store the maximum number of required verify pulses based on the approximate values and step sizes of the threshold voltage distribution discussed above. In step 912, a request for a stylized message is received. The dashed line between step 910 and step 912 indicates an unpredictable amount of time and an intermediate operation can be performed between steps 91 and 912. In step 914, the data is stylized into a memory unit using a separate stylization process. In another embodiment, step 914 can include implementing a multi-pass procedure. In step 91 6 the data is read from the memory unit and reported to the user or host. 128993.doc -39· 200849247 Step 914 can be performed using the process of Figure 15; however, when implementing an early unique stylization process, the step size of each pass does not change. Rather, it remains at a constant value determined based on device characteristics (eg, 〇.1_〇4 • volts). In one embodiment, the process of the figure may also include setting the magnitude of the initial program pulse based on the soft programming as discussed above. In one embodiment, the towel 'syllabicizes the word line in the order from the word line closest to the source line and to the bit line contact; for example, starting at WL〇 and at the end ('end. Therefore, Figure 15: Process, each word line will be implemented 64 times in a single stylization process. Figure 18 is a diagram of the process of performing step 842 of Figure 15 when the process of Figure 15 is used to perform step 914 of Figure 17. The process of Figure 18 performs the following concepts: • Validation using only a finite set of pulses, where the finite set is (possibly) smaller than the total set. For the example as described above for Figure 17, only use between program pulses No more than 8 verification pulses instead of all b verification pulses. However, the set of 8 verification pulses applied is based on the normal state threshold voltage distribution of the memory and the body unit and the state of the stylization process over time. Change. - The system knows the normal state of the memory cell; the width of the knife cloth, the system will estimate the distribution of the normal threshold voltage along the coordinate of Figure 6. Figure 910 of Figure 17 calculates the maximum of the verification pulse This determines the maximum width of the set of verification pulses. For example, if the maximum number of verification pulses is 8, then the set of verification pulses expected in the second 18 contains up to _ verification pulses. As the stylization process continues (via Figure 15) The various iterations, the set of verification pulses will move so that the different verification pulses become part of the set 128993.doc -40 - 200849247. For example, the set can start with a verification pulse containing a data state. The set is incremented to include a verify pulse of data state 0 to data state 7, and then the set is moved to include a verify pulse of data states 1 through 8, followed by data states 2 through 9, and so on. In step 928 of Figure 18, the verification set is identified based on the maximum number of verification pulses and based on the highest level of state that any memory unit can achieve during the current stylization process. In Figure 18, the Ren-Kun Long unit The state of the most poor material that is reached is referred to as state X. The set of verification pulses will contain the verification pulse required to verify - the state above the highest data state reached and below The verify pulse of the state of the state, but not greater than the maximum number of validated verify pulses. In Figure 18, the state above the highest data state achieved is called state X+1. For example, if the stylization process is just The highest data state achieved by opening X can be state E, so the verification pulse set will only contain a verification pulse of one state. If the memory cell only reaches the shape and the maximum number of verification pulses determined is 8, the verification The pulse set will contain a verify pulse of state 0-6. If the stylization process has performed that most of the memory cells have reached state 7, and the maximum number of validated verify pulses is 8, then the set of verify pulses will contain state 8. The verification pulse, if the memory unit has reached the state (4) and the determined number of verification pulses is 8 ', the verification pulse set will contain the verification pulse of state 4] i. If the memory cell has reached the (four) state 13 and the determined maximum number of verify pulses is 8 ' then the set of verify pulses will contain the verify pulse of state 7_14. In step 930, the lowest verify pulse of the set of verify pulses 128993.doc -41 - 200849247 identified in step 928 is applied to the selected word line. The magnitude of the one pulse is set to the verification level of the corresponding data state. In some embodiments, the verify level of a data state is equal to the lowest threshold voltage of the data state (see, for example, Vvl of state 1 in Figure 6). In step 932, the program pulse result is sensed. That is, it is determined whether the memory unit of interest (or a plurality of memory units) is turned on or not turned on. In step 934, the sensed results are compared to the data for each memory unit. If the memory unit is to be programmed to the target level just verified and it has reached the level, then in step 963, the memory unit is blocked by raising the bit line voltage of the memory unit. In step 938, it is determined if there are still valid verification pulses within the set of verification pulses. If not, then in step 942, it is determined if any of the memory cells have reached state χ +1. If so, the indication of the highest state (state X) is updated and the process of Figure 18 is completed (step 842 of Figure 15 is also completed). If there are still more verify pulses that are not yet applied in the set of verify pulses (step 938)' then the next highest verify pulse is applied in step 940 and the process loops back to step 932. For example, when the set of verification pulses identified in the step contains a verify pulse of state 2_1, the loop of Figure 18 will be performed 8 times (steps 932-938). In the virtue of stylized data, the apparent charge transfer on the floating gate is due to the fact that I recognizes μ + ^ based on the electrical (four) junction stored in the adjacent floating pole. The phenomenon of this floating idle pole to the floating closed pole is described in the U.S. Patent: Zheng 9, the entire disclosure of which is incorporated herein by reference: the floating closed pole to a target floating closed pole can be included in the same position On the meta-line; adjacent floating gates, adjacent floating gates on the gate lines on the same green...+ & line, or floating gates diagonal to the floating gates of the 128993.doc -42-200849247 standard ( This is because the gates are on both adjacent bit lines and on an adjacent word line. The floating gate to floating surface of the gate 见 j appears most obviously between adjacent sets of memory cells that are stylized at different times. For example, the memory cell is formed by a charge on the floating gate of the first memory cell corresponding to a data set. The one or more adjacent memory cells are then r-supplied with the charge level of the second data set on the floating gate of one or more adjacent ones of the memory cells. After stylizing one or more (four) neighboring memory cells, the level of charge read from the first memory cell appears to be different from the programmed charge level, which is due to the charge effect on the thief's adjacent memory cell. Coupled to the first memory unit. Coupling with adjacent memory cells can shift the read apparent charge level by a sufficient amount to cause erroneous reading of the stored data. An attempt to solve the floating gate coupling problem can be found in the guilty

Mokhlesi在2006年3月17曰申請的美國專利申請案 j 1 1/377^972 "System For Performing Read Operation 〇nUS Patent Application for Mokhlesi, filed March 17, 2006 j 1 1/377^972 "System For Performing Read Operation 〇n

Non-Volatile Storage With Compensation For Coupling'1, 此案之全文以引用方式併入本文中。在該申請案中所描述 -之系統包含在讀取一目標記憶體單元時對相鄰記憶體單元 •施加補償電壓。 圖19描繪當使用本文所述之四遍程式化技術來程式化記 憶體單元時限制浮動閘極搞合效應之方法。在一通常讀取 過程中，經選擇欲讀取之一 NAND串記憶體單元在其控制 閘極處接收一等於（或近似等於）在兩個相鄰資料狀態之間 128993.doc -43- 200849247Non-Volatile Storage With Compensation For Coupling '1, the entire contents of which is hereby incorporated by reference. The system described in this application includes applying a compensation voltage to an adjacent memory cell when reading a target memory cell. Figure 19 depicts a method of limiting the floating gate engagement effect when using the four pass programming techniques described herein to program a memory cell. During a normal read, one of the NAND string memory cells selected to be read receives at its control gate an equal (or approximately equal) between two adjacent data states. 128993.doc -43 - 200849247

之一臨限電壓。例如，鸟了放〜 ^ L 马了確疋一記憶體單元是否處於資 料狀悲0 4忑隐體單元之控制閘極會接收W (見圖6)。 為了確定-記憶體單元是否處於狀態】，將實施兩次讀取 作業：第-次讀取作業將對該記憶體單元施加vri且第二 讀取作業將對該記憶體單亓竑士 v 1 / a门 丨〜蒞早兀靶加Vr2(見圖6)。端視該記憶 體單元是否回應於控制闡搞齋网二憎、=上 紅市』閘極電壓而導通或關閉，使用邏輯 來確定該記憶體單元處於何種狀態。One threshold voltage. For example, if the bird has placed ~ ^ L, it is true whether a memory unit is in a data-like manner. 4 The control gate of the hidden unit will receive W (see Figure 6). In order to determine whether the memory cell is in the state, two read jobs will be performed: the first read job will apply vri to the memory cell and the second read job will be a single gentleman v 1 / a for the memory Threshold ~ the early target and Vr2 (see Figure 6). Depending on whether the memory unit is turned on or off in response to the control, the logic is used to determine the state of the memory cell.

類似地纟驗也過程中’將一驗證比較電壓施加至欲 驗證記憶體單元之控制閘極上。通常情況係該驗證比較電 壓與資料狀態之最低臨限電壓類似。例如，資料狀態κ 驗證電壓為Vvl。資料狀態2之驗證電壓為vv2。當實施一 讀取或驗證過程時，_NAND串上之未選擇記憶體軍元將 接收-稱作vread之控制閘極電壓，丨比資料狀態15之臨 限电壓间侍多。此電壓Vread(超驅動電壓）將確保所有未選 擇記憶體單元將導通並允許電流在該NAND$中流動以便 该NAND串之電流流動僅由目標記憶體單元確定。 圖19之過程提供—種讀取已使用以上所述四遍程式化過 程程式化之記憶體單元之方式以限制來自相鄰浮動間極之 耦合。在圖18之過程中所應用之理論為：在—讀取過程 十’在相同NAND串上，目標記憶體單元之沒極側的下一 個記憶體單元有時會基於其資料接收不同的電心補償浮 動閘極耦合。例如，當讀取一連接至WL12之記憶體單元 k ’連接至WL13之記憶體單元會接收不同電。在驗證 過程中’⑨了源極側相鄰記憶體單元之外的所有記憶體單 128993.doc -44- 200849247 元皆會接收Vread， 於Vread·和△(例如 而该源極側相鄰記憶體單元會接收小 其中△可端視裝置特徵為1伏或其他 值）。將此其他值表示為Vreadx 其中 VreadX=Vread-A。 在驗證期間’除了相鄰記憶體單元將接收νΓ_χ之外，所 有未選擇記憶體單元將接收Vread。在一隨後讀取過程 中，若源極側相鄰記憶體單元為_偶數狀態（狀態〇、2、 6 8 10 12、丨4)，則源極側相鄰記憶體單元將接收Similarly, during the test, a verification comparison voltage is applied to the control gate of the memory cell to be verified. Normally, this verification compares the voltage to the lowest threshold voltage of the data state. For example, the data state κ verification voltage is Vvl. The verification voltage of data state 2 is vv2. When a read or verify process is implemented, the unselected memory cells on the _NAND string will receive a control gate voltage called vread, which is more than the threshold voltage of the data state 15. This voltage Vread (overdrive voltage) will ensure that all unselected memory cells will turn on and allow current to flow in the NAND$ so that the current flow of the NAND string is only determined by the target memory cell. The process of Figure 19 provides a way to read the memory cells that have been programmed using the four-pass stylization process described above to limit coupling from adjacent floating electrodes. The theory applied in the process of FIG. 18 is that in the -read process ten' on the same NAND string, the next memory cell on the non-polar side of the target memory cell sometimes receives different cores based on its data. Compensate for floating gate coupling. For example, when a memory cell connected to WL13 is connected to a memory cell k' connected to WL12, it receives different power. During the verification process, all memory banks except the source side adjacent memory unit 128993.doc -44- 200849247 will receive Vread, Vread· and △ (for example, the source side adjacent memory The body unit will receive a small one where the Δ can be viewed as a 1 volt or other value. This other value is represented as Vreadx where VreadX=Vread-A. During the verification period, all unselected memory cells will receive Vread except that adjacent memory cells will receive νΓ_χ. In a subsequent read process, if the source side adjacent memory cells are in the _ even state (state 〇, 2, 6 8 10 12, 丨 4), the source side adjacent memory cells will receive

CC

VreadX而所有其他未選擇記憶體單元將接收一然 而，若源極側相己憶體單元為一奇數狀態（狀態卜3、 9 11 13、15)，則在讀取過程中，相鄰記憶體單 元將接收Vread。此導轻相柳4卜立μ 口口 ¥致相W ζ憶體单元為奇數狀態時將 會接收補償。 再返回觀察圖11Ε，處於奇數狀態之記憶體單元比偶數 狀態之記憶體單元自相應中間狀態受到較強程式化。因 此，處於奇數狀態之相鄰記憶體單元會具有較大麵合效 應。若使用圖13之序列來實施四遍程式化過程，則在一目 標記憶體單元之相鄰者的前三遍程式化之後但第四遍程式 化之前針對該目標記憶體單元實施第四遍程式化。因此， 僅相鄰者之第四遍程式化會導致目標記憶體單元上浮動間 極到汙動閘極之耦纟且端視相鄰記憶體單元之第四遍程式 化是將該記憶體單元置於奇數還是偶數狀態來使用二元 (開/關或低/高）補償。 圖19之步驟980包含接收—讀取一特定字線wLn上之資 料之請求。因此心為選擇字線。在步驟982中，針對相 128993.doc -45- 200849247 鄰字線WLn+l上之所有記憶體單元實施一讀取過程。步驟 982包含確定所有連接至WLn+1之記憶體單元處在何種資 料狀態。在步驟984中，針對每一位元線，儲存在…。^ 上之相鄰記憶體單元處於一偶數狀態或一奇數狀態之指 示。此僅需要每一位元線儲存一位元（奇數/偶數）。例如， 可使用一個位元鎖存器。在步驟986中，針對字線實 施一讀取過程。在步驟986之過程中，對WLn+1施加 ( Vread。步驟986包含實施以上所論述之補償。在步驟988 中，對於與處於奇數狀態之相鄰記憶體單元相關聯之彼等 位凡線，儲存來自步驟986之讀取過程之資料。例如，系 統可校驗該一個位元鎖存器來判斷其是否指示一處於奇數 狀態之相鄰者且，若如此，則儲存步驟986之結果。彼等 具有一處於偶數狀態之相鄰記憶體單元的位元線不儲存來 自步驟986之讀取過程之資料。在步驟99〇中，針對字線 WLn實施讀取過程，其中相鄰字線買“+丨接收VRadx。在 ί;: 纟驟992中’彼等具有—處於偶數狀態之相鄰記憶體單元 之位το線之資料將儲存來自步驟99〇之讀取過程之資料。 在步驟994中，將報告所儲存之資料（步驟992或步驟988)。 ’ 出於例證及說明之目的，上文已對本發明進行了詳細說 ， 日月。本文不意欲作為包羅無遺的闡述或將本發明限制於所 揭示之精確形式。根據上文之教示亦可作出許多種修改及 改變。所述實施例之選擇旨在最佳地解釋本發明之原理及 其實際應用，藉以使其他熟習此項技術者能夠以適合於所 構想具體應用之各種實施例形式及使用各種修改來最佳地 128993.doc -46 - 200849247 制本發明。本發明的料擬由隨㈣請專㈣ 定。 巧丨 【圖式簡單說明】 圖1係一 NAND串之俯視圖。 圖2係該NAND串之等效電路圖。 圖3係一非揮發性記憶體系統之方塊圖。 圖4係一繪示記憶陣列之一實施例之方塊圖。 圖5係一繪示感測塊之一實施例之方塊圖。 圖6繪示一實例性臨限電壓分佈集合。 圖7繪示一實例性臨限電壓分佈集合。 圖8繪示將資料編碼成一與臨限電壓分佈相關聯之資料 狀態集合之一實例。 、” 圖9繪示將資料編碼成一與臨限電壓分佈相關聯之資料 狀態集合之一實例。 、 圖10係一流程圖，其闡述一種用於操作非揮發性儲存器 之方法之一實施例。 °° 圖11A-11E繪示一種多遍程式化過程。 圖12係-流程圖，其闡述-種程式化非揮發性儲存器之 方法之一實施例。 圖12A繪示施加至所選圯憶體單元之控制閘極之程式化 脈衝及驗證脈衝。 圖13係一圖表，其闡述對多個字線實施四遍程式化過程 之序列之一實施例。 圖14係一流程圖，其闡述一種操作非揮發性儲存器之方 128993.doc -47- 200849247 法之一實施例。 圖1 5係一流程圖，其闡述一種程式化非揮發性儲存器之 方法之一實施例。 圖1 6係一流程圖，其闡述一種操作非揮發性儲存器之方 法之一實施例。 圖1 7係一流程圖，其闡述一種操作非揮發性儲存器之方 法之一實施例。 圖1 8係一流程圖，其闡述一種驗證方法之一實施例。 圖1 9係一流程圖，其闡述一種讀取資料之方法之一實施 例。 【主要元件符號說明】 100 電晶體 102 電晶體 104 電晶體 106 電晶體 100FG 浮動閘極 100CG 控制閘極 102FG 浮動閘極 102CG 控制閘極 104FG 浮動閘極 104CG 控制閘極 106FG 浮動閘極 106CG 控制閘極 120 選擇閘極 128993.doc -48- 200849247 122 選擇閘極 126 位元線觸點 128 源極線 SGD 汲極側選擇線 SGS 源極側選擇線 WLO 字線0 WL1 字線1 WL2 字線2 WL3 字線3 210 非揮發性儲存裝置 212 記憶體晶粒或晶片 200 記憶陣列 220 控制電路 222 狀態機 224 晶片上位址解碼器 226 功率控制模組 232 線 244 控制器 234 線 230A 讀取/寫入電路 230B 讀取/寫入電路 240A 列解碼器 240B 列解碼器 242A 行解碼器 128993.doc -49- 200849247 242B 行解碼器 300 感測塊 BLO 位元線 BL1 位元線 BL2 位元線 BL3 位元線 BL4 位元線 BL5 位元線 BLx 位元線 WL_dl 虛擬字線 WL_dO 虛擬字線 WL0-WL63 資料字線 470 感測電路 472 匯流排 480 感測模組 482 位元線鎖存器 490 共同部分 492 處理器 493 輸入線 494 資料鎖存器 496 I/O介面 420 資料匯流排 128993.doc -50-VreadX and all other unselected memory cells will receive one. However, if the source side phase memory cell is in an odd state (states 3, 9 11 13, 15), adjacent memory during reading The unit will receive Vread. This guide light phase willow 4 Bu Li μ mouth ¥ 致 phase W ζ memory unit will receive compensation when it is in odd state. Returning to Fig. 11Ε, the memory cells in the odd state are more strongly programmed from the corresponding intermediate states than the memory cells in the even state. Therefore, adjacent memory cells in an odd state will have a large surface effect. If the sequence of FIG. 13 is used to implement the four-pass programming process, the fourth pass program is executed for the target memory unit after the first three passes of the neighbors of the target memory unit but before the fourth pass of the stylization. Chemical. Therefore, only the fourth pass of the neighbors will cause the floating-to-smooth gate coupling on the target memory cell and the fourth-pass stylization of the adjacent memory cell is the memory cell. Place in odd or even state to use binary (on/off or low/high) compensation. Step 980 of Figure 19 includes receiving a request to read the information on a particular word line wLn. So the heart is choosing the word line. In step 982, a read process is performed for all of the memory cells on phase 128993.doc -45 - 200849247 adjacent word line WLn+1. Step 982 includes determining what data state the memory cells connected to WLn+1 are in. In step 984, for each bit line, it is stored in... ^ The adjacent memory cell is in an even state or an odd state. This only requires one bit (odd/even) to be stored per bit line. For example, a bit latch can be used. In step 986, a read process is performed for the word line. During the process of step 986, WLn+1 is applied (Vread. Step 986 includes performing the compensation discussed above. In step 988, for the bit line associated with the adjacent memory cells in the odd state, The data from the read process of step 986 is stored. For example, the system can verify the one bit latch to determine if it indicates a neighbor in an odd state and, if so, store the result of step 986. The bit line having an adjacent memory cell in an even state does not store the data from the read process of step 986. In step 99, a read process is performed for the word line WLn, wherein the adjacent word line is bought. +丨 Receive VRadx. In ί;: 992, 'the data of the bits το of the adjacent memory cells in the even state will store the data from the reading process of step 99. In step 994 The stored information will be reported (step 992 or step 988). ' For purposes of illustration and description, the present invention has been described in detail above, the sun and the moon. This article is not intended to be an exhaustive explanation or The invention is limited to the precise forms disclosed, and many modifications and changes can be made in accordance with the teachings hereinabove. The selection of the embodiments is intended to best explain the principles of the invention and its practical application. The present invention is capable of making the invention optimally in the form of various embodiments suitable for the particular application contemplated and using various modifications. The invention is intended to be prepared by (4). BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a top view of a NAND string. Figure 2 is an equivalent circuit diagram of the NAND string. Figure 3 is a block diagram of a non-volatile memory system. Figure 4 is a block diagram of a memory array implementation Figure 5 is a block diagram showing one embodiment of a sensing block. Figure 6 illustrates an exemplary threshold voltage distribution set. Figure 7 illustrates an exemplary threshold voltage distribution set. An example of encoding a data into a set of data states associated with a threshold voltage distribution is shown. Figure 9 illustrates an example of encoding a data into a set of data states associated with a threshold voltage distribution. One Flowchart, which illustrates an embodiment of a method for operating a non-volatile reservoir. °° Figures 11A-11E illustrate a multi-pass stylization process. Figure 12 is a flow diagram illustrating a stylized non- One embodiment of a method of volatile storage. Figure 12A illustrates a programmed pulse and a verify pulse applied to a control gate of a selected memory unit. Figure 13 is a diagram illustrating four implementations of a plurality of word lines. One embodiment of a sequence of programming steps. Figure 14 is a flow chart illustrating one embodiment of a method for operating a non-volatile memory 128993.doc -47 - 200849247. Figure 15 is a flow chart, It illustrates one embodiment of a method of staging a non-volatile storage. Figure 16 is a flow diagram illustrating one embodiment of a method of operating a non-volatile reservoir. Figure 17 is a flow diagram illustrating one embodiment of a method of operating a non-volatile reservoir. Figure 18 is a flow chart illustrating one embodiment of a verification method. Figure 9 is a flow chart illustrating an embodiment of a method of reading data. [Main component symbol description] 100 transistor 102 transistor 104 transistor 106 transistor 100FG floating gate 100CG control gate 102FG floating gate 102CG control gate 104FG floating gate 104CG control gate 106FG floating gate 106CG control gate 120 Select Gate 128993.doc -48- 200849247 122 Select Gate 126 Bit Line Contact 128 Source Line SGD Side Select Line SGS Source Side Select Line WLO Word Line 0 WL1 Word Line 1 WL2 Word Line 2 WL3 Word line 3 210 Non-volatile storage device 212 Memory die or wafer 200 Memory array 220 Control circuit 222 State machine 224 On-chip address decoder 226 Power control module 232 Line 244 Controller 234 Line 230A Read/write circuit 230B Read/Write Circuit 240A Column Decoder 240B Column Decoder 242A Line Decoder 128993.doc -49- 200849247 242B Line Decoder 300 Sensing Block BLO Bit Line BL1 Bit Line BL2 Bit Line BL3 Bit Line BL4 bit line BL5 bit line BLx bit line WL_dl dummy word line WL_dO dummy word line WL0-WL63 data word line 470 sensing circuit 472 Bus 480 Sensing Module 482 Bit Line Latch 490 Common Section 492 Processor 493 Input Line 494 Data Latch 496 I/O Interface 420 Data Bus 128993.doc -50-

Claims (1)

200849247 十、申請專利範圍： 1 · 一種操作非揮發性儲存器之方法，其包括： 對複數個非揮發性儲存元件實施一第一程式化母 程；及 過 在該第一程式化過程後對該等非揮發性儲存元件實施 一第二程式化過程，該第二程式化過程包含至少部分地 基於該第一程式化過程之一組驗證作業。 2 ·如請求項1之方法，其中： 該第一程式化過程為一用於緊密一擦除臨限分佈之軟 程式化過程。 3·如請求項2之方法，其進一步包括： 基於該第一程式化過程磘定該等非揮發性儲存元件之 一臨限電壓分佈之一近似值，該等驗證作業至少部分地 基於該臨限電壓分佈之該近似值。 4·如請求項1之方法，其中： 該第一程式化過程對該等非揮發性儲存元件施加程式 化脈衝； 該方法進一步包括在該第一程式化過程期間識別一達 成一第一結果所需之第一程式脈衝及在該第一程式化過 程期間識別一達成一第二結果所需之第二程式脈衝；及 該第二程式化過程在程式脈衝之間使用驗證脈衝，基 於該第一程式脈衝及該第二程式脈衝來限制該等驗證脈 衝。 5 ·如請求項1之方法，其進一步包括： 128993.doc 200849247 擦除該等非揮發性儲存元件，該第〜 :該擦除聯合實施之軟程式化過程;為-含對該等非揮發性儲衫件施加脈衝； <化過程包 識別一與完成該軟程式化之一第一兔 非揮發性儲在 個或夕個該等 _ 儲存70件相關聯之第一程式脈衝；及 硪別一與完成該軟程式化之 η十夕月丨一咏 取後一組外之 $夕4等非揮發性儲存元件相 衝，兮笙-Y L W <乐一私式脈 =：程式化過程包含基於該第-程式脈衝及該第 耘式脈衝來實施驗證作業。 6.如請求項1之方法，其進一步包括： 二察：該等非揮發性儲存元件，該第—程式化過程為一 聯合實施之軟程式化過程，該軟程式化包含對 ^專非揮發性儲存元件施加脈衝； =別—與完成該軟程式化之―第—組―個或多個該等 非揮發性儲存元件相關聯之第—程式脈衝；及 Ο 識別-與完成該軟程式化之所有但除一最後一組外之 〇或多個該等非揮發性儲存元件相關聯之第二程式脈 衝；及 …基於該第—程式化脈衝及該第二程式化脈衝來識別一 範圍4第一权式化過程包含基於該範圍施加若干驗證 脈衝。 如請求項1之方法，其進一步包括： 擦除該等非揮發性儲存元件，該第一程式化過程為一 ”該ii·、除合實施之軟程式化過程，該軟程式化包含對 128993.doc 200849247 該等非揮發性儲存元件施加脈衝； 戠別” 70成，亥軟程式化之_第一組一個或多個該等 非揮發性儲存元件相關聯之第一程式脈衝；及 硪別與凡成該軟程式化之所有但除一最後一組外之 〇或多個該等非揮發性儲存元件相關聯之第二程式脈 衝；及 执基於該第—程式化脈衝及該第二程式化脈衝來識別驗 衝之數目，遺第二程式化過程包含在程式脈衝之 間=加多達該數目之脈衝用以驗證程式化。 符月长項7之方法’其中該在程式脈衝之間施加多達該 最大數目之驗證脈衝以驗證程式化包括： I ()、十對狀恶變化窗之一最低狀態，向該等非揮發性 健存元件之控制閘極施加一脈衝； (b)感測結果； )才鎖已達到其相應目標之非揮發性儲存元件；及 針對該窗中之其他狀態重複步驟（aHc)。 9·如請求項7之方法，其中·· 該第—組一個或多個該等非揮發性儲存元件精確地由 一個非揮發性儲存元件組成；及 該最後-組-個或多㈣等非揮發性儲存元件由〇個 非揮發性儲存元件組成。 1〇·如請求項！之方法，其進一步包括： ^除該等非揮發性儲存元件，㈣—程式化過程為與 …除聯合實施之軟程式化過程，該軟程式化包含對該 128993.doc 200849247 等非揮發性儲存元件施加脈衝； 識別-與完成該軟程式化之—第一組一個或多個該等 非揮發性儲存元件㈣聯之[程式脈衝；及 識別一與完成該軟程式化之所有但除一最後—組外之 〇或多個該等非捏發性健左^ ^ 予非俾I f生储存凡件相關聯之第二程式脈 衝；及 &於該第-程式脈衝及該第二程式脈衝計算該等非揮 r 發性儲存元件之一臨限分佈之一近似值；及 ' I於該臨限分佈之該近似值及該第二程式化過程之— 程式脈衝步長來計算驗證脈衝之—最大數目，該第二程 式化過程包含在程式脈衝之間施加多達該最大數目之驗 證脈衝用以驗證程式化。 11 · 一種非揮發性儲存系統，其包括： 複數個非揮發性儲存元件；及 -個或多個管理電路’其與該複數個非揮發性儲存元 L 件連通’該—個或多個管理電路對該等非揮發性儲存元 件實施一第一程式化過程且在該第一程式化過程後對該 等非揮發性儲存元件實施一第二程式化過程該第二2 .. 式化過程包含至少部分地基於該第一程式化過程之一： • 驗證作業。 ''' 12 ·如請求項11之非揮發性儲存系統，其中·· 該第一程式化過程為一用於緊密一擦除臨限分佈之 程式化過程。 13 ·如請求項12之非揮發性儲存系統，其中： 128993.doc 200849247 該一個或多個管理電路基於該第一程式化過程確定該 等非揮發性儲存元件之—臨限電壓分佈之—近似值，該 等驗迅作業至少部分地基於該臨限電壓分佈之該近似 值0 14·如請求項11之非揮發性儲存系統，其_ : 人务程式化過程包含該一個或多個管理電路對該等 非揮發性儲存元件施加程式化脈衝； ^個或夕個I理電路在該第一程式化過程期間確定 獲得帛、、、σ果所需之第—程式脈衝且在該程式化過 程期間確定-獲得-第二結果所需之第二程式脈衝；及 在該第二程式化過程期間，該一個或多個管理電路在 程式脈衝之間使用該等驗證脈衝，該等驗證脈衝受該第 一程式脈衝及該第二程式脈衝限制。 15·如請求項11之非揮發性儲存系統，其中： 個或多個管理電路擦除該等非揮發性儲存元件，200849247 X. Patent Application Range: 1 . A method of operating a non-volatile memory, comprising: implementing a first stylized master for a plurality of non-volatile storage elements; and after the first stylization process The non-volatile storage elements implement a second stylization process that includes verifying the job based at least in part on the first stylized process. 2. The method of claim 1, wherein: the first stylization process is a soft stylization process for tightly erasing the threshold distribution. 3. The method of claim 2, further comprising: determining an approximation of one of the threshold voltage distributions of the non-volatile storage elements based on the first stylization process, the verifying operations being based at least in part on the threshold This approximation of the voltage distribution. 4. The method of claim 1, wherein: the first stylization process applies a stylized pulse to the non-volatile storage elements; the method further comprising identifying a first result during the first stylization process Requiring a first program pulse and identifying a second program pulse required to achieve a second result during the first stylization process; and the second stylization process uses a verify pulse between the program pulses, based on the first The program pulse and the second program pulse limit the verify pulses. 5. The method of claim 1, further comprising: 128993.doc 200849247 erasing the non-volatile storage elements, the first: the erasing joint implementation of the soft stylization process; Applying a pulse to the storage device; <the process packet identifies a first program pulse associated with completing one of the first stylized non-volatile storage of one or the other of the 70 pieces; Others are incompatible with the non-volatile storage elements such as $4, which are completed after the completion of the soft stylization, 兮笙-YLW <Leyi private vein =: stylization process The verification operation is performed based on the first program pulse and the third pulse. 6. The method of claim 1, further comprising: a second non-volatile storage element, the first stylization process being a joint implementation of a soft stylization process, the soft stylization comprising a non-volatile non-volatile The storage element applies a pulse; = not - the first program pulse associated with the "group" - one or more of the non-volatile storage elements that complete the soft programming; and Ο the identification - and completion of the soft programming a second program pulse associated with all but one or a plurality of the non-volatile storage elements; and... identifying a range 4 based on the first stylized pulse and the second stylized pulse The first weighting process includes applying a number of verification pulses based on the range. The method of claim 1, further comprising: erasing the non-volatile storage elements, the first stylization process being a "software" process of the ii. .doc 200849247 The non-volatile storage elements are pulsed; the screening is 70%, the first program pulse associated with the first group of one or more of the non-volatile storage elements; a second program pulse associated with all or a plurality of such non-volatile storage elements of the soft-programmed but one of the last set; and performing the first stylized pulse and the second program The pulse is used to identify the number of inspections, and the second stylization process is included between the program pulses = up to the number of pulses to verify the stylization. The method of the term 7 of the month of the month, wherein the application of up to the maximum number of verification pulses between the program pulses to verify the stylization includes: I (), the lowest state of one of the ten pairs of change windows, to the non-volatile The control gate of the sexual storage component applies a pulse; (b) the sensing result; ) the non-volatile storage element that has reached its corresponding target; and repeats the step (aHc) for the other states in the window. 9. The method of claim 7, wherein: the first group of one or more of the non-volatile storage elements consists precisely of a non-volatile storage element; and the last-group-one or more (four) The volatile storage element consists of one non-volatile storage element. 1〇·If requested! The method further includes: ^ in addition to the non-volatile storage elements, (4) - the stylization process is a soft stylization process performed in conjunction with ..., the soft programming includes non-volatile storage of the 128993.doc 200849247 Applying a pulse to the component; identifying - and completing the soft programming - the first set of one or more of the non-volatile storage components (four) associated with the [program pulse; and identifying one and completing the soft stylization but all but one last - a second program pulse associated with the component or a plurality of such non-pinch-forward devices; and & the 'the first program pulse and the second program pulse Calculating an approximation of one of the threshold distributions of the non-volatile storage elements; and 'I approximating the threshold distribution and the second stylization process—the program pulse step length to calculate the verification pulse—maximum The second stylization process includes applying up to the maximum number of verify pulses between program pulses to verify stylization. 11 - A non-volatile storage system comprising: a plurality of non-volatile storage elements; and - one or more management circuits 'connecting to the plurality of non-volatile storage elements L" - one or more management The circuit performs a first stylization process on the non-volatile storage elements and performs a second stylization process on the non-volatile storage elements after the first stylization process. The second 2: Based at least in part on one of the first stylization processes: • Verifying the job. ''' 12] The non-volatile storage system of claim 11, wherein the first stylization process is a stylization process for tightly erasing the threshold distribution. 13. The non-volatile storage system of claim 12, wherein: 128993.doc 200849247 the one or more management circuits determine an approximation of a threshold voltage distribution of the non-volatile storage elements based on the first stylization process The expedited operation is based, at least in part, on the approximation of the threshold voltage distribution. The non-volatile storage system of claim 11, wherein the personal stylization process includes the one or more management circuits And the non-volatile storage element applies a stylized pulse; the first or the first circuit determines the first program pulse required to obtain the 帛, , σ fruit during the first stylization process and is determined during the stylization process - obtaining a second program pulse required for the second result; and during the second stylization process, the one or more management circuits use the verify pulses between the program pulses, the verify pulses being subjected to the first Program pulse and the second program pulse limit. 15. The non-volatile storage system of claim 11, wherein: one or more management circuits erase the non-volatile storage elements, 該第一程式化過程為一與該擦除聯纟實施之軟程式化過 程，該軟程式化包含一個或多個管理電路對該等非揮發 性儲存元件施加脈衝； X ’ I m，Umm _ 個或多個該等非揮發性儲存元件 衝； 干之一弟一程式脈 該一個或多個管理電路識別完成該軟程式化之所有但 除一最後一組外之0或多個該等非揮 一 一 r生健存7L件之一 弟一程式脈衝；且 128993.doc 200849247 該-個或多個管理電路基於該第一程式脈衝及該第二 程式脈衝來識別驗證脈衝之一數目，該第二程式化過程 包含該一個或多個營王甲φ^ & 人&理私路在程式脈衝之間施加多達該 數目之驗證脈衝用以驗證程式化。 16·如請求項15之非揮發性儲存系統，其中： 該第-組一個或多個該等非揮發性儲存元件精確地由 一個非揮發性儲存元件組成；及The first stylization process is a soft stylization process implemented with the eraser, the soft programming comprising one or more management circuits applying pulses to the non-volatile storage elements; X ' I m, Umm _ One or more of the non-volatile storage elements; the one or more management circuits identify all but one or more of the last set One or more management circuits recognize the number of one of the verification pulses based on the first program pulse and the second program pulse, the 128993.doc 200849247 The second stylization process includes the one or more battalion φ^ & human & 私私路 applies up to the number of verification pulses between the program pulses to verify the stylization. 16. The non-volatile storage system of claim 15, wherein: the first set of one or more of the non-volatile storage elements consists precisely of a non-volatile storage element; 該最後-組-個或多個該等非揮發性儲存元件由〇個 非揮發性儲存元件組成。 17.如請求項11之非揮發性儲存系統，其中： 該-個或多個管理電路擦除該等非揮發性儲存元件， 該第-程式化過程為—與該擦除聯合實施之軟程式化過 程，該軟程式化過程包含該—個或多 非揮發性儲存元件施加脈衝； ^ 該一個或多個管理電路識別冑成該軟程式化之一第一 組-個或多個該等非揮發性儲存元件之第—程式脈衝； 該：個或多個管理電路識別完成該軟程式化之所有但 除最後組外之〇或多個該等非揮發性儲存元件之第 一程式脈衝；且 該-個或多個管理電路基於該等第一程式脈衝及該第 二程式脈衝來計算該#非揮發性儲存元件之—臨限分佈 之一近似值；及 該-個或多個管理電路基於該臨限分佈之該近似值》 該第二程式化過程之—程式脈衝步長來計算驗證脈衝戈 128993.doc 200849247 一最大數目，該第二程式化禍和a A ^ ^ 八過秩包含該一個或多個管理 電路在程式脈衝之間施加多迳兮曰 Λ , ^ ^ ^ ’運4取大數目之驗證脈衝用 以驗證程式化。 18·如請求項17之非揮發性儲存系統，其中： 該一個或多個管理電路接盼 ^ 电降按收一程式化資料之請求，該 請求在確定程式化脈衝之該篦- J <成弟一數目之後予以接收，該 第二程式化過程由該一個或容細μ 丨u Α夕個官理電路回應於該請求 而實施。 19·如請求項11之非揮發性儲存系統，其中·· λ第私式化過m玄等非揮發性儲存元件處於一與 被擦除相關聯之狀態；且 η .亥第一矛王式化過程將使用者資料程式化於該等非揮發 性儲存元件中。 20. 如請求項11之非揮發性儲存系統，其中： ”亥複數個非揮發性儲存元件係多狀態nand快閃記情 體裝置。 °心 21. 如請求項丨丨之非揮發性儲存系統，其中： 該複數個非揮發性儲存元件❹狀態快閃記憶體裝 置。 又 22. 如請求训之非揮發性儲存系統，其中： 邊複數個非揮發性儲存元件係nand快閃記憶體裝 128993.docThe last-group-one or more of the non-volatile storage elements consist of a plurality of non-volatile storage elements. 17. The non-volatile storage system of claim 11, wherein: the one or more management circuits erase the non-volatile storage elements, the first stylization process being - a software program implemented in conjunction with the erasing a process of applying the pulse to the one or more non-volatile storage elements; ^ the one or more management circuits identifying the first group of the one of the soft stylizations - one or more of the non- a first program pulse of the volatile storage element; the one or more management circuits identify a first program pulse that completes all but the last group of the non-volatile storage elements; The one or more management circuits calculate an approximation of the threshold distribution of the #non-volatile storage element based on the first program pulse and the second program pulse; and the one or more management circuits are based on the The approximation of the threshold distribution" The second stylization process - the program pulse step size to calculate the verification pulse Ge 128993.doc 200849247 a maximum number, the second stylization disaster and a A ^ ^ eight over rank containing the one or Multiple management circuits impose multiple Λ 程式 between the program pulses, and ^^^'s take a large number of verify pulses to verify the stylization. 18. The non-volatile storage system of claim 17, wherein: the one or more management circuits are responsive to a request to receive a stylized data, the request determining the stylized pulse - J < After the number of brothers is received, the second stylization process is carried out by the one or the squad, which is responsive to the request. 19. The non-volatile storage system of claim 11, wherein the non-volatile storage element, such as λ, is in a state associated with being erased; and the first spearing process The user profile is programmed into the non-volatile storage elements. 20. The non-volatile storage system of claim 11, wherein: the plurality of non-volatile storage elements are multi-state nand flash memory devices. ° heart 21. If the non-volatile storage system of the request item is Wherein: the plurality of non-volatile storage components, the state flash memory device. 22. The non-volatile storage system, wherein: the plurality of non-volatile storage components are nand flash memory devices 128993. Doc
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