TW200847241A - Fabrication process for nanotube-CMOS integration - Google Patents

Fabrication process for nanotube-CMOS integration Download PDF

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Publication number
TW200847241A
TW200847241A TW97103384A TW97103384A TW200847241A TW 200847241 A TW200847241 A TW 200847241A TW 97103384 A TW97103384 A TW 97103384A TW 97103384 A TW97103384 A TW 97103384A TW 200847241 A TW200847241 A TW 200847241A
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Taiwan
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nanotube
cmos
dielectric
protective layer
wafer
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TW97103384A
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Chinese (zh)
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Peter J Burke
Steffen Mckernan
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Peter J Burke
Steffen Mckernan
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Publication of TW200847241A publication Critical patent/TW200847241A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Abstract

A method is provided for preparing a nanotube coated wafer with electrical contacts and a dielectric that is compatible with follow-on industry standard CMOS processing steps. In one or more embodiments of the present disclosure, a process is provided for fabricating CNT FET devices comprising providing nanotube coated wafers for subsequent CMOS processing steps (e.g., by providing the nanotube coated wafer to a semiconductor foundry) that (1) are fully compatible with existing semiconductor foundry equipment, (2) provide protection for the nanotubes already in place on the wafer from certain CMOS processing steps that could otherwise be damaging (e.g., preprocessing cleaning steps in CMOS), and (3) do not expose existing semiconductor processing equipment to any new materials, i.e. all exposed materials are industry standard to CMOS processing and well-characterized.

Description

200847241 九、發明說明： 【發明所屬之技術領域】 本揭示案大體而言係關於奈米管塗佈晶圓領域，且更詳 言之，係關於製造與後續工業標準CMOS加工步驟相容之 具有電接點及介電質之奈米管塗佈晶圓的方法。 【先前技術】 碳奈米管（Carbon nanotube，CNT)場效應電晶體（field-effect transistor ， FET) 器件 ，單壁 奈米管 （Singie waiied nanotube ’ SWNT)與多壁奈米管（multiwalled nanotube， MWNT)，在電子學中前景廣闊。在一些應用中，CNT FET 效能可優於Si CMOS效能，尤其在需要高頻率、高功率密 度、高線性及低雜訊之模擬應用中。然而，Si CMOS為發 展良好之成熟技術，在其他衡量標準方面，尤其就數位邏 輯及電路密度而言，其可具有優於碳奈米管器件之特徵。 先前整合Si CMOS與CNT FET以利用與兩種技術相關之 益處之努力遭遇許多障礙。一種該先前技術方法描述於論 文 Y· C· Tseng，P. Q· Xuan，A. Javey，R. Malloy，Q. Wang，J· Bokor 及H· J. Dai之’’Monolithic Integration of Carbon Nanotube Devices with Silicon Mos Technology’’，4，第 123-127 頁， (2004)中。該方法首先製造Si MOS電路，包括數個互連 層，且隨後在該電路之頂部生長碳奈米管。為使用化學氣 相沈積（chemical vapor deposition，CVD)生長高品質單壁 碳奈米管（S WNT)，通常需要900°C或以上之生長溫度。該 等高溫往往會破壞標準Si MOS電路，包括（但不限於）Si 128819.doc 200847241 MOS電路中通常使用之互連金屬（cu)。出於該原因，該先 前技術方法使用耐熔金屬（Mo)用於互連，其不為si MOS工 業方法中之標準物且具有比Cu高之電阻率。因此，Mo並 非Si MOS電路之理想互連材料，且該整合si CMOS與CNT FET之方法具有重大障礙。 整合Si CMOS與CNT FET之另一方法包括SWNT CVD技 術，其在預先存在之Si CMOS電路之頂部合成SWNT，如 "Catalytic Chemical Vapor Deposition of Single-Wall Carbon Nanotubes at Low Temperatures’’，M. Cantoro, S. Hofmann, S. Pisana, V. Scardaci, A. Parvez, C. Ducati, A. C. Ferrari, A. M. Blackburn，K. Y· Wang及 J· Robertson,論⑽ Le你rs，6，1107-1112, (2006)中所述。該方法具有所合成之SWNT可能會具有高得 多的缺陷密度的障礙，其將會使SWNT FET器件產生較低 移動性且因此產生較低速度。 試圖整合CNT與CMOS方法之另一方法包括將奈米管溶 解於溶液中，且隨後由溶液技術沈積於預製造Si CMOS電 路上而將其置放於適當位置。該方法之溶解奈米管不合需 要，因為其通常會充滿缺陷，此又限制CNT FET器件之移 動性且最終限制其速度。 【發明内容】 根據本揭示案之一特徵，提供一種以與後續工業標準 CMOS加工步驟相容之方式製造具有電接點及介電質之奈 米管塗佈晶圓的方法。 在本發明揭示案之一或多個實施例中，提供一種製造 128819.doc 200847241200847241 IX. INSTRUCTIONS: TECHNICAL FIELD OF THE INVENTION The present disclosure relates generally to the field of nanotube coated wafers and, more particularly, to manufacturing compatible with subsequent industry standard CMOS processing steps. A method of coating a wafer with an electrical contact and a dielectric nanotube. [Prior Art] Carbon nanotube (CNT) field-effect transistor (FET) device, single-walled nanotube (Singie waiied nanotube 'SWNT) and multi-walled nanotube (multiwalled nanotube, MWNT) has a bright future in electronics. In some applications, CNT FET performance is superior to Si CMOS performance, especially in analog applications that require high frequency, high power density, high linearity, and low noise. However, Si CMOS is a well-developed and well-developed technology that is superior to carbon nanotube devices in terms of other metrics, especially in terms of digital logic and circuit density. Previous efforts to integrate Si CMOS and CNT FETs to take advantage of the benefits associated with both technologies have encountered many obstacles. One such prior art method is described in the paper Y. C. Tseng, P. Q. Xuan, A. Javey, R. Malloy, Q. Wang, J. Bokor and H. J. Dai's Monolithic Integration of Carbon Nanotube Devices With Silicon Mos Technology'', 4, pp. 123-127, (2004). The method first fabricates a Si MOS circuit comprising a plurality of interconnect layers and subsequently growing a carbon nanotube on top of the circuit. In order to grow high quality single-walled carbon nanotubes (S WNT) using chemical vapor deposition (CVD), a growth temperature of 900 ° C or higher is usually required. These high temperatures tend to damage standard Si MOS circuits, including, but not limited to, the interconnect metal (cu) commonly used in MOS circuits in Si 128819.doc 200847241. For this reason, the prior art method uses a refractory metal (Mo) for interconnection, which is not a standard in the si MOS industrial process and has a higher resistivity than Cu. Therefore, Mo is not an ideal interconnect material for Si MOS circuits, and this method of integrating si CMOS and CNT FETs has major obstacles. Another method of integrating Si CMOS and CNT FETs involves SWNT CVD, which synthesizes SWNTs on top of pre-existing Si CMOS circuits, such as "Catalytic Chemical Vapor Deposition of Single-Wall Carbon Nanotubes at Low Temperatures'', M. Cantoro , S. Hofmann, S. Pisana, V. Scardaci, A. Parvez, C. Ducati, AC Ferrari, AM Blackburn, K. Y· Wang and J. Robertson, on (10) Le you rs, 6, 1107-1112, ( Said in 2006). This approach has the barrier that the synthesized SWNTs may have much higher defect densities that will cause the SWNT FET devices to produce lower mobility and therefore lower speeds. Another method of attempting to integrate CNT and CMOS methods involves dissolving the nanotubes in solution and then depositing them on a pre-fabricated Si CMOS circuit by solution techniques and placing them in place. The dissolved nanotubes of this method are undesirable because they are often full of defects, which in turn limits the mobility of the CNT FET device and ultimately limits its speed. SUMMARY OF THE INVENTION In accordance with one feature of the present disclosure, a method of fabricating a wafer coated with an electrical contact and a dielectric nanotube in a manner compatible with subsequent industry standard CMOS processing steps is provided. In one or more embodiments of the present disclosure, a fabrication is provided 128819.doc 200847241

CNT FET器件之方法，其包含提供奈米管塗佈晶圓以用於 隨後CMOS加工步驟（例如，提供半導體鑄造廠奈米管塗佈 晶圓），所述晶圓（1)與現有半導體鑄造設備完全相容，（2) 提供已沈積於晶圓上之奈米管保護以免受某些隨後CMOS 加工步驟（例如，CMOS中之預加工清潔步驟），否則其會 受到破壞，及（3)使現有半導體加工設備不暴露於任何新穎 材料中，亦即，所有會暴露於隨後CMOS加工之用於形成 CNT FET之材料對CMOS方法而言為工業標準且經充分表 徵。 在一或多個實施例中，提供一種製造適於隨後CM〇s加 工之具有電接點及介電質之奈米管塗佈晶圓的方法。最 初，在潔淨的裸矽（Si)晶圓上沈積介電質，諸如墊式介電 質。隨後’在墊式介電質上沈積觸媒。隨後使用諸如_ 之技術在塾式彳電質上鄰接於觸媒沈積奈㈣。隨後與奈 米管接觸沈積電接點。最後，在奈米管上沈積保護介電 層’諸如SiN。以此方式形成之奈米管塗佈晶圓與後續工 業標準CMOS加工步驟相容。在_或多個實㈣中，奈米 管保護層亦可充當隨後形成於晶圓上之⑽s電路中: 極電極。 【實施方式】 隨圖式中類似參考 目標將變得更顯而 工業標準CMOS加 與附隨圖式結合參考下列描述，在附 數字表示類似元件，本發明上述特徵及 易見。 本發明揭示案係關於一種製造與後續 128819.doc 200847241 工步驟相容之具有電接點及介電質之奈米管塗佈晶圓的方 法。在以下描述中，陳述許多實施例以提供對本發明之徹 底理解。然而，對熟習此項技術者應顯而易見，該等及其 、只知例可在無该等詳情之情況下實施。在其他情況中， 為了不使本發明不明確，未詳細描述熟知特徵。 在一或多個實施例中，將參考圖丨_6中所說明之製程流 私圖中之橫截面圖描述一製造奈米管塗佈晶圓之方法。最 初、、二由工業標準方法在潔淨的裸矽（Si)晶圓1〇〇上沈積墊 式介電質102，其中墊式介電質1〇2可包含氧化物、氮化物 或半&體工業中常用之其他介電材料。在一實施例中，以 晶圓 100 包含 150 mm p 型 <100> 3663 n_cm si。然而，應 理解，晶圓100可由任何類型之“或(：：^1〇8方法中常用之其 他晶圓材料形成。晶圓102將包括奈米管電路區104及 CMOS電路區106 〇 隨後在奈米管電路區104中一部分墊式介電質1〇2上沈積 觸媒108，其中觸媒log係有效促進奈米管之合成。在一或 夕個貝施例中，觸媒1 〇8包含過渡金屬，諸如卜、川或 Cu。奴後使用工業標準方法（例如，使用cVD技術）在墊式 介電質102上鄰接於觸媒1〇8處沈積奈米管11〇。奈米管ιι〇 可包含任何類型之奈米管，包括（但不限於）碳奈米管 (CNT)，單壁奈米管（swNT)與多壁奈米管（MWNT)。在奈 米管110上沈積電接點112(例如，Pd或奈米管中常用之另 一金屬）。在一實施例中，可在電接點丨12上沈積銅或任何 其他工業標準金屬（未圖示）之層以防止電接點112在晶圓 128819.doc 200847241 100後加工期間暴露出來。 隨後在奈米管電路區104及CM0S電路區106之表面上沈 積保護層114。保護層114可包含氮化物層，諸如siN或 CMOS方法中常用之另一保護材料。在一或多個實施例 中’保濩層114係充當需要閘極之奈米管器件(諸如，電晶 體）之电層。在-或多個實施例中，保護層i 14係充當防 止奈米管110在習知C M 〇 S製造方法中晶圓丨〇 〇上進行之隨 後製程期間受到破壞之保護層。舉例而言，保護層丨丨斗提 供對抗酸（HF)清洗步驟及其他CM〇s製程之保護。在一或 夕個貝她例中，保護層丨14進一步阻止隨後（：]^〇8製程步驟 中所使用之CMOS加工設備暴露於任何在CM〇s方法中通 常不會遇到之新穎材料。以此方式，保護層114包括在隨 後CMOS加工步驟中通常會遇到之材料且充當保護層ιΐ4下 方之奈米管電路區丨04中之材料的屏障。 在一或多個實施例中，在完成上述加工步驟以形成奈米 管電路區104之組件後，CMOS電路區1〇6將不含有任何奈 米官110，而僅含有CMOS方法中通常使用之工業標準材料 (例如，僅包含諸如Si/Si〇2/SiN之材料）。另外，奈米管電 路區104將由包含CM0S方法亦通常使用之材料之保護層 114覆盍。由此，根據本文所述之一或多個實施例所形成 具有電接點112及介電質114之奈米管塗佈晶圓100隨後與 任何後縯工業標準CMOS加工步驟相容。工業標準CMOS 方法之一個實例為由UC Berkeley Microlab使用之CMOS方 法’如儲存於http://microlabZberkeley.edu/baseline下之電 128819.doc -10- 200847241 文件 baseline—xsection—2005 一 UCBerkeley.pdf中所述，其 谷以引用之方式併入本文中。UC Berkeley Microlab CMOS方法描述使用某種起始材料以用於以cm〇s方法中 (例如，如文件之第2個幻燈片上所示般），其中本發明揭示 木教示種產生可用作UC Berkeley Microlab CMOS方法 之起始材料之經改質所得材料（以及奈米管電路區工⑸中的 内埋式奈米官器件）之方法。然而，應理解，本發明不意A method of a CNT FET device, comprising providing a nanotube coated wafer for subsequent CMOS processing steps (eg, providing a semiconductor foundry nanotube coated wafer), the wafer (1) and existing semiconductor casting The device is fully compatible, (2) provides nanotube protection that has been deposited on the wafer from certain subsequent CMOS processing steps (eg, pre-process cleaning steps in CMOS) that would otherwise be compromised, and (3) Existing semiconductor processing equipment is not exposed to any novel materials, i.e., all materials used to form CNT FETs that are exposed to subsequent CMOS processing are industry standard and well characterized for CMOS methods. In one or more embodiments, a method of making a nanotube coated wafer having electrical contacts and dielectric suitable for subsequent CM〇s processing is provided. Initially, dielectrics such as mat dielectrics were deposited on clean bare silicon (Si) wafers. The catalyst is then deposited on the mat dielectric. Subsequent to the catalytic deposition of na[beta] on the 塾-type 彳, using techniques such as _. The electrical contacts are then deposited in contact with the nanotubes. Finally, a protective dielectric layer such as SiN is deposited on the nanotube. The nanotube coated wafers formed in this manner are compatible with subsequent industry standard CMOS processing steps. In _ or multiple real (four), the nanotube protective layer can also act as a (10) s circuit that is subsequently formed on the wafer: a pole electrode. [Embodiment] A similar reference object will become more apparent in the drawings. The industry standard CMOS is added to the accompanying drawings in conjunction with the following description. SUMMARY OF THE INVENTION The present invention is directed to a method of fabricating a wafer having electrical contacts and dielectric nanotubes that are compatible with subsequent processing steps 128819.doc 200847241. In the following description, numerous embodiments are set forth to provide a thorough understanding of the invention. However, it should be apparent to those skilled in the art that these and other examples can be implemented without such details. In other instances, well-known features have not been described in detail in order not to obscure the invention. In one or more embodiments, a method of fabricating a nanotube coated wafer will be described with reference to a cross-sectional view in the process flow diagram illustrated in Figure -6. Initially, a pad-type dielectric 102 is deposited on a clean bare (Si) wafer 1 by an industry standard method, wherein the pad dielectric 1 〇 2 may comprise an oxide, a nitride or a semi-amp; Other dielectric materials commonly used in the body industry. In one embodiment, the wafer 100 contains 150 mm p-type <100> 3663 n_cm si. However, it should be understood that the wafer 100 can be formed of any type of other wafer material commonly used in the "::1" method. The wafer 102 will include the nanotube circuit region 104 and the CMOS circuit region 106. Catalyst 108 is deposited on a portion of the pad dielectric 1〇2 in the nanotube circuit region 104, wherein the catalyst log is effective to promote the synthesis of the nanotubes. In one or the case, the catalyst 1 〇8 Containing a transition metal such as Bu, Chuan or Cu. The slave is deposited on the mat dielectric 102 adjacent to the catalyst 1〇8 using an industry standard method (for example, using cVD technology). Ιι〇 can comprise any type of nanotubes including, but not limited to, carbon nanotubes (CNT), single-walled nanotubes (swNT) and multi-walled nanotubes (MWNT). Deposited on nanotubes 110 Electrical contact 112 (e.g., another metal commonly used in Pd or nanotubes). In one embodiment, a layer of copper or any other industry standard metal (not shown) may be deposited on electrical contact 12 The electrical contact 112 is prevented from being exposed during post-processing of the wafer 128819.doc 200847241 100. Subsequent to the nanotube circuit area 10 4 and a surface of the CMOS circuit region 106 is deposited with a protective layer 114. The protective layer 114 may comprise a nitride layer, such as another protective material commonly used in siN or CMOS methods. In one or more embodiments, the 'protective layer 114 Acting as an electrical layer of a nanotube device (such as a transistor) that requires a gate. In one or more embodiments, the protective layer i 14 acts as a wafer to prevent the nanotube 110 from being fabricated in a conventional CM 〇S manufacturing process. A protective layer that is destroyed during subsequent processing on the crucible. For example, the protective layer bucket provides protection against acid (HF) cleaning steps and other CM〇s processes. The protective layer 14 further prevents subsequent exposure of the CMOS processing equipment used in the (:) 8 process step to any novel material that would not normally be encountered in the CM〇s method. In this manner, the protective layer 114 is included Subsequent materials that are typically encountered in the CMOS processing steps and act as a barrier to the material in the nanotube circuit region 下方04 under the protective layer ΐ4. In one or more embodiments, the above processing steps are completed to form the nanotubes After the components of circuit area 104 The CMOS circuit area 〇6 will not contain any nano-110, but only the industry standard materials commonly used in CMOS methods (for example, only materials such as Si/Si〇2/SiN). In addition, the nanotube circuit The region 104 will be covered by a protective layer 114 comprising a material that is also commonly used by the CMOS process. Thus, a nanotube coating having an electrical contact 112 and a dielectric 114 is formed in accordance with one or more embodiments described herein. Wafer 100 is then compatible with any post-production industry standard CMOS processing steps. An example of an industry standard CMOS method is the CMOS method used by UC Berkeley Microlab 'as stored at http://microlabZberkeley.edu/baseline, 128819. Doc -10- 200847241 Document baseline—xsection—2005 As described in UC Berkeley.pdf, its valley is incorporated herein by reference. The UC Berkeley Microlab CMOS method describes the use of certain starting materials for use in the cm〇s method (for example, as shown on the second slide of the document), wherein the present invention discloses that wood teaches seed production as UC Berkeley Method of upgrading the material of the starting material of the Microlab CMOS method (and the embedded nanomanipulator in the nanotube circuit division (5)). However, it should be understood that the present invention is not intended

欲偈限於UC Berkeley Micr〇lab CM〇s；^法而可用作任: Pic後工業CMOS方法之起始材料。 或夕個實施例中，電接點112可以產生與電接點墊 m之已知位置相符之器件圖的方式沈積，如此該等器件 可與後續CMOS加工步驟吱直讪★丁止时丄 具他加工步驟中所產生之其他 電路電連接。其他電路之接赴轨 电峪之接點墊112較佳係用與隨後製程 具有最大相容性之材料所製造。該等奈米管器件之已知電 特性隨後可添加至且利用於巧斗太 用於°又5十套組中以進一步簡化具有 元件及互連之混合物之更具功能性的電路設計。 在-或多個實施例中，保護層114可完全覆蓋晶圓1〇〇之 表面或者僅覆蓋彼等待保鳟 保邊之部分(例如，僅奈米管電路 區104)。在一或多個實施例中， 甲1極（未圖示）可在沈積保 施例中，所進行之 100之Γ步加η包括移除不需要奈米管⑽器件之晶圓 100區域上的奈米管11〇器件。 在一或爹個實施例中，如本 圓 1ΛΛ々十土 —曰 又所迷之製造奈米管塗佈晶 100之方法在晶圓100上提供 接'點奈米管11 0以用於隨 128819.doc 200847241 後CMOS加工中而 之新穎材 ^入隨後CM〇W卫期間將會遇到 之成功替：工業標準物以實現CNT與CM〇S方法 或多個實施例中，可提供類似於簡 電路大，使用之多晶石夕奈米管間極，且CN 丁可以糾囊 也路大體上相同夕士 ^ , 式互連，其中例外者為與奈米管電路 ”中的Pd奈米管源電極/汲電極接點將於氮化矽中需要 孔0 ^ ’、方法之各種怨樣可用於任何需要CNT-CMOS整合之 電路’例如無線通信及有線通信電路之好混合信號晶片。 一雖’、、;已就目鈾視為特定實施例描述系統及方法，但本揭 ,、木不必侷限於忒等所揭示之實施例。意欲涵蓋申請專利 範圍之精神及範疇内所包括之各種修改及類似排列，申請 專利範圍之範哿應符合最廣泛的解釋以涵蓋所有該等修改 及類似結構。本發明揭示案包括下列申請專利範圍之任何 及所有實施例。 【圖式簡單說明】 圖1-6說明一種根據本發明揭示案之一或多個實施例的 衣造與後續工業標準CMOS加工步驟相容之具有電接點及 介電質之奈米管塗佈晶圓的方法。 【主要元件符號說明】 100 晶圓 102 墊式介電質 104 奈米管電路區 1288l9.doc -12- 200847241 106 CMOS電路區 108 觸媒 110 奈米管 112 電接點/電接點墊 114 保護層The UC Berkeley Micr〇lab CM〇s method can be used as the starting material for the post-Pic industrial CMOS method. In one embodiment, the electrical contacts 112 can be deposited in a manner that produces a device map that matches the known location of the electrical contact pads m, such that the devices can be compared to subsequent CMOS processing steps. Other circuits that are generated during his processing steps are electrically connected. The other pads of the electrical circuit are preferably fabricated using materials that have the greatest compatibility with subsequent processes. The known electrical characteristics of the nanotube devices can then be added to and utilized in the quaternary set to further simplify the more functional circuit design with a mixture of components and interconnects. In one or more embodiments, the protective layer 114 may completely cover the surface of the wafer 1 or may only cover portions of the wafer that are awaiting edge protection (e.g., only the nanotube circuit region 104). In one or more embodiments, the first pole (not shown) may be in the deposition embodiment, and the step 100 performed by adding η includes removing the wafer 100 region of the device that does not require the nanotube (10) device. The nanotubes are 11 〇 devices. In one or more embodiments, a method of fabricating a nanotube coating crystal 100, such as the present invention, is provided on the wafer 100 to provide a 'nanotube 110' for use with 128819.doc 200847241 After the CMOS processing, the novel material will be successfully replaced by the CM 〇W industry: the industry standard to implement the CNT and CM〇S method or multiple embodiments, can provide similar The simple circuit is large, the polycrystalline stone is used between the mid-tubes, and the CN can be used to correct the sacs. The roads are basically the same as the Xis ^, and the interconnections, the exception of which is the Pd nanometer in the circuit with the nanotubes. The tube source electrode/germanium electrode contact will require hole 0 ^ ' in tantalum nitride. The various complaints of the method can be used for any mixed signal chip such as wireless communication and wired communication circuit that requires CNT-CMOS integration. The system and method have been described with respect to the specific embodiments of the uranium, but it is not intended to be limited to the disclosed embodiments, and the various modifications included in the spirit and scope of the patent application are intended to be included. And similar arrangements, the scope of the patent application scope The invention is broadly construed to cover all such modifications and similar structures. The present invention includes any and all embodiments of the following claims. FIG. 1-6 illustrates one of the disclosures of the present invention or A method of coating a wafer with electrical contacts and dielectric nanotubes compatible with subsequent industrial standard CMOS processing steps of various embodiments. [Main component symbol description] 100 wafer 102 pad dielectric 104 silicon tube circuit area 1288l9.doc -12- 200847241 106 CMOS circuit area 108 catalyst 110 nanotube 112 electrical contact / electrical contact pad 114 protective layer

128819.doc -13-128819.doc -13-

Claims (1)

200847241 十、申請專利範圍： 1· 一種奈米管-互補式金屬氧化物半導體（CMOS)整合之方 法，其包含： 衣k 一奈来管塗佈晶圓’其係用於在該奈米管塗佈晶 圓上之隨後CMOS加工步驟。 2.如請求項1之方法，其中該奈米管塗佈晶圓係經製造具 有電接點及介電質。 3·如請求項1之方法，其中該奈米管塗佈晶圓係藉由以下 步驟製造： 在一矽晶圓上沈積一墊式介電質； 在該墊式介電質上沈積一觸媒； 在該墊式介電質上鄰接於該觸媒處沈積奈米管； 與该等奈米管接觸地沈積電接點；及 在10亥寺奈米管及该專電接點上沈積一保護層，其中在 該保護層中為一介電材料。 4·如請求項3之方法，其進一步包含用一CVD法沈積該等 奈米管。 ' 5 ·如明求項3之方法，其中該等電接點包含鈀（Pd)。 6 士明求項3之方法，其進一步包含在沈積該保護層之前 在該等電接點上沈積一金屬層。 7·如巧求項3之方法，其中該保護層為SiN。 8· 士明求項1之方法，其中該所製造之奈米管塗佈晶圓係 與CMOS加工步驟相容。 9，如請求項8之方法，其中該所製造之奈米管塗佈晶圓防 128819.doc 200847241 護奈米管特定材料以备、〇 # μ 士 免文該專隨後CMOS加工步驟。 10. 一種用於CMOS加工中夕壯 朴a人 γ之叙置，其包含： 一於適於CMOS電敗π二、也丨 兒路形成製程之一基板晶圓上之CMOS 電路區；及 一奈米管電路區，其包含： 一基板； 該基板上之一介電質； p 該介電質上之一觸媒； 该介電質上鄰接於該觸媒處之奈米管； 與該等奈米管接觸之電接點；及 口玄等示米官及該等電接點上之一保護層，其中在該 保護層中為介電材料。 11·，請求項ίο之裝置，其中該保護層防護該等奈米管及該 等電接點以免暴露於CMOS電路形成製程中。 12.如請求項1〇之裝置，其中該等電接點包含鈀㈣。 (;13.如請求項10之裝置，其進一步包含一沈積於該等電接點 與该保護層之間的金屬層。 • 14·如請求項10之裝置，其中該保護層為SiN。 I5·如明求項10之裝置，其中該保護層為一與CMOS加工步 • 驟相容之材料。 16· 士明求項1〇之裝置，其進一步包含一形成於該等奈米管 上之多晶石夕閘極。 17· —種奈米管_CM〇s整合之方法，其包含： 在一晶圓上製造一奈米管電路區； 128819.doc 200847241 使用一 CMOS加工材料在該奈米管電路區上形成保護 層以保護該奈米管電路區免受CMOS加工步驟； 在具有該所製造之奈米管電路區之該同一晶圓之 CMOS電路區上進行CMOS加工步驟。 18. 如請求項1 7之方法，其進一步包含防護用於進行該等 CMOS加工步驟之CMOS加工設備免受用於形成該奈米管 電路區之奈米管特定材料。200847241 X. Patent application scope: 1. A method for integrating a nanotube-complementary metal oxide semiconductor (CMOS), comprising: a coating tube coated with a wafer, which is used in the nanotube Subsequent CMOS processing steps on the coated wafer. 2. The method of claim 1, wherein the nanotube coated wafer is fabricated with electrical contacts and dielectric. 3. The method of claim 1, wherein the nanotube coated wafer is fabricated by: depositing a mat dielectric on a wafer; depositing a touch on the mat dielectric a dielectric tube is deposited adjacent to the catalyst on the mat dielectric; an electrical contact is deposited in contact with the nano tube; and a deposit is deposited on the 10Hi tube and the special contact a protective layer, wherein the protective layer is a dielectric material. 4. The method of claim 3, further comprising depositing the nanotubes by a CVD method. The method of claim 3, wherein the electrical contacts comprise palladium (Pd). The method of claim 3, further comprising depositing a metal layer on the electrical contacts prior to depositing the protective layer. 7. The method of claim 3, wherein the protective layer is SiN. 8. The method of claim 1, wherein the manufactured nanotube coated wafer is compatible with the CMOS processing steps. 9. The method of claim 8, wherein the manufactured nanotube coated wafer is protected by a specific material for preparation, and the subsequent CMOS processing steps are omitted. 10. A CMOS device for CMOS processing, comprising: a CMOS circuit region on a substrate wafer suitable for CMOS electrical failure π2, also a circuit formation process; and a nanotube circuit region, comprising: a substrate; a dielectric on the substrate; p a catalyst on the dielectric; the dielectric adjacent to the catalyst at the dielectric; An electrical contact that is in contact with the nanotube; and a protective layer on the display and the electrical contact, wherein the protective layer is a dielectric material. 11. The device of claim ί, wherein the protective layer protects the nanotubes and the electrical contacts from exposure to a CMOS circuit forming process. 12. The device of claim 1 wherein the electrical contacts comprise palladium (d). (13) The apparatus of claim 10, further comprising a metal layer deposited between the electrical contacts and the protective layer. The device of claim 10, wherein the protective layer is SiN. The device of claim 10, wherein the protective layer is a material compatible with the CMOS processing step. 16. The apparatus of the present invention, further comprising a layer formed on the nanotubes A polycrystalline stone etch gate. A method of integrating a nanotube _CM〇s, comprising: fabricating a nanotube circuit region on a wafer; 128819.doc 200847241 using a CMOS processing material in the nano A protective layer is formed over the rice tube circuit region to protect the nanotube circuit region from the CMOS processing step; the CMOS processing step is performed on the CMOS circuit region of the same wafer having the fabricated nanotube circuit region. The method of claim 17, further comprising protecting the CMOS processing apparatus for performing the CMOS processing steps from the nanotube-specific material used to form the nanotube circuit region. 128819.doc128819.doc
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