200845162 (1) 九、發明說明 【發明所屬之技術領域】 本發明大致關係於電抛光，更明確地說，有關於使用 電抛光製程，移除阻障層。 【先前技術】 半導體裝置係使用若干不同處理步驟，在半導體晶圓 Φ 上加以製造，以建立電晶體與內連線元件。爲了電連接相 關於半導體晶圓的電晶體端，導電（例如金屬）溝渠、導孔 等係被形成在作爲半導體裝置的一部份之介電材料中。溝 渠及導孔耦接電晶體、半導體裝置內部電路、及在半導體 裝置外的電路間之電信號與電功率。 在形成內連線元件中，半導體晶圓可能受到例如遮罩 、触刻、及沈積製程，以形成半導體裝置的想要電子電路 。尤其是，可以執行多數遮罩及蝕刻步驟，以在半導體晶 Φ 圓上之介電層中形成凹陷區圖案，其作爲內連線用之溝渠 與導孔。可以然後執行一沈積製程，以沈積一金屬層在該 半導體晶圓上，藉以沈積金屬在溝渠及導孔中，及在半導 體晶圓的非凹陷區上。爲了隔離內連線，例如有圖案之溝 渠及導孔，沈積在半導體晶圓的非凹陷區中之金屬被移除 〇 傳統由沈積在半導體晶圓的介電層之非凹陷區上移除 金屬膜的方法包含例如化學機械硏磨（CMP)。CMP法係被 大量使用半導體工業中，以硏磨及平坦化在介電層中之非 -4- 200845162 (2) 凹陷區之溝渠及導孔內的金屬層，以形成內連線。 在CMP製程中，一晶圓組件被定位在位在平台或網 上之CMP墊上。晶圓組件包含一具有一或多數層及/或特 性，如形成在介電層中之內連線元件的基材。然後，施加 一力量，以將晶圓組件壓向CMP墊。CMP墊及基材組件 係被彼此移動靠近，同時，施加力量以硏磨及平坦化晶圓 的表面。然後，稱爲硏漿的硏磨溶液係被灑在CMP墊上 0 ，以促成該硏磨。硏漿典型包含磨料並可化學反應，以選 擇地自晶圓移除不想要的材料，例如金屬層，這係較例如 介電材料之其他材料更快速。 然而，因爲涉及相當強的機械力量，所以，CMP法 可能對下層之半導體結構有幾項有害影響。例如，當內連 線幾何移動至〇 . 1 3微米及更低時，在例如，銅之導電材料 及用於典型嵌入製程中之低k膜之機械特性間有可能有很 大差異。例如，低k介電膜的楊氏係數可能低於銅的楊氏 Φ 係數超出10數量級。因此，在CMP製程中，施加至介電 膜與銅等等材料中之相當強機械力可能在半導體結構上造 成應力有關的缺陷，其包含剝離、碟化、腐蝕、膜抬起、 刮傷等等。 因此，有想要新製程技術。例如，一金屬層可能使用 電抛光製程，從一晶圓移除或蝕刻。通常，在電拋光製程 中，在予以被硏磨之晶圓的部份係被浸漬於電解溶液中， 然後，施加電荷至晶圓。這些狀態造成銅被移除或由晶圓 移除。 -5- 200845162 (3) 例如鉅、氮化鉅、鈦、及氮化鈦之阻障層不能藉由磷 酸及硫酸爲主之電解液所電抛光。因此，阻障層係典型地 由電漿蝕刻或化學機械硏磨（CMP)所移除。然而，電漿触 刻加入其他製程步驟，及CMP損害在阻障層下之低k介 電質。 【發明內容】 ϋ 在一例示實施例中，一第一介電層係被形成在半導體 晶圓上。第一介電層係對抗於氫氟酸的蝕刻。一第二介電 層係被形成在該半導體晶圓上之第一介電層上。該第二介 電層易受到氫氟酸所蝕刻。第二介電層係被形成有凹陷區 及非凹陷區。凹陷區被延伸內該第一介電層。一阻障層係 被形成以覆蓋該凹陷區及非凹陷區。該金屬層係被形成以 塡入凹陷區及覆蓋非凹陷區。該金屬層及阻障層係被電抛 光，以使用含氫氟酸之電解液，曝露出該非凹陷區。 【實施方式】 在一例示實施例中，第1Α至1C圖描繪使用噴嘴之電 抛光製程的細節。爲了完全移除阻障層11 1 2，製程較佳以 第1 Α至1 C圖所示之過硏磨量，由晶圓1 1 1 4的中心執行至 晶圚1 114的邊緣。以此方式，電抛光電流1 1 16將容易流經 阻障層1 112並至鄰近Cu膜1 1 10，然後至如第1C圖所示之 晶圓邊緣。當包圍銅溝渠1120之阻障層被電抛光製程移除 時，在結構1 1 20中之銅及阻障金屬失去電路徑。因此’在 200845162 (4) 結構1 120上之電抛光製程自動停止，如第1C圖所示。 同時，移除阻障層及銅的電解液係被列入如下： 氫氟酸（HF)(49%wt) : 10 ml，範圍由 4至 40 nm ; 磷酸 H304(8 5%wt) :20〇1111，範圍由〇至30〇1111; 硫酸 H3S04(9 8%wt) : 60 ml，範圍由 〇至 80 ml ; 乙二醇：100 ml，範圍由0至200 ml;及 甘油：5 0 ml，範圍由0至1 00 ml。 φ 在上述電解液中，氫氟酸（HF)係被用以移除在上述電 抛光製程時所形成之金屬氧化物，例如氧化鉅及氧化鈦。 應說明的是，HF酸可以組合其他鹽類，例如A1C13、 ZnCl2、MgCl2、Cr03、（NH4)HP04、（NH4)2S04、NH4F、 NH4N03、及酸類，例如HN〇3、HC1、HCl〇4、及表面活 性劑，例如苯並***（C6H5N3)。 氫氟酸很強烈地攻擊氧化砂或氧化砂爲主之介電質。 因此，較佳地使用抗HF介電材料1 1 1 4，例如聚醯亞胺、 φ 氟化聚醯亞胺、聚醯亞胺奈米泡沬、聚對二甲苯基N、聚 (芳醚）、聚（芳族）、聚萘類、芳香烴（SiLK)、非晶碳膜、 鐵氟龍-AF、鐵氟龍微乳化液等等。 如果使用氧矽爲主之介電質，則這些氧化矽爲主之介 電質較佳係爲另一層具有高抵抗或阻擋HF所形成混合結 構效能的介電層所覆蓋（予以參考第3 A至3 I圖所述）。 另一例示實施例係移除阻障層，如第2 A至21圖所示 。該製程步驟係列出如下： 步驟1 :沈積第一介電層2006在形成在前一金屬層中 200845162 (5) 之現行介電層20 12上，如第2A圖所示。此現行介電層 2012係由碳化矽（SiC)、碳氮化矽（SiCN)、或具有高抵抗 HF或阻擋HF效能的其他介電材料所作成。沈積法可以 是化學氣相沈積（CVD)或旋塗介電質法。 介電層200 6包含聚醯亞胺、氟化聚醯亞胺、聚醯亞胺 奈米泡沬、聚對二甲苯基N、聚（芳醚）、聚（芳族）、聚萘 類系、芳香烴（SiLK)、非晶碳膜、鐵氟龍-AF、鐵氟龍微 φ 乳化液或其他具有高抵抗及阻擋HF的低k介電質。 步驟2:沈積第二介電層2001在第一介電層2006上， 如第2A圖所示。第二介電層2001可以爲氧化矽、氧化矽 爲主之介電質、氟化矽石、摻碳矽石、及無孔矽石。第二 介電質可以爲任意介電材料，其係容易受到HF所損壞者 〇 步驟3 :以電漿蝕刻導孔20 10及溝渠2009，如第2B圖 所示。 # 步驟4 :沈積阻障層2004及銅種層2003，如第2C圖所 示。通常，阻障層2004係由鉬、氮化鉅、鈦、氮化鈦、鎢 、氮化鎢、釕、氮化釕、鉻、鈮、鉬、鐯、鍺、鈀、給、 銶、鐵及銥作成。 步驟5 :電鍍銅層2002，以塡充導孔及溝渠，如第2D 圖所示。被鍍之銅層可以進一步以化學機械硏磨（CMP)加 以平坦化，如PCT專利申請PCT/US02/26 1 67及美國專利 申請1 0/486,982號案所揭示，這些案係倂入作爲參考，並 可以藉由使用PCT專利申請PCT/US03/11417及美國專利 200845162 (6) 申請1 0/5 1 0,656所揭示之虛擬結構加以形成，這些案係倂 入作爲參考，或者，可以被美國臨時申請案60/73 8,25 0所 揭示之接觸墊噴嘴加以電抛光，這案也倂入作爲參考。 步驟6:使用參考第1A至1C圖所述之電抛光製程及 參考第8A至8F圖所述之設備移除銅層。 第2E圖顯示藉由使用電抛光製程，從阻障層2005移 除的銅層2002的銅內連線結構的剖面圖。當電抛光製程持 φ 續時，溝渠中之銅膜將開始下陷，及阻障層將被移除，如 第2F圖所示。因爲阻障層被移除，所以電拋光電流由於 沒有導通路徑而停止。因此，在銅溝渠及介電層間之溝渠 與阻障層內之銅將隔開電拋光製程，或抛光製程將自終止 。另一方面，阻障殘留201 5將保留在第二介電層200 1之表 面上，如第2F圖所示。因此，建議使用定電壓以執行上 述電抛光製程。 如上所述，第二介電層2 0 〇 1係由氧化矽、氧化矽爲主 • 之介電質、氟化政石、摻碳砂石、及無孔砂石作成，這係 容易爲HF所蝕刻。因此，第二介電層係爲在電解液中之 HF所蝕去，如第2G圖所示。當飩刻製程持續時，最後阻 障殘留2015將由於下方之介電質2021的底切蝕刻而移除， 如第2G及2H圖所示。 步驟7:沈積 SiC或SiCN層2008在銅2002及介電層 2006上，如第21圖所示。 步驟8 :重覆步驟1至7，以形成另一層內連線層，如 第2J圖所不。 -9 - 200845162 (7) 另一例示實施例以移除阻障層，如第3 A至3 I圖所示 。製程步驟係被列出如下： 步驟1:沈積第一介電層3052，及沈積第二介電層（鈾 刻停止層）3 050，如第3A圖所示。沈積法可以爲化學氣相 沈積（CVD)或旋塗介電質法。第一介電層3 05 2包含二氧化 矽、氟化矽玻璃03〇)、1133(5、鑽石狀碳、摻碳“〇2、 MSSQ、及無孔矽石。第二介電層3050主要用以停止在電 φ 漿蝕刻時，導孔與溝渠間之蝕刻製程。第二介電層3 050的 第二功能爲阻擋HF或氟原子/離子擴散入第三介電層 300 6(如下述），而在雷射電抛光製程時，到達第一介電層 3 0 5 2，這將參考第3 G圖加以詳述。明顯地，如果HF或氟 離子穿透第二介電層3050，則其將摧毀第一介電層3052。 第二介電層3 050包含碳化矽（SiC)、碳氮化矽（SiCN)、或 其他具有高抵抗及阻擋HF能力的介電材料。換句話說， HF或氟原子/離子都不應穿透被選定的第二介電質。 φ 步驟2 :沈積第三介電層3006在第二介電層3〇5〇上， 如第3A圖所示。沈積法可以爲化學氣相沈積法（CVD)或旋 塗介電質法。第三介電層3006包含聚醯亞胺、氟化聚醯亞 胺、聚醯亞胺奈米泡沬、聚對二甲苯基N、聚（芳醚）、聚（ 芳族）、聚萘類、芳香烴（SiLK)、非晶碳膜、鐵氟龍-AF、 鐵氟龍微乳化液或其他低k介電質、或具有高抵抗hf的 超低k介電質。 步驟3:沈積第四介電層（或犧牲層）3 00 1在第三介電 層3 006上，如第3A圖所示。第四介電層3 00 1可以爲氧化 -10- 200845162 (8) 矽、氧化矽爲主之介電質、氟化矽石、摻碳矽石、及無孔 矽石。第四介電層300 1應選擇能爲HF酸所蝕去者。 步驟4:沈積額外遮罩層，用以製造雙層嵌入結構。 微影步驟的細節係爲本技藝所知，因此，不再說明。 步驟5 :以電漿蝕刻導孔3010及溝渠3 009，及如第3B 圖所示剝離光阻。 步驟6:沈積阻障層3004及銅種層3003，如第3C圖所 φ 示。通常，阻障層3004係由如鉅、氮化鉅、鈦、氮化鈦、 鎢、氮化鎢、釕、鉻、鈮、鉬、鐯、铑、鈀、給、銶、餓 及銥之單一金屬層或金屬層組合。 步驟7 :電鍍銅層3 002，以塡入導孔及溝渠，如第3D 圖所示。所電鍍之銅可以進一步藉由如 PCT專利申請 PCT/US 02/26 1 67及美國專利申請1 0/486,982案所揭示之化 學機械硏磨（CMP)加以平坦化，該等案係倂入作爲參考； 或者，也可以藉由使用如PCT專利申請PCT/US03/11417 • 及美國專利申請1 0/5 1 0,656案所揭示之使用虛擬結構之平 面電鍍加以形成，該等案係倂入作爲參考；或者，也可以 使用美國臨時申請案60/73 8,2 5 0所揭示之以接觸墊噴嘴進 行電抛光加以平坦化，該案也倂入本案作爲參考。 步驟8:使用參考第1A至1C圖所述之電抛光製程及 予以參考第8A至8F圖所述之設備，加以移除銅層。 第3E圖顯示藉由使用電抛光製程，使銅層3 002之銅 內連線結構被自阻障層3005上移除的剖面圖。當電抛光製 程持續時，在溝渠中之銅膜將開始下凹，及阻障層將被移 -11 - 200845162 (9) 除，如第3F圖所示。因爲阻障層被移除，所以電抛光電 流將由於沒有導通路徑被停止。因此，在溝渠內之銅及銅 溝渠與介電質間之阻障層將與電抛光製程隔開，或者，硏 磨製程將自動終止。另一方面，由於相同理由，阻障層殘 留3015將保留在介電層3 00 1之表面上，如第3F圖所示。 因此，推薦使用定電壓以執行上述電抛光製程。 如前所述，第四介電層3001係由氧化矽、氧化矽爲主 φ 之介電質、氟化矽石、摻碳矽石、及無孔矽石所作成，這 些係容易爲HF酸所蝕刻。因此，第四介電層係爲電解液 中之HF酸所蝕去，如第3 G圖所示。當蝕刻製程持續時， 最後，阻障層殘留3 0 1 5將由於在下之介電層3 02 1之底切鈾 刻而被移除，如第3 G及3 Η圖所示。 在電抛光後，晶圓被傳送至一潔淨室，用以移除所有 化學品。另外之HF爲主之化學品可以進一步被噴在晶圓 表面上’以蝕去當部份阻障層殘留在電抛光室中未全然移 • 除的阻障層殘留。例如，對於5%(重量）HF濃度，鉬的蝕 刻率約1.5nm/分。HF濃度係在範圍l%wt至10%wt。檸檬 酸（C6H8〇7)〇.5%wt也可以加入清潔程序中，以移除氧化 銅。檸檬酸濃度範圍由〇. 1 %wt至1 %wt。然後，晶圓被進 一步爲純DI水所清洗。 步驟9:沈積SiC或SiCN層3008在銅3 002及介電層 3 006上，如第31圖所示。 步驟10:重覆步驟1至步驟9，以形成另一層之內連線 層（未示出）。 -12- 200845162 (10) 另一例示實施例移除阻障層，如第4A至41圖所示。 該製程步驟係如下列： 步驟1 :沈積第一介電層405 1、沈積第二介電層（飩刻 停止層）4050、及沈積第三介電層4006，如第4A圖所示。 沈積方法可以爲化學氣相沈積（C V D)或旋塗介電質法。第 一及第三介電層包含聚醯亞胺、氟化聚醯亞胺、聚醯亞胺 奈米泡沬、聚對二甲苯基N、聚（芳醚）、聚（芳族）、聚萘 φ 類、芳香烴（SiLK)、非晶碳膜、鐵氟龍-AF、鐵氟龍微乳 化液或其他低k介電質、或具有高抵抗HF的超低k介電 質。該第二介電層405主要用以在電漿蝕刻時，清洗在導 孔與溝渠間之触刻停止層。第二介電層的第二功能爲阻擋 HF或氟原子/離子在電抛光製程中，擴散經由第三介電層 4006，這將參考第4G圖加以詳述。第二介電材料4050包 含碳化矽（SiC)、碳氮化矽（SiCN)、或具有高抵抗或阻擋 HF功能的其他介電材料。換句話說，HF或氟原子/離子 # 都不應穿透被選擇之第二介電層。 步驟2 :沈積第四介電層400 1在第三介電層4006上， 如第4A圖所示。第四介電層400 1可以爲氧化矽、氧化矽 爲主之介電質、摻氟矽石、摻碳矽石、及無孔矽石。第四 介電層400 1應被選擇以容易爲HF酸所蝕刻者。 步驟3:沈積其他遮罩層，用以製造雙層嵌入結構。 微影步驟的細節係爲本技藝所知，並不再說明。200845162 (1) Description of the Invention [Technical Field of the Invention] The present invention relates generally to electropolishing, and more particularly to the use of an electropolishing process to remove a barrier layer. [Prior Art] A semiconductor device is fabricated on a semiconductor wafer Φ using a number of different processing steps to create a transistor and interconnect components. In order to electrically connect the phase to the transistor end of the semiconductor wafer, conductive (e.g., metal) trenches, vias, etc. are formed in a dielectric material that is part of the semiconductor device. The trenches and vias are coupled to electrical signals and electrical power between the transistors, the internal circuitry of the semiconductor device, and the circuitry external to the semiconductor device. In forming the interconnect components, the semiconductor wafer may be subjected to, for example, masking, lithography, and deposition processes to form desired electronic circuitry for the semiconductor device. In particular, a plurality of masking and etching steps can be performed to form a recess pattern in the dielectric layer on the semiconductor crystal Φ circle, which serves as a trench and via for the interconnect. A deposition process can then be performed to deposit a metal layer on the semiconductor wafer to deposit metal in the trenches and vias, and on the non-recessed regions of the semiconductor wafer. In order to isolate interconnects, such as patterned trenches and vias, the metal deposited in the non-recessed regions of the semiconductor wafer is removed and the metal is conventionally removed from the non-recessed regions of the dielectric layer deposited on the semiconductor wafer. The method of the membrane includes, for example, chemical mechanical honing (CMP). The CMP method is widely used in the semiconductor industry to honing and planarizing the metal layers in the trenches and vias of the non-200845162(2) recessed regions in the dielectric layer to form interconnects. In a CMP process, a wafer assembly is positioned on a CMP pad on a platform or mesh. The wafer assembly includes a substrate having one or more layers and/or features, such as interconnect components formed in the dielectric layer. A force is then applied to force the wafer assembly against the CMP pad. The CMP pad and substrate components are moved closer to each other while force is applied to honing and planarizing the surface of the wafer. Then, a honing solution called mash is sprinkled on the CMP pad to promote the honing. The slurry typically contains an abrasive and can be chemically reacted to selectively remove unwanted materials, such as metal layers, from the wafer, which is faster than other materials such as dielectric materials. However, because of the relatively strong mechanical forces involved, the CMP process may have several deleterious effects on the underlying semiconductor structure. For example, when the interconnect geometry is moved to 〇 1 3 μm and lower, there may be a large difference between, for example, the conductive material of copper and the mechanical properties of the low-k film used in a typical embedding process. For example, the Young's modulus of a low-k dielectric film may be lower than the Young's Φ coefficient of copper by more than 10 orders of magnitude. Therefore, in the CMP process, a relatively strong mechanical force applied to a dielectric film and a material such as copper may cause stress-related defects in the semiconductor structure, including peeling, dishing, corrosion, film lift, scratching, and the like. Wait. Therefore, there is a desire for new process technology. For example, a metal layer may be removed or etched from a wafer using an electropolishing process. Usually, in the electropolishing process, a portion of the wafer to be honed is immersed in an electrolytic solution, and then a charge is applied to the wafer. These conditions cause the copper to be removed or removed from the wafer. -5- 200845162 (3) For example, barrier layers of giant, nitrided, titanium, and titanium nitride cannot be electropolished by an electrolyte mainly composed of phosphoric acid and sulfuric acid. Therefore, the barrier layer is typically removed by plasma etching or chemical mechanical honing (CMP). However, the plasma is etched into other process steps, and the CMP damages the low-k dielectric under the barrier layer. SUMMARY OF THE INVENTION In an exemplary embodiment, a first dielectric layer is formed on a semiconductor wafer. The first dielectric layer is resistant to etching of hydrofluoric acid. A second dielectric layer is formed on the first dielectric layer on the semiconductor wafer. The second dielectric layer is susceptible to etching by hydrofluoric acid. The second dielectric layer is formed with recessed regions and non-recessed regions. The recessed region is extended within the first dielectric layer. A barrier layer is formed to cover the recessed region and the non-recessed region. The metal layer is formed to penetrate the recessed region and cover the non-recessed region. The metal layer and the barrier layer are electrically polished to expose the non-recessed region using an electrolyte containing hydrofluoric acid. [Embodiment] In an exemplary embodiment, the first to the 1C drawings depict details of an electropolishing process using a nozzle. In order to completely remove the barrier layer 11 1 2, the process is preferably performed from the center of the wafer 1 1 1 4 to the edge of the wafer 1 114 by the amount of overbursing shown in Figs. 1 to 1 C. In this manner, the electropolishing current 1 1 16 will readily flow through the barrier layer 1 112 and to the adjacent Cu film 1 1 10 and then to the edge of the wafer as shown in Figure 1C. When the barrier layer surrounding the copper trench 1120 is removed by the electropolishing process, the copper and barrier metal in the structure 1 1 20 loses electrical path. Therefore, the electropolishing process on the structure 1 120 of 200845162 (4) is automatically stopped, as shown in Fig. 1C. At the same time, the electrolyte system for removing the barrier layer and copper is listed as follows: Hydrofluoric acid (HF) (49% wt): 10 ml, ranging from 4 to 40 nm; Phosphoric acid H304 (8 5% wt): 20 〇1111, ranging from 〇 to 30〇1111; sulphuric acid H3S04 (9 8%wt): 60 ml, ranging from 〇 to 80 ml; ethylene glycol: 100 ml, ranging from 0 to 200 ml; and glycerol: 50 ml , ranging from 0 to 100 ml. φ In the above electrolyte, hydrofluoric acid (HF) is used to remove metal oxides formed during the above electropolishing process, such as oxidized giant and titanium oxide. It should be noted that the HF acid may be combined with other salts such as A1C13, ZnCl2, MgCl2, Cr03, (NH4)HP04, (NH4)2S04, NH4F, NH4N03, and acids such as HN〇3, HC1, HCl〇4, And a surfactant such as benzotriazole (C6H5N3). Hydrofluoric acid strongly attacks the dielectric dominated by oxidized sand or oxidized sand. Therefore, it is preferred to use an anti-HF dielectric material 1 1 1 4 such as polyimine, φ fluorinated polyimine, poly phthalimide, poly(p-phenylene N), poly(aryl ether). ), poly (aromatic), polynaphthalene, aromatic hydrocarbon (SiLK), amorphous carbon film, Teflon-AF, Teflon microemulsion, and the like. If a ruthenium-based dielectric is used, these ruthenium oxide-based dielectrics are preferably covered by another layer of dielectric layer that has high resistance or prevents the formation of mixed structures of HF (see reference 3 A). To 3 I picture). Another illustrative embodiment removes the barrier layer as shown in Figures 2A-21. The series of process steps are as follows: Step 1: Depositing a first dielectric layer 2006 on the current dielectric layer 20 12 formed in the previous metal layer 200845162 (5), as shown in FIG. 2A. This current dielectric layer 2012 is made of tantalum carbide (SiC), tantalum carbonitride (SiCN), or other dielectric materials that have high resistance to HF or HF blocking. The deposition method may be chemical vapor deposition (CVD) or spin coating dielectric. The dielectric layer 200 6 comprises a polyimine, a fluorinated polyimine, a polyamidene, a poly(p-phenylene N), a poly(aryl ether), a poly(aromatic), a polynaphthalene , aromatic hydrocarbon (SiLK), amorphous carbon film, Teflon-AF, Teflon micro φ emulsion or other low-k dielectric with high resistance and blocking HF. Step 2: Depositing a second dielectric layer 2001 on the first dielectric layer 2006, as shown in FIG. 2A. The second dielectric layer 2001 may be a ruthenium oxide, a ruthenium oxide-based dielectric, a fluorinated vermiculite, a carbon-doped vermiculite, and a non-porous vermiculite. The second dielectric can be any dielectric material that is susceptible to damage by HF. Step 3: Plasma etch the vias 20 10 and trenches 2009 as shown in Figure 2B. #Step 4: Deposit barrier layer 2004 and copper seed layer 2003, as shown in Figure 2C. Generally, the barrier layer 2004 is composed of molybdenum, arsenic, titanium, titanium nitride, tungsten, tungsten nitride, tantalum, tantalum nitride, chromium, niobium, molybdenum, niobium, tantalum, palladium, niobium, tantalum, iron, and Make it. Step 5: Electroplating the copper layer 2002 to fill the vias and trenches as shown in Fig. 2D. The plated copper layer can be further planarized by chemical mechanical honing (CMP), as disclosed in PCT Patent Application No. PCT/US02/26, 167, and U.S. Patent Application Serial No. 10/486,982, the disclosure of which is incorporated herein by reference. And can be formed by using the virtual structure disclosed in PCT Patent Application No. PCT/US03/11417 and U.S. Patent No. 200845162 (6), the application of which is incorporated herein by reference. The contact pad nozzle disclosed in the application 60/73 8, 25 0 is electropolished, and this case is also incorporated by reference. Step 6: The copper layer is removed using the electropolishing process described with reference to Figures 1A through 1C and the apparatus described with reference to Figures 8A through 8F. Fig. 2E is a cross-sectional view showing the copper interconnect structure of the copper layer 2002 removed from the barrier layer 2005 by using an electropolishing process. When the electropolishing process continues for φ, the copper film in the trench will begin to sink and the barrier layer will be removed, as shown in Figure 2F. Since the barrier layer is removed, the electropolishing current stops because there is no conduction path. Therefore, the copper in the trench between the copper trench and the dielectric layer and the copper in the barrier layer will be separated from the electropolishing process, or the polishing process will be self-terminating. On the other hand, the barrier residue 201 5 will remain on the surface of the second dielectric layer 200 1 as shown in Fig. 2F. Therefore, it is recommended to use a constant voltage to perform the above electropolishing process. As described above, the second dielectric layer 20 〇 1 is made of yttrium oxide, yttrium oxide-based dielectric, fluoridated political stone, carbon-doped sandstone, and non-porous sandstone, which is easily HF. Etched. Therefore, the second dielectric layer is etched away by HF in the electrolyte as shown in Fig. 2G. When the engraving process continues, the last barrier residue 2015 will be removed by undercut etching of the underlying dielectric 2021, as shown in Figures 2G and 2H. Step 7: Deposition of SiC or SiCN layer 2008 on copper 2002 and dielectric layer 2006, as shown in Figure 21. Step 8: Repeat steps 1 through 7 to form another layer of interconnect layers, as shown in Figure 2J. -9 - 200845162 (7) Another exemplary embodiment is to remove the barrier layer as shown in Figures 3A to 3I. The process steps are listed below: Step 1: Deposit a first dielectric layer 3052, and deposit a second dielectric layer (uranium stop layer) 3 050, as shown in Figure 3A. The deposition method may be a chemical vapor deposition (CVD) or a spin-on dielectric method. The first dielectric layer 3 05 2 comprises cerium oxide, cerium fluoride glass 03 〇), 1133 (5, diamond-like carbon, carbon-doped "〇2, MSSQ, and non-porous vermiculite. The second dielectric layer 3050 is mainly The second dielectric layer 3 050 has a second function of blocking HF or fluorine atoms/ions from diffusing into the third dielectric layer 300 6 (as described below) for stopping the etching process between the via holes and the trenches. ), while in the laser electropolishing process, reaching the first dielectric layer 3 0 5 2 , which will be described in detail with reference to Figure 3 G. Obviously, if HF or fluoride ions penetrate the second dielectric layer 3050, then It will destroy the first dielectric layer 3052. The second dielectric layer 3 050 comprises tantalum carbide (SiC), tantalum carbonitride (SiCN), or other dielectric material having high resistance and HF blocking ability. In other words, Neither HF nor fluorine atoms/ions should penetrate the selected second dielectric. φ Step 2: Deposit a third dielectric layer 3006 on the second dielectric layer 3〇5〇 as shown in Figure 3A. The deposition method may be a chemical vapor deposition (CVD) method or a spin-on dielectric method. The third dielectric layer 3006 comprises a polyimide, a fluorinated polyimide, a polyimide, and a polyimide. , poly(p-phenylene N), poly(aryl ether), poly(aromatic), polynaphthalene, aromatic hydrocarbon (SiLK), amorphous carbon film, Teflon-AF, Teflon microemulsion or other low k dielectric, or ultra low k dielectric with high resistance to hf. Step 3: deposit a fourth dielectric layer (or sacrificial layer) 3 00 1 on the third dielectric layer 3 006, as shown in Figure 3A The fourth dielectric layer 3 00 1 may be oxidized-10-200845162 (8) yttrium, yttrium oxide-based dielectric, fluorinated vermiculite, carbon-doped vermiculite, and non-porous meteorite. The electrical layer 300 1 should be selected to be etched by the HF acid. Step 4: Deposit an additional mask layer to create a two-layer embedded structure. The details of the lithography step are known in the art and, therefore, will not be described. Step 5: etch the via holes 3010 and the trenches 3 009 by plasma, and strip the photoresist as shown in Fig. 3B. Step 6: deposit the barrier layer 3004 and the copper seed layer 3003 as shown in Fig. 3C. The barrier layer 3004 is composed of a single metal layer such as giant, nitrided, titanium, titanium nitride, tungsten, tungsten nitride, tantalum, chromium, niobium, molybdenum, niobium, tantalum, palladium, niobium, tantalum, niobium and tantalum. Or a combination of metal layers. Step 7: Electroplating a copper layer 3 002 to penetrate the vias and trenches as shown in Figure 3D. The electroplated copper can be further processed by, for example, PCT Patent Application No. PCT/US 02/26 1 67 and U.S. Patent Application Serial No. The chemical mechanical honing (CMP) disclosed in the '486, 982 is planarized, and such cases are incorporated by reference; or by the use of, for example, PCT Patent Application No. PCT/US03/11417 and U.S. Patent Application Serial No. U.S. Patent Application Serial No. 5,0,656, the disclosure of which is incorporated herein by reference. Electropolishing was used to planarize, and the case is also incorporated into the present application. Step 8: The copper layer is removed using the electropolishing process described with reference to Figures 1A through 1C and the apparatus described with reference to Figures 8A through 8F. Fig. 3E is a cross-sectional view showing the copper interconnect structure of the copper layer 3 002 being removed from the barrier layer 3005 by using an electropolishing process. When the electropolishing process continues, the copper film in the trench will begin to sag and the barrier layer will be removed by -11 - 200845162 (9), as shown in Figure 3F. Since the barrier layer is removed, the electropolishing current will be stopped due to the absence of a conduction path. Therefore, the barrier layer between the copper and copper trenches and the dielectric in the trench will be separated from the electropolishing process, or the honing process will be automatically terminated. On the other hand, for the same reason, the barrier layer residue 3015 will remain on the surface of the dielectric layer 3001 as shown in Fig. 3F. Therefore, it is recommended to use a constant voltage to perform the above electropolishing process. As described above, the fourth dielectric layer 3001 is made of yttrium oxide, yttrium oxide-based dielectric φ, fluorite vermiculite, carbon-doped vermiculite, and non-porous vermiculite. These are easily HF acids. Etched. Therefore, the fourth dielectric layer is etched away by the HF acid in the electrolyte as shown in Fig. 3G. When the etching process continues, finally, the barrier layer residue 3 0 15 will be removed due to the undercut uranium under the dielectric layer 301, as shown in Figures 3G and 3. After electropolishing, the wafer is transferred to a clean room to remove all chemicals. In addition, the HF-based chemical can be further sprayed onto the surface of the wafer to etch away the barrier layer remaining when the portion of the barrier layer remains in the electropolishing chamber. For example, for a 5% by weight HF concentration, the molybdenum has an etch rate of about 1.5 nm/min. The HF concentration is in the range of 1% wt to 10% wt. Lemon acid (C6H8〇7) 〇.5%wt can also be added to the cleaning procedure to remove copper oxide. The citric acid concentration ranges from 0.1% by weight to 1% by weight. The wafer is then further cleaned with pure DI water. Step 9: Deposit SiC or SiCN layer 3008 on copper 3 002 and dielectric layer 3 006 as shown in FIG. Step 10: Steps 1 through 9 are repeated to form an inner wiring layer (not shown) of the other layer. -12- 200845162 (10) Another exemplary embodiment removes the barrier layer as shown in Figures 4A through 41. The process steps are as follows: Step 1: Deposit a first dielectric layer 405 1 , deposit a second dielectric layer (etch stop layer) 4050, and deposit a third dielectric layer 4006 as shown in FIG. 4A. The deposition method may be chemical vapor deposition (C V D) or spin-on dielectric method. The first and third dielectric layers comprise polyimide, fluorinated polyimine, polyamidene fluorene, polyparaphenylene N, poly(aryl ether), poly(aromatic), poly Naphthalene φ, aromatic hydrocarbon (SiLK), amorphous carbon film, Teflon-AF, Teflon microemulsion or other low-k dielectric, or ultra-low-k dielectric with high resistance to HF. The second dielectric layer 405 is mainly used to clean the etch stop layer between the via and the trench during plasma etching. The second function of the second dielectric layer is to block HF or fluorine atoms/ions from diffusing through the third dielectric layer 4006 during the electropolishing process, as will be detailed with reference to Figure 4G. The second dielectric material 4050 comprises tantalum carbide (SiC), tantalum carbonitride (SiCN), or other dielectric material having high resistance or HF blocking properties. In other words, neither HF nor fluorine atoms/ions # should penetrate the selected second dielectric layer. Step 2: depositing a fourth dielectric layer 400 1 on the third dielectric layer 4006, as shown in FIG. 4A. The fourth dielectric layer 400 1 may be a ruthenium oxide, a ruthenium oxide-based dielectric, a fluorine-doped vermiculite, a carbon-doped vermiculite, and a non-porous vermiculite. The fourth dielectric layer 400 1 should be selected to be easily etched by the HF acid. Step 3: Deposit other mask layers to create a two-layer embedded structure. The details of the lithography step are known to the art and will not be described.
步驟4 :藉由電漿蝕刻導孔4 0 1 0及溝渠4 0 0 9，如第4 B 圖所示。 -13 - 200845162 (11) 步驟5 :沈積阻障層4004及銅種層4003，如第4C圖所 示。通常，阻障層4004係由鉅、氮化鉅、鈦、氮化鈦、鎢 、氮化鎢、釕、鉻、銀、銦、褡、錢、勸、給、銶、餓、 及銥所作成。 步驟6 :鍍銅層4002，以塡入導孔及溝渠，如第4D圖 所示。所鍍的銅層可以進一步以如 PCT專利申請 PCT/U S0 2/2 6 1 67及美國專利申請1 0/486,9 82所揭示之化學 φ 機械硏磨（CMP)加以平坦化，該兩案係倂入作爲參考；或 者，也可以藉由使用如PCT專利申請PCT/US03/11417及 美國專利申請1 0/5 10,656案所揭示之使用虛擬結構之平面 電鍍加以形成，該等案係倂入作爲參考；或者，也可以使 用美國臨時申請案60/73 8，250所揭示之以接觸墊噴嘴進行 電抛光加以平坦化，該案也倂入本案作爲參考。 步驟7:使用參考第1A至1C圖所述之電抛光製程及 予以參考第8A至8F圖所述之設備，加以移除銅層。 Φ 第4E圖顯示銅層4002之銅內連線結構被藉由使用電 抛光製程，自阻障層4005上移除的剖面圖。當電抛光製程 持續時，在溝渠中之銅膜將開始下凹，及阻障層將被移除 ，如第4F圖所示。因爲阻障層被移除，所以電抛光電流 將由於沒有導通路徑被停止。因此，在溝渠內之銅及銅溝 渠與介電質間之阻障層將與電抛光製程隔開，或者，硏磨 製程將自動終止。另一方面，阻障層殘留40 15將保留在介 電層4001之表面上，如第3F圖所示。因此’推薦使用定 電壓以執行上述電抛光製程。 -14- 200845162 (12) 如前所述，第四介電層400 1係由氧化矽、氧化矽爲主 介電質、氟化矽石、摻碳矽石、及無孔矽石所作成’這些 係容易爲HF酸所蝕刻。因此，第四介電層係爲電解液中 之HF酸所蝕去，如第4G圖所示。當蝕刻製程持續時，最 後，阻障層殘留401 5將由於在下之介電層402 1之底切蝕刻 而被移除，如第4G及4H圖所示。 在電抛光後，晶圓被傳送至一潔淨室，用以移除所有 φ 化學品。另外之HF爲主之化學品可以進一步被噴在晶圓 表面上，以蝕去當部份阻障層殘留在電抛光室中未全然移 除的阻障層殘留。例如，對於5%(重量）HF濃度，鉬的鈾 刻率約1.5nm/分。HF濃度係在範圍l%wt至10%wt。檸檬 酸（C6H8O7)0.5%wt也可以加入清潔程序中，以移除氧化 銅。檸檬酸濃度範圍由0.1%wt至l%wt。然後，晶圓被進 一步爲純DI水所清洗。 步驟8:沈積SiC或Si CN層4008在銅4002及介電層 _ 4006上，如第31圖所示。 步驟9 :重置步驟1至8，以形成另一內連線層（未示出 )° 另一用以移除阻障層之例示實施例係如第5A至5J圖 所示。製程步驟係如下列： 步驟1 :沈積第一介電層5 0 0 6在事先形成在金屬層中 之現行介電層5012上，及沈積第二介電層5007係如第5A 圖所示。現行介電層5012係由碳化矽（SiC)、碳氮化砂 (SiCN)、或其他具有高抵抗或阻擋功能的介電材料。沈積 -15- 200845162 (13) 方法可以爲化學氣相沈積（CVD)、或旋塗介電質法。第〜 介電層5006包含聚醯亞胺、氟化聚驢亞胺、聚醯亞胺奈米 泡沬、聚對二甲苯基N、聚（方醚）、聚（芳族）、聚萘類系 、芳香烴（SiLK)、非晶碳膜、鐵氟龍-AF、鐵氟龍微乳化 液、氧化矽、摻氟氧化矽、有機矽酸鹽材料，例如Step 4: etch the via 4 0 1 0 and the trench 4 0 0 by plasma, as shown in Fig. 4B. -13 - 200845162 (11) Step 5: Deposit barrier layer 4004 and copper seed layer 4003 as shown in Figure 4C. Generally, the barrier layer 4004 is made of giant, nitrided, titanium, titanium nitride, tungsten, tungsten nitride, tantalum, chromium, silver, indium, antimony, money, persuasion, giving, sputum, hungry, and sputum. . Step 6: A copper plating layer 4002 is inserted into the via holes and the trenches as shown in Fig. 4D. The plated copper layer can be further planarized by chemical φ mechanical honing (CMP) as disclosed in PCT Patent Application No. PCT/U S0 2/2 6 1 67 and U.S. Patent Application Serial No. 10/486,9,82 The case is incorporated by reference; or it can be formed by using planar plating using a virtual structure as disclosed in PCT Patent Application No. PCT/US03/11417 and U.S. Patent Application Serial No. 1 0/5 10,656. Alternatively, it can be planarized by electro-polishing with a contact pad nozzle as disclosed in U.S. Provisional Application Serial No. 60/73,250, which is incorporated herein by reference. Step 7: The copper layer is removed using the electropolishing process described with reference to Figures 1A through 1C and the apparatus described with reference to Figures 8A through 8F. Φ Figure 4E shows a cross-sectional view of the copper interconnect structure of the copper layer 4002 removed from the barrier layer 4005 by using an electropolishing process. As the electropolishing process continues, the copper film in the trench will begin to sag and the barrier layer will be removed, as shown in Figure 4F. Since the barrier layer is removed, the electropolishing current will be stopped because there is no conduction path. Therefore, the barrier layer between the copper and copper trenches and the dielectric in the trench will be separated from the electropolishing process, or the honing process will be automatically terminated. On the other hand, the barrier layer residue 40 15 will remain on the surface of the dielectric layer 4001 as shown in Fig. 3F. Therefore, it is recommended to use a constant voltage to perform the above electropolishing process. -14- 200845162 (12) As mentioned above, the fourth dielectric layer 400 1 is made of yttrium oxide, yttrium oxide as the main dielectric, fluorite vermiculite, carbon-doped vermiculite, and non-porous vermiculite. These lines are easily etched by HF acid. Therefore, the fourth dielectric layer is etched away by the HF acid in the electrolyte as shown in Fig. 4G. When the etching process continues, finally, the barrier layer residue 401 5 will be removed by undercut etching of the underlying dielectric layer 402 1 as shown in Figures 4G and 4H. After electropolishing, the wafer is transferred to a clean room to remove all φ chemicals. In addition, the HF-based chemical can be further sprayed on the surface of the wafer to etch away the barrier layer remaining when the portion of the barrier layer remains in the electropolishing chamber. For example, for a 5% by weight HF concentration, the uranium engraving rate of molybdenum is about 1.5 nm/min. The HF concentration is in the range of 1% wt to 10% wt. Lemon acid (C6H8O7) 0.5% wt can also be added to the cleaning procedure to remove copper oxide. The citric acid concentration ranges from 0.1% by weight to 1% by weight. The wafer is then further cleaned with pure DI water. Step 8: Deposit SiC or Si CN layer 4008 on copper 4002 and dielectric layer _ 4006 as shown in FIG. Step 9: Steps 1 through 8 are reset to form another interconnect layer (not shown). Another exemplary embodiment for removing the barrier layer is shown in Figures 5A through 5J. The process steps are as follows: Step 1: Depositing a first dielectric layer 506 on the current dielectric layer 5012 previously formed in the metal layer, and depositing the second dielectric layer 5007 as shown in FIG. 5A. The current dielectric layer 5012 is made of tantalum carbide (SiC), carbonitrided sand (SiCN), or other dielectric material having high resistance or barrier function. Deposition -15- 200845162 (13) The method can be chemical vapor deposition (CVD), or spin-on dielectric method. The first dielectric layer 5006 comprises polyimine, fluorinated polyimine, polyamidene fluorene, polyparaphenylene N, poly(butyl ether), poly(aromatic), polynaphthalene System, aromatic hydrocarbon (SiLK), amorphous carbon film, Teflon-AF, Teflon microemulsion, cerium oxide, fluorine-doped cerium oxide, organic silicate material, for example
Aurora、黑鑽石、及Coral、旋塗MSQ/HSQ、或其他低1^ 介電質、或超低k介電質。第二介電層5007主要用以防止 Φ 電解液攻擊第一層介電層5006。第二介電材料5〇〇7包含碳 化矽（SiC)、碳氮化矽（SiCN)、氧化鋁（Al2〇3)、或其他具 有高抵抗及阻擋HF酸效能的介電材料。換句話說，jjf 或氟原子/離子不應穿過被選擇之第二介電質。 步驟2:沈積具有厚度Η的第三介電層5〇〇1在第二介 電層2007上，如第5Α圖所示。第三介電層5001可以爲氧 化矽、氧化矽爲主之介電質、氟化矽石、摻碳矽石、及無 孔矽石。第三介電層5 00 1應被選擇容易受到HF所蝕刻者 步驟3 :旋塗光阻，及微影步驟的細節係爲本技藝所 知，並不再說明。 步驟4:以電漿蝕刻導孔5010及溝渠5009，如第5Β圖 所示。 步驟5:沈積阻障層5004及銅種層5003，如第5C圖所 示。通常，阻障層5004係由鉅、氮化鉅、鈦、氮化鈦、鎢 、氮化鎢、釕、鉻、鈮、鉬、鐯、鍺、鈀、給、銶、鐵及 銥作成。 -16- 200845162 (14) 步驟6 :電鍍銅層5 002，以塡充導孔及溝渠，如第5D 圖所示。被鍍之銅層可以進一步以化學機械硏磨（CMP)加 以平坦化，如PCT專利申請PCT/US02/26 1 67及美國專利 申請1 0/486,982號案所揭示，這些案係倂入作爲參考；或 可以藉由使用PCT專利申請PCT/US03/11417及美國專利 申請1 0/5 1 0,6 5 6所揭示之使用虛擬結構之平面電鍍加以形 成，這些案係倂入作爲參考；或者，可以被美國臨時申請 φ 案60/73 8,25 0所揭示之接觸墊噴嘴加以電抛光，這案也倂 入作爲參考。 步驟7:使用參考第1A至1C圖所述之電抛光製程及 參考第8A至8F圖所述之設備移除銅層。 第5E圖顯示藉由使用電抛光製程，從阻障層5 00 5移 除銅層5002的銅內連線結構的剖面圖。當電抛光製程持續 時，溝渠中之銅膜將開始下陷，及阻障層將被移除，如第 5F圖所示。因爲阻障層被移除，所以電抛光電流由於沒 ® 有電流導通路徑而停止。因此，在溝渠5002內之銅及銅溝 渠與介電層間之阻障層將隔開電抛光製程，或抛光製程將 自終止。另一方面，阻障殘留5015將保留在第三介電層 5001之表面上，如第5F圖所示。因此，建議使用定電壓 以執行上述電抛光製程。 如上所述，第三介電層5 0 0 1係由氧化矽、氧化矽爲主 之介電質、氟化矽石、摻碳矽石、及無孔矽石作成’這係 容易爲HF所餓刻。因此，第四介電層係爲在電解液中之 HF所蝕去，如第5 G圖所示。當鈾刻製程持續時，最後阻 -17- 200845162 (15) 障殘留5 0 1 5將由於下方之介電質5 02 1的底切鈾刻而移除， 如第5G及5H圖所示。第二介電層500 7係由碳化矽（Si C)、 碳氮化矽（SiCN)、氧化鋁（A1203)或其他具有高抵抗及阻擋 HF酸的介電材料。因此，在第二介電層下之第一介電層 5 00 6係被保護不受電解液所攻撃。取決於半導體製造節點 ，第二介電層的厚度係由範圍5 nm至100 nm。 重要的是取得如第5H圖所示之平面，以給予以下微 φ 影製程較佳的效能。因此，如第5 F圖所示之銅溝渠凹陷 應被控制以等於第三介電層5001的厚度Η。銅凹陷D可以 爲阻障層對銅金屬的移除率加以控制。更明確地說，在電 解液中之HF濃度決定阻障層對銅金屬層之移除率比値。 例如，以5%wt之HF濃度，阻障層（Ta及/或TaN)對銅金 屬層之移除比率幾乎成比例於HF濃度。因此，製程應執 行如下： a.根據每一製造節點之阻障層厚度，決定HF濃度， Φ 以完成最小之銅凹陷及同時，所有之銅殘留在阻障層被移 除前被移除。最小銅凹陷可以範圍由阻障層5004的厚度的 2至1〇倍；及 b ·根據銅溝渠的量測最小凹陷，則第三介電層之厚度 設計等於銅溝渠凹陷的最小量。 例如，對於65 nm製造節點，阻障層的厚度爲7 nm。 如果5%wt之HF濃度用於磷/硫酸/乙二醇/甘油爲主之電 解液，則銅凹陷將約30 nm。因此，第三介電層500 1的厚 度應設計約3〇 nm。 -18- 200845162 (16) 例如：對於65 nm製造節點，阻障層厚度爲7 nm。如 果2.5%wt之HF濃度被用於磷/硫酸乙二醇/甘油爲主電解 液中，則銅凹陷將約60 nm。因此，第三介電層500 1的厚 度應設計約60 nm。 在電拋光後，晶圓將被傳送至一潔淨室’用以移除所 有化學品。另外之HF爲主之化學品可以進一步被噴在晶 圓表面上，以蝕去當部份阻障層殘留在電抛光室中未全然 φ 移除的阻障層殘留。例如，對於5%(重量）HF濃度，鉅的 蝕刻率約1.5nm/分。HF濃度係在範圍l%wt至10%wt。檸 檬酸（C6H8O7)0.5%wt也可以加入清潔程序中，以移除氧 化銅。檸檬酸濃度範圍由〇.l%wt至l%wt。然後，晶圓被 進一步爲純DI水所清洗。 步驟8:沈積SiC或SiCN層5008在銅5 002及第二介 電層5007上，如第51圖所示。 步驟9:重覆步驟1至步驟8，以形成另一層之內連線 _ 層如第5 J圖所示。 另一例示實施例移除阻障層，如第6A至61圖所示。 該製程步驟係如下列： 步驟1 :沈積第一介電層6052、沈積第二介電層6006 、及沈積第三介電層6007，如第6A圖所示。沈積方法可 以爲化學氣相沈積（CVD)或旋塗介電質法。第一介電層 6052及第二介電層6006包含聚醯亞胺、氟化聚醯亞胺、聚 醯亞胺奈米泡沬、聚對二甲苯基N、聚（芳醚）、聚（芳族） 、聚萘類、芳香烴（SiLK)、非晶碳膜、鐵氟龍-AF、鐵氟 200845162 (17) 龍微乳化液、氧化矽、摻氟氧化矽、有機矽酸鹽類，例如 Aurora、黑鑽石、及Coral、旋塗MSQ/HSQ、或其他低k 介電質、或超低k介電質。該第三介電層60 0 7主要用以防 止電解液攻擊第二介電層6006。第三介電材料6007包含碳 化矽（SiC)、碳氮化砍（SiCN)、氧化銘（Al2〇3)、或其他具 有高抵抗及阻擋HF酸功能的介電材料。換句話說，HF 或氟原子/離子都不應穿透被選擇之第二介電層。 φ 步驟2:沈積具有厚度Η的第四介電層6001在第三介 電層6007上，如第6Α圖所示。第四介電層6 001可以爲氧 化矽、氧化矽爲主之介電質、氟化矽石、摻碳矽石、及無 孔矽石。第四介電層600 1應被選擇以容易爲HF酸所蝕刻 者。 步驟3:旋塗光阻，及微影步驟的細節係爲本技藝所 知，並不再說明。 步驟4 :以電漿飩刻導孔60 10及溝渠6009，如第6Β圖 所示。 步驟5 :沈積阻障層6004及銅種層6003，如第6C圖所 示。通常，阻障層6004係由鉬、氮化鉬、鈦、氮化鈦、鎢 、氮化鎢、釕、鉻、鈮、鉬、褡、鍺、鈀、鈴、銶、餓、 及銥所作成。 步驟6 :鍍銅層6002，以塡入導孔及溝渠，如第6D圖 所示。所鍍的銅層可以進一步以如 PCT專利申請 PCT/US02/26 1 67及美國專利申請1 0/486，982所揭示之化學 機械硏磨（CMP)加以平坦化，該兩案係倂入作爲參考；或 -20- (18) (18)200845162 者，也可以藉由使用如PCT專利申請PCT/US03/11417及 美國專利申請1 0/510,656案所揭示之使用虛擬結構之平面 電鍍加以形成，該等案係倂入作爲參考；或者，也可以使 用美國臨時申請案60/73 8，25 0所揭示之以接觸墊噴嘴進行 電抛光加以平坦化，該案也倂入本案作爲參考。 步驟7 :使用參考第1 A至1 C圖所述之電拋光製程及 予以參考第8 A至8F圖所述之設備，加以移除銅層。 第6E圖顯示作爲銅層6002之銅內連線結構被藉由使 用電抛光製程，自阻障層6004上移除的剖面圖。當電抛光 製程持續時，在溝渠中之銅膜將開始下凹，及阻障層將被 移除，如第6F圖所示。因爲阻障層被移除，所以電抛光 電流將由於沒有導通路徑被停止。因此，在溝渠內之銅及 銅溝渠與介電質間之阻障層將與電抛光製程隔開，或者， 硏磨製程將自動終止。另一方面，阻障層殘留6 0 1 5將保留 在介電層60 0 1之表面上，如第6F圖所示。因此，推薦使 用定電壓以執行上述電抛光製程。 如前所述，第四介電層6001係由氧化矽、氧化矽爲主 之介電質、氟化砂石、摻碳砍石、及無孔砂石所作成，這 些係可以爲HF酸所触刻。因此，第四介電層係爲電解液 中之HF酸所蝕去，如第6 G圖所示。當飩刻製程持續時， 最後，阻障層殘留6015將由於在下之介電層6 021之底切飩 刻而被移除，如第6G及6H圖所示。第三介電層607係由 碳化砂（SiC)、碳氮化砍（SiCN)、氧化銘（a12〇3)、或其他 具有高抵抗及阻擋HF功能的介電材料。因此，在第三介 -21 - 200845162 (19) 電層6007下之第二介電層6006係被保護不受電解液，主要 是HF所攻擊。第三介電層6007係在範圍5 nm至1〇〇 nm， 取決於半導體製造節點。 重要的是取得如第6H圖所示之平面，以對以下微影 製程給予較佳效能。因此，如第6F圖所示之銅溝渠凹陷 D應被控制以等於第四介電層600 1的厚度Η。銅凹陷D可 以藉由阻障層至銅金屬的移除率比加以控制。更明確地說 φ ，在電解液中之HF濃度決定阻障層對金屬層之移除率比 。例如，在5%wt之HF濃度內，阻障層（Ta及/或TaN)對 銅金屬層之移除率比幾乎成比例於HF濃度。因此，製程 應被執行如下： a.根據每一製造節點之阻障層厚度，決定HF濃度， 以確保最小之銅凹陷及同時，所有之銅殘留在阻障層被移 除前被移除。最小銅凹陷可以範圍由阻障層6004的厚度的 2至10倍；及 Φ b.根據銅溝渠的量測最小凹陷，則第四介電層之厚度 設計等於銅溝渠凹陷的最小量。 例如，對於65 nm製造節點，阻障層的厚度爲7 nm。 如果5%wt之HF濃度用於磷/硫酸/乙二醇/甘油爲主之電 解液，則銅凹陷將約30 nm。因此，第四介電層600 1的厚 度應設計約30 nm。 例如：對於6 5 nm製造節點，阻障層厚度爲7 nm。如 果2.5%wt之HF濃度被用於磷/硫酸乙二醇/甘油爲主電解 液中，則銅凹陷將約60 nm。因此，第四介電層600 1的厚 -22- (20) 200845162 度應設計約60 nm。 HF的濃度愈高將減少銅凹陷。然而，愈高之HF濃 度將在電抛光製程中，在銅線6002側，造成凹穴或微溝渠 6100，如第61圖所示。以相同方式，在銅線側壁之阻障 層可以藉由使用高HF濃度快速移除，如第61圖。因此， 終點作用及角落損失或凹穴應藉由調整HF濃度加以平衡 。H F濃度範圍在0.5 % w t至5 % w t範圍內。 • 在電拋光後，晶圓將被傳送至一潔淨室，用以移除所 有化學品。另外之HF爲主之化學品可以進一步被噴在晶 圓表面上，以蝕去當部份阻障層殘留在電抛光室中未全然 移除的阻障層殘留。例如，對於5 %(重量）HF濃度，鉅的 蝕刻率約1.5nm/分。HF濃度係在範圍l%wt至10%wt。檸 檬酸（C6H807)(K5%wt也可以加入清潔程序中，以移除氧 化銅。檸檬酸濃度範圍由0.1 %wt至l%wt。然後，晶圓被 進一步爲純DI水所清洗。 # 步驟8 ··沈積SiC或SiCN層6008在銅6002及第二介 電層6007上，如第61圖所示。 步驟9 :重覆步驟1至步驟8，以形成另一層之內連線 層（未所出）。 另一移除阻障層之例示實施例係如第7A至71圖所示 。該製程步驟係如下列： 步驟1 :沈積第一介電層7052、沈積第二介電層7050 、沈積第三介電層7006、及沈積第四介電層7007係如第 7A圖所示。沈積方法可以爲化學氣相沈積（CVD)、或旋塗 -23- 200845162 (21) 介電質法。第一介電層7 052包含二氧化矽、氟矽玻璃 (FSG)、HSSQ、鑽石狀碳、摻碳si02、MSSQ、及無孔矽 石。第二介電層7050主要是在電漿鈾刻時作爲導孔與溝渠 間之鈾刻停止。第二介電層705 0的第二功能爲阻擋HF或 氟原子/離子在隨後電抛光製程中，擴散經第三介電層 70 06 (如下述）而到達第一介電層7 〇52，這將參考第7G圖 加以說明。明顯地，如果HF或氟離子穿透第二介電層 • 7050，則它們將摧毀第—介電層7052。第二介電層7050包 含碳化矽（SiC)、碳氮化矽（SiCN)、或其他具有高抵抗及 阻擋HF酸效能的介電材料。換句話說，HF或氟原子/離 子不應穿過被選擇之第二介電質。 第三介電層7006包含聚醯亞胺、氟化聚醯亞胺、聚醯 亞胺奈米泡沬、聚對二甲苯基N、聚（芳醚）、聚（芳族）、 聚萘類、芳香烴（SiLK)、非晶碳膜、鐵氟龍-AF、鐵氟龍 微乳化液、或其他低k介電質、或超低k介電質。第四介 馨 電層7〇〇7主要用以防止電解液攻擊第三介電層7006。第四 介電材料7007包含碳化矽（SiC)、碳氮化矽（SiCN)、氧化 鋁（Al2〇3)、或其他具有高抵抗及阻擋HF酸功能的介電材 料。換句話說，HF或氟原子/離子都不應穿透被選擇之第 四介電層。 步驟2:沈積具有厚度Η的第五介電層7001在第四介 電層7007上，如第7Α圖所示。第五介電層7001可以爲氧 化矽、氧化矽爲主之介電質、氟化矽石、摻碳矽石、及無 孔矽石。第五介電層700 1應被選擇容易受到HF所蝕刻者 24- (22) (22)200845162 步驟3 :旋塗光阻，及微影步驟的細節係爲本技藝所 知，並不再說明。 步驟4 :以電漿蝕刻導孔70 1〇及溝渠7009，如第7B圖 所示。 步驟5 :沈積阻障層7004及銅種層7003，如第7C圖所 示。通常，阻障層7004係由鉬、氮化鉅、鈦、氮化鈦、鎢 、氮化鎢、釕、鉻、鈮、鉬、鐯、铑、鈀、給、銶、餓及 銥作成。 步驟6 :電鍍銅層7002，以塡充導孔及溝渠，如第7D 圖所示。被鍍之銅層可以進一步以化學機械硏磨（CMP)加 以平坦化，如PCT專利申請PCT/US02/261 67及美國專利 申請1 0/486,982號案所揭示，這些案係倂入作爲參考；或 可以藉由使用P C T專利申請P C T/U S 0 3 / 1 1 4 1 7及美國專利 申請1 0/5 1 0,65 6所揭示之使用虛擬結構之平面電鍍加以形 成，這些案係倂入作爲參考；或者，可以被美國臨時申請 案60/73 8,250所揭示之接觸墊噴嘴加以電抛光，這案也倂 入作爲參考。 步驟7:使用參考第1A至1C圖所述之電抛光製程及 參考第8A至8F圖所述之設備移除銅層。 第7E圖顯示藉由使用電抛光製程，從阻障層7004移 除銅層7002的銅內連線結構的剖面圖。當電抛光製程持續 時，溝渠中之銅膜將開始下陷，及阻障層將被移除，如第 7F圖所示。因爲阻障層被移除，所以電抛光製程由於沒 -25- 200845162 (23) 有電流導通路徑而停止。因此，在溝渠7002內之銅及銅溝 渠7002與介電層間之阻障層將隔開電拋光製程，或抛光製 程將自終止。另一方面，阻障殘留701 5將保留在第四介電 層700 1之表面上，如第7F圖所示。因此，建議使用定電 壓以執行上述電抛光製程。 如上所述，第三介電層700 1係由氧化矽、氧化矽爲主 之介電質、氟化矽石、摻碳矽石、及無孔矽石作成，這係 φ 可以爲HF所蝕刻。因此，第五介電層係爲在電解液中之 HF所飩去，如第7G圖所示。當蝕刻製程持續時，最後阻 障殘留7015將由於下方之介電質7021的底切飩刻而移除， 如第7G及7H圖所示。第四介電層7007係由碳化矽（SiC)、 碳氮化矽（SiCN)、氧化鋁（Al2〇3)或其他具有高抵抗及阻擋 HF酸的介電材料。因此，在第四介電層7007下之第三介 電層70 0 6係被保護不受電解液，主要是HF所攻擊。取決 於半導體製造節點，第四介電層7007的厚度係由範圍5 nm 至 1 00 nm。 重要的是取得如第7H圖所示之平面，以給予以下微 影製程較佳的效能。因此，如第7F圖所示之銅溝渠凹陷 應被控制以等於第三介電層7001的厚度Η。銅凹陷D可以 爲阻障層對銅金屬的移除率比加以控制。更明確地說，在 電解液中之HF濃度決定阻障層對銅金屬層之移除率比値 。例如，以5%wt之HF濃度，阻障層（Ta及/或TaN)對銅 金屬層之移除率比幾乎成比例於HF濃度。因此，製程應 執行如下： -26- (24) (24)200845162 a·根據每一製造節點之阻障層厚度，決定HF濃度， 以確定最小之銅凹陷及同時，所有之銅殘留在阻障層被移 除前被移除。最小銅凹陷可以範圍由阻障層7004的厚度的 2至10倍；及 b·根據銅溝渠的量測最小凹陷，則第五介電層之厚度 設計等於銅溝渠凹陷的最小量。 例如，對於65 nm製造節點，阻障層的厚度爲7 nm。 如果5%wt之HF濃度用於磷/硫酸/乙二醇/甘油爲主之電 解液，則銅凹陷將約30 nm。因此，第五介電層7001的厚 度應設計約30 nm。 例如：對於65 nm製造節點，阻障層厚度爲7 nm。如 果2.5%wt之HF濃度被用於磷/硫酸乙二醇/甘油爲主電解 液中，則銅凹陷將約60 nm。因此，第三介電層7001的厚 度應設計約60 nm。 在電抛光後，晶圓將被傳送至一潔淨室，用以移除所 有化學品。另外之HF爲主之化學品可以進一步被噴在晶 圓表面上’以触去當部份阻障層殘留在電抛光室中未全然 移除的阻障層殘留。例如，對於5%(重量）HF濃度，鉅的 蝕刻率約1.5nm/分。HF濃度係在範圍l%wt至10%wt。檸 檬酸（C6H8〇7)0.5%wt也可以加入清潔程序中，以移除氧 化銅。檸橡酸濃度範圍由0.1 % w t至1 % w t。然後，晶圓被 進一步爲純DI水所清洗。 步驟8 :沈積SiC或SiCN層7008在銅7002及第四介 電層7007上，如第71圖所示。 -27- 200845162 (25) 步驟9:重覆步驟1至步驟8，以形成另一層之內連線 層（未示出）。 第8A至81圖顯示具有可動噴嘴及/或可動夾盤之晶圓 電抛光工具的例示實施例。在抛光時，因爲晶圓80 14被繞 著其中心軸旋轉，夾盤8020被橫向移動，使得電解液柱 8034可以被選擇地抛光金屬層8013的任一部份，如第8B 及8C圖所示。再者，不同於橫向移動夾盤8020，噴嘴 φ 8032也可以橫向移動如第8E及8F圖所示。橫向速度及抛 光電流係爲控制晶圓80 1 4表面之抛光率分佈的兩個主要參 數。通常，抛光率在某些電流區係成比例於抛光電流，並 反比例於夾盤8020與噴嘴8032之相對速度。 如第8A至8F圖所示，電抛光工具可以包含一電源 8030。如第8A圖所示，電抛光工具可以包含連接至夾盤 8020與噴嘴8032之控制系統8036。控制系統8036可以架構 以使用噴嘴施加電解液蒸汽至金屬層，以由晶圓的中心噴 # 至晶圓的邊緣，以電拋光金屬層及阻障層，以曝露非凹陷 區。應得知的是，於第8B至8F圖所繪之電抛光工具的各 種實施例也可以包含第8A圖所示之控制系統803 6。 雖然本發明已經以部份實施例、例子及應用加以描述 ，但可以爲熟習於本技藝者所了解，各種修改與變化可以 在不脫離本發明下加以完成。例如，HF酸也可以爲了相 同目的被組合其他鹽類及酸類，以形成電解液。 【圖式簡單說明】 -28- (26) 200845162 第1A-1C圖描繪例示電拋光製程的結果； 第2A至圖描繪另一例示電抛光製程的結果； 第3A至3J圖描繪另一例示電抛光製程的結果； 第4A至41圖描繪另一例示電抛光製程的結果； 第5A至5〗圖描繪另一例示電抛光製程的結果； 第6A至6J圖描繪另一例示電抛光製程的結果； 第7A至71圖描繪另一例示電抛光製程的結果； 第8A至8F圖爲例示電抛光工具的方塊圖。 【主要元件符號說明】 1 1 10 :銅膜 1 1 1 2 :阻障層 1 1 1 4 :晶圓 1 1 1 6 :電抛光電流 112 0 ：銅溝渠Aurora, black diamond, and Coral, spin-on MSQ/HSQ, or other low dielectric, or ultra-low k dielectric. The second dielectric layer 5007 is mainly used to prevent the Φ electrolyte from attacking the first dielectric layer 5006. The second dielectric material 5〇〇7 comprises tantalum carbide (SiC), tantalum carbonitride (SiCN), aluminum oxide (Al2〇3), or other dielectric material having high resistance and blocking HF acid performance. In other words, jjf or fluorine atoms/ions should not pass through the selected second dielectric. Step 2: depositing a third dielectric layer 5?1 having a thickness Η on the second dielectric layer 2007, as shown in Fig. 5. The third dielectric layer 5001 may be a cerium oxide, a cerium oxide-based dielectric, a fluorite vermiculite, a carbon-doped vermiculite, and a non-porous vermiculite. The third dielectric layer 5 00 1 should be selected to be susceptible to etch by HF. Step 3: Spin-coating photoresist, and the details of the lithography step are known in the art and will not be described. Step 4: The vias 5010 and the trenches 5009 are etched by plasma, as shown in FIG. Step 5: depositing barrier layer 5004 and copper seed layer 5003 as shown in Figure 5C. Generally, the barrier layer 5004 is made of giant, nitrided, titanium, titanium nitride, tungsten, tungsten nitride, tantalum, chromium, niobium, molybdenum, niobium, tantalum, palladium, niobium, tantalum, iron, and niobium. -16- 200845162 (14) Step 6: Electroplating copper layer 5 002 to fill the holes and ditches, as shown in Figure 5D. The plated copper layer can be further planarized by chemical mechanical honing (CMP), as disclosed in PCT Patent Application No. PCT/US02/26, 167, and U.S. Patent Application Serial No. 10/486,982, the disclosure of which is incorporated herein by reference. Or may be formed by planar electroplating using a virtual structure as disclosed in PCT Patent Application No. PCT/US03/11417 and U.S. Patent Application Serial No. 1 0/5 1 0,6, the disclosure of each of which is incorporated herein by reference. It can be electropolished by a contact pad nozzle disclosed in U.S. Provisional Application No. 60/73 8,250, which is incorporated herein by reference. Step 7: The copper layer is removed using the electropolishing process described with reference to Figures 1A through 1C and the apparatus described with reference to Figures 8A through 8F. Fig. 5E is a cross-sectional view showing the copper interconnect structure of the copper layer 5002 removed from the barrier layer 5 00 5 by using an electropolishing process. As the electropolishing process continues, the copper film in the trench will begin to sink and the barrier layer will be removed, as shown in Figure 5F. Since the barrier layer is removed, the electropolishing current stops because there is no current conduction path. Therefore, the barrier layer between the copper and copper trenches and the dielectric layer in the trench 5002 will be separated from the electropolishing process, or the polishing process will be self-terminating. On the other hand, the barrier residue 5015 will remain on the surface of the third dielectric layer 5001 as shown in Fig. 5F. Therefore, it is recommended to use a constant voltage to perform the above electropolishing process. As described above, the third dielectric layer 5 0 0 1 is made of yttrium oxide, yttrium oxide-based dielectric, fluorite vermiculite, carbon-doped vermiculite, and non-porous vermiculite. Hungry. Therefore, the fourth dielectric layer is etched away by HF in the electrolyte as shown in Fig. 5G. When the uranium engraving process continues, the final resistance -17- 200845162 (15) barrier residue 5 0 1 5 will be removed due to the underlying dielectric etch 5 0 1 undercut uranium, as shown in Figures 5G and 5H. The second dielectric layer 500 7 is made of tantalum carbide (Si C), tantalum carbonitride (SiCN), aluminum oxide (A1203) or other dielectric material having high resistance and blocking HF acid. Therefore, the first dielectric layer 5 00 6 under the second dielectric layer is protected from the electrolyte. Depending on the semiconductor fabrication node, the thickness of the second dielectric layer ranges from 5 nm to 100 nm. It is important to obtain a plane as shown in Fig. 5H to give better performance to the following micro φ shadowing process. Therefore, the copper trench depression as shown in Fig. 5F should be controlled to be equal to the thickness Η of the third dielectric layer 5001. The copper recess D can control the removal rate of copper metal for the barrier layer. More specifically, the HF concentration in the electrolyte determines the removal ratio of the barrier layer to the copper metal layer. For example, at a HF concentration of 5% by weight, the removal ratio of the barrier layer (Ta and/or TaN) to the copper metal layer is almost proportional to the HF concentration. Therefore, the process should be performed as follows: a. Determine the HF concentration based on the barrier layer thickness of each fabrication node, Φ to complete the minimum copper sag and at the same time, all copper residues are removed before the barrier layer is removed. The minimum copper recess may range from 2 to 1 times the thickness of the barrier layer 5004; and b. The minimum recess is measured according to the measurement of the copper trench, and the thickness of the third dielectric layer is designed to be the minimum amount of the copper trench recess. For example, for a 65 nm fabrication node, the barrier layer has a thickness of 7 nm. If a 5% wt HF concentration is used for the phosphorus/sulfuric acid/ethylene glycol/glycerol based electrolyte, the copper depression will be about 30 nm. Therefore, the thickness of the third dielectric layer 500 1 should be designed to be about 3 〇 nm. -18- 200845162 (16) For example: for a 65 nm fabrication node, the barrier layer thickness is 7 nm. If a 2.5% by weight HF concentration is used in the phosphorus/sulfate/glycol-based electrolyte, the copper depression will be about 60 nm. Therefore, the thickness of the third dielectric layer 500 1 should be designed to be about 60 nm. After electropolishing, the wafer will be transferred to a clean room' to remove all chemicals. In addition, the HF-based chemical can be further sprayed on the surface of the wafer to etch away the barrier layer remaining in the electropolished chamber when the portion of the barrier layer is not completely removed by φ. For example, for a 5% by weight HF concentration, the giant etch rate is about 1.5 nm/min. The HF concentration is in the range of 1% wt to 10% wt. Citric acid (C6H8O7) 0.5% wt can also be added to the cleaning procedure to remove copper oxide. The citric acid concentration ranges from 〇.l%wt to 1%wt. The wafer is then further cleaned with pure DI water. Step 8: Deposit SiC or SiCN layer 5008 on copper 5 002 and second dielectric layer 5007 as shown in FIG. Step 9: Repeat steps 1 through 8 to form an interconnect within another layer. The layer is as shown in Figure 5J. Another illustrative embodiment removes the barrier layer as shown in Figures 6A-61. The process steps are as follows: Step 1: Deposit a first dielectric layer 6052, deposit a second dielectric layer 6006, and deposit a third dielectric layer 6007, as shown in FIG. 6A. The deposition method may be a chemical vapor deposition (CVD) or a spin-on dielectric method. The first dielectric layer 6052 and the second dielectric layer 6006 comprise polyimine, fluorinated polyimine, polyamidene fluorene, polyparaphenylene N, poly(aryl ether), poly( Aromatic), polynaphthalene, aromatic hydrocarbon (SiLK), amorphous carbon film, Teflon-AF, iron fluoride 200845162 (17) dragon microemulsion, cerium oxide, fluorine-doped cerium oxide, organic cerium salt, For example, Aurora, black diamond, and Coral, spin-on MSQ/HSQ, or other low-k dielectric, or ultra-low-k dielectric. The third dielectric layer 60 0 7 is mainly used to prevent the electrolyte from attacking the second dielectric layer 6006. The third dielectric material 6007 comprises tantalum carbide (SiC), carbonitride (SiCN), oxidized (Al2〇3), or other dielectric material having high resistance and blocking HF acid function. In other words, neither HF nor fluorine atoms/ions should penetrate the selected second dielectric layer. φ Step 2: Deposit a fourth dielectric layer 6001 having a thickness Η on the third dielectric layer 6007 as shown in Fig. 6 . The fourth dielectric layer 6 001 may be a cerium oxide, a cerium oxide-based dielectric, a fluorite vermiculite, a carbon-doped vermiculite, and a non-porous vermiculite. The fourth dielectric layer 600 1 should be selected to be easily etched by the HF acid. Step 3: Spin-coating photoresist, and the details of the lithography step are known to the art and will not be described. Step 4: The vias 60 10 and the trenches 6009 are etched by plasma, as shown in Fig. 6. Step 5: depositing a barrier layer 6004 and a copper seed layer 6003 as shown in Fig. 6C. Generally, the barrier layer 6004 is made of molybdenum, molybdenum nitride, titanium, titanium nitride, tungsten, tungsten nitride, tantalum, chromium, niobium, molybdenum, niobium, tantalum, palladium, bell, samarium, hungry, and strontium. . Step 6: The copper layer 6002 is plated to penetrate the via holes and the trenches as shown in Fig. 6D. The plated copper layer can be further planarized by chemical mechanical honing (CMP) as disclosed in PCT Patent Application No. PCT/US02/26 1 67 and U.S. Patent Application Serial No. 10/486,982, both of which are incorporated herein by reference. References; or -20-(18) (18)200845162, may also be formed by planar electroplating using a virtual structure as disclosed in PCT Patent Application No. PCT/US03/11417, and U.S. Patent Application Serial No. </RTI> Such cases are incorporated by reference; or they may be planarized by electro-polishing with a contact pad nozzle as disclosed in U.S. Provisional Application Serial No. 60/73,025, which is incorporated herein by reference. Step 7: The copper layer is removed using the electropolishing process described with reference to Figures 1A through 1C and with reference to the apparatus described in Figures 8A through 8F. Fig. 6E shows a cross-sectional view of the copper interconnect structure as the copper layer 6002 removed from the barrier layer 6004 by using an electropolishing process. As the electropolishing process continues, the copper film in the trench will begin to sag and the barrier layer will be removed, as shown in Figure 6F. Since the barrier layer is removed, the electropolishing current will be stopped because there is no conduction path. Therefore, the barrier layer between the copper and copper trenches and the dielectric in the trench will be separated from the electropolishing process, or the honing process will be automatically terminated. On the other hand, the barrier layer remaining 60 1 5 will remain on the surface of the dielectric layer 60 0 1 as shown in Fig. 6F. Therefore, it is recommended to use a constant voltage to perform the above electropolishing process. As described above, the fourth dielectric layer 6001 is made of yttrium oxide, yttrium oxide-based dielectric, fluorinated sand, carbon-doped stone, and non-porous sandstone. These systems may be HF acid. Touched. Therefore, the fourth dielectric layer is etched away by the HF acid in the electrolyte as shown in Fig. 6G. Finally, the barrier residue 6015 will be removed due to the undercut of the underlying dielectric layer 6 021, as shown in Figures 6G and 6H. The third dielectric layer 607 is made of carbonized sand (SiC), carbonitrided (SiCN), oxidized (a12〇3), or other dielectric material having high resistance and blocking HF function. Therefore, the second dielectric layer 6006 under the third layer -21 - 200845162 (19) electrical layer 6007 is protected from the electrolyte, mainly HF. The third dielectric layer 6007 is in the range of 5 nm to 1 〇〇 nm, depending on the semiconductor fabrication node. It is important to obtain a plane as shown in Fig. 6H to give better performance to the following lithography process. Therefore, the copper trench depression D as shown in Fig. 6F should be controlled to be equal to the thickness Η of the fourth dielectric layer 600 1 . The copper recess D can be controlled by the removal ratio of the barrier layer to the copper metal. More specifically, φ, the HF concentration in the electrolyte determines the removal ratio of the barrier layer to the metal layer. For example, at a HF concentration of 5% wt, the removal ratio of the barrier layer (Ta and/or TaN) to the copper metal layer is almost proportional to the HF concentration. Therefore, the process should be performed as follows: a. Determine the HF concentration based on the barrier layer thickness at each fabrication node to ensure minimal copper sag and at the same time, all copper residue is removed before the barrier layer is removed. The minimum copper depression may range from 2 to 10 times the thickness of the barrier layer 6004; and Φ b. The minimum dielectric depression is measured according to the measurement of the copper trench, and the thickness of the fourth dielectric layer is equal to the minimum amount of the copper trench depression. For example, for a 65 nm fabrication node, the barrier layer has a thickness of 7 nm. If a 5% wt HF concentration is used for the phosphorus/sulfuric acid/ethylene glycol/glycerol based electrolyte, the copper depression will be about 30 nm. Therefore, the thickness of the fourth dielectric layer 600 1 should be designed to be about 30 nm. For example, for a 6 5 nm fabrication node, the barrier layer thickness is 7 nm. If a 2.5% by weight HF concentration is used in the phosphorus/sulfate/glycol-based electrolyte, the copper depression will be about 60 nm. Therefore, the thickness of the fourth dielectric layer 600 1 -22-(20) 200845162 should be designed to be about 60 nm. The higher the concentration of HF, the less copper sag. However, the higher the HF concentration will result in a pocket or microchannel 6100 on the side of the copper wire 6002 during the electropolishing process, as shown in Fig. 61. In the same manner, the barrier layer on the sidewall of the copper wire can be quickly removed by using a high HF concentration, as shown in Fig. 61. Therefore, the end point effect and corner loss or pocket should be balanced by adjusting the HF concentration. The H F concentration ranges from 0.5% w t to 5% w t . • After electropolishing, the wafer is transferred to a clean room to remove all chemicals. Further HF-based chemicals can be further sprayed onto the surface of the wafer to etch away the barrier layer remaining in the electropolished chamber when some of the barrier layer remains. For example, for a 5% by weight HF concentration, the giant etch rate is about 1.5 nm/min. The HF concentration is in the range of 1% wt to 10% wt. Citric acid (C6H807) (K5% wt can also be added to the cleaning procedure to remove copper oxide. The citric acid concentration ranges from 0.1% wt to 1% wt. The wafer is then further cleaned with pure DI water. #步8. Depositing SiC or SiCN layer 6008 on copper 6002 and second dielectric layer 6007, as shown in Fig. 61. Step 9: Repeat steps 1 through 8 to form an interconnect layer of another layer (not An exemplary embodiment of removing the barrier layer is as shown in Figures 7A through 71. The process steps are as follows: Step 1: depositing a first dielectric layer 7052, depositing a second dielectric layer 7050 Depositing a third dielectric layer 7006, and depositing a fourth dielectric layer 7007 as shown in Figure 7A. The deposition method may be chemical vapor deposition (CVD), or spin coating -23-200845162 (21) dielectric The first dielectric layer 7 052 comprises cerium oxide, fluorocarbon glass (FSG), HSSQ, diamond-like carbon, carbon-doped si02, MSSQ, and non-porous vermiculite. The second dielectric layer 7050 is mainly in the plasma. The uranium engraving between the via hole and the trench is stopped when the uranium is engraved. The second function of the second dielectric layer 7050 is to block the HF or the fluorine atom/ion in the subsequent electropolishing process. The diffusion reaches the first dielectric layer 7 〇 52 via the third dielectric layer 70 06 (as described below), which will be described with reference to Figure 7G. Obviously, if HF or fluoride ions penetrate the second dielectric layer • 7050, they will destroy the first dielectric layer 7052. The second dielectric layer 7050 contains tantalum carbide (SiC), tantalum carbonitride (SiCN), or other dielectric materials with high resistance and HF acid blocking performance. In other words, the HF or fluorine atoms/ions should not pass through the selected second dielectric. The third dielectric layer 7006 comprises polyimide, fluorinated polyimine, polyamidene nanobubbles , poly(p-phenylene N), poly(aryl ether), poly(aromatic), polynaphthalene, aromatic hydrocarbon (SiLK), amorphous carbon film, Teflon-AF, Teflon microemulsion, or other Low-k dielectric, or ultra-low-k dielectric. The fourth dielectric layer 7〇〇7 is mainly used to prevent electrolyte from attacking the third dielectric layer 7006. The fourth dielectric material 7007 contains tantalum carbide (SiC). , carbonitride (SiCN), alumina (Al2〇3), or other dielectric materials with high resistance and resistance to HF acid. In other words, HF or fluorine atoms/ions The selected fourth dielectric layer should be penetrated. Step 2: depositing a fifth dielectric layer 7001 having a thickness Η on the fourth dielectric layer 7007, as shown in Fig. 7. The fifth dielectric layer 7001 may be Cerium oxide, yttrium oxide-based dielectric, fluorinated vermiculite, carbon-doped vermiculite, and non-porous vermiculite. The fifth dielectric layer 700 1 should be selected to be easily etched by HF 24-(22) ( 22) 200845162 Step 3: The details of the spin-on photoresist and the lithography steps are known to the art and will not be described. Step 4: etch the via holes 70 1 〇 and the trenches 7009 by plasma, as shown in Fig. 7B. Step 5: depositing a barrier layer 7004 and a copper seed layer 7003 as shown in Fig. 7C. Generally, the barrier layer 7004 is made of molybdenum, arsenic, titanium, titanium nitride, tungsten, tungsten nitride, tantalum, chromium, niobium, molybdenum, niobium, tantalum, palladium, niobium, tantalum, hungry and tantalum. Step 6: Electroplating a copper layer 7002 to fill the vias and trenches as shown in Fig. 7D. The plated copper layer can be further planarized by chemical mechanical honing (CMP), as disclosed in PCT Patent Application No. PCT/US02/261,67, and U.S. Patent Application Serial No. 10/486,982, the disclosure of each of Alternatively, it may be formed by planar plating using a virtual structure as disclosed in PCT Patent Application No. PCT/US 0 3 /1 1 4 1 7 and U.S. Patent Application Serial No. 1 0/5 1 0,65, References; or, can be electropolished by a contact pad nozzle as disclosed in U.S. Provisional Application Serial No. 60/73,250, which is incorporated herein by reference. Step 7: The copper layer is removed using the electropolishing process described with reference to Figures 1A through 1C and the apparatus described with reference to Figures 8A through 8F. Fig. 7E is a cross-sectional view showing the copper interconnect structure of the copper layer 7002 removed from the barrier layer 7004 by using an electropolishing process. As the electropolishing process continues, the copper film in the trench will begin to sink and the barrier layer will be removed, as shown in Figure 7F. Since the barrier layer is removed, the electropolishing process is stopped because there is no current conduction path -25- 200845162 (23). Therefore, the barrier layer between the copper and copper trench 7002 and the dielectric layer in the trench 7002 will be separated from the electropolishing process, or the polishing process will be self-terminating. On the other hand, the barrier residue 701 5 will remain on the surface of the fourth dielectric layer 700 1 as shown in Fig. 7F. Therefore, it is recommended to use a constant voltage to perform the above electropolishing process. As described above, the third dielectric layer 700 1 is made of yttrium oxide, yttrium oxide-based dielectric, fluorite vermiculite, carbon-doped vermiculite, and non-porous vermiculite, which can be etched by HF. . Therefore, the fifth dielectric layer is removed by HF in the electrolyte as shown in Fig. 7G. When the etch process continues, the last barrier residue 7015 will be removed by the undercut engraving of the underlying dielectric 7021, as shown in Figures 7G and 7H. The fourth dielectric layer 7007 is made of tantalum carbide (SiC), tantalum carbonitride (SiCN), aluminum oxide (Al2〇3) or other dielectric material having high resistance and blocking HF acid. Therefore, the third dielectric layer 70 0 6 under the fourth dielectric layer 7007 is protected from the electrolyte, mainly HF. Depending on the semiconductor fabrication node, the thickness of the fourth dielectric layer 7007 ranges from 5 nm to 100 nm. It is important to obtain a plane as shown in Figure 7H to give better performance to the following lithography processes. Therefore, the copper trench depression as shown in Fig. 7F should be controlled to be equal to the thickness Η of the third dielectric layer 7001. The copper recess D can control the removal ratio of copper metal to the barrier layer. More specifically, the HF concentration in the electrolyte determines the removal ratio of the barrier layer to the copper metal layer. For example, at a HF concentration of 5% by weight, the removal ratio of the barrier layer (Ta and/or TaN) to the copper metal layer is almost proportional to the HF concentration. Therefore, the process should be performed as follows: -26- (24) (24) 200845162 a· Determine the HF concentration according to the barrier layer thickness of each fabrication node to determine the minimum copper sag and at the same time, all copper remains in the barrier The layer was removed before being removed. The minimum copper recess may range from 2 to 10 times the thickness of the barrier layer 7004; and b. The minimum recess is measured according to the measurement of the copper trench, and the thickness of the fifth dielectric layer is designed to be the minimum amount of the copper trench recess. For example, for a 65 nm fabrication node, the barrier layer has a thickness of 7 nm. If a 5% wt HF concentration is used for the phosphorus/sulfuric acid/ethylene glycol/glycerol based electrolyte, the copper depression will be about 30 nm. Therefore, the thickness of the fifth dielectric layer 7001 should be designed to be about 30 nm. For example, for a 65 nm fabrication node, the barrier layer thickness is 7 nm. If a 2.5% by weight HF concentration is used in the phosphorus/sulfate/glycol-based electrolyte, the copper depression will be about 60 nm. Therefore, the thickness of the third dielectric layer 7001 should be designed to be about 60 nm. After electropolishing, the wafer is transferred to a clean room to remove all chemicals. Further, the HF-based chemical can be further sprayed on the surface of the wafer to resist the residual layer of the barrier layer which is not completely removed in the electropolished chamber when a part of the barrier layer remains. For example, for a 5% by weight HF concentration, the giant etch rate is about 1.5 nm/min. The HF concentration is in the range of 1% wt to 10% wt. Citric acid (C6H8〇7) 0.5%wt can also be added to the cleaning procedure to remove copper oxide. The citrate concentration ranges from 0.1% w t to 1 % w t. The wafer is then further cleaned with pure DI water. Step 8: depositing a SiC or SiCN layer 7008 on the copper 7002 and the fourth dielectric layer 7007, as shown in Fig. 71. -27- 200845162 (25) Step 9: Steps 1 to 8 are repeated to form an inner wiring layer (not shown) of another layer. Figures 8A through 81 show an illustrative embodiment of a wafer electropolishing tool having a movable nozzle and/or a movable chuck. At the time of polishing, since the wafer 80 14 is rotated about its central axis, the chuck 8020 is laterally moved so that the electrolyte column 8034 can be selectively polished to any portion of the metal layer 8013, as shown in Figures 8B and 8C. Show. Further, unlike the lateral movement chuck 8020, the nozzle φ 8032 can also be moved laterally as shown in Figs. 8E and 8F. The lateral velocity and the polishing current are the two main parameters controlling the polishing rate distribution of the surface of the wafer 80 1 4 . Typically, the polishing rate is proportional to the polishing current in certain current zones and inversely proportional to the relative velocity of chuck 8020 to nozzle 8032. As shown in Figures 8A through 8F, the electropolishing tool can include a power source 8030. As shown in Figure 8A, the electropolishing tool can include a control system 8036 coupled to the chuck 8020 and the nozzle 8032. Control system 8036 can be configured to apply electrolyte vapor to the metal layer using a nozzle to eject the center of the wafer from the center of the wafer to the edge of the wafer to electrically polish the metal layer and the barrier layer to expose the non-recessed regions. It will be appreciated that various embodiments of the electropolishing tool depicted in Figures 8B through 8F may also include control system 803 6 as shown in Figure 8A. Although the present invention has been described in terms of some embodiments, examples and applications, it will be understood by those skilled in the art that various modifications and changes can be made without departing from the invention. For example, HF acid may be combined with other salts and acids for the same purpose to form an electrolyte. [Simple Description of the Drawings] -28- (26) 200845162 The 1A-1C drawing depicts the results of the electropolishing process; the 2A to the figure illustrate the results of another exemplary electropolishing process; and the 3A to 3J drawings depict another example of the electric The results of the polishing process; FIGS. 4A to 41 depict another example of the results of the electropolishing process; FIGS. 5A to 5D depict the results of another exemplary electropolishing process; and FIGS. 6A to 6J depict the results of another exemplary electropolishing process 7A to 71 depict another example of the results of the electropolishing process; FIGS. 8A to 8F are block diagrams illustrating the electropolishing tool. [Main component symbol description] 1 1 10 : Copper film 1 1 1 2 : Barrier layer 1 1 1 4 : Wafer 1 1 1 6 : Electropolishing current 112 0 : Copper trench
200 1 :第二介電層 2 0 06 ：第一介電層 2009 :溝渠 2010 ：導孔 2015 ：阻障殘留 2003 :銅種層 2004 :阻障層 2012 :介電層 2 0 2 1 :介電質 -29 - (27) 200845162200 1 : second dielectric layer 2 0 06 : first dielectric layer 2009 : trench 2010 : via hole 2015 : barrier residue 2003 : copper seed layer 2004 : barrier layer 2012 : dielectric layer 2 0 2 1 : Electrothermal -29 - (27) 200845162
3 0 0 1 :第四介電層 3006 ：第三介電層 3 052 ：第一介電層 3 0 50 ：第二介電層 3 009 :溝渠 3 0 1 0 :導孔 3 0 0 3 :銅種層 3 0 0 4 :阻障層 3 002 :銅層 3 005 ：阻障層 3 0 15:阻障殘留 3 02 1 :介電質 3008 : SiC 層 4001 ：第四介電層 4 0 0 2 :銅層 4 0 0 3 :銅種層 4 0 0 3 ·阻障層 4 0 0 5 :阻障層 4006 :第三介電層 4008 ： SiC 層 4009 :溝渠 4010 :導孔 4015 :阻障殘留 40 5 0 ：第二介電層 (28) 200845162 4 0 5 2 :第一介電層 5 00 1 ：第三介電層 5002 :銅層 5 0 0 3:銅種層 5004 :阻障層 5 005 :阻障層 5006:第一介電層3 0 0 1 : fourth dielectric layer 3006 : third dielectric layer 3 052 : first dielectric layer 3 0 50 : second dielectric layer 3 009 : trench 3 0 1 0 : via 3 0 0 3 : Copper seed layer 3 0 0 4 : barrier layer 3 002 : copper layer 3 005 : barrier layer 3 0 15 : barrier residue 3 02 1 : dielectric 3008 : SiC layer 4001 : fourth dielectric layer 4 0 0 2: copper layer 4 0 0 3 : copper seed layer 4 0 0 3 · barrier layer 4 0 0 5 : barrier layer 4006 : third dielectric layer 4008 : SiC layer 4009 : trench 4010 : via 4015 : barrier Residue 40 5 0 : second dielectric layer (28) 200845162 4 0 5 2 : first dielectric layer 5 00 1 : third dielectric layer 5002 : copper layer 5 0 0 3: copper seed layer 5004 : barrier layer 5 005 : barrier layer 5006: first dielectric layer
5007 ：第二介電層 5008 : SiC 層 5009 :溝渠 5 0 1 0 :導孔 5012 ：介電層 5015 :阻障殘留 502 1 ：介電質 600 1 :第四介電層 6002 :銅溝渠 6 0 0 4 :阻障層 6 003:銅種層 6 0 06:第二介電層 6007 :第三介電層 6015 :阻障殘留 6 0 2 1 :介電質 6008 ： SiC 層 6052 :第一介電層 200845162 (29) 6100 ： 7001 : 700 2 ： 700 3 ： 7004 ： 7006 ： 7007 ： 7009 ： 7015 ： 7 02 1 ： 7050 ： 7052 ： 70 0 8 ： 8013 ： 8014 ： 8020 ： 803 4 ： 803 2 ： 8 03 0 :5007 : second dielectric layer 5008 : SiC layer 5009 : trench 5 0 1 0 : via 5012 : dielectric layer 5015 : barrier residue 502 1 : dielectric 600 1 : fourth dielectric layer 6002 : copper trench 6 0 0 4 : barrier layer 6 003: copper seed layer 6 0 06: second dielectric layer 6007: third dielectric layer 6015: barrier residue 6 0 2 1 : dielectric 6008: SiC layer 6052: first Dielectric layer 200845162 (29) 6100 : 7001 : 700 2 : 700 3 : 7004 : 7006 : 7007 : 7009 : 7015 : 7 02 1 : 7050 : 7052 : 70 0 8 : 8013 : 8014 : 8020 : 803 4 : 803 2 : 8 03 0 :
803 6 凹穴 第五介電層 銅層 銅種層 阻障層 第三介電層 第四介電層 溝渠 阻障殘留 介電質 第二介電層 第一介電層 S i C層 金屬層 晶圓 夾盤 電解液柱 噴嘴 電源 控制系統803 6 cavity fifth dielectric layer copper layer copper layer barrier layer third dielectric layer fourth dielectric layer trench barrier residual dielectric second dielectric layer first dielectric layer S i C layer metal layer Wafer chuck electrolyte column nozzle power control system