TW200843087A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

Info

Publication number
TW200843087A
TW200843087A TW97100903A TW97100903A TW200843087A TW 200843087 A TW200843087 A TW 200843087A TW 97100903 A TW97100903 A TW 97100903A TW 97100903 A TW97100903 A TW 97100903A TW 200843087 A TW200843087 A TW 200843087A
Authority
TW
Taiwan
Prior art keywords
film
region
semiconductor device
substrate
tantalum nitride
Prior art date
Application number
TW97100903A
Other languages
Chinese (zh)
Inventor
Junichi Nozaki
Original Assignee
Sharp Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Kk filed Critical Sharp Kk
Publication of TW200843087A publication Critical patent/TW200843087A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Introduction of nitrogen onto a surface of a silicon oxide film in an analog circuit element region (25), and formation of a silicon nitride film (27) in a digital circuit element region (24) are performed in a same step by plasma nitriding method. Therefore, a gate electrode pattern of the digital circuit element region (24) and the gate electrode pattern of the analog circuit element region (25) can be formed in the same photolithography step. Two MOS semiconductor elements, which are formed by having gate electrode patterns on two gate insulating films having compositions different from each other, can be easily formed with a small number of steps. Furthermore, process accuracy is improved with the reduced number of steps.

Description

200843087 九、發明說明： • 【發明所屬之技術領域】 本發明係關於具有形成於同一基板上之複數個半導體元 件之半導體裝置以及其製造方法。 【先前技術】 ^ 先前，為了形成用於行動電話或便攜式小型受像機等上200843087 IX. DESCRIPTION OF THE INVENTION: 1. Field of the Invention The present invention relates to a semiconductor device having a plurality of semiconductor elements formed on the same substrate and a method of fabricating the same. [Prior Art] ^ Previously, in order to form a mobile phone or a portable compact camera, etc.

、 的無線通信用半導體積體電路裝置，主要採用Bi-CMOS (Bipolar-CMOS ， Complementary Metal Oxide 馨 Semiconductor，雙重互補金屬氧化物半導體）製程，該製 程中於同一基板上形成用於類比電路元件區域之雙極元件 與用於數位電路元件區域之CMOS(互補金屬氧化物半導體 (Complementary Metal Oxide Semiconductor))元件。然 而，雙極製程與CMOS製程之混合存在會使形成積體電路 裝置之製程變得複雜，從而正在開發一種於CMOS製程中 一併形成類比電路元件區域與數位電路元件區域的技術。 作為CMOS電晶體之閘極絕緣膜，一般使用的是藉由使 ® 用有N20或NO等含氮之氣體之熱氧化法而形成的氮氧化矽 膜（SiOxN^x ; 0<χ<1)，或者，藉由使用有02等氣體之熱氧 ^ 化法而形成的氧化石夕膜（Si〇2)。此時，眾所周知的是，於 藉由使用有N20或NO等含氮之氣體的熱氧化法而形成的氮 氧化矽膜中，會產生尤其在低頻類比電路中成為問題之1/f 雜訊，例如，於"J.-P.Xu et al.，Solid-State Electronics 45，p431，2001"中記載了如下内容，與氧化矽膜相比，氮氧 化矽膜中之Ι/f雜訊強度大約多出1位。雖然Ι/f雜訊產生之 128042.doc 200843087 構造尚未完全解明，但可知係因c婦"晶體中會週期性 地由閘極絕緣膜之能階捕獲載子。 又，日本專利特開2000-77533號公報（專利文獻】）中揭 示有^下半導體積體電路裝置，該半導體積體電路裝置中 使用氧化矽膜作為類比電路元件區域之閘極絕緣膜，另— 方面’使用氮氧切膜作為數位電路元件區域之閘極絕緣 膜。該半導體積體電路裝置可按照如下方式而形成。 如圖4Α所示，在由形成於半導體基板i上之氧化石夕膜所 構成的且藉由元件分離區域2而隔開的數位電路元件區域3 與類比電路元件區域4上，藉由使用有Ν2〇之熱氧化法來形 成氮氧化梦膜5。進而，在該氮氧化梦膜5上堆積多晶石夕層 6以及氧化矽膜層7，利用利電極圖案形成用之光阻遮罩8 而形成於數位電路元件區域3上。 其次，如圖4Β所示，使用上述光阻遮罩8，依次對氧化 矽膜層7以及多晶矽層6進行乾式蝕刻而形成電極圖案。進 而，使用氟酸等選擇性地去除氮氧化矽膜5，於數位電路 元件區域3上形成利用由氧化矽膜7所構成的頂蓋層覆蓋之 閘極電極圖案。 其次，如圖4C所示，於上述類比電路元件區域4上形成 氧化矽膜9，藉由與數位電路元件區域3上相同之方法，使 多晶矽層10以及氧化矽膜層U堆積，藉由乾式蝕刻形成電 極圖案。如此，形成利用由氧化矽膜丨！所構成之頂蓋層覆 蓋的閘極電極圖案。 最後，如圖4D所示，利用氟酸等去除由上述氧化矽膜層 128042.doc 200843087 7以及氧化矽膜層11所構成的頂蓋層，而保留閘極電極圖 案。 然而，上述專利文獻1中所揭示之先前之半導體積體電 路裝置中’存在如以下般之問題。亦即，於半導體裝置 中，伴隨半導體製程之微細化，構成數位電路部之cM〇s 電晶體的閘極絕緣膜之薄膜化發展，先前所使用之氮氧化 矽膜之物理膜厚為1 nm左右，接近臨界值，又，藉由薄膜 化發展，流通於閘極絕緣膜之洩漏電流亦不斷增大。 進而，關於構成上述類比電路元件區域之電晶體與構成 上述數位電路元件區域之電晶體，係分別於不同步驟中形 成閘極絕緣膜以及閘極電極，因此，步驟複雜且變得多工 數，從而加工精度方面亦存在問題。 【發明内容】 [發明所欲解決之問題] 因此，本發明之課題在提供一種以較少之步驟即可簡便 地製造且於同一基板上具有複數個半導體元件的半導體裝 置以及其製造方法。 义 [解決問題之技術手段] 為了解決上述課題，本發明之半導體裝置的特徵在於包 括： 第 1MOS (Metal_〇xide semiconductor，金屬氧化物半導 體）型半導體元件，其形成於半導體基板之第丨區域上；及 第2MOS型半導體元件，其形成於上述半導體基板之第2 區域上； 128042.doc 200843087 产上述第1MGS型半導體元件包含：第丨絕緣膜，其包括使 氧化石夕族之表面氮化而形成之氮氧切模；及第！導電性 電極，其形成於該第1絕緣膜上； 上述第2MOS型半導體元件包含：第2絕緣膜，其包括氮 化石夕膜，·及第2導電性電極，其以與上述第咖8型半導體 元件之上述第i導電性電極同—步㈣成^該第2絕緣膜 上。 根據上述構成，第1M〇S型半導體元件之形成於由氮氧 化矽膜所構成的第1絕緣膜上的第！導電性電極，與第 2MOS型半導體元件之形成於由氮化矽膜所構成之第2絕緣 膜上的第2導電性電極，可於同一步驟中形成。因此，以 車父少之步驟即可簡單地形成具有2個半導體元件之半導體 裝置，亦可提咼加工精度，上述2個半導體元件係分別於 具有彼此不同之組成之2個絕緣膜上形成導電性電極而 成。 又，一實施形態之半導體裝置中， 上述半導體基板係形成有矽井之半導體基板或者矽基 板； 構成上述第2絕緣膜之上述氮化矽膜，係使上述半導體 基板之石夕井或者上述石夕基板之表面氮化而形成的薄膜。 根據本實施形態，上述氮化矽膜係使上述半導體基板之 矽井或者上述矽基板之表面之矽氮化而形成。因此，藉由 使用電漿氮化法等，可簡單地形成上述氮化矽膜。 又，一實施形態之半導體裝置中， 128042.doc 200843087 構成上述第i絕緣膜之述氮氧化矽膜，係於形成上述氮 化矽膜時，僅於使上述半導體基板之矽井或者上述矽基板 之表面氧化而形成的氧化矽膜之表面，導入氮而形成之薄 膜。 根據本實施形態，上述第1區域之上述氧化矽膜之氮化 與上述第2區域之上述氮化矽膜之形成可同時進行。因 、 此，可於同一步驟中，形成第1MOS型半導體元件之第工導 電性電極與第2MOS型半導體元件之第2導電性電極。 馨 又，一實施形態之半導體裝置中， 上述氮氧化石夕膜僅於自表面最多至膜厚方向之一半為止 之區域導入有氮。 根據本實施形態，利用電漿氮化法等，僅於自上述第1 區域之上述氧化矽膜之表面最多至膜厚方向之一半為止之 區域，導入有氮，而構成上述氮氧化矽膜。因此，與藉由 使用有N2〇之熱氧化法形成氮氧化矽膜的情形相比，可獲 得Ι/f雜訊產生較少之MOS型半導體元件。 又，本發明之半導體裝置之製造方法的特徵在於包含如 下步驟： • 於形成於半導體基板之碎井或者石夕基板之第1區域上， . 形成氧化矽膜； 與於形成於上述半導體基板上之石夕井或者上述石夕基板之 第2區域之表面導入氮，於上述第2區域上形成氮化矽膜的 同時，於自上述第1區域上之氧化矽膜之表面至1 以上 且2 nm以下之深度為止之區域導入氮，形成氮氧化矽膜；及 128042.doc 200843087 於上述第1區域之氮氧化矽膜上與上述第2區域之氮化矽 膜上，形成導電性電極。 根據上述構成，因同時進行形成於第丨區域上之氧化矽 膜之氮化與形成於第2區域上之氮化矽膜之形成，故可於 同步驟中形成上述第i區域之導電性電極與上述第2區域 之導電性電極。因&，根據本發明，以較少之步驟即可簡 單地形成具有2個半導體元件之半導體裝置，亦可提高加 工精度，上述2個半導體元件係分別於具有彼此不同之組 成之2個絕緣膜上形成導電性電極而成。 進而，上述氮氧化矽膜，係例如使用電漿氮化法，僅於 上述氧化矽膜之表面以1 nm以上且2 nm以下之深度導入氮 而形成。因此，與藉由使用有!^^之熱氧化法而形成氮氧 化矽膜之情形相比，可形成1/f雜訊產生較少之半導體元 件。又，具有氮化矽膜之絕緣膜的半導體裝置，可實現較 高之介電常數，因此與具有相同膜厚之氧化矽膜或者氮氧 化石夕膜之絕緣膜的半導體裝置相比，可減少洩漏電流。上 述構成中，因於上述第2區域上形成氮化矽膜，故與形成 氧化石夕膜或者氮氧化矽膜之情形相比，可使洩漏電流下降 為1 /10以下。 亦即’根據本發明，可於同一基板上形成l/f雜訊產生較 少之半導體元件與洩漏電流為1/10以下之半導體元件。 又’ 一實施形態之半導體裝置之製造方法中， 上述第2區域上之上述氮化矽膜之形成，係藉由於上述 第2區域上露出之矽與經活化之氮之反應而形成。 128042.doc -10- 200843087 根據本實施形態，上述氮化矽膜係使上述第2區域之表 面之矽氮化而形成。因此，藉由使用電漿氮化法等，可簡 單地形成上述氮化石夕膜。 [發明之效果] 由以上可知，本發明之半導體裝置由如下導電性電極構 成，因此可以較少之步驟簡單地形成具有於具有彼此不同 之組成之2個絕緣膜上之各個形成導電性電極而成的2個半 導體元件的半導體裝置，上述導電性電極係於同一步驟中 形成第1MOS型半導體元件之由氮氧化矽膜構成之第〗絕緣 膜上所形成的第1導電性電極與第2MOS型半導體元件之由 氮化矽膜構成之第2絕緣膜上所形成的第2導電性電極。因 此’僅步驟較少之部分即可提高加工精度。 又，本發明之半導體裝置之製造方法，因同時進行形成 於第1區域上之氧化矽膜之氮化與第2區域上之氮化矽膜之 形成，故可於同一步驟中形成上述第丨區域之導電性電極 與上述第2區域之導電性電極。因此，根據本發明，可以 較少之步驟簡單地形成具有2個半導體元件之半導體裝 置，亦可提高加工精度，上述2個半導體元件係於具有彼 此不同之組成之2個絕緣膜上之各個形成導電性電極而 成。 再者，於上述第1區域上形成氮氡化矽膜，並且於上述 第2區域上形成氮化矽膜，因此可於同一基板上形成雜 訊產生較少之半導體元件與洩漏電流為1/1〇以下之半導體 元件。 128042.doc 11- 200843087 【實施方式】 以下，藉由圖示之實施形態來詳細說明本發明。再者 各實施形態中用於說明的圖中，對具有相同功能之部八附 上相同符號，並省略其重複之說明…對製造步驟：： 加以詳細敍述之部分可使用眾所周知之手段。 •第1實施形態 明7八〜圖1輯本實施形態之半導體裝置之製造方法的說 再者’本半導體裝置係於同一基板上混合裝載有數位電 路凡件以及類比電路元件之半導體裝置。 如圖1Α所示，於石夕基板21卜舌為、在—τ 土扳1上重複進打光阻遮罩之形成與 子注入，形成p型井區域與„型井區域，將所形成 井區域以及η型井區域作為S件形成區域23。其中，圖1A〜 圖1F中’僅表示了將上述P型井區域以及η型井區域中的任 一個作為凡件形成區域23。進而，利用眾所周知之方法， :夕基板21上形成由氧化碎膜所構成之元件分離區域η， 、'將兀件瓜成區域23分離為數位電路元件區域以與類比電 路元件區域25。谁而，& 為了调整閾值電壓，使用光阻遮 罩’分別於數位電路元侔 件£域24與類比電路元件區域25上 選擇f生地進仃離子注入。 其次，如圖1B所示，於 於上述類比電路元件區域25之表 面，以3 nm〜5〇 上 之膜厚形成氧化矽膜26。該氧化矽 膜26可按照如下方 ,^ ^ 式而形成。亦即，使用700。〇〜l〇〇〇°C左 右之熱氧化法，於开杜於上 牛形成區域23之表面形成氧化矽膜。 128042.doc -12- 200843087 此處’為了形成氧化矽膜層而以使用熱氧化法為一例，亦 可使用RTO (Rapid Thermal Oxidation，快速加熱氧化）法 或電漿氧化法。其次，形成覆蓋類比電路元件區域25之光 阻遮罩之圖案，使用1%左右之濃度之氟酸來去除形成於 作為開口部之數位電路元件區域24上的氧化矽膜。如此， 僅於類比電路元件區域25上保留有氧化矽膜26。繼而，藉 由氧電漿之灰化處理以及使用有硫酸之剝離處理來去除上 述光阻遮罩。 其次，如圖1C所示，藉由400°C〜800°C左右之電漿氮化 法，於數位電路元件區域24之表面，以2 ηπι〜4 nm左右之 膜厚形成氮化矽膜27。此時，於已形成於類比電路元件區 域25之氧化石夕膜26之表面，同時以1 nm〜2 nm左右之深度 導入有氮，形成氮氧化矽膜28。以下，將表面導入有氮之 整個氧化矽膜26稱作氮氧化矽膜28。 其次，如圖1D所示般，使用LP-CVD (Low Pressure Chemical Vapor Deposition，低壓化學氣相沈積）法，以 100 nm左右之膜厚堆積之後會作為閘極電極之多晶矽薄膜 層29。於本實施形態中，是將上述多晶矽薄膜層29用作構 成導電性電極之材料之一例，但為了形成該導電性電極， 亦可使用非晶質矽薄膜或金屬薄膜等。繼而，分別於數位 電路元件區域24與類比電路元件區域25上形成閘極電極形 成用之光阻遮罩30。 其次，如圖1E所示，將上述光阻遮罩3〇作為遮罩，藉由 使用有CL、HBr或〇2等蝕刻氣體之乾式蝕刻，餘刻並去除 128042.doc -13- 200843087 多晶矽薄膜層29，直至氮化矽膜27以及氮氧化矽膜28之上 表面露出為止。進而，使用磷酸來選擇性地去除上表面已 露出之氮化矽膜27。繼而，使用氟酸來選擇性地去除上表 面已露出之氮氧化矽膜28。如此，數位電路元件區域24之 閘極電極圖案與類比電路元件區域25之閘極電極圖案，可 藉由同一光微影步驟而形成。 其次，彔終於LDD (Lightly Doped Drain，輕微摻雜的沒 極）區域進行離子注入之後，如圖1F所示，藉由LP_cvd法A semiconductor integrated circuit device for wireless communication mainly uses a Bi-CMOS (Bipolar-CMOS, Complementary Metal Oxide Semiconductor) system in which an analog circuit device region is formed on the same substrate. A bipolar element and a CMOS (Complementary Metal Oxide Semiconductor) element for a digital circuit element region. However, the combination of a bipolar process and a CMOS process complicates the process of forming an integrated circuit device, and a technique for forming an analog circuit element region and a digital circuit device region in a CMOS process is being developed. As a gate insulating film of a CMOS transistor, a yttrium oxynitride film formed by using a thermal oxidation method of a nitrogen-containing gas such as N20 or NO (SiOxN^x; 0<χ<1) is generally used. Or, an oxidized stone film (Si〇2) formed by a thermal oxidation method using a gas such as 02. At this time, it is known that a ruthenium oxynitride film formed by a thermal oxidation method using a nitrogen-containing gas such as N20 or NO causes a 1/f noise which is a problem particularly in a low-frequency analog circuit. For example, in "J.-P.Xu et al., Solid-State Electronics 45, p431, 2001", the following is a description of the Ι/f noise intensity in the yttrium oxynitride film compared to the yttrium oxide film. About one more. Although the structure of 128042.doc 200843087 produced by Ι/f noise has not been fully explained, it can be seen that the carrier is periodically captured by the energy level of the gate insulating film in the crystal. Further, Japanese Laid-Open Patent Publication No. 2000-77533 (Patent Literature) discloses a semiconductor integrated circuit device in which a ruthenium oxide film is used as a gate insulating film of an analog circuit element region, and - Aspect 'Use a oxynitride film as a gate insulating film for the area of the digital circuit component. The semiconductor integrated circuit device can be formed as follows. As shown in FIG. 4A, on the digital circuit element region 3 and the analog circuit device region 4 which are formed by the oxidized oxide film formed on the semiconductor substrate i and separated by the element isolation region 2, The thermal oxidation method of Ν2〇 forms a nitrogen oxide dream film 5. Further, the polycrystalline oxide layer 6 and the yttrium oxide film layer 7 are deposited on the oxynitride film 5, and are formed on the digital circuit element region 3 by the photoresist mask 8 for forming a favorable electrode pattern. Next, as shown in Fig. 4A, the ruthenium oxide film layer 7 and the polysilicon layer 6 are sequentially dry-etched using the photoresist mask 8 to form an electrode pattern. Further, the ytterbium oxynitride film 5 is selectively removed by using hydrofluoric acid or the like, and a gate electrode pattern covered with a cap layer composed of the yttrium oxide film 7 is formed on the digital circuit element region 3. Next, as shown in FIG. 4C, a tantalum oxide film 9 is formed on the analog circuit element region 4, and the polysilicon layer 10 and the hafnium oxide layer U are stacked by the same method as in the digital circuit element region 3, by dry type. Etching forms an electrode pattern. So, the formation is utilized by the yttrium oxide film! The gate electrode pattern covered by the cap layer is formed. Finally, as shown in Fig. 4D, the cap layer composed of the above-mentioned yttrium oxide film layer 128042.doc 200843087 7 and the yttrium oxide film layer 11 is removed by using hydrofluoric acid or the like, and the gate electrode pattern is retained. However, in the conventional semiconductor integrated circuit device disclosed in the above Patent Document 1, there is a problem as follows. That is, in the semiconductor device, the thin film of the gate insulating film of the cM 〇s transistor constituting the digital circuit portion is developed along with the miniaturization of the semiconductor process, and the physical thickness of the yttrium oxynitride film previously used is 1 nm. Left and right, close to the critical value, and by the development of thin film, the leakage current flowing through the gate insulating film is also increasing. Further, the transistor constituting the analog circuit element region and the transistor constituting the digital circuit device region are respectively formed with a gate insulating film and a gate electrode in different steps, and therefore, the steps are complicated and become multiplexed. Therefore, there are problems in processing accuracy. SUMMARY OF THE INVENTION [Problems to be Solved by the Invention] Accordingly, an object of the present invention is to provide a semiconductor device which can be easily manufactured in a small number of steps and which has a plurality of semiconductor elements on the same substrate, and a method of manufacturing the same. [Means for Solving the Problems] In order to solve the above problems, a semiconductor device of the present invention includes: a first MOS (Metal Semiconductor) semiconductor device formed on a third region of a semiconductor substrate And the second MOS type semiconductor device is formed on the second region of the semiconductor substrate; 128042.doc 200843087 The first MGS-type semiconductor device comprises: a second insulating film comprising nitriding a surface of the oxidized stone family And the formation of the oxynitride die; and the first! a conductive electrode formed on the first insulating film; the second MOS type semiconductor device includes a second insulating film including a nitride film and a second conductive electrode, and the The ith conductive electrode of the semiconductor element is formed on the second insulating film in the same step (4). According to the above configuration, the first M〇S-type semiconductor element is formed on the first insulating film made of the hafnium oxynitride film! The conductive electrode and the second conductive electrode formed on the second insulating film made of the tantalum nitride film of the second MOS type semiconductor device can be formed in the same step. Therefore, the semiconductor device having two semiconductor elements can be simply formed by a step of the carrier, and the processing precision can be improved. The two semiconductor elements are respectively formed on the two insulating films having different compositions from each other. Made of sexual electrodes. Further, in the semiconductor device of the embodiment, the semiconductor substrate is formed with a semiconductor substrate or a germanium substrate; and the tantalum nitride film constituting the second insulating film is a stone substrate or the stone of the semiconductor substrate. A film formed by nitriding the surface of the substrate. According to this embodiment, the tantalum nitride film is formed by nitriding the surface of the well of the semiconductor substrate or the surface of the germanium substrate. Therefore, the above-described tantalum nitride film can be easily formed by using a plasma nitridation method or the like. Further, in the semiconductor device of the embodiment, 128042.doc 200843087 constitutes the yttrium oxynitride film of the ith insulating film, and when the tantalum nitride film is formed, only the well of the semiconductor substrate or the ruthenium substrate is formed. A film formed by introducing nitrogen into the surface of the ruthenium oxide film formed by oxidation of the surface. According to this embodiment, the nitridation of the yttrium oxide film in the first region and the formation of the tantalum nitride film in the second region can be simultaneously performed. Therefore, in the same step, the first conductive electrode of the first MOS type semiconductor element and the second conductive electrode of the second MOS type semiconductor element can be formed. Further, in the semiconductor device of the embodiment, the oxynitride film is introduced with nitrogen only in a region from the surface up to a half of the film thickness direction. According to the present embodiment, the yttrium oxynitride film is formed by introducing nitrogen into the region from the surface of the yttrium oxide film in the first region to at least one half of the film thickness direction by the plasma nitridation method or the like. Therefore, compared with the case where the yttrium oxynitride film is formed by the thermal oxidation method using N2 ,, a MOS type semiconductor element which generates less Ι/f noise can be obtained. Further, the method of fabricating a semiconductor device of the present invention is characterized by comprising the steps of: forming a yttrium oxide film on a first region of a fractured or a slab substrate formed on a semiconductor substrate; and forming on the semiconductor substrate Nitrogen is introduced into the surface of the second region of the Shishijing or the above-mentioned Shishi substrate, and a tantalum nitride film is formed on the second region, and the surface of the tantalum oxide film on the first region is 1 or more and 2 Nitrogen is introduced into a region up to a depth of nm to form a ruthenium oxynitride film; and 128042.doc 200843087 A conductive electrode is formed on the yttrium oxynitride film of the first region and the tantalum nitride film of the second region. According to the above configuration, since the nitridation of the yttrium oxide film formed on the second region and the formation of the tantalum nitride film formed on the second region are simultaneously performed, the conductive electrode of the ith region can be formed in the same step. The conductive electrode of the second region described above. According to the present invention, a semiconductor device having two semiconductor elements can be easily formed in a small number of steps, and the processing accuracy can be improved. The two semiconductor elements are respectively provided with two insulations having different compositions from each other. A conductive electrode is formed on the film. Further, the ytterbium oxynitride film is formed by introducing nitrogen into the surface of the yttrium oxide film at a depth of not less than 1 nm and not more than 2 nm, for example, by a plasma nitridation method. Therefore, compared with the case where the hafnium oxynitride film is formed by the thermal oxidation method of ?^, a semiconductor element which generates less 1/f noise can be formed. Further, since the semiconductor device having the insulating film of the tantalum nitride film can realize a high dielectric constant, it can be reduced as compared with a semiconductor device having an oxide film of the same film thickness or an insulating film of the oxynitride film. Leakage current. In the above configuration, since the tantalum nitride film is formed on the second region, the leakage current can be reduced to 1/10 or less as compared with the case where the oxide oxide film or the hafnium oxynitride film is formed. That is, according to the present invention, it is possible to form a semiconductor element having a small amount of semiconductor elements and a leakage current of 1/10 or less on the same substrate. In the method of fabricating a semiconductor device according to the embodiment, the formation of the tantalum nitride film on the second region is formed by a reaction between the exposed germanium in the second region and the activated nitrogen. 128042.doc -10- 200843087 According to the embodiment, the tantalum nitride film is formed by nitriding the surface of the second region. Therefore, the above-described nitride film can be simply formed by using a plasma nitridation method or the like. [Effect of the Invention] As described above, the semiconductor device of the present invention is composed of the following conductive electrodes. Therefore, it is possible to easily form each of the two conductive films having different compositions from each other to form a conductive electrode in a small number of steps. In the semiconductor device of the two semiconductor elements, the conductive electrode is a first conductive electrode and a second MOS type formed on the first insulating film made of a hafnium oxide film of the first MOS type semiconductor device in the same step. A second conductive electrode formed on the second insulating film made of a tantalum nitride film of the semiconductor element. Therefore, only a small number of steps can improve the machining accuracy. Further, in the method of fabricating the semiconductor device of the present invention, since the nitridation of the hafnium oxide film formed on the first region and the formation of the tantalum nitride film on the second region are simultaneously performed, the third step can be formed in the same step. The conductive electrode of the region and the conductive electrode of the second region. Therefore, according to the present invention, it is possible to easily form a semiconductor device having two semiconductor elements in a small number of steps, and it is also possible to improve the processing accuracy, and the two semiconductor elements are formed on each of two insulating films having mutually different compositions. Conductive electrode. Further, a germanium nitride film is formed on the first region, and a tantalum nitride film is formed on the second region. Therefore, a semiconductor element having less noise can be formed on the same substrate and a leakage current is 1/1. 1半导体 below the semiconductor component. 128042.doc 11-200843087 [Embodiment] Hereinafter, the present invention will be described in detail by way of embodiments shown in the drawings. In the drawings for the description of the embodiments, the same reference numerals will be given to the parts having the same functions, and the description thereof will be omitted. For the manufacturing steps: a part of the detailed description can be used. (First Embodiment) A method of manufacturing a semiconductor device according to the present embodiment is as follows. The present semiconductor device is a semiconductor device in which a digital circuit device and an analog circuit device are mixed and mounted on the same substrate. As shown in FIG. 1A, the formation and sub-injection of the photoresist mask are repeated on the base plate of the Shixi substrate, and the formation of the p-type well region and the sub-well region are formed on the -1 soil plate 1 to form a well. The region and the n-type well region are referred to as the S-piece forming region 23. Here, in FIGS. 1A to 1F, 'only one of the above-described P-type well region and n-type well region is shown as the article forming region 23. Further, As is well known, an element separation region η composed of an oxidized chip is formed on the substrate 21, and the element 23 is separated into a digital circuit element region and an analog circuit device region 25. Who, & In order to adjust the threshold voltage, a photoresist mask is used to select the input ion source in the digital circuit element 24 and the analog circuit element region 25 respectively. Next, as shown in FIG. 1B, the analog circuit component is used. On the surface of the region 25, a ruthenium oxide film 26 is formed with a film thickness of 3 nm to 5 Å. The yttrium oxide film 26 can be formed as follows. That is, 700 is used. 〇~l〇〇〇° Thermal oxidation method around C, in the opening of the top of the cattle A ruthenium oxide film is formed on the surface of the formation region 23. 128042.doc -12- 200843087 Here, in order to form a ruthenium oxide film layer, a thermal oxidation method may be used as an example, and an RTO (Rapid Thermal Oxidation) method or Plasma oxidation method. Next, a pattern of a photoresist mask covering the analog circuit element region 25 is formed, and a cerium oxide film formed on the digital circuit element region 24 as an opening portion is removed using a fluoric acid having a concentration of about 1%. Thus, only the yttrium oxide film 26 remains on the analog circuit element region 25. Then, the above-described photoresist mask is removed by ashing treatment of oxygen plasma and stripping treatment with sulfuric acid. Next, as shown in Fig. 1C The tantalum nitride film 27 is formed on the surface of the digital circuit device region 24 by a plasma nitridation method at a temperature of about 400 ° C to 800 ° C at a film thickness of about 2 η π 4 4 nm. On the surface of the oxidized oxide film 26 of the analog circuit element region 25, nitrogen is introduced at a depth of about 1 nm to 2 nm to form a yttrium oxynitride film 28. Hereinafter, the entire yttrium oxide film 26 having a surface introduced with nitrogen is called Nitrogen The ruthenium film 28. Next, as shown in FIG. 1D, a polycrystalline tantalum film which is used as a gate electrode after being deposited at a film thickness of about 100 nm using a LP-CVD (Low Pressure Chemical Vapor Deposition) method. In the present embodiment, the polycrystalline silicon thin film layer 29 is used as an example of a material constituting the conductive electrode. However, in order to form the conductive electrode, an amorphous tantalum film or a metal thin film may be used. A photoresist mask 30 for forming a gate electrode is formed on the digital circuit element region 24 and the analog circuit device region 25, respectively. Next, as shown in FIG. 1E, the photoresist mask 3 is used as a mask, and a dry etching using an etching gas such as CL, HBr or 〇2 is used to remove and remove the 128042.doc -13-200843087 polycrystalline germanium film. The layer 29 is exposed until the upper surface of the tantalum nitride film 27 and the hafnium oxynitride film 28 is exposed. Further, phosphoric acid is used to selectively remove the tantalum nitride film 27 which is exposed on the upper surface. Then, hydrofluoric acid is used to selectively remove the yttrium oxide ruthenium film 28 which has been exposed on the upper surface. Thus, the gate electrode pattern of the digital circuit element region 24 and the gate electrode pattern of the analog circuit device region 25 can be formed by the same photolithography step. Secondly, after the ion implantation of the LDD (Lightly Doped Drain) region, as shown in Fig. 1F, by the LP_cvd method

以50 nm左右之膜厚堆積氮化石夕膜，並對該氮化石夕膜進行 敍刻’藉此於閘極電極側壁形成側壁3丨。進而，於源極區 域以及汲極區域進行離子注入之後，藉由1〇〇〇。〇左右之 RTA (rapid thermal annealing，快速高熱退火）法進行活 化。繼而，於閘極電極、源極電極以及汲極電極之表面形 成矽化物層32。進而，於整個面上堆積蝕刻阻止膜之氮化 石夕膜33,並於該氮化㈣33之上層堆積氧化賴系之層間 、巴緣膜 34 ’ 之後’藉由 CMP (Chemical Mechanical Polishing，化學機械研磨）法等而使表面平坦化。 而且’藉由光微影法與乾式蝕刻法使接觸孔開口，於該 接觸孔内堆積障壁膜之TiN與鎢膜35，使層間絕緣膜批 表面與鶴膜35之表面以成為相同高度之方式而平坦化。繼 而，堆積作為金屬配線層之銘膜，藉由光微影法與乾式儀 刻法形成金屬配線層36，從而形成本實施形態之半導體裝 圖3A表示剖面模式圖 該剖面模式圖表示本實施形態之 128042.doc -14- 200843087 混合搭載有數位電路元件（MOS電晶體）與類比電路元件 (MOS電晶體）的矽基板上之各元件之閘極絕緣膜構造。再 者’ 24係數位電路元件區域，25係類比電路元件區域，27 係氮化矽膜，28係氮氧化矽膜。 進而，圖3C表示上述專利文獻}中所揭示之半導體積體 電路裝置之剖面模式圖。再者，3係數位電路元件區域，4 係類比電路元件區域，5係氮氧化矽膜，9係氧化矽膜。 •弟2實施形態The nitride film is deposited at a film thickness of about 50 nm, and the nitride film is etched to form a sidewall 3丨 on the sidewall of the gate electrode. Further, after ion implantation in the source region and the drain region, 1 〇〇〇 is performed. The RTA (rapid thermal annealing) method is activated by the RTA (rapid thermal annealing) method. Then, a vaporized layer 32 is formed on the surfaces of the gate electrode, the source electrode, and the drain electrode. Further, a nitride film 33 of an etching stopper film is deposited on the entire surface, and a layer of an oxide layer is laminated on the layer of the nitride layer 34, and after the edge film 34' is formed by CMP (Chemical Mechanical Polishing). ) The method is to flatten the surface. Further, 'the contact hole is opened by the photolithography method and the dry etching method, and the TiN and the tungsten film 35 of the barrier film are deposited in the contact hole so that the surface of the interlayer insulating film and the surface of the film 35 are at the same height. And flattened. Then, the metal wiring layer 36 is formed by the photolithography method and the dry etching method, and the semiconductor wiring layer 36 is formed by the photolithography method and the dry etching method. FIG. 3A is a cross-sectional schematic view showing the embodiment. 128042.doc -14- 200843087 A gate insulating film structure of each element on a germanium substrate on which a digital circuit element (MOS transistor) and an analog circuit element (MOS transistor) are mixed is mounted. Further, the '24 coefficient bit circuit element region, the 25 series analog circuit element region, the 27 series tantalum nitride film, and the 28 series yttria film. Further, Fig. 3C is a schematic cross-sectional view showing the semiconductor integrated circuit device disclosed in the above Patent Document. Further, the three-coefficient circuit element region, the four-system analog circuit element region, the five-system yttria film, and the nine-system yttrium oxide film. • Brother 2 implementation

圖2A〜圖2F係本實施形態之半導體裝置之製造方法之說 明圖。再者，本半導體裝置係於同一基板上混合搭載有數 位電路元件以及類比電路元件之半導體裝置。 如圖2A所示，於矽基板41上，重複進行光阻遮罩之形成 與離子注入’形成P型井區域與㈣井區域，將所形成之p 型井區域以及η型井區域作為元件形成區域43。其中，圖 2Α〜圖2F中’僅表示了將上述ρ型井區域以及η型井區域中 的任一個作為元件形成區域43。進而，抑眾所周知之方 法，於石夕基板41上形成由氧化石夕膜所構成之元件分離區域 卫將讀形成區域43分離為數位電路元件區域44與類 2路7G件區域45。進而，為了調整閾值電|，使用光阻2A to 2F are explanatory views of a method of manufacturing the semiconductor device of the embodiment. Further, this semiconductor device is a semiconductor device in which a digital circuit element and an analog circuit element are mixed and mounted on the same substrate. As shown in FIG. 2A, on the germanium substrate 41, the formation of the photoresist mask and the ion implantation 'formation of the P-type well region and the (4) well region are repeated, and the formed p-type well region and the n-type well region are formed as elements. Area 43. Here, in Fig. 2A to Fig. 2F, only one of the above-described p-type well region and n-type well region is shown as the element formation region 43. Further, in the well-known method, the element isolation region composed of the oxidized stone film is formed on the Shih-hsing substrate 41, and the read formation region 43 is separated into the digital circuit element region 44 and the class 2 7G device region 45. Furthermore, in order to adjust the threshold power |, use a photoresist

遮罩，分別於數位電路元件區域44與類比電路元件區域C 上選擇性地進行離子注入。 人如圖2Β所不，於上述類比電路元件區域c之表 膜4’二則。nm左右之膜厚形成氧切⑽。該氧化石夕 、按照如下方式而形成。亦即，使用7〇(rc〜i〇〇(rc左 128042.doc -15- 200843087 右之熱氧化法’於元件形成區域43之表面形成氧化矽膜。 此處，為了形成氧切膜層而使用熱氧化法作為—例，亦 可使用RTQ法或i漿氧化法。其次，形成覆蓋類比電路元 件區域45之光阻遮罩圖案，使用1%左右之濃度之氣酸來 去除形成於作為開口部之數位電路元件區域料上的氧化矽 膜。如此，僅於類比電路元件區域45上保留有氧化矽膜 46。繼而，藉由氧電漿之灰化處理以及使用有硫酸之剝離 處理來去除上述光阻遮罩。 其次，如圖2C所示，藉由4〇{rc〜8〇(rc左右之電漿氮化 法，於數位電路元件區域44之表面，以2 nm〜4 nm左右之 膜厚形成氮化矽膜47。此時，於已形成於類比電路元件區 域45之氧化石夕膜46之表面’同樣以1 nm〜2 nm左右之深度 導入有氮，形成氮氧化矽膜48。以下，將表面導入有氮之 整個氧化矽膜46稱作氮氧化矽膜48。 其次，如圖2D所示，以250°C〜350°C左右之溫度，藉由 ALD (Atomic Layer Deposition，原子層沈積）法或者]^-CVD (Low Pressure Chemical Vapor Deposition，低壓化學 氣相沈積）法，以2 nm〜3 nm左右之膜厚堆積由HfA10x等而 構成之高介電體薄膜層49。進而，使用LP-CVD法，以1〇〇 nm左右之膜厚堆積之後會作為閘極電極之多晶矽薄膜層 5〇。本實施形態中，將上述多晶矽薄膜層50用作構成導電 性電極之材料之一例，但亦可於該導電性電極中使用非晶 質矽薄膜或金屬薄膜等。繼而，分別於數位電路元件區域 44與類比電路元件區域45上形成閘極電極形成用之光阻遮 128042.doc -16 - 200843087 罩51 〇 其次，如圖2Ε所示，將上述光阻遮罩5〗作為遮罩，藉由 使用有Ch、HBr或〇2等蝕刻氣體之乾式蝕刻，對多晶石夕薄 膜層50進行蝕刻，直至高介電體薄膜層49之上表面露出為 止。進而，使用對高介電體材料進行濕式蝕刻之藥液，選 擇性地去除高介電體薄膜層49。此處，作為上述藥液，可 使用含有氟化合物之藥液或者熱濃硫酸。或者，為了去除 尚介電體薄膜層49，可使用利用有eh以及HBr等氣體之乾 式蝕刻法。繼而，使用磷酸來選擇性地去除上表面已露出 的氮化矽膜47。繼而，使用氟酸來選擇性地去除上表面已 露出的氮氧化矽膜48。如此，數位電路元件區域44之閘極 電極圖案與類比電路元件區域45之閘極電極圖案係藉由同 一光微影步驟而形成。 其次，最終於LDD區域進行離子注入之後，如圖21?所 示，藉由LP-CVD法使氮化碎膜以50 nm左右之膜厚堆積， 藉由對該氮化石夕膜進行餘刻而於閘極電極側壁形成侧壁 52。進而，於源極區域以及汲極區域進行離子注入之後， 藉由1000°C左右之RTA法進行活化。繼而，於閘極電極、 源極電極以及沒極電極之表面形成梦化物層5 3。進而，於 整個面上堆積蝕刻阻止膜之氮化矽膜54，並於該氮化石夕膜 54之上層堆積氧化矽膜系之層間絕緣膜55，之後，藉由 CMP法等使表面平坦化。 而且，藉由光微影法與乾式蝕刻法使接觸孔開口，於該 接觸孔内堆積障壁膜之TiN與鎮膜56，並使層間絕緣膜55 128042.doc -17- 200843087 之表面與鶴膜5 6之表面以成為ρη 一 取馬同一鬲度之方式平坦化。繼 而，堆積作為金屬配線層之叙膜，藉由光微影法與乾式餘 刻法形成金屬配線層57 ’從而形成本實施形態之半導體裝 置。 =示剖面模式圖，該剖面模式圖表示本實施形態中 之此合裝載有數位電路元件（M〇s電晶體）與類比電路元件 (MOS電日日體）之石夕基板上的各元件之閘極絕緣膜構造。再 者，44係數位電路元件區域，45係類比電路元件區域，〇 係氮化矽膜，48係氮氧化矽膜，49係高介電體薄膜層。 如以上所述，上述各實施形態中，可藉由電漿氮化法， 於同一步驟中進行對上述類比電路元件區域25、45之氧化 矽膜26、46之表面之氮導入，以及數位電路元件區域以、 44之氮化矽膜27、47之形成。因此，可藉由同一光微影步 驟’开> 成數位電路元件區域24、44之閘極電極圖案與類比 電路元件區域25、45之閘極電極圖案。其結果，能以較少 之步驟簡單地形成2個MOS半導體元件，從而以較少之步 驟即可提高加工精度，上述2個MOS半導體元件係分別於 具有彼此不同之組成之2個閘極絕緣膜上形成閘極電極圖 案而成。 又，上述類比電路元件區域25、45之氮氧化石夕膜28、 48，係使用電漿氮化法等，藉由於氧化石夕膜26、46之表面 以1 nm〜2 nm左右之深度導入氮而形成。因此，與藉由使 用有N20之熱氧化法來形成氮氧化石夕膜的情形相比，可形 成Ι/f雜訊產生較少之MOS電晶體。 128042.doc -18- 200843087 又，如上所述般，於上述數位電路元件區域24、44上， 形成有對矽基板21、41進行氮化而成的氮化矽膜27、 因此，可形成介電常數較高之絕緣膜，從而與形成氮氧化 矽膜之情形相比，可使洩漏電流為1/1〇以下。 再者，上述各實施形態中，以矽基板21、41上形成氮化 矽膜27、47以及氮氧化矽膜28、48之情形為例加以了說 明。然而，本發明並不限定於此，可於半導體基板上所形 成之矽井上形成氮化矽膜以及氮氧化矽膜。 又，上述各實施形態中，例示了形成M〇s電晶體作為 MOS型半導體元件之情形，但只要具有M〇s型構造即可， 並非限定於電晶體。 【圖式簡單說明】 圖1A係用以說明本發明之半導體裝置之製造方法之剖面 圖。 圖1B係繼圖1A之後的用以說明製造方法之剖面圖。 圖1C係繼圖1B之後的用以說明製造方法之剖面圖。 圖1D係繼圖1C之後的用以說明製造方法之剖面圖。 圖1E係繼圖1D之後的用以說明製造方法之剖面圖。 圖1F係繼圖1E之後的用以說明製造方法之剖面圖。 圖2A係用以說明與圖1A〜圖if不同之半導體裝置之製造 方法之剖面圖。 圖2B係繼圖2A之後的用以說明製造方法之剖面圖。 圖2C係繼圖2B之後的用以說明製造方法之剖面圖。 圖2D係繼圖2C之後的用以說明製造方法之剖面圖。 128042.doc -19- 200843087 圖2E係繼圖2D之後的用以說明製造方法之剖面圖。 圖2F係繼圖2E之後的用以說明製造方法之剖面圖。 圖3 A係表示圖1A〜圖1F所示之本發明之半導體裝置的各 元件之閘極絕緣膜之構造的剖面圖。 圖3B係表示圖2A〜圖2F所示的本發明之半導體裝置之各 元件之閘極絕緣膜之構造的剖面圖。 圖3 C係表示先前之半導體裝置的各元件之閘極絕緣膜之 構造的面圖。 圖4A係用以說明先前之半導體裝置之製造方法 ^ 呵Μ面 圖。 圖4B係用以說明圖4A之後的製造方法之剖面圖。 圖4C係用以說明圖4B之後的製造方法之剖面圖。 圖4D係用以說明圖4C之後的製造方法之剖面圖。 【主要元件符號說明】 21、41 矽基板 22、42 元件分離區域 23、43 元件形成區域 24 〜44 數位電路元件區域 25、45 類比電路元件區域 26、46 氧化矽膜 27 、 33 、 47 、 54 氮化矽膜 28、48 氮氧化矽膜 29、50 多晶石夕薄膜層 30、51 光阻遮罩 128042.doc •20- 200843087 31、52 側壁 32、53 矽化物層 34、55 層間絕緣膜 35、56 嫣膜 36 > 57 金屬配線層 49 高介電體薄膜層 128042.doc -21 -The mask selectively performs ion implantation on the digital circuit element region 44 and the analog circuit element region C, respectively. As shown in Fig. 2, the person is in the above-mentioned analog circuit element region c. The film thickness around nm forms oxygen cut (10). This oxide oxide was formed as follows. That is, a ruthenium oxide film is formed on the surface of the element formation region 43 using 7 〇 (rc~i〇〇(rc left 128042.doc -15-200843087 right thermal oxidation method). Here, in order to form an oxygen-cut film layer The thermal oxidation method is used as an example, and an RTQ method or an i-electrode oxidation method may be used. Secondly, a photoresist mask pattern covering the analog circuit element region 45 is formed, and a gas acid having a concentration of about 1% is used to remove the formation as an opening. The yttrium oxide film on the portion of the digital circuit component region. Thus, only the yttrium oxide film 46 remains on the analog circuit device region 45. Then, it is removed by ashing treatment of oxygen plasma and using a stripping treatment with sulfuric acid. The photoresist mask is as follows. Next, as shown in FIG. 2C, by 4 〇 { rc 〜 8 〇 (the plasma nitridation method of about rc, on the surface of the digital circuit device region 44, about 2 nm to 4 nm The tantalum nitride film 47 is formed in a film thickness. At this time, nitrogen is introduced at a depth of about 1 nm to 2 nm on the surface 'of the oxidized stone film 46 formed on the analog circuit element region 45 to form a hafnium oxynitride film 48. Hereinafter, the entire surface of the yttrium oxide film 46 is introduced into the surface. It is called yttrium oxynitride film 48. Next, as shown in Fig. 2D, at a temperature of about 250 ° C to 350 ° C, by ALD (Atomic Layer Deposition) method or [^-CVD (Low Pressure Chemical) Vapor Deposition, low-pressure chemical vapor deposition method, depositing a high dielectric thin film layer 49 composed of HfA10x or the like at a film thickness of about 2 nm to 3 nm. Further, using LP-CVD method, about 1 〇〇 nm After the film thickness is deposited, the polysilicon film layer 5 is used as a gate electrode. In the present embodiment, the polysilicon film layer 50 is used as an example of a material constituting the conductive electrode, but a non-conductive electrode may be used. A crystalline germanium film, a metal thin film, etc. Then, a photoresist for forming a gate electrode is formed on the digital circuit element region 44 and the analog circuit device region 45, respectively. 128042.doc -16 - 200843087 Cover 51 Next, as shown in Fig. 2 As shown in the figure, the photoresist mask 5 is used as a mask, and the polycrystalline thin film layer 50 is etched by dry etching using an etching gas such as Ch, HBr or 〇2 until a high dielectric thin film layer is formed. The surface above 49 is exposed Further, the high dielectric thin film layer 49 is selectively removed by using a chemical liquid which is wet-etched with a high dielectric material. Here, as the chemical liquid, a chemical liquid containing a fluorine compound or hot concentrated sulfuric acid can be used. Alternatively, in order to remove the dielectric thin film layer 49, a dry etching method using a gas such as eh or HBr may be used. Then, phosphoric acid is used to selectively remove the tantalum nitride film 47 exposed on the upper surface. Then, fluorine is used. The acid selectively removes the yttrium oxynitride film 48 that has been exposed on the upper surface. Thus, the gate electrode pattern of the digital circuit device region 44 and the gate electrode pattern of the analog circuit device region 45 are formed by the same photolithography step. Next, after the ion implantation is finally performed in the LDD region, as shown in FIG. 21, the nitrided film is deposited by a film thickness of about 50 nm by LP-CVD, by engraving the nitride film. A sidewall 52 is formed on the sidewall of the gate electrode. Further, after ion implantation in the source region and the drain region, activation is performed by an RTA method at about 1000 °C. Then, a dream layer 53 is formed on the surfaces of the gate electrode, the source electrode, and the electrodeless electrode. Further, a tantalum nitride film 54 of an etching stopper film is deposited on the entire surface, and an interlayer insulating film 55 of a hafnium oxide film layer is deposited on the surface of the nitride film 54, and then the surface is flattened by a CMP method or the like. Moreover, the contact hole is opened by photolithography and dry etching, and the TiN and the interlayer film 56 of the barrier film are deposited in the contact hole, and the surface of the interlayer insulating film 55 128042.doc -17- 200843087 and the film are coated. The surface of 5 6 is flattened in such a way that it becomes the same degree of ρη. Then, as a film of the metal wiring layer, the metal wiring layer 57' is formed by photolithography and dry etching to form the semiconductor device of the present embodiment. = a cross-sectional pattern diagram showing the components on the Shishi substrate on which the digital circuit component (M〇s transistor) and the analog circuit component (MOS solar cell) are mounted in the present embodiment. Gate insulating film construction. Further, the 44 coefficient bit circuit element region, the 45 series analog circuit element region, the tantalum nitride film, the 48 series yttria film, and the 49 series high dielectric film layer. As described above, in the above embodiments, the introduction of nitrogen into the surfaces of the yttrium oxide films 26 and 46 of the analog circuit element regions 25 and 45 and the digital circuit can be performed in the same step by the plasma nitridation method. The element region is formed of a tantalum nitride film 27, 47 of 44. Therefore, the gate electrode patterns of the digital circuit element regions 24, 44 and the gate electrode patterns of the analog circuit element regions 25, 45 can be formed by the same photolithography step. As a result, it is possible to easily form two MOS semiconductor elements in a small number of steps, thereby improving the processing accuracy in a small number of steps, and the two MOS semiconductor elements are respectively insulated by two gates having different compositions from each other. A gate electrode pattern is formed on the film. Further, the oxynitride films 28 and 48 of the analog circuit element regions 25 and 45 are formed by plasma nitriding or the like by using the surface of the oxidized stone films 26 and 46 at a depth of about 1 nm to 2 nm. Formed by nitrogen. Therefore, compared with the case where the oxynitride film is formed by the thermal oxidation method using N20, Ι/f noise can be formed to generate less MOS transistors. Further, as described above, the tantalum nitride film 27 obtained by nitriding the tantalum substrates 21 and 41 is formed on the above-described digital circuit element regions 24 and 44, so that a dielectric layer can be formed. An insulating film having a high electric constant can cause a leakage current of 1/1 〇 or less as compared with a case where a yttrium oxynitride film is formed. Further, in each of the above embodiments, the case where the tantalum nitride films 27 and 47 and the hafnium oxynitride films 28 and 48 are formed on the tantalum substrates 21 and 41 has been described as an example. However, the present invention is not limited thereto, and a tantalum nitride film and a hafnium oxynitride film may be formed on the well formed on the semiconductor substrate. In the above-described embodiments, the case where the M 〇s transistor is formed as the MOS type semiconductor element is exemplified. However, the M 〇 s type structure is not limited to the transistor. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a cross-sectional view for explaining a method of manufacturing a semiconductor device of the present invention. Fig. 1B is a cross-sectional view subsequent to Fig. 1A for explaining a manufacturing method. Fig. 1C is a cross-sectional view subsequent to Fig. 1B for explaining a manufacturing method. Fig. 1D is a cross-sectional view subsequent to Fig. 1C for explaining a manufacturing method. Fig. 1E is a cross-sectional view subsequent to Fig. 1D for explaining a manufacturing method. Fig. 1F is a cross-sectional view subsequent to Fig. 1E for explaining a manufacturing method. Fig. 2A is a cross-sectional view for explaining a method of manufacturing a semiconductor device different from Fig. 1A to Fig. Fig. 2B is a cross-sectional view subsequent to Fig. 2A for explaining the manufacturing method. Fig. 2C is a cross-sectional view subsequent to Fig. 2B for explaining the manufacturing method. 2D is a cross-sectional view subsequent to FIG. 2C for explaining a manufacturing method. 128042.doc -19- 200843087 FIG. 2E is a cross-sectional view subsequent to FIG. 2D for explaining a manufacturing method. 2F is a cross-sectional view subsequent to FIG. 2E for explaining a manufacturing method. Fig. 3A is a cross-sectional view showing the structure of a gate insulating film of each element of the semiconductor device of the present invention shown in Figs. 1A to 1F. Fig. 3B is a cross-sectional view showing the structure of a gate insulating film of each element of the semiconductor device of the present invention shown in Figs. 2A to 2F. Fig. 3C is a plan view showing the configuration of a gate insulating film of each element of the prior semiconductor device. Fig. 4A is a view for explaining a method of manufacturing a conventional semiconductor device. Fig. 4B is a cross-sectional view for explaining the manufacturing method subsequent to Fig. 4A. Fig. 4C is a cross-sectional view for explaining the manufacturing method subsequent to Fig. 4B. 4D is a cross-sectional view for explaining the manufacturing method subsequent to FIG. 4C. [Main component symbol description] 21, 41 矽 substrate 22, 42 component separation region 23, 43 component formation region 24 to 44 digital circuit component region 25, 45 analog circuit device region 26, 46 yttrium oxide film 27, 33, 47, 54 Tantalum nitride film 28, 48 yttrium oxynitride film 29, 50 polycrystalline film layer 30, 51 photoresist mask 128042.doc • 20- 200843087 31, 52 sidewall 32, 53 bismuth layer 34, 55 interlayer insulating film 35, 56 嫣 film 36 > 57 metal wiring layer 49 high dielectric film layer 128042.doc -21 -

Claims (1)

200843087 十、申請專利範圍： 1 · 一種半導體裝置，其特徵在於包括： 第1MOS型半導體元件，其形成於半導體基板之第1區 域（25 、 45)上；及 第2MOS型半導體元件，其形成於上述半導體基板之 弟2區域（24、44)上；且 上述第1MOS型半導體元件包含：第丨絕緣膜，其包括 使氧化矽膜（26、46)之表面氮化而形成之氮氧化矽膜 (28、48)，及第1導電性電極（29、5〇)，其形成於該第i 絕緣膜上； 上述第2MOS型半導體元件包含：第2絕緣膜，其包括 氮化矽膜（27、47);及第2導電性電極（29、5〇)，其以與 上述第1MOS型半導體元件之上述第〗導電性電極（29、 50)同一步驟形成於該第2絕緣膜上。 2·如請求項1之半導體裝置，其中200843087 X. Patent Application Range: 1 A semiconductor device comprising: a first MOS type semiconductor device formed on a first region (25, 45) of a semiconductor substrate; and a second MOS type semiconductor device formed on the second MOS type semiconductor device The second MOS type semiconductor device includes: a second insulating film including a yttria film formed by nitriding a surface of the yttrium oxide film (26, 46). (28, 48), and a first conductive electrode (29, 5) formed on the ith insulating film, and the second MOS type semiconductor device includes a second insulating film including a tantalum nitride film (27) And a second conductive electrode (29, 5) formed on the second insulating film in the same step as the first conductive electrode (29, 50) of the first MOS type semiconductor device. 2. The semiconductor device of claim 1, wherein 上述半導體基板係形成有矽井之半導體基板（21、41) 或者矽基板； 構成上述第2絕緣膜之上述氮化矽膜（27、4乃，係使上 述半導體基板（21、4丨）之♦井或者上述碎基板之表面氮 化而形成的薄膜。 3·如請求項2之半導體裝置，其中 構成上述第1絕緣膜之上述氮氧化矽臈（28、48)，係於 形成上述氮化矽膜（27、47)時，僅於使上述半導體基板 (21 41)之石夕井或者上述石夕基板之表面氧化而形成的氧 128042.doc 200843087 化矽膜（26、46)之表面，導入氮而形成之薄膜。 4·如請求項3之半導體裝置，其中 上述氮氧化矽膜（28、48)僅於自表面最多至膜厚方向 之一半為止之區域導入有氮。 5_ —種半導體裝置之製造方法，其特徵在於包含如下步 驟： 於形成於半導體基板（21、41)之矽井或者矽基板之第i 區域（25、45)上，形成氧化矽膜（26、46); 與於形成於上述半導體基板（21、41)上之矽井或者上 述石夕基板之第2區域（24、44)之表面導入氮，於上述第2 區域（24、44)上形成氮化矽膜（27、47)的同時，於自上 述第1區域（25、45)上之氧化矽膜（26、46)之表面至丨nm 以上且2 nm以下之珠度為止之區域導入氮，形成氮氧化 矽膜（28、48);及 於上述第1區域（25、45)之氮氧化矽膜（28、48)上與上 述第2區域（24、44)之氮化矽膜（27、47)上，形成導電性 電極（29、50)。 6·如請求項5之半導體裝置之製造方法，其中 上述第2區域（24、44)上之上述氮化矽膜（27、47)之形 成’係藉由於上述第2區域（24、44)上露出之石夕與經活化 之氮之反應而形成。 128042.docThe semiconductor substrate is formed with a semiconductor substrate (21, 41) or a germanium substrate; and the tantalum nitride film (27, 4) constituting the second insulating film is made of the semiconductor substrate (21, 4) A thin film formed by nitriding the surface of the well or the above-mentioned broken substrate. The semiconductor device according to claim 2, wherein the arsenic oxynitride (28, 48) constituting the first insulating film is formed by the nitriding. In the case of the ruthenium film (27, 47), the surface of the ruthenium film (26, 46) of the oxygen 128042.doc 200843087 formed only by oxidizing the surface of the Si Xijing or the shishan substrate of the semiconductor substrate (21 41), A semiconductor device according to claim 3, wherein the ytterbium oxynitride film (28, 48) is introduced with nitrogen only in a region from the surface up to one-half of the film thickness direction. A method of manufacturing a device, comprising the steps of: forming a hafnium oxide film (26, 46) on an i-th region (25, 45) of a germanium or germanium substrate formed on a semiconductor substrate (21, 41); Formed in the above half Nitrogen is introduced into the surface of the crucible on the bulk substrate (21, 41) or the second region (24, 44) of the above-mentioned Asah substrate, and a tantalum nitride film is formed on the second region (24, 44) (27, 47). At the same time, nitrogen is introduced from the surface of the yttrium oxide film (26, 46) on the first region (25, 45) to a thickness of 丨 nm or more and 2 nm or less to form a ruthenium oxynitride film ( 28, 48); and forming on the tantalum nitride film (28, 48) of the first region (25, 45) and the tantalum nitride film (27, 47) of the second region (24, 44) The method of manufacturing a semiconductor device according to claim 5, wherein the formation of the tantalum nitride film (27, 47) on the second region (24, 44) is caused by The above-mentioned exposed regions of the second region (24, 44) are formed by the reaction of activated nitrogen. 128042.doc
TW97100903A 2007-02-15 2008-01-09 Semiconductor device and method for manufacturing the same TW200843087A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007034309A JP4156008B2 (en) 2007-02-15 2007-02-15 Semiconductor device and manufacturing method thereof

Publications (1)

Publication Number Publication Date
TW200843087A true TW200843087A (en) 2008-11-01

Family

ID=39689815

Family Applications (1)

Application Number Title Priority Date Filing Date
TW97100903A TW200843087A (en) 2007-02-15 2008-01-09 Semiconductor device and method for manufacturing the same

Country Status (3)

Country Link
JP (1) JP4156008B2 (en)
TW (1) TW200843087A (en)
WO (1) WO2008099565A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10438951B2 (en) 2017-03-24 2019-10-08 Asahi Kasei Microdevices Corporation Semiconductor device and manufacturing method thereof
JP7228020B2 (en) * 2017-11-14 2023-02-22 ルネサスエレクトロニクス株式会社 semiconductor equipment

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1197439A (en) * 1997-09-17 1999-04-09 Toshiba Corp Semiconductor device and manufacture thereof
JP2003133550A (en) * 2001-07-18 2003-05-09 Matsushita Electric Ind Co Ltd Semiconductor device and manufacturing method therefor
JP4128396B2 (en) * 2002-06-07 2008-07-30 株式会社ルネサステクノロジ Manufacturing method of semiconductor device
US7183165B2 (en) * 2002-11-25 2007-02-27 Texas Instruments Incorporated Reliable high voltage gate dielectric layers using a dual nitridation process
JP2005136070A (en) * 2003-10-29 2005-05-26 Seiko Epson Corp Method for manufacturing semiconductor device
KR100611784B1 (en) * 2004-12-29 2006-08-10 주식회사 하이닉스반도체 Semiconductor device with multi-gate dielectric and method for manufacturing the same

Also Published As

Publication number Publication date
JP2008198889A (en) 2008-08-28
WO2008099565A1 (en) 2008-08-21
JP4156008B2 (en) 2008-09-24

Similar Documents

Publication Publication Date Title
JP3974507B2 (en) Manufacturing method of semiconductor device
US7635620B2 (en) Semiconductor device structure having enhanced performance FET device
US8022486B2 (en) CMOS semiconductor device
US7754593B2 (en) Semiconductor device and manufacturing method therefor
TWI302729B (en) Semionductor device having cell transistor with recess channel structure and method of manufacturing the same
JP2004072094A (en) Gate structure and method
TW200531169A (en) Semiconductor device and manufacturing method therefor
JP2004253767A (en) Dual gate structure and method for manufacturing integrated circuit having same
TW201017730A (en) Implantation method for reducing threshold voltage for high-k metal gate device
JP5368584B2 (en) Semiconductor device and manufacturing method thereof
JP2011044580A (en) Semiconductor device and method of manufacturing the same
TWI818928B (en) Method for fabricating semiconductor device
JP4505349B2 (en) Manufacturing method of semiconductor device
JP2006202860A (en) Semiconductor device and its manufacturing method
JP2009117621A (en) Semiconductor device and manufacturing method thereof
JP4112404B2 (en) Manufacturing method of semiconductor device
TW200843087A (en) Semiconductor device and method for manufacturing the same
JP5410398B2 (en) Semiconductor device
JP2006013270A (en) Semiconductor device and its manufacturing method
JP2010129926A (en) Semiconductor device and manufacturing method thereof
TW202301443A (en) Semiconductor device and method of manufacturing
JP4589219B2 (en) Manufacturing method of semiconductor device
JP2008117842A (en) Semiconductor device, and method for manufacturing the same
JP2012028562A (en) Method of manufacturing semiconductor device
JP2005294422A (en) Semiconductor device and its manufacturing method