200836316 九、發明說明： 【發明所屬之技術領域】 本么月係有關於-種積體電路封襄之可挽 特別係有關於-種防止薄膜變二 【先前技術】 屬膜覆曰曰封裝基板 ’薄膜覆晶封裝構造 薄膜覆晶封裝基板上 晶封裝基板上的内引 例如熱壓共晶接合 (NCP bonding)與異方 。當晶片接合採用熱 Ο u 在眾多積體電路封裝類型中 (COF)是利用凸塊化晶片接合在_ 並封膠。目前晶片之凸塊與薄膜覆 腳的接合方法亦有多種技術， (Eutectic bonding)、非導電膠接合 性導電膜接合（ACF bonding)等等 壓共晶接合時，可以達到較佳的焊接導電效果。此外 可以沿用既有的捲帶式承載封裝（Tcp)之内引腳接合 (ILB)設備，一熱壓合頭係先加壓並加熱至薄膜覆晶封 裝基板’再壓接至晶片之凸塊，然此一方式會導致薄膜 覆a曰封裝基板受熱產生塌陷（c〇llapSe)或勉曲（warpage) 等變形，使得後續塗膠困難，良率降低。更會影響封裝 構造之品質與後續外引腳接合（〇uter Lead Bonding， OLB)之組裝製程。 如第1圖所示，一種習知之薄膜覆晶封裝基板1 00 係包含一可撓性介電層11 0、複數個引腳1 2 0以及一防 銲層130。該可撓性介電層11〇係具有一上表面111及 一下表面112，且該上表面111係定義有一晶片覆蓋 區。該些引腳120係設置於該可撓性介電層110之該上 5 200836316 表面1 1 1 °該防銲層丨3 〇係形成於該可撓性介電層n 〇 之該上表面111，並局部覆蓋該些引腳120。該防銲層 1 3 0之一開孔1 3 1係略大於該晶片覆蓋區，以顯露該些 引腳120之内端121，以供一晶片21〇之複數個凸塊211 接合。 請參閱第2圖所示，在晶片接合過程中，一晶片21〇 係取放在一可加熱之載台1〇上，並以一熱壓合頭20壓 迫該薄膜覆晶封裝基板100，以將該些引腳120之内端 〇 1 2 1接合至該晶片2 1 0之複數個凸塊2 1 1，該薄膜覆晶 封裝基板1 〇〇會受熱導致塌陷變形，使得該薄膜覆晶封 裝基板1 〇〇與該晶片21 〇之間的間隙會產生不受控制之 不規則變化，甚至該薄膜覆晶封裝基板1 〇〇會直接貼觸 該晶片210。因此，請參閱第3圖所示，在後續的封膠 作業中，一點塗形成之封膠體220將無法藉由毛細作用 填滿該晶片2 1 0與該薄膜覆晶封裝基板1 00之間隙，故 在塌陷變形處會產生填膠缺失之氣泡22 1，使得該封膠 體220在高溫下易於產生爆開之破裂現象。此外，如第 4圖所示，利用習知之薄膜覆晶封裝基板丨〇〇可封裝成 薄膜覆晶封裝構造（COF package)，製程中遭受的加熱 處理將使得該薄膜覆晶封裝基板1 〇 〇在該晶片2 1 0之外 兩側產生翹曲變形，進而導致後續外引腳接合（Outer Lead Bonding, 〇LB)之組裝製程難以順利進行。 【發明内容】 本發明之主要目的係在於提供一種防止薄膜變形之 6 200836316 薄膜覆晶封裝基板，可加強該薄膜覆晶封裝基板之晶片 覆蓋區之支撐性，以避免在晶片接合時該薄膜覆晶封裴 基板產生塌陷之變形。 本發明之次一目的係在於提供一種防止薄膜變形之 薄膜覆晶封裝基板，減輕翹曲之變形，以利外引腳接合 (Outer Lead Bonding，OLB)之組裝製程。200836316 IX. Description of the invention: [Technical field to which the invention pertains] This month, there is a special type of integrated circuit for the sealing of the circuit, which is related to the prevention of the film. [Prior Art] 'Insulation on the on-chip package substrate on the film-on-film package substrate, such as NCP bonding, and the like. When the wafer is bonded using a thermal Ο u in a number of integrated circuit package types (COF), the bumped wafer is bonded to the _ and the sealant. At present, there are various techniques for bonding the bumps of the wafer to the film-covered feet. When the eutectic bonding is performed, such as Eutectic bonding, ACF bonding, etc., a better welding conductive effect can be achieved. . In addition, an existing roll-on-package (Tcp) lead-on-bond (ILB) device can be used, and a thermocompression head is first pressurized and heated to the film flip chip substrate and then crimped to the bump of the wafer. However, this method may cause deformation of the film-coated package substrate by heat (c〇llapSe) or warpage, which makes the subsequent coating difficult and the yield is lowered. It also affects the quality of the package structure and the subsequent assembly process of 〇uter Lead Bonding (OLB). As shown in FIG. 1, a conventional film flip chip package substrate 100 includes a flexible dielectric layer 110, a plurality of pins 120, and a solder resist layer 130. The flexible dielectric layer 11 has an upper surface 111 and a lower surface 112, and the upper surface 111 defines a wafer footprint. The pins 120 are disposed on the upper surface of the flexible dielectric layer 110. The surface of the flexible dielectric layer n is formed on the upper surface 111 of the flexible dielectric layer n 1 And partially covering the pins 120. One of the solder masks 1 3 0 is slightly larger than the wafer footprint to expose the inner ends 121 of the pins 120 for bonding a plurality of bumps 211 of a wafer 21 . Referring to FIG. 2, in the wafer bonding process, a wafer 21 is placed on a heatable stage 1 and the film flip chip 20 is pressed by a thermal bonding head 20 to Bonding the inner end 〇1 2 1 of the pins 120 to the plurality of bumps 2 1 1 of the wafer 2 1 0, the film flip-chip package substrate 1 is thermally deformed to cause collapse deformation, so that the film flip chip package The gap between the substrate 1 and the wafer 21 turns uncontrolled irregularities, and even the thin film flip chip substrate 1 directly contacts the wafer 210. Therefore, as shown in FIG. 3, in the subsequent sealing operation, the one-step forming encapsulant 220 will not be able to fill the gap between the wafer 210 and the film flip-chip substrate 100 by capillary action. Therefore, the bubble 22 1 which is missing in the glue is generated at the collapse deformation, so that the sealant 220 is prone to bursting at a high temperature. In addition, as shown in FIG. 4, the conventional film-wrapped package substrate can be packaged into a film-on-film package structure (COF package), and the heat treatment subjected to the process will cause the film to be on-chip package substrate 1 The warpage deformation occurs on both sides of the wafer 210, which further causes the subsequent assembly process of the Outer Lead Bonding (〇LB) to be difficult to proceed smoothly. SUMMARY OF THE INVENTION The main object of the present invention is to provide a 610336316 film flip-chip package substrate for preventing deformation of a film, which can enhance the support of the wafer cover area of the film flip chip package substrate, so as to avoid the film cover during wafer bonding. The crystal-sealed germanium substrate is deformed by collapse. A second object of the present invention is to provide a thin film flip chip package substrate for preventing deformation of a film, which can reduce warpage deformation and to be assembled by an Outer Lead Bonding (OLB) process.
U 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。依據本發明，一種防止薄膜變形之薄膜覆 曰曰封裝基板主要包含一可撓性介電層、複數個引腳、一 防銲層以及一強化層（stiffener layer)。該可撓性介電層 係具有一上表面及一下表面，其中該上表面 晶片覆蓋區。該些引腳係設置於該可撓性介電層之該上 表面，其中該些引腳之内端更延伸至該晶片覆蓋區内。 该防銲層係形成於該可撓性介電層之該上表面，以局部 覆蓋該些引腳。該強化層係形成於該可撓性介電層之該 下表面，且對應設置於該晶片覆蓋區。在不同實施例 中’該強化層係可對應設置於該晶片覆蓋區以外之 域。U The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. According to the present invention, a film-covered package substrate for preventing deformation of a film mainly comprises a flexible dielectric layer, a plurality of leads, a solder resist layer and a stiffener layer. The flexible dielectric layer has an upper surface and a lower surface, wherein the upper surface is a wafer footprint. The leads are disposed on the upper surface of the flexible dielectric layer, wherein the inner ends of the pins extend further into the wafer footprint. The solder resist layer is formed on the upper surface of the flexible dielectric layer to partially cover the leads. The strengthening layer is formed on the lower surface of the flexible dielectric layer and correspondingly disposed on the wafer footprint. In various embodiments, the reinforcement layer can be correspondingly disposed outside of the wafer footprint.
本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 H 在前述的薄膜覆晶封裝基板中，該強化層與該防銲 層係可為相同材質。 在前述的薄膜覆晶封裝基板中，該防銲層係可具有 一概呈矩形之開孔，其係對應於該晶片覆蓋區。八 7 200836316 在前述的薄膜覆晶封裝基板中，該強化層之覆蓋面 積係可大於該防銲層之該開孔。 在刖述的薄膜覆晶封裝基板中，該強化層係可由複 數個補強條所組成。 在刖述的薄膜覆晶封裝基板中，該些補強條係大致 平行於該防銲層之開孔之較短邊。 【實施方式】 Ο 1， 依據本t明之第一具體實施例，揭示一種防止薄膜 變形之薄膜覆晶封裝基板。第5圖係為該薄膜覆晶封裝 基板之截面示意圖，第6圖係為該薄膜覆晶封裝基板之 底面局部示意圖。請參閱第5圖所示，該薄膜覆晶封裝 基板300主要包含一可撓性介電層31〇、複數個引腳 320、 一防銲層330以及一強化層34〇。該可撓性介電 層310係具有一上表面311及一下表面312，其中該上 表面311係定義有一晶片覆蓋區313(請參閱第6圖所 示）。其中，該晶片覆蓋區3 13之尺寸係實質對應於一 晶片之尺寸。通常該可撓性介電層3 1 0之材質係可為聚 亞醢胺（polyimide，PI)，而具有良好可撓曲性。在封裝 前’複數個基板可一體形成於一捲帶，以供捲帶式傳輸 進行薄膜覆晶封裝作業。 該些引腳320係設置於該可撓性介電層31〇之該上 表面311，其中該些引腳320之内端321更延伸至該晶 片覆蓋區313内，而呈顯露狀。通常該些引腳32〇之封 貝係為銅’並且應相當地薄以提供適當之可繞曲性。 8 200836316 該防銲層330係形成於該可撓性介電層310之 表面311，以局部覆蓋該些引腳320，能防土該些 3 2 0因外露被污染而短路。該防銲層3 3 0係具有 331，其係對應於該晶片覆蓋區313,以顯露該些 3 20之内端321。通常該防銲層330之開孔331係 於該晶片覆蓋區3 1 3。 配合參閱第6圖所示，該強化層340係形成於 撓性介電層3 1 0之該下表面3 1 2，並對應設置於該 Ο 覆蓋區3 1 3。在本實施例中，該強化層3 4 0係由複 圖案化區塊所組成。該強化層340之形狀係玎用以 該防銲層3 3 0之該開孔3 3 1，以強化該薄膜覆晶封 板300之強度，故在晶片接合過程中可避免受熱之 膜覆晶封裝基板3 0 0的晶片覆蓋區3 1 3產生下沉變 請再參閱第6圖所示，該強化層340之覆蓋面積係 於該防銲層3 3 0之該開孔3 3 1。較佳地，該強化層 與該防銲層3 3 0係可為相同材質，故該強化層3 40The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. H In the above-described thin film flip-chip package substrate, the reinforcing layer and the solder resist layer may be made of the same material. In the foregoing film flip chip package substrate, the solder resist layer may have a substantially rectangular opening corresponding to the wafer footprint. VIII 7 200836316 In the foregoing film flip chip package substrate, the adhesion layer may have a coverage area larger than the opening of the solder resist layer. In the thin film flip chip package substrate described above, the reinforcement layer may be composed of a plurality of reinforcing strips. In the thin film flip chip package substrate described above, the reinforcing strips are substantially parallel to the shorter sides of the openings of the solder resist layer. [Embodiment] Ο 1. According to a first embodiment of the present invention, a film flip chip package substrate for preventing deformation of a film is disclosed. Fig. 5 is a schematic cross-sectional view showing the film flip chip package substrate, and Fig. 6 is a partial schematic view showing the bottom surface of the film flip chip package substrate. Referring to FIG. 5, the thin film flip chip substrate 300 mainly includes a flexible dielectric layer 31, a plurality of pins 320, a solder resist layer 330, and a strengthening layer 34. The flexible dielectric layer 310 has an upper surface 311 defining a wafer footprint 313 (see Figure 6). The size of the wafer footprint 3 13 substantially corresponds to the size of a wafer. Generally, the material of the flexible dielectric layer 310 may be polyimide (PI) and has good flexibility. Before the package, a plurality of substrates can be integrally formed on a tape for tape-and-reel transfer for film flip-chip packaging. The pins 320 are disposed on the upper surface 311 of the flexible dielectric layer 31, wherein the inner ends 321 of the pins 320 extend into the wafer footprint 313 to be exposed. Typically the pins of the pins 32 are copper ' and should be relatively thin to provide adequate resilience. 8 200836316 The solder resist layer 330 is formed on the surface 311 of the flexible dielectric layer 310 to partially cover the pins 320, so as to prevent the soil from being short-circuited due to contamination. The solder resist layer 305 has a 331, which corresponds to the wafer footprint 313 to expose the inner ends 321 of the 316. Typically, the opening 331 of the solder resist layer 330 is attached to the wafer footprint 31. Referring to FIG. 6, the reinforcing layer 340 is formed on the lower surface 3 1 2 of the flexible dielectric layer 310, and is disposed correspondingly to the 覆盖 coverage area 313. In this embodiment, the strengthening layer 300 is composed of complex patterned blocks. The shape of the reinforcing layer 340 is used for the opening 313 of the solder resist layer 303 to strengthen the strength of the film-coated slab 300, so that the film can be prevented from being heated during the wafer bonding process. The wafer cover area 3 1 3 of the package substrate 300 has a sinking change. Referring to FIG. 6 again, the coverage area of the reinforcement layer 340 is applied to the opening 3 31 of the solder resist layer 300. Preferably, the reinforcing layer and the solder resist layer 300 are the same material, so the reinforcing layer 3 40
U ^ 防銲層3 3 0可利用同一製程形成，而不致增加元件 成本與製程複雜度。 請參閱第7圖所示，在内引腳接合過程中，一 410可取放在一載台1〇上，一熱壓合頭2〇會施加 力與加熱該薄膜覆晶封裝基板3 00之該可撓性介 310之該下表面312，使該些引腳32〇之内端321 至該晶片410之複數個凸塊411。而該強化層34〇 成於該可撓性介電層31 該上 引腳 開孔 引腳 稍大 該可 晶片 數個 補償 裝基 該薄 :形。 可大 340 與該 設置 晶片 壓合 電層 鍵合 係形 〇之該下表面312。當該熱壓合 200836316 頭20加壓與加熱於該可撓性介電層31〇之該 312，該強化層340可加強該薄膜覆晶封裝基板 該晶片覆蓋區313的強度，以避免受熱之該薄膜 裝基板3 0 0產生塌陷之變形現象。在後續的封 中，如第8圖所示，一封膠體420能充填在該晶 與該薄膜覆晶封裝基板3 0 0之間，使内部不會產 之問題。 依據本發明之第一具體實施例，該薄膜覆晶 Ο 板300可進一步應用於一薄膜覆晶封裝構造。請 8圖所示，一種薄膜覆晶封裝構造主要包含前述 覆晶封裝基板3 00及一晶片4 ! 〇。該晶片4 ! 〇係 忒基板3 0 〇之該晶片覆蓋區3丨3並電性連接至該 320。在本實施例中，該晶片410係設有複數 4 1 1其係接合至該些引腳320之内端321。該 晶封裝構造並可另包含有一封膠體42〇，例如一 I 化前具高流動性之點塗膠體，其係形成於該晶片 該基板300之間，以密封該些凸塊411以及該 320之裸露内端321，以防止訊號短路與金屬氧 依據本發明之第二具體實施例，揭示另一種 膜變幵v之薄膜覆晶封裝基板。第9圖係為該薄膜 裝基板之底面局部示意圖，第10圖係為該薄膜 裝基板沿第9圖1〇-10線剖切之截面示意圖。請 9及1〇圖所示，該薄膜覆晶封裝基板5〇〇主要 可撓〖生介電層510、複數個引腳52〇、一防銲層 下表面 300於 覆晶封 膠步驟 丨片410 生氣泡 封裝基 參閱第 之薄膜 設置於 些引腳 個凸塊 薄膜覆 種在固 410與 些引腳 化。 防止薄 覆晶封 覆晶封 參閱第 包含一 53 0以 10 200836316 及一強化層540。該可撓性介電層510係具有一上表面 511及一下表面512，其中該上表面511係定義有一晶 片覆蓋區513。該些引腳520係設置於該可撓性介電層 510之該上表面511，其中該些引腳520之内端521更 延伸至該晶片覆蓋區513内（請參閱第9圖所示）。 該防銲層530係形成於該可撓性介電層51〇之該上 表面511，以局部覆蓋該些引腳52〇，能防止該些引腳 5 2 0因外露被污染而短路。該防銲層5 3 〇係可具有一開 〇 孔531，其係對應且稍大於該晶片覆蓋區513。該強化 層5 40係形成於該可撓性介電層51〇之該下表面512， 並對應没置於該晶片覆蓋區513。請再參閱第9圖所 示，在本實施例中，該強化層540係可由複數個補強條 541所組成。該防銲層53〇之開孔531係可概呈矩形， 該些補強條541係大致平行於該防銲層530之開孔531 之較短邊。 I 因此’該強化層540對該薄膜覆晶封裝基板5〇〇之 晶片覆蓋區5 1 3提供更為強化的支撐作用，使得該薄膜 覆晶封裝基板5〇〇之晶片覆蓋區513不易於晶片接合過 程中產生塌陷之變形現象。此外，於封膠製程中，可使 得封膠體均句地填入至晶片與該薄膜覆晶封裝基板 之間，不會發生氣泡。 依據本發明之第三具體實施例，揭示另一種防止 膜變形之薄膜覆晶封裝基板，能減少薄膜覆晶封穿構& (COF package)產生翹曲之變形。請參閱第u ^ ^ 7f\ ， 200836316 該薄膜覆晶封裝基板600主要包含一可撓性介電層 610、複數個引腳62〇以及一強化層630 °該可撓性介 電層610之上表面係定義有一晶片覆蓋區611’作為晶 片設置區域。該可撓性介電層6 1 0在兩傳輸侧且在封裝 單元之外的部位可形成有複數個等距排列之鍵齒孔 612 ° 該些引腳620係設置於該可撓性介電層610之該上 表面，故以虛線繪示。其中’每一引腳620係具有一内 Ο 端621(或稱内引腳）與一外端622(或稱外引腳）。該些内 端621更延伸至該晶片覆蓋區611内且外露在一防銲層 之開口，以供接合一晶片之凸塊（圖未繪出）。一防銲層 係形成於該可撓性介電層6 1 0之上表面，以局部覆蓋該 些引腳620。該強化層630係形成於該可撓性介電層610 之一下表面，且對應設置於該晶片覆蓋區6 1 1以外之區 域’當使用該薄膜覆晶封裝基板封裝成薄膜覆晶封裝產 q 品時’能用以減輕該可撓性介電層610產生之翹曲變 形。更具體說明之，該強化層63〇係具有一開孔613，其 係對應並稍大於該晶片覆蓋區011。在本實施例中，該強 化層630係為框條形。較佳地，該強化層63〇係可具有複數 個補強條631，其係對應該些引腳620之外端622 ,能減輕 X可撓1± ;丨電層6丨〇之兩外接合側之翹曲變形，以避免 影響後續外引腳接合（OLB)製程。 依據本發明之第四具體實施例，揭示另一種防止薄 、I形之薄膜覆晶封裝基板，能減少翹曲之變形。請參 12 200836316 閱第12圖所示，該薄膜覆晶封裝基板700主要包含一 可撓性介電層7 1 0、複數個引腳（圖未繪出）以及一強化 層720。該可撓性介電層710之_上表面係定義有一晶 片覆蓋區711。該可撓性介電層710在兩傳輸側且在封 裝單元之外的部位可形成有複數個等距排列之鏈齒孔 7 1 2。該可撓性介電層7 1 0之上表面係設置該些引腳與 一防銲層。而該強化層720係形成於該可撓性介電層 7 1 〇之一下表面，且對應設置於該晶片覆蓋區7丨丨以外 D 之區域。藉此，減少該可撓性介電層710之翹曲變形現 象。在本實施例中，該強化層720係具有一開孔721，對 應於該晶片覆蓋區711，在一封装單元之其餘下表面則被該 強化層720佔據，故該強化層72〇係覆蓋於該可撓性介電層 71〇之下表面中對應於該晶片覆蓋區711以外之其餘表面。 該強化層720係可為一防銲材料。 以上所述’僅是本發明的較佳實施例而已，並非對 ◎ 本^月作任何形式上的限制，雖然本發明已以較佳實施 例揭路如上，然而並非用以限定本發明，任何熟悉本專 業的技術人員，在不脫離本發明技術方案範圍内，當可 ^用上述揭不的技術内容作出些許更動或修飾為等同 ，化的等效實施例，但凡是未脫離本發明技術方案的内 : 據本^明的技術實質對以上實施例所作的任何簡 單仏改等同變化與修飾，均仍屬於本發明技術方案的 範圍内。 【圖式簡單說明】 13 200836316 第1圖：習知薄膜覆晶封裝基板之截面示意圖。 第2圖：習知薄膜覆晶封裝基板與晶片接合時產生塌陷 變形之截面示意圖。 第3圖：習知薄膜覆晶封裝基板應用於一薄膜覆晶封裝 構造之截面示意圖。 第4圖：習知薄膜覆晶封裝基板應用於一薄膜覆晶封裝 構造之產生翹曲變形之側面示意圖。 第5圖：依據本發明之第一具體實施例，一種防止薄膜 〇 變形之薄膜覆晶封裝基板之截面示意圖。 第6圖：依據本發明之第一具體實施例，該薄膜覆晶封 裝基板之底面局部示意圖。 第7圖：依據本發明之第一具體實施例，該薄膜覆晶封 裝基板與晶片接合時之截面示意圖。 第8圖：依據本發明之第一具體實施例，使用該薄膜覆 晶封裝基板之一種薄膜覆晶封裝構造之截面 示意圖。 第9圖：依據本發明之第二具體實施例，另一種防止薄 膜變形之薄膜覆晶封裝基板之底面局部示意 圖。 第1 0圖：依據本發明之第二具體實施例，該薄膜覆晶 封裝基板沿第 9圖1 0-1 0線剖切之截面示意 圖。 第11圖··依據本發明之第三具體實施例，另一種防止 薄膜變形之薄膜覆晶封裝基板之底面示意圖。 14 200836316The U ^ solder mask 3 3 0 can be formed using the same process without increasing component cost and process complexity. Referring to FIG. 7 , during the internal pin bonding process, a 410 can be placed on a stage 1 , and a thermal bonding head 2 施加 applies force and heats the film flip chip substrate 300 . The lower surface 312 of the flexible dielectric 310 is such that the inner ends 321 of the pins 32 are folded to the plurality of bumps 411 of the wafer 410. The reinforcing layer 34 is formed on the flexible dielectric layer 31. The upper pin has a slightly larger opening, and the wafer has a plurality of compensation bases. The lower surface 312 can be bonded to the set of wafers to bond the electrical layer. When the heat-pressed 200836316 head 20 is pressed and heated to the 312 of the flexible dielectric layer 31, the strengthening layer 340 can strengthen the strength of the wafer-covered area 313 of the film-coated package substrate to avoid heat. The film-mounted substrate 300 has a deformation phenomenon of collapse. In the subsequent sealing, as shown in Fig. 8, a colloid 420 can be filled between the crystal and the film flip chip substrate 300, so that the inside does not cause a problem. According to the first embodiment of the present invention, the thin film flip chip 300 can be further applied to a thin film flip chip package structure. As shown in FIG. 8, a thin film flip chip package structure mainly includes the above flip chip package substrate 300 and a wafer 4 〇. The wafer 4 〇 the substrate 30 〇 the wafer footprint 3 丨 3 and is electrically connected to the 320. In the present embodiment, the wafer 410 is provided with a plurality of 411 connected to the inner ends 321 of the pins 320. The crystal package structure may further comprise a gel 42 〇, such as a high-flow dot-coating gel, which is formed between the substrate 300 of the wafer to seal the bumps 411 and 320. The bare inner end 321 is used to prevent signal short circuit and metal oxygen. According to the second embodiment of the present invention, another film-varnished package substrate is disclosed. Fig. 9 is a partial schematic view showing the bottom surface of the film-mounted substrate, and Fig. 10 is a schematic cross-sectional view of the film-mounted substrate taken along line 〇10-10 of Fig. 9. As shown in FIG. 9 and FIG. 1 , the thin film flip chip substrate 5 〇〇 is mainly capable of flexing the dielectric layer 510 , the plurality of pins 52 , and the under surface of the solder resist layer 300 in the flip chip sealing step. The 410 bubble encapsulation base is referred to as the first film disposed on some of the pins and the bump film is coated on the solid 410 with some pins. To prevent the thin-film seal from covering the crystal seal, refer to Section 530 to 10 200836316 and a reinforcement layer 540. The flexible dielectric layer 510 has an upper surface 511 and a lower surface 512, wherein the upper surface 511 defines a wafer footprint 513. The pins 520 are disposed on the upper surface 511 of the flexible dielectric layer 510, wherein the inner ends 521 of the pins 520 extend into the wafer footprint 513 (see FIG. 9). . The solder resist layer 530 is formed on the upper surface 511 of the flexible dielectric layer 51 to partially cover the pins 52 〇 to prevent the pins 52 to be short-circuited due to contamination. The solder resist layer 5 3 may have an opening 531 corresponding to and slightly larger than the wafer footprint 513. The reinforcing layer 540 is formed on the lower surface 512 of the flexible dielectric layer 51 and is not disposed in the wafer footprint 513. Referring to FIG. 9 again, in the embodiment, the reinforcing layer 540 may be composed of a plurality of reinforcing strips 541. The openings 531 of the solder resist layer 53 are substantially rectangular, and the reinforcing strips 541 are substantially parallel to the shorter sides of the openings 531 of the solder resist layer 530. Therefore, the strengthening layer 540 provides a more intensive supporting effect on the wafer covering area 513 of the film flip chip substrate 5, so that the wafer covering area 513 of the film flip chip substrate 5 is not easy to be wafer. Deformation occurs during the joining process. In addition, in the encapsulation process, the encapsulant can be uniformly filled between the wafer and the film flip chip substrate without air bubbles. According to the third embodiment of the present invention, another film flip-chip package substrate for preventing deformation of the film is disclosed, which can reduce the warpage deformation caused by the film over-molding & COF package. Please refer to page u ^ ^ 7f \ , 200836316. The film flip chip package substrate 600 mainly comprises a flexible dielectric layer 610 , a plurality of leads 62 〇 and a reinforcing layer 630 ° above the flexible dielectric layer 610 . The surface system defines a wafer footprint 611' as a wafer placement area. The flexible dielectric layer 610 may be formed with a plurality of equally spaced keyholes 612 on the two transmission sides and outside the package unit. The pins 620 are disposed on the flexible dielectric. The upper surface of layer 610 is shown in dashed lines. Wherein each pin 620 has an inner end 621 (or inner pin) and an outer end 622 (or outer pin). The inner ends 621 extend into the wafer footprint 611 and are exposed to openings in a solder mask for bonding bumps of a wafer (not shown). A solder mask layer is formed on the upper surface of the flexible dielectric layer 610 to partially cover the leads 620. The reinforcing layer 630 is formed on a lower surface of the flexible dielectric layer 610 and correspondingly disposed in a region other than the wafer covering region 161. When the thin film flip-chip package is used for packaging, the film is packaged into a thin film flip chip package. The product can be used to reduce the warpage deformation generated by the flexible dielectric layer 610. More specifically, the reinforcing layer 63 has an opening 613 which corresponds to and is slightly larger than the wafer footprint 011. In the present embodiment, the strengthening layer 630 is in the form of a frame strip. Preferably, the reinforcing layer 63 can have a plurality of reinforcing strips 631 corresponding to the outer ends 622 of the pins 620, which can reduce the X-flexible 1±; the two outer sides of the tantalum layer 6丨〇 The warp is deformed to avoid affecting the subsequent outer pin bonding (OLB) process. According to the fourth embodiment of the present invention, another thin film, I-shaped thin film flip chip substrate is disclosed, which can reduce warpage deformation. Referring to FIG. 12, which is shown in FIG. 12, the film flip chip package substrate 700 mainly includes a flexible dielectric layer 710, a plurality of pins (not shown), and a strengthening layer 720. The upper surface of the flexible dielectric layer 710 defines a wafer footprint 711. The flexible dielectric layer 710 may be formed with a plurality of equally spaced sprocket holes 7 1 2 on the two transmission sides and outside the package unit. The pins and the solder resist layer are disposed on the upper surface of the flexible dielectric layer 710. The reinforcing layer 720 is formed on a lower surface of the flexible dielectric layer 71 1 , and correspondingly disposed in a region other than the wafer covering area 7 D D. Thereby, the warpage deformation of the flexible dielectric layer 710 is reduced. In this embodiment, the reinforcing layer 720 has an opening 721 corresponding to the wafer covering area 711, and the remaining lower surface of a package unit is occupied by the reinforcing layer 720, so the reinforcing layer 72 is covered by the reinforcing layer 72. The lower surface of the flexible dielectric layer 71 corresponds to the remaining surface except the wafer footprint 711. The reinforcing layer 720 can be a solder resist material. The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed above by the preferred embodiments, it is not intended to limit the present invention. A person skilled in the art can make some modifications or modifications to the equivalent embodiments, without departing from the technical solution of the present invention, without departing from the technical scope of the present invention. Any simple tampering equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention are still within the scope of the technical solution of the present invention. [Simple description of the figure] 13 200836316 Fig. 1 is a schematic cross-sectional view of a conventional film flip chip package substrate. Fig. 2 is a schematic cross-sectional view showing a collapse deformation of a conventional film flip chip package substrate when bonded to a wafer. Fig. 3 is a schematic cross-sectional view showing a conventional film flip chip package substrate applied to a film flip chip package structure. Fig. 4 is a side view showing the use of a conventional film flip chip package substrate for warpage deformation of a film flip chip package structure. Fig. 5 is a cross-sectional view showing a film-coated package substrate for preventing deformation of a film 依据 according to a first embodiment of the present invention. Figure 6 is a partial schematic view showing the bottom surface of the film-coated package substrate in accordance with a first embodiment of the present invention. Figure 7 is a cross-sectional view showing the film-on-film package substrate bonded to a wafer in accordance with a first embodiment of the present invention. Figure 8 is a cross-sectional view showing a thin film flip chip package structure using the thin film overprint package substrate in accordance with a first embodiment of the present invention. Fig. 9 is a partial schematic view showing the bottom surface of a film-coated package substrate for preventing deformation of a film according to a second embodiment of the present invention. Fig. 10 is a cross-sectional view of the film flip chip substrate taken along line 0-1 0 of Fig. 9, in accordance with a second embodiment of the present invention. Fig. 11 is a schematic view showing the underside of a film-coated package substrate for preventing deformation of a film according to a third embodiment of the present invention. 14 200836316
Cl ο 第1 2圖·依據本發明之第四具體實施例，另一種防止 薄膜變形之薄膜覆晶封裝基板之底面示意圖。 【主要元件符號說明】 1〇載台 20熱壓合頭 1〇〇薄膜覆晶封裝基板 110可撓性介電層111上表面 12()引腳 121內端 130防銲層 131開孔 2 1 〇晶片 211凸塊 220封膠體 221氣泡 300薄膜覆晶封裝基板 31〇可撓性介電層311上表面 3 13晶片覆蓋區 320引腳 321内端 3 3 0防銲層 3 3 1開孔 41 〇晶片 411凸塊 500薄膜覆晶封裝基板 51〇可撓性介電層511上表面 5 13晶片覆蓋區 520引腳 521內端 5 3 0防銲層 5 3 1開孔 540強化層 541補強條 600薄膜覆晶封裝基板 6 1 〇可撓性介電層6 11晶片覆蓋區 11 2下表面 312下表面 340強化層 420封膠體 512下表面 61 2鏈齒孔 15 200836316 6 13開孔 620引腳 621内端 622外端 630強化層 631補強條 700薄膜覆晶封裝基板 710可撓性介電層711晶片覆蓋區 712鏈齒孔 720強化層 721開孔 〇 〇 16Cl ο Figure 1 2 is a schematic view of a bottom surface of another film flip chip substrate for preventing deformation of a film according to a fourth embodiment of the present invention. [Main component symbol description] 1 〇 stage 20 thermocompression head 1 〇〇 film flip chip package substrate 110 flexible dielectric layer 111 upper surface 12 () pin 121 inner end 130 solder resist layer 131 opening 2 1 〇 wafer 211 bump 220 encapsulant 221 bubble 300 film flip chip substrate 31 〇 flexible dielectric layer 311 upper surface 3 13 wafer footprint 320 pin 321 inner end 3 3 0 solder mask 3 3 1 opening 41 〇 wafer 411 bump 500 film flip chip substrate 51 〇 flexible dielectric layer 511 upper surface 5 13 wafer footprint 520 pin 521 inner end 5 3 0 solder mask 5 3 1 opening 540 reinforcement layer 541 reinforcing strip 600 film flip chip substrate 6 1 〇 flexible dielectric layer 6 11 wafer footprint 11 2 lower surface 312 lower surface 340 strengthening layer 420 sealing body 512 lower surface 61 2 chain perforation 15 200836316 6 13 opening 620 pin 621 inner end 622 outer end 630 strengthening layer 631 reinforcing strip 700 film flip chip substrate 710 flexible dielectric layer 711 wafer covering area 712 sprocket hole 720 strengthening layer 721 opening 〇〇 16