200828614 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種固態發光元件（solid-state light- emitting device) ， 特別是 指一種 固態發 光元件 及其製 作方法 〇 【先前技術】 目前影響發光二極體（led)之發光效率值的因素，分別 有内部量子效率（internal quantum efficiency)及外部 (external)量子效率，其中，構成低内部量子效率的主要原 因，則是形成於磊晶膜中的差排量。舉例來說，藍寶石 (sapphire，化學式為Al2〇3)基板與氮化鎵（GaN)系材料兩者 間存在有晶格不匹配度（lattice mismatch)的問題，因此，在 蠢晶過程中亦同時地構成了大量的貫穿式差排（threading dislocation) 〇 一般而言，於sapphire或碳化矽（SiC)基板上磊製m-V 族氮化物（如：GaN·.·等）磊晶膜時，多半因為sapphire與其 上方蠢晶膜之間的晶格常數差異（lattice constant difference ，簡稱△ a)過大，及兩者間的原子搞合（atomic coupling)相 當地微弱等原因，因此，在sapphire基板上成長蠢晶膜期 間，皿-V族氮化物的晶體方位（crystal orientation)無法正確 地向上延續，並使得Π-V族氮化物中存在有起伏的晶體方 位[即，所謂的馬賽克晶體（mosaic crystal)];其中，晶體方 位圍繞著垂直於基板表面的主軸之轉動方向而起伏變化的 扭轉式（twist)馬賽克晶體，以及晶體方位自一垂直方向的軸 5 200828614 向起伏變化的傾斜式（tilt)馬賽克晶體，最終則成為m-v族 氮化物之磊晶膜中的貫穿式差排。 以現有的技術觀之，大多數是對sapphire基板施予凹 凸化處理藉以使差排產生彎折並降低形成於磊晶膜中的貫 穿式差排。 參閱圖1，一種固態發光元件1，包含：一圖案化 (patterned)藍寶石基板u及一磊製於該圖案化藍寶石基板 11上之以GaN為主的磊晶膜12。該圖案化藍寶石基板n 具有複數相間隔地形成於其一表面且深度是介於〇 5 μηι〜5 μιη之間的等深凹槽m，其中，該磊晶膜12與每一等深凹 槽111之間共同界定複數封閉孔13。該等等深凹槽1丨丨是 利用乾式韻刻法（dry etching)所構成。 开> 成於該圖案化藍寶石基板Η之磊晶膜12主要是藉由 降低其與該圖案化藍寶石基板u的接觸面積，進而使得位 於該等封閉孔13上方的磊晶膜12未產生有差排。該圖案 化藍寶石基板11雖可降低該磊晶膜12内的差排13量，然 而，其表面所形成的等深凹槽U1不僅尺寸過大，且深度皆 相同，因此，可降低該磊晶膜12中之差排13量的貢獻度 有限。 另，參閱圖2，一種固態半導體裝置用之磊晶基板2， 包含·一板本體21、一形成於該板本體21上的緩衝膜22 及複數疊置於該緩衝膜22上的蠢晶膜23。 在该磊晶基板2的製作過程中，於完成第一層磊晶臈 23之後，第一層磊晶膜23的一表面主要是利用濕式蝕刻法 200828614 (we etch ^ ^ 面形成複數深度約細⑽〜5⑽⑽之間的非等深凹槽231 。藉該等非等深凹槽231以降低形成於第_層蟲晶膜23上 之苐一層蟲晶膜23内的差排量。 依此類推地，於完成第二層蠢晶膜23之後，亦對第二 層磊晶膜23的一表面施予蝕刻處理以於第二層磊晶膜Μ 上形成複數非等深凹槽231，藉以進—步地降低形成於第二 層磊晶膜23上之第三層磊晶膜23的差排量。因此，當磊 晶膜23的層數越多’最上方㈣晶膜23内之差排量越低 。該遙晶基板2雖然可解決差排問題，但其所形成的非等 深凹槽231對該等蟲晶膜23之差生f折的貢獻度亦有 限，此外，諸多蝕刻及磊晶等繁複的製程，亦不符製造成 ° 參閱圖3，US 6,504,183揭示一種氮化物半導體之磊晶 成長。US 6,504，183主要是於一藍寶石基板31上形成一高 度约介於1 nm〜10 nm之間的多重核種（multiple rmcleiiSeS)321、322。進一步地，依序於該多重核種321、 322上形成一差排抑制層33及一形成於該差排抑制層33的 磊晶層34。該多重核種321、322主要是分別由不同材質所 構成。藉由不同材質之核種的晶格常數及該多重核楂321、 322與藍寶石基板31間的高度差以調整差排35的形成速度 及方向’並抑制因晶格常數差所致的應力。差排3 5則是被 限制地沿著該多重核種321、322的側邊成長並產生彎折， 因此，降低延伸至該磊晶層34中的差排35量。 7 200828614 US 6,504，183所揭示的内容雖可降低磊晶層34内的差 排35量，但由於該多重核種321、322與藍寶石基板31間 的高度差異變化量不足，因此，差排量過高的問題仍具改 善的空間。 參閱圖4，US 6，936,851揭示一種半導體發光裝置之製 作方法。其主要是利用濕式蝕刻法於一基板41的一表面施 予濕式姓刻以於該基板41形成複數由數微型晶面（micr〇_ facet)所構成的溝槽。進一步地，依序於該基板41上形成一 傾斜層42及一上層區43。該基板41的溝槽（即，微型晶面） 長:供利於優先成核的位置，因此，該傾斜層42主要是自相 鄰微型晶面的接合處顯露出來並於該等溝槽處結合。另， 該上層區43於成長過程中的傾斜成長（incHne(j gr〇wth)已趨 於緩丨哭，因此，該上層區43的一表面已呈現平坦化的狀態 〇 於US 6,936,851所揭示的内容中，其差排主要是朝向 溝槽的中心並向上傳播，其中，呈反向延伸之相近的差排 相遇後合併且朝上延伸。雖然US 6,936,851所揭示的内容 可減少蟲晶膜内的差排量，但此等微型晶面於表面的變化 里仍嫌不足，因此，對於降低磊晶膜内的差排量之貢獻度 亦有限。 .參閱圖5，US 7,033,854揭露一種於藍寶石基板上對 皿—V族氮化物結晶化（cry stallizing)的方法。其主要是於一 C面藍寶石基板51上形成複數深度大於1〇 nm的等深凹槽 511 ’並於該C面藍寶石基板51上磊製一磊晶膜52。該磊 8 200828614 晶膜52具有複數分別填置於該等等深凹槽511内的AlxGale XN晶體Ml、一覆蓋該等Α1χ(}αι_χΝ晶體521及c面藍寶石 基板51的缓衝層522及一覆蓋該緩衝層522的無摻雜 (undoped)GaN 層。 US 7,033,854主要是利用該等等深凹槽511以增加該c 面藍寶石基板（即，Al2〇3)51與該磊晶膜52兩者間原子交互 作用的接觸面積，進而使得該c面藍寶石基板51中的A1 原子可因表面積增加而提昇其向上擴散的機率，並使得上 方之AlxGa^N晶體521是含A1量較高的晶體；另，由於 AlxGai_xN/Sapphire間的晶袼常數差（△ a)是明顯地小於 GaN/sapphire間的晶格常數差，因此，在晶袼不匹配度降低 的情況下，該箏AlxGai』晶體521之馬賽克晶體含量較低 且晶體方位較為均勻化；又，該c面藍寶石基板51上方的 a曰體方位可殳到構成該4等深凹槽5 1 1之複數傾斜表面所 作用的k向約束力（lateral c〇nstrain f〇rce)所限制，因此，藉 該等等深凹槽511以控制晶體方位，進而降低產生馬賽克晶 體的機率；此外’於完成該緩衝^ 522之後，對該緩衝層 522連續升溫並施予退火處理，且利用最終的退火溫度於該 緩衝層522上形成該無摻雜㈣^ 523，藉由此種分段成 長（interruption of growth)而使得該緩衝層似及該無摻雜 GaN層523的晶體方位更為一致。 經前述幾篇先前技術的說明可知，目前大致上是使用 凹凸化基板的技術手段以解決蟲晶膜中差排量過高的問題 。然而’此等凹凸化表面所形成的等深凹槽多呈規則性排 200828614 列，因此，單位面積内所產生的表面起伏之變化性並不顯 著n咸少的差排量亦有限。即便是呈不規則性排列的 非等深凹槽所構成的凹凸化表面，其表面起伏的變化性亦 不夠明顯。因此，蟲晶膜中之差排量過高的問冑，仍有許 多改善的空間。 【發明内容】 因此本發明之目的，即在提供一種固態發光元件。 本發明之另一目的，即在提供一種固態發光元件的製 作方法。 於是，本發明低固態發光元件，包含：一具有一外輪 廓面的基材，及一覆蓋該基材之外輪廓面的半導體化合物 磊晶膜。該外輪廓面具有複數相間隔地向一實質上垂直於 ^基材的第方向凸伸的突出區。每兩相鄰的突出區共同 定義出-向-相反於該第-方向的第二方向凹陷的凹穴區 。該基材之外輪廓面的部分突出區分別具有複數相間隔地 向該第一方向凸伸而出的峰部。每兩相鄰的峰部共同定義 出一向該第二方向凹陷的谷部。 .另，本發明固態發光元件的製作方法，包含以下步驟 〇)於一基材上形成一預定成形膜； (b)對該預定成形膜施予粗化（r〇ughen)處理以使該預定 成形膜形成一粗化表面； ⑷對該粗化表面施予_處理以移除該預定成形膜並 使該基材根據該粗化表面形成一外輪廓面，·及 10 200828614 (d)於該外輪廓面磊製一半導體化合物磊晶膜。 本發明之功效在於，藉由前述基材之突出區的峰部、 谷部及凹陷區所定義的外輪廓面，以增加差排產生彎折的 機率，進而降低磊晶膜内的差排密度並增加固態發光元件 整體的内部量子效率。 【實施方式】 <發明詳細說明> 參閱圖6及^ 7，本發明固態發光元件的一較佳實施例 ’包含：-具有—外輪廓面61的基材6,及—覆蓋該基材 6之外輪廓面61的半導體化合物磊晶膜7。該外輪廓面61 具有複數相間隔地向一實質上垂直於該基材6的第一方向 Υι凸伸的突出區611 ’每兩相鄰的突出區611共同定義出一 向-相反於該第-方向Yl的第二方向γ2凹陷的凹穴區612 。該基材6之外輪廓面61的部分突出區6ιι分別具有複數 相間隔地向該第-方向γ]凸伸而出的峰部613。每兩相鄰 的峰部613共同定義屮—& J疋我出向該第·二方向Υ2凹陷的谷部614 為增加差排產生彎折的機率，主要是經由增加單位面 積内表面起伏㈣化量。因此，較佳地，該基# 6之外輪 廟面61㈣分凹穴區612分別具有複數相間隔地向該第-•方向Yl凸伸而出的峰部6心每兩相鄰的峰部615丘同定 義出-向該第二方向Y2凹陷的谷部61“ 值得—提的是，當該外輪心61的平均⑽度㈣過 0，將使得該半導體化合物蟲晶膜7因未能覆蓋該外輪 11 200828614 廓面61而無法成膜，另，當該外輪廓面61的平均粗糙度 過小時，則無法致使差排產生彎折。因此，更佳地，該等 突出區611及凹穴區612的峰部613、615及谷部614、616 共同界定出該外輪廓面61的平均粗糙度是介於〇.5 nm 〜1000 nm之間。又更佳地，該外輪廓面61的平均粗糙度 是介於0.5 nm〜500 nm之間。 較佳地，該半導體化合物磊晶膜7具有一覆蓋該外輪 廓面61的成核層71及一覆蓋該成核層71的磊晶層72。更 佳地°亥成核層71的成膜溫度是不高於⑻。◦;該蠢晶層 72的成膜溫度是不低於65〇艽。又更佳地，該成核層71的 成膜溫度是介於45(TC——1000。(：之間；該磊晶層72的成膜 溫度是介於650°C〜1300°C之間。 較佳地，該半導體化合物磊晶膜7是由瓜_ v族化合物 所構成，該磊晶層72具有一覆蓋該成核層7 i之第一導電 型半導體721、一局部覆蓋該第一導電型半導體721的多重 里子井722及一覆蓋該多重量子井722的第二導電型半導 體723 ;且本發明低差排密度之固態發光元件更包含兩分別 設置於該第一導電型半導體721及第二導電型半導體723 的接觸電極8。 適用於本發明之ΠΙ族元素是選自B、A卜Ga、In、Ti， 或此專之一組合，適用於本發明之V族元素是選自n、p、 As、Sb、Bi，或此等之一組合；另，適用於本發明的基材6 可以疋呈單晶結構且晶格常數與GaN系材料相近的藍寶石 、碳化矽（SiC)、矽（Si)、氧化辞（ZnO)、砷化鎵（GaAs)、氮 12 200828614 化鎵（GaN)，或呈尖晶石（spinel)結構之鋁酸鎂（MgAi2〇4)。 參閱圖8,本發明固態發光元件的製作方法之一較佳實 施例，包含以下步驟： (a) 於一基材6,上形成一預定成形膜9 ; (b) 對該預定成形膜9施予粗化處理以使該預定成形膜 9形成一粗化表面91 ; (c) 對該粗化表面91施予蝕刻處理以移除該預定成形膜 9並使該基材6’根據該粗化表面91形成一外輪廓面 61，；及 (d) 於該外輪廓面61，磊製一半導體化合物磊晶膜7,。 較佳地，該步驟（b)之粗化處理是選自退火處理 (annealing treatment)、濕式蝕刻、機械研磨（削 lapping)，或噴砂處理（beadbiasting);該步驟（d)之半導體化 合物磊晶膜7,是依序於該基材6，上磊製一覆蓋該外輪廓面 61’的成核層71，並於該成核層71，上磊製一覆蓋該成核層 71’的磊晶層72,；該步驟（d)之磊晶層72，具有一覆蓋該成核 層71’的第一導電型半導體、一局部覆蓋該第一導電型半導 體的多重量子井及一覆蓋該多重量子井的第二導電型半導 體（圖8未示）；且，於該步驟（d)之後更包含一於該第一導電 型半導體及第二導電型半導體上分別形成一接觸電極的步 驟（e)(圖8未示）；更佳地，該步驟（d)之成核層71，及磊晶層 72’的成膜溫度分別是不高於1〇〇〇t：及不低於65〇弋；又更 佳地，該步驟（d)之成核層71，的成膜溫度是介於45〇〇c〜 1000 C之間’該步驟（d)之磊晶層72’的成膜溫度是介於65〇 13 200828614 °C〜13〇〇°c之間。 在一具體例中，該步驟（b)之粗化處理是退火處理，且 該步驟（a)之預定成形膜9於退火處理後是呈壓應力及張應 力其中一者；較佳地，該步驟（a)之預定成形膜9於退火處 理後是呈壓應力；更佳地，該步驟（a)之預定成形膜9是選 自一光阻（photo resistor)材料或一金屬材料；又更佳地，該 步驟（a)之預定成形膜9是選自一金屬材料；適用於本發明 之金屬材料是選自Ni、Ag、A卜Au、Pt、Pd、Zn、Cd、Cu ’或此等之一組合；且在該具體例中，該金屬材料是Ni。 値得一提的是，在該具體例中，當該預定成形膜9的 厚度過大時，於實施退火處理時該預定成形膜9則不易見 有壓應力的作用，反之，當該預定成形膜9的厚度不足時 ’該預定成形膜9於退火處理時雖可因材料本身壓應力的 作用而見有粗化現象，但將因厚度不足而導致該粗化表面 61無法取得充分的起伏變化量；因此，較佳地，該步驟^) 之預定成形膜9的厚度是介於50 nm〜2000 nm之間。 又，當該步驟（b)的退火處理溫度過高時，將使得該預 定成形膜9產生汽化或導致其材料產生變質的問題，反之 ，當該步驟（b)之退火處理溫度過低時，該預定成形膜9之 原子將因無法取得足夠的熱能以產生原子遷移而導致該粗 化表面91之起伏變化量不足；因此，較佳地，該步驟（1))之 退火處理溫度是介於400°C〜1000。(：之間；更佳地，該步 驟（b)之退火處理溫度是介於50(rc〜8〇〇。(：之間；又更佳地 ’該步驟（b)之退火處理溫度是介於60CTC〜750°C之間。 14 200828614 雖然本發明在該具體例中是使用於退火處理時呈壓應 力之金屬材料來做為該預定成形膜9。而値得一提的是，適 用於本發明之呈壓應力的光阻材料，可以是選自SU-8、 BCB、polyimide、EPG-516、AZ-5214，或 DNR-L300-D1 等 光阻材料。舉例來說，本發明亦可於該基材61’上直接依序 地形成一氧化石夕（Si 〇2)層及一 EPG-5 16光阻層以作為一預定 成形膜（圖8未示），並使用蝕刻法移除該預定成形膜以於該 基材6’表面形成該外輪廓面61’。 在另一具體例中，該步驟（b)之粗化處理是噴砂處理， 且該步驟（a)之預定成形膜9是金屬材料；較佳地，該步驟 (b)之喷砂處理所使用的砂粒（bead)是選自氧化鋁（Al2〇3)、碳 化石夕（SiC)、金剛砂（black alumina)、鋼珠（steel shot)、銅珠 (bronze alloy shots)、陶莞石少（ceramic bead)、IS 石少（alumina) 、鋼石樂（stainless shot)、塑膠砂（plastic bead)、核桃砂 (walnut powder)、二氧化石夕（Si〇2)、碳化硼（B4C)，或此等之 一組合，該步驟（a)之預定成形膜9的厚度是介於50 nm〜 5μπι之間，且該步驟（b)之砂粒的粒徑尺寸是介於0.05 μπι〜 500 μιη之間；此外，適用於該另一具體例之步驟（b)的金屬 材料是選自Ni、Cu、Ti、Au、Pt，或此等之一組合；更佳 地，該另一具體之步驟（b)的砂粒之粒徑尺寸是介於3 μιη〜 10 μιη之間。 值得一提的是，當該步驟（b)之喷砂處理所實施的壓力 過大將破損該預定成形膜9，反之，當該步驟（b)之喷砂處理 所實施的壓力不足時，亦將無法達到所欲之4且化效果。因 15 200828614 此，更佳地，該步驟（b)所使用的壓力是介於5 g/cm2〜丨Q kg/cm2 之間。 另，該預定成形膜9與該步驟（b)之一喷砂裝置之噴嘴 (nozzle，圖8未示）的間距是介於20 cm〜30 cm之間。值得 一提的是，該步驟（b)之喷砂裝置的喷嘴與該預定成形膜9 之間距大小僅決定作用於該預定成形膜9之面積大小，對 於該預定成形膜9之粗化表面91的平均粗糙度影響不大， 因此，重點在於該喷嘴與預定成形膜9之間距所構成的噴 砂作用面積，是可覆蓋該預定成形膜9即可。 又，値得一提的是，該步驟（d)的外輪廓面61，是依據該 粗化表面91所構成，為使得該步驟（d)之半導體化合物磊晶 膜7’得以均勻地成膜並使其差排適度地彎折以降低向圖6 所不之第一方向Yi延伸的貫穿式差排密度。因此，較佳地 ，該步驟（b)之粗化表面91的平均粗糙度是介於〇·5 〜 1000 nm之間，且該步驟（〇是使用非等向性（anis〇tr〇pic)蝕 刻法；更佳地，該步驟（b)之粗化表面91的平均粗糙度是介 於0.5 nm〜500 nm之間；且，適用於本發明之非等向性蝕 刻法可以是現有技術中的任何一乾式蝕刻法。 另，適用於本發明談步驟（句之半導體化合物磊晶膜7, 的材質已說明於前述内容中，於此不再多加贅述之。€ 參閱圖9,本發明固態發光元件之製作方法的另一較佳 實施例，包含以下步驟： (A)對一基材6”施予粗化處理以於該基材6，，的一表面 形成一外輪廓面.61，，，粗化處理是選自噴砂處理及 16 200828614 機械研磨其中一者；及 (B)於該外輪廓面61”磊製一半導體化合物磊晶膜7”。 在又一具體例中，該步驟（A)之粗化處理是噴砂處理； 較佳地，該步驟（A)之喷砂處理所使用的砂粒，以及該步驟 (A)之基材6”與一喷砂裝置之喷嘴92的間距，是相同於前 述之該另一具體例的步驟（b)。 值得一提的是，在該又一具體例中，是直接對硬度較 高的基材（如：sapphire)6”施予喷砂處理，當該步驟（A)之砂 粒的粒徑尺寸過小時，該基材將無法取得足夠的撞擊力已 產生適當的粗化效果；另，當該步驟（A)之噴砂處理所實施 的壓力過高或過低時，該外輪廓面61”之平均粗糙度將不適 用於本發明；因此，較佳地，該步驟（A)之砂粒的粒徑尺寸 是介於1 μπι〜500 μηι之間，該步驟（A)所使用的壓力是介 於50 g/cm2〜50 kg/cm2之間，且該步驟（Α)之外輪廓面61” 的平均粗糙度是介於〇·5 nm〜1000 nm之間；又更佳地，該 步驟（A)之外輪廓面61，，的平均粗糙度是介於〇.5 〜500 nm之間。 另，該步驟（B)之半導體化合物磊晶膜7，，是依序於該基 材6”上磊製一覆蓋該外輪廓面61，，的成核層71，;並於該成核 層71”上磊製一覆蓋該成核層71，，的磊晶層72，，；又，該步 驟（B)之成核層71”及磊晶層72，，妁成膜溫度、該步驟⑺）之 半導體化合物蟲晶膜7”的材質、該步驟（B)之蠢晶層72，，的 膜層結構皆相同於前，於此不再多加贅述之。此外，本發 明該又一具體例於該步驟（B)之後，更包含一於該第一導電 17 200828614 型半導體及第二導電型半導體上分別形成一接觸電極的步 驟（C)(圖9未示）。 有關本發明之前述及其他技術内容、特點與功效，在 以下配合參考圖式之三個具體例的詳細說明中，將可清楚 的呈現。 <具體例一> 本發明固態發光元件的製作方法之一具體例是簡單地 說明於下。 首先，利用電子束蒸鍍法（e-beam evaporation)以600°C 的工作溫度於一藍寶石基材上鍍製一厚度約300 nm的Ni 鍍膜；進一步地，對鍍製有Ni鍍膜的藍寶石基材施予600 °C且持溫10分鐘的退火處理，以使Ni鍍膜透過原子遷移 的作用而產生表面粗化。 於完成退火處理後，利用反應式離子餘刻法（reactive ion etching，簡稱RIE)對Ni鍍膜施予蝕刻處理以移除Ni鍍 膜，並使該藍寶石基材根據該Ni鍍膜的粗化表面形成如圖 8所示的外輪廓面61’。參閱圖10，是本發明於完成RIE蝕 刻處理後利用原子力顯微鏡（atomic force microscope，簡稱 AFM)所取得的表面形貌，且經AFM所取得的Ra值約等於 10 nm 〇 後續，於一 MOCVD系統中引入NH3/TMG[(CH3)3Ga] 之流量比等於500的反應源，並於500 mTon*的工作壓力及 至540°C的成膜溫度下形成一 GaN成核層；進一步地，於 該MOCVD系統中引入NH3/TMG等於2500的反應源，並 18 200828614 於200 mT〇rr的工作壓力及⑺贼的成膜溫度下形成一以200828614 IX. Description of the Invention: [Technical Field] The present invention relates to a solid-state light-emitting device, and more particularly to a solid-state light-emitting device and a method of fabricating the same. [Prior Art] Current influence The luminous efficiency values of the light-emitting diodes have internal quantum efficiency and external quantum efficiency, respectively. Among them, the main reason for the low internal quantum efficiency is formed on the epitaxial film. The difference in displacement. For example, there is a problem of lattice mismatch between sapphire (chemical formula Al2〇3) substrate and gallium nitride (GaN)-based material, and therefore, in the process of stupid crystal The ground constitutes a large number of threading dislocations. In general, when epitaxial films of mV-type nitrides (such as GaN, etc.) are deposited on sapphire or tantalum carbide (SiC) substrates, most of them The lattice constant difference (Δ a) between sapphire and the above-mentioned stupid film is too large, and the atomic coupling between them is rather weak, so it grows stupid on the sapphire substrate. During the crystal film, the crystal orientation of the dish-V nitride does not continue upwards correctly, and there is an undulating crystal orientation in the bismuth-V nitride [ie, so-called mosaic crystal] Wherein, the crystal orientation is around a twist mosaic crystal that varies in a direction perpendicular to the direction of rotation of the major axis of the substrate surface, and the axis of the crystal orientation from a vertical direction 5 200828614 A tilted mosaic crystal that changes in undulation, and finally becomes a through-type difference in the epitaxial film of m-v nitride. According to the prior art, most of the sapphire substrates are subjected to a concave convex treatment to bend the difference and reduce the through-type difference formed in the epitaxial film. Referring to Figure 1, a solid state light emitting device 1 includes a patterned sapphire substrate u and a GaN-based epitaxial film 12 deposited on the patterned sapphire substrate 11. The patterned sapphire substrate n has a plurality of equal-depth grooves m formed on a surface thereof at a depth of between μ5 μηι and 5 μηη, wherein the epitaxial film 12 and each of the iso-depth grooves A plurality of closed holes 13 are commonly defined between 111. The deep grooves 1 构成 are formed by dry etching. The epitaxial film 12 formed on the patterned sapphire substrate is mainly formed by reducing the contact area with the patterned sapphire substrate u, so that the epitaxial film 12 located above the closed holes 13 is not generated. Poor row. The patterned sapphire substrate 11 can reduce the amount of the difference 13 in the epitaxial film 12. However, the isobath groove U1 formed on the surface is not only oversized, but also has the same depth, so that the epitaxial film can be lowered. The contribution of the amount of 13 in the 12 is limited. In addition, referring to FIG. 2, an epitaxial substrate 2 for a solid-state semiconductor device includes a board body 21, a buffer film 22 formed on the board body 21, and a plurality of stray films stacked on the buffer film 22. twenty three. In the fabrication process of the epitaxial substrate 2, after the first epitaxial germanium 23 is completed, a surface of the first epitaxial film 23 is mainly formed by wet etching method 200828614 (we etch ^ ^ surface forms a complex depth The non-equivalent grooves 231 between the fine (10) and 5 (10) (10) are used to reduce the difference in the displacement of the layer of the insect crystal film 23 formed on the first layer of the crystal film 23. Similarly, after the second layer of the dummy film 23 is completed, a surface of the second layer of the epitaxial film 23 is also subjected to an etching treatment to form a plurality of non-isocenter grooves 231 on the second layer of epitaxial film ,, thereby The difference in displacement of the third epitaxial film 23 formed on the second epitaxial film 23 is further reduced. Therefore, when the number of layers of the epitaxial film 23 is larger, the difference between the uppermost (four) crystal film 23 The lower the displacement, the retardation problem can be solved by the remote crystal substrate 2, but the non-isocenter groove 231 formed by the crystal substrate 2 has a limited contribution to the difference of the crystal film 23, and more etching and A complicated process such as epitaxy does not conform to manufacturing. Referring to Figure 3, US 6,504,183 discloses epitaxial growth of a nitride semiconductor. US 6,504 183 is mainly formed on a sapphire substrate 31 with a plurality of nucleus (Syle rmcleiiSeS) 321 and 322 having a height of about 1 nm to 10 nm. Further, a difference row is formed on the multiplexed species 321 and 322. a suppression layer 33 and an epitaxial layer 34 formed on the difference suppression layer 33. The multiple core species 321, 322 are mainly composed of different materials. The lattice constants of the nuclear species of different materials and the multiple cores 321 And a height difference between 322 and the sapphire substrate 31 to adjust the formation speed and direction ' of the difference row 35 and to suppress stress caused by a difference in lattice constant. The difference row 3 5 is restricted along the multiple core species 321, 322 The sides grow and bend, thus reducing the amount of the difference 35 extending into the epitaxial layer 34. 7 200828614 US 6,504,183 discloses that the amount of the difference 35 in the epitaxial layer 34 can be reduced, However, since the amount of change in the height difference between the multiplexed species 321 and 322 and the sapphire substrate 31 is insufficient, the problem of excessively high displacement is still improved. Referring to FIG. 4, US 6,936,851 discloses the fabrication of a semiconductor light-emitting device. Method. its main Applying a wet pattern to a surface of a substrate 41 by wet etching to form a plurality of grooves formed by the plurality of microcrystal faces (micr〇_facet). Further, sequentially An inclined layer 42 and an upper layer region 43 are formed on the substrate 41. The groove (i.e., the microcrystalline surface) of the substrate 41 is long: a position for preferential nucleation, and therefore, the inclined layer 42 is mainly from adjacent microcrystals. The joints of the faces are exposed and joined at the grooves. In addition, the upper layer region 43 grows obliquely during growth (incHne(j gr〇wth) has tended to cry, therefore, the upper layer region 43 In a state in which the surface has been flattened, as disclosed in US 6,936,851, the difference is mainly toward the center of the groove and propagates upward, wherein the adjacent rows of oppositely extending opposite sides meet and extend upward. . Although the content disclosed in US 6,936,851 can reduce the difference in the displacement of the insect crystal film, these micro crystal faces are still insufficient in the surface change, and therefore, the contribution to the reduction of the differential displacement in the epitaxial film is limited. . Referring to Figure 5, US 7,033,854 discloses a method of crystallizing a group-V nitride on a sapphire substrate. The main surface of the C-plane sapphire substrate 51 is formed with a plurality of equal-depth grooves 511 ′ having a depth greater than 1 〇 nm and an epitaxial film 52 is formed on the C-plane sapphire substrate 51. The Lei 8 200828614 has a plurality of AlxGale XN crystals M1 respectively filled in the deep grooves 511, and a buffer layer 522 covering the Α1χ(}αι_χΝ crystal 521 and the c-plane sapphire substrate 51 and a buffer layer 522 An undoped GaN layer covering the buffer layer 522. US 7,033,854 mainly utilizes such deep grooves 511 to increase both the c-plane sapphire substrate (i.e., Al2〇3) 51 and the epitaxial film 52. The contact area between the atoms interacts, so that the A1 atom in the c-plane sapphire substrate 51 can increase the probability of upward diffusion due to an increase in surface area, and the upper AlxGa^N crystal 521 is a crystal containing a higher amount of A1; In addition, since the crystal constant difference (Δ a) between AlxGai_xN/Sapphire is significantly smaller than the lattice constant difference between GaN/sapphire, the crystal of the zirconia AlxGai 521 is reduced in the case where the degree of wafer mismatch is lowered. The mosaic crystal content is low and the crystal orientation is relatively uniform; further, the a-body orientation above the c-plane sapphire substrate 51 can reach the k-direction binding force acting on the plurality of inclined surfaces constituting the 4-depth groove 5 1 1 (lateral c〇nstrain f〇rce) Therefore, the deep groove 511 is used to control the crystal orientation, thereby reducing the probability of generating the mosaic crystal; furthermore, after the buffer 522 is completed, the buffer layer 522 is continuously heated and subjected to annealing treatment, and utilized. The final annealing temperature forms the undoped (tetra) 523 on the buffer layer 522. The buffer layer and the crystal orientation of the undoped GaN layer 523 are made by such an interruption of growth. According to the foregoing descriptions of the prior art, it is known that the technique of using a embossed substrate is generally used to solve the problem of excessive displacement in the crystal film. However, the iso-depth formed by the embossed surface The grooves are regularly arranged in the 200828614 column, so the undulation of the surface undulations per unit area is not significant. The difference between the rare and the poor is also limited. Even the irregularities are irregularly arranged. The embossed surface has a variability in surface undulation which is not sufficiently obvious. Therefore, there is still much room for improvement in the case where the difference in the displacement of the insect crystal film is too high. It is an object of the invention to provide a solid state light emitting device. Another object of the present invention is to provide a method for fabricating a solid state light emitting device. Thus, the low solid state light emitting device of the present invention comprises: a substrate having an outer contoured surface And a semiconductor compound epitaxial film covering the outer contour surface of the substrate. The outer contour surface has a plurality of protruding regions which are spaced apart from each other substantially perpendicular to the first direction of the substrate. The protruding regions collectively define a pocket region that is recessed in a second direction opposite to the first direction. The partial protruding regions of the outer contour surface of the substrate respectively have peak portions which are protruded in the first direction at a plurality of intervals. Each two adjacent peaks collectively define a valley that is recessed in the second direction. Further, the method for fabricating the solid-state light-emitting device of the present invention comprises the steps of: forming a predetermined formed film on a substrate; (b) applying a roughening treatment to the predetermined formed film to make the predetermined Forming the film to form a roughened surface; (4) applying a treatment to the roughened surface to remove the predetermined formed film and forming the outer contoured surface according to the roughened surface, and 10 200828614 (d) A semiconductor compound epitaxial film is formed on the outer contour surface. The utility model has the advantages that the outer contour surface defined by the peak portion, the valley portion and the concave portion of the protruding portion of the substrate can increase the probability of occurrence of bending of the difference row, thereby reducing the difference density in the epitaxial film. And increase the internal quantum efficiency of the solid state light-emitting element as a whole. [Embodiment] <Detailed Description of the Invention> Referring to Figures 6 and 7, a preferred embodiment of the solid state light-emitting device of the present invention comprises: - a substrate 6 having an outer contoured surface 61, and - covering the substrate 6 The semiconductor compound epitaxial film 7 of the outer contour surface 61. The outer contour surface 61 has a plurality of spaced apart projections 611 ′ protruding substantially perpendicular to the first direction 该 of the substrate 6 . Each two adjacent protruding regions 611 define a common direction - opposite to the first - A pocket region 612 that is recessed in the second direction γ2 of the direction Y1. The partial protruding regions 6 ι of the outer contour surface 61 of the base material 6 respectively have peak portions 613 which are protruded from the first direction γ] at a plurality of intervals. Each two adjacent peaks 613 define a 屮-& J 疋 出 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷the amount. Therefore, preferably, the base #6 outer wheel temple 61 (four) sub-cavity region 612 has a peak portion 6 protruding from the first-direction Y1 at a plurality of intervals, respectively, and two adjacent peak portions 615 The same as the valley defines a valley 61 that is recessed in the second direction Y2. It is worth mentioning that when the average (10) degree (four) of the outer core 61 is zero, the semiconductor compound crystal film 7 will fail to cover the The outer wheel 11 200828614 has a profile 61 and cannot be formed into a film. Further, when the average roughness of the outer contour surface 61 is too small, the difference row cannot be bent. Therefore, more preferably, the protrusion area 611 and the pocket area The peaks 613, 615 and the valleys 614, 616 of 612 collectively define that the average roughness of the outer contour surface 61 is between 〇.5 nm and 1000 nm. More preferably, the average of the outer contour surface 61 The roughness is between 0.5 nm and 500 nm. Preferably, the semiconductor compound epitaxial film 7 has a nucleation layer 71 covering the outer contour surface 61 and an epitaxial layer 72 covering the nucleation layer 71. More preferably, the film forming temperature of the nucleation layer 71 is not higher than (8). The film formation temperature of the stray layer 72 is not less than 65 Å. More preferably, the film forming temperature of the nucleation layer 71 is between 45 (TC - 1000 Å); the film forming temperature of the epitaxial layer 72 is between 650 ° C and 1300 ° C. Preferably, the semiconductor compound epitaxial film 7 is composed of a melon-v compound having a first conductive semiconductor 721 covering the nucleation layer 7 i and partially covering the first conductive The multiple neutron well 722 of the type semiconductor 721 and the second conductive type semiconductor 723 covering the multiple quantum well 722; and the low-difference density solid-state light-emitting element of the present invention further comprises two first conductive type semiconductors 721 and The contact electrode 8 of the second conductivity type semiconductor 723. The lanthanum element suitable for use in the present invention is selected from the group consisting of B, A, Ga, In, Ti, or a combination thereof, and the group V element suitable for use in the present invention is selected from the group consisting of n , p, As, Sb, Bi, or a combination of these; in addition, the substrate 6 suitable for the present invention may have a single crystal structure and a sapphire, tantalum carbide (SiC) having a lattice constant similar to that of the GaN-based material,矽(Si), oxidized (ZnO), gallium arsenide (GaAs), nitrogen 12 200828614 gallium (GaN), or pointed Magnesium aluminate (MgAi2〇4) of a spinel structure. Referring to Figure 8, a preferred embodiment of a method for fabricating a solid state light-emitting device of the present invention comprises the following steps: (a) forming a substrate 6 The formed film 9 is predetermined; (b) the predetermined formed film 9 is subjected to a roughening treatment to form the roughened surface 91; (c) the roughened surface 91 is subjected to an etching treatment to remove the The formed film 9 is predetermined such that the substrate 6' forms an outer contour surface 61 according to the roughened surface 91; and (d) the outer contour surface 61, a semiconductor compound epitaxial film 7 is formed. Preferably, the roughening treatment of the step (b) is selected from an annealing treatment, a wet etching, a mechanical lapping, or a sand blasting process; the semiconductor compound of the step (d) The crystal film 7 is sequentially formed on the substrate 6, and a nucleation layer 71 covering the outer contour surface 61' is formed on the substrate 7, and a nucleation layer 71 is formed on the nucleation layer 71 to cover the nucleation layer 71'. The epitaxial layer 72, the epitaxial layer 72 of the step (d) has a first conductive semiconductor covering the nucleation layer 71', a multiple quantum well partially covering the first conductive semiconductor, and a cover a second conductivity type semiconductor of the plurality of quantum wells (not shown in FIG. 8); and further comprising, after the step (d), a step of forming a contact electrode on the first conductive type semiconductor and the second conductive type semiconductor ( e) (not shown in FIG. 8); more preferably, the film forming temperature of the nucleation layer 71 and the epitaxial layer 72' of the step (d) are not higher than 1 〇〇〇 t: and not lower than 65, respectively. 〇弋; more preferably, the nucleation layer 71 of the step (d) has a film forming temperature of between 45 〇〇 c and 1000 C. Film-forming temperature (D) of the epitaxial layer 72 'is between 13 200828614 ° 65〇 C~13〇〇 ° c. In a specific example, the roughening treatment of the step (b) is an annealing treatment, and the predetermined formed film 9 of the step (a) is one of a compressive stress and a tensile stress after the annealing treatment; preferably, the The predetermined formed film 9 of the step (a) is subjected to a compressive stress after the annealing treatment; more preferably, the predetermined formed film 9 of the step (a) is selected from a photo resistor material or a metal material; Preferably, the predetermined formed film 9 of the step (a) is selected from a metal material; the metal material suitable for the present invention is selected from the group consisting of Ni, Ag, A, Au, Pt, Pd, Zn, Cd, Cu' or One of the combinations; and in this specific example, the metallic material is Ni. It is to be noted that, in this specific example, when the thickness of the predetermined formed film 9 is excessively large, the predetermined formed film 9 is less likely to exhibit compressive stress during the annealing treatment, and conversely, when the predetermined formed film is formed. When the thickness of 9 is insufficient, the predetermined formed film 9 may be roughened by the action of the compressive stress of the material during the annealing treatment, but the roughened surface 61 may not be sufficiently undulated due to insufficient thickness. Therefore, preferably, the thickness of the predetermined formed film 9 of the step () is between 50 nm and 2000 nm. Moreover, when the annealing treatment temperature of the step (b) is too high, the predetermined formed film 9 is caused to vaporize or cause deterioration of the material thereof. Conversely, when the annealing temperature of the step (b) is too low, The atom of the predetermined formed film 9 will have insufficient amount of fluctuation of the roughened surface 91 due to the inability to obtain sufficient thermal energy to cause atomic migration; therefore, preferably, the annealing temperature of the step (1)) is between 400 ° C ~ 1000. (Between; preferably; the annealing treatment temperature of the step (b) is between 50 (rc~8 〇〇. (: between; and more preferably 'the annealing temperature of the step (b) is Between 60 CTC and 750 ° C. 14 200828614 Although the present invention is a metal material which is subjected to compressive stress during annealing treatment as the predetermined formed film 9 in this specific example, it is preferable to apply The photoresist material of the present invention may be a photoresist material selected from the group consisting of SU-8, BCB, polyimide, EPG-516, AZ-5214, or DNR-L300-D1. For example, the present invention may also A layer of a oxidized stone (Si 〇 2) layer and an EPG-5 16 photoresist layer are sequentially formed on the substrate 61 ′ as a predetermined formed film (not shown in FIG. 8 ), and are removed by etching. The predetermined formed film forms the outer contour surface 61' on the surface of the substrate 6'. In another specific example, the roughening treatment of the step (b) is sand blasting, and the predetermined formed film of the step (a) 9 is a metal material; preferably, the sand used in the sandblasting treatment of the step (b) is selected from the group consisting of alumina (Al2〇3) and carbonized stone (S) iC), black alumina, steel shot, bronze alloy shots, ceramic bead, IS alumina, small shot, plastic bead ), walnut powder, silica dioxide (Si〇2), boron carbide (B4C), or a combination thereof, the thickness of the predetermined formed film 9 of the step (a) is 50 nm~ Between 5 μm, and the particle size of the grit of the step (b) is between 0.05 μm and 500 μm; further, the metal material suitable for the step (b) of the other specific example is selected from the group consisting of Ni and Cu. , Ti, Au, Pt, or a combination thereof; more preferably, the particle size of the sand of the other specific step (b) is between 3 μm and 10 μmη. It is worth mentioning that When the pressure applied by the blasting treatment of the step (b) is too large, the predetermined formed film 9 will be damaged. Conversely, when the pressure applied by the blasting treatment of the step (b) is insufficient, the desired one will not be achieved. And the effect of the effect. Because 15 200828614 Therefore, more preferably, the pressure used in the step (b) is between 5 g / cm 2丨Q kg/cm2. Further, the distance between the predetermined formed film 9 and the nozzle (not shown in Fig. 8) of the blasting device of the step (b) is between 20 cm and 30 cm. It is to be noted that the distance between the nozzle of the blasting apparatus of the step (b) and the predetermined formed film 9 is determined only by the size of the area of the predetermined formed film 9, for the roughened surface 91 of the predetermined formed film 9. The average roughness has little effect, and therefore, the focus is on the blasting area formed by the distance between the nozzle and the predetermined formed film 9, and the predetermined formed film 9 can be covered. Moreover, it is noted that the outer contour surface 61 of the step (d) is formed according to the roughened surface 91, so that the semiconductor compound epitaxial film 7' of the step (d) is uniformly formed into a film. And the difference is moderately bent to reduce the through-difference density extending in the first direction Yi which is not shown in FIG. Therefore, preferably, the average roughness of the roughened surface 91 of the step (b) is between 〇·5 and 1000 nm, and the step (〇 is to use anisotropy (anis〇tr〇pic) Etching method; more preferably, the average roughness of the roughened surface 91 of the step (b) is between 0.5 nm and 500 nm; and the anisotropic etching method suitable for the present invention may be in the prior art. Any of the dry etching methods. Further, the material of the semiconductor compound epitaxial film 7 which is applicable to the steps of the present invention has been described in the foregoing, and will not be further described herein. Referring to Figure 9, the solid state of the present invention Another preferred embodiment of the method for fabricating a light-emitting device comprises the steps of: (A) applying a roughening treatment to a substrate 6" to form a contoured surface 61 on a surface of the substrate 6, , the roughening treatment is selected from the group consisting of sand blasting and mechanical polishing of 16 200828614; and (B) forming a semiconductor compound epitaxial film 7" on the outer contour surface 61". In still another embodiment, the step The roughening treatment of (A) is sandblasting; preferably, the sandblasting treatment of the step (A) is The sand used, and the distance between the substrate 6" of the step (A) and the nozzle 92 of a sand blasting device are the same as the step (b) of the other specific example described above. It is worth mentioning that In another specific example, the substrate having a higher hardness (for example, sapphire) 6" is directly subjected to blasting. When the particle size of the sand of the step (A) is too small, the substrate may not be sufficient. The impact force has produced an appropriate roughening effect; in addition, when the pressure applied by the blasting treatment of the step (A) is too high or too low, the average roughness of the outer contour surface 61" will not be suitable for the present invention; Therefore, preferably, the particle size of the sand particles in the step (A) is between 1 μπι and 500 μηι, and the pressure used in the step (A) is between 50 g/cm 2 and 50 kg/cm 2 . And the average roughness of the contour surface 61" outside the step (Α) is between 〇·5 nm and 1000 nm; and more preferably, the average of the contour surface 61, outside the step (A) The roughness is between 〇.5 and 500 nm. In addition, the semiconductor compound epitaxial film 7 of the step (B) is sequentially on the substrate 6" Extending a nucleation layer 71 covering the outer contour surface 61, and depositing an epitaxial layer 72 covering the nucleation layer 71 on the nucleation layer 71"; (B) the nucleation layer 71" and the epitaxial layer 72, the film formation temperature, the material of the semiconductor compound crystal film 7" of the step (7), and the film of the stray layer 72 of the step (B) The layer structure is the same as the former, and the details are not described herein. Further, after the step (B), the further embodiment of the present invention further includes the first conductive 17 200828614 type semiconductor and the second conductive type semiconductor. A step (C) of forming a contact electrode is separately formed (not shown in Fig. 9). The above and other technical contents, features and effects of the present invention will be apparent from the following detailed description of the specific embodiments of the accompanying drawings. <Specific Example 1> A specific example of the method for producing the solid-state light-emitting device of the present invention will be briefly described below. First, a Ni plating film having a thickness of about 300 nm is plated on a sapphire substrate by an e-beam evaporation method at an operating temperature of 600 ° C; further, a sapphire base plated with a Ni plating film is applied. The material was subjected to an annealing treatment at 600 ° C for 10 minutes to cause surface roughening by the action of atomic migration of the Ni plating film. After the annealing treatment is completed, the Ni plating film is subjected to an etching treatment by reactive ion etching (RIE) to remove the Ni plating film, and the sapphire substrate is formed according to the roughened surface of the Ni plating film. The outer contour surface 61' shown in Fig. 8. Referring to FIG. 10, the surface morphology obtained by the atomic force microscope (AFM) after the RIE etching process is completed, and the Ra value obtained by the AFM is about 10 nm, followed by an MOCVD system. Introducing a reaction source of NH3/TMG[(CH3)3Ga] having a flow ratio equal to 500, and forming a GaN nucleation layer at a working pressure of 500 mTon* and a film formation temperature of 540 ° C; further, in the MOCVD A reaction source with NH3/TMG equal to 2500 is introduced in the system, and 18 200828614 is formed at a working pressure of 200 mT 〇rr and (7) a thief film forming temperature.
GaN為主的磊晶層。 * ,最後，對該具體例之磊晶層施予元件製程及接觸電極 等製作"“壬，進而製得如圖7所示之固態發光元件。在本 發明該具體例t，成核層、蟲晶層、元件製程、接觸電極 並非本發明之技術特徵，m成核n晶層、元件 製程、接觸電極等相關的細節技術，於此不再多加贅述之 <具體例二> 本發明固態發光元件及其製作方法之一具體例二，大 致上疋相同於，亥具體例一，其不同處在於，於該藍寶石基 材上是形成-500 nm厚的Ni鍍膜，並對該具體例二之犯 鍍膜施予喷砂處理。 為使得本發明該具體例二之㈣石基材在完成喷砂處 理及RIE钕刻處理後的外輪廓面得以如圖$所示（即，突出 區1及凹八區612上皆分別形成有峰部…S1 $及谷部 614 616) ’在本發明该具體例二中，噴砂處理用之砂粒是 混合20 _、10 _及5 _之體積比為ι: 1:丨的si〇2粒 子，該具體例二之藍寶石基材與喷砂裳置之喷嘴的間距約 20 cm且該具體例—之噴砂處理所實施的壓力及時間分別 為 100 g/cm^及5秒鐘，y兮目胁λ·， 又該具體例二之藍寶石基材的Ra 值約10 nm。 <具體例三〉 本發明固態發光元件及其製作方法之—具體例三，大 19 200828614 致上是相同於該具體例二，其不同處在於，於該具體例三 之藍寶石基材上是未形成有Ni鍍膜，且該具體例三之噴砂 處理是直接實施於該藍寶石基材上。 在本發明該具體例三中，喷砂處理用之砂粒是混合5〇GaN-based epitaxial layer. * Finally, the specific layer of the epitaxial layer is applied to the device process and the contact electrode, etc., to produce a solid state light-emitting element as shown in Fig. 7. In the specific example t of the present invention, the nucleation layer The insect crystal layer, the component process, and the contact electrode are not the technical features of the present invention, m nucleation n crystal layer, component process, contact electrode, and the like, and the related details are not described herein. [Specific Example 2] One embodiment of the solid-state light-emitting device and the manufacturing method thereof are substantially the same as the first embodiment, and the difference is that a Ni-plated film of -500 nm thickness is formed on the sapphire substrate, and the specific The coating of Example 2 is subjected to sand blasting treatment. The outer contour surface of the (4) stone substrate of the specific example 2 of the present invention after completion of the sand blasting treatment and the RIE engraving treatment is as shown in Fig. $ (i.e., the protruding area 1 and In the concave eight-zone 612, a peak portion...S1 $ and a valley portion 614 616) are respectively formed. In the second specific example of the present invention, the sand blasting sand is mixed with 20 _, 10 _, and 5 _ by volume ι : 1: 〇 si〇2 particles, the specific example of the sapphire base The distance from the nozzle for sandblasting is about 20 cm, and the pressure and time for the sandblasting treatment of this specific example are 100 g/cm^ and 5 seconds, respectively, y兮 胁 λ·, and the specific example 2 The sapphire substrate has an Ra value of about 10 nm. <Specific Example 3> The solid-state light-emitting device of the present invention and the method for fabricating the same, and the specific example 3, the large 19 200828614 is the same as the specific example 2, the difference is that In the sapphire substrate of the specific example 3, the Ni plating film is not formed, and the blasting treatment of the specific example 3 is directly performed on the sapphire substrate. In the third embodiment of the present invention, the sand blasting sand is used. Is mixed 5〇
Km、20 μηι及10 μηι之體積比為1 : 1 : 1的sic粒子，該 具體例二之藍寶石基材與喷砂裝置之喷嘴的間距約Η ^历， 且該具體例三之喷砂處理所實施的壓力及時間分別為2The volume ratio of Km, 20 μηι, and 10 μηι is 1:1:1 sic particles, and the spacing between the sapphire substrate of the specific example 2 and the nozzle of the sand blasting device is about Η, and the specific example 3 is sandblasted. The pressure and time implemented are 2
Kg/cm2及60秒鐘，又該具體例三之藍寶石基材的Ra值約 15 nm。 本發明主要是藉由如圖6所示的突出區611及凹穴區 612之峰部613、615及谷部614、616，以提升該外輪廓面 61於單位面積内的起伏變化量，並使得提供差排產生彎折 的位置得以增加。差排於產生彎折後將無法向該第一方向 Y!延伸，因此，有效地降低該磊晶層72内的貫穿式差排密 度並大幅提升固態發光元件的内部量子效率。 綜上所述，本發明固態發光元件及其製作方法，可藉 由前述基材之外輪廓面以增加差排產生彎折的機率，進而 降低磊晶膜内的差排密度並增加固態發光元件整體的内部 量子效率，確實達到本發明之目的。 惟以上所述者，僅為本發明之較佳實施例而已，當不 能以此限定本發明實施之範圍，即大凡依本發明申請專利 範圍及發明說明内容所作之簡單的等效變化與修飾，皆仍 屬本發明專利涵蓋之範圍内。 【圖式簡單說明】 20 200828614 件； 是一局部剖視示意圖 說明習知一種固態發光元 圖2是-局部剖視示意圖，說明習知一種固態半導體 裝置用之蠢晶基板； 圖3是-製作流程示意圖，說明仍6,5()4，183之氮化 物半導體之蠢晶成長； 圖4是一製作流程示意圖，說明仍6,936,851之半導 體發光裝置； 圖5是-局部剖視示意圖，說明仍7，㈣，以所揭示 之冚—V族氮化物的結晶化處理之膜層結構； 圖6疋一正視示意圖，說明本發明固態發光元件的一 較佳實施例之局部放大結構； 圖7是該較佳實施例之正視示意圖； ，圖8疋製作流程示意圖，說明本發明固態發光元件 之製作方法的一較佳實施例； I作^程示意圖，說明本發明固態發光元件 ，作方法的另一較佳實施例；及 、、圖1〇是一 AFM表面形貌圖，說明由本發明之製作方 去的—具體例一所製得之基材的表面形貌。 21 200828614 【主要元件符號說明】 6 ....... •…基材 71 ····· —成核層 69…… •…基材 71，···· •…成核層 6”…… •…基材 71”… •…成核層 61…… •…外輪廓面 72••… …日日層 61，·… …·外輪廓面 72，···· 麻日日層 61”… •…外輪廓面 72，，… 麻日日層 611… •…突出區 721… …·第一導電型半導體 612… •…凹穴區 722… …·多重量子井 613… •…峰部 723… …·第二導電型半導體 614… •…谷部 8…… 接觸電極 615… •…峰部 9…… …·預定成形膜 616… •…谷部 91 ••… •…粗化表面 7…… 半導體化合物日日膜 92"… …·喷嘴 7’ ····· •…半導體化合物猫日日膜 Υι…·· —第 方向 7”…·· 半V體化合物>5«日日膜 Y2····· —第一方向 22Kg/cm2 and 60 seconds, and the sapphire substrate of the specific example 3 has an Ra value of about 15 nm. The present invention mainly enhances the fluctuation amount of the outer contour surface 61 in the unit area by the protruding portion 611 and the peak portions 613, 615 and the valley portions 614, 616 of the pocket portion 612 as shown in FIG. The position at which the differential row is bent is increased. The difference is not extended to the first direction Y! after the bending occurs, so that the through-difference density in the epitaxial layer 72 is effectively reduced and the internal quantum efficiency of the solid-state light-emitting element is greatly improved. In summary, the solid-state light-emitting device of the present invention and the method for fabricating the same can increase the probability of bending in the outer surface of the substrate by increasing the difference in the outer surface of the substrate, thereby reducing the differential discharge density in the epitaxial film and increasing the solid-state light-emitting element. The overall internal quantum efficiency does achieve the object of the present invention. The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are All remain within the scope of the invention patent. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 3 is a partial cross-sectional view illustrating a solid-state illuminating element. FIG. 2 is a partial cross-sectional view showing a conventional stray substrate for a solid-state semiconductor device; The flow diagram shows the stupid crystal growth of the nitride semiconductor of 6,5() 4,183; FIG. 4 is a schematic diagram of the fabrication process, illustrating the semiconductor light-emitting device still in 6,936,851; FIG. 5 is a partial cross-sectional view showing that still 7 (4), a film structure of the disclosed crystallization of the group V nitride; FIG. 6 is a front elevational view showing a partially enlarged structure of a preferred embodiment of the solid state light emitting device of the present invention; A schematic view of a preferred embodiment of the present invention; FIG. 8 is a schematic flow chart showing a preferred embodiment of the method for fabricating the solid-state light-emitting device of the present invention; FIG. 1 is a schematic view showing the solid-state light-emitting device of the present invention, and another method of the method Preferred Embodiments; and FIG. 1A is an AFM surface topography showing the surface topography of the substrate prepared by the manufacturer of the present invention. 21 200828614 [Explanation of main component symbols] 6 ....... •...Substrate 71 ····· — Nucleation layer 69... •...Substrate 71,····•...Nuclear layer 6” ......•...Substrate 71"...•...Nuclear layer 61...•...Outer contour surface 72••...day layer 61,·......outer contour surface 72,····· 麻日日层61 "..." outer contour surface 72,,... 麻日日层611... •... protruding area 721...·first conductive type semiconductor 612... •... pocket area 722...·multiple quantum well 613... •...peak 723... the second conductive type semiconductor 614... • the valley portion 8... the contact electrode 615... • the peak portion 9... the predetermined formed film 616... • the valley portion 91 ••... •...the roughened surface 7 ...... Semiconductor compound day film 92"... nozzle 7' ······...Semiconductor compound cat day film Υι...··—direction 7”...·· 半 V body compound>5«日日Membrane Y2····· — first direction 22