200824250 九、發明說明: 【發明所屬之技術領域】 本發明係有關一種切換式電源轉換器,特別是關於一 種切換式電源轉換器的負載變動補償電路。 【先前技術】 切換式電源轉換器可以達到以較小的尺寸及較佳的 效能產生受調節的輸出電壓。具有變壓器耦合 (transformer-coupled)架構的切換式電源轉換器,例如反馳 (flyback)轉換器與順向(forward)轉換器,其功率輸出端係 藉變壓器與功率輸入端隔離,而功率開關則位於變壓器的 一次侧。脈寬調變(Pulse Width Modulation; PWM)是切換 式電源轉換器用來調節輸出電壓的一種方式,其係偵測輸 出電壓與參考值之間的差值,藉以決定功率開關的責任週 期(duty cycle)。 例如,考慮圖1所示的反驰轉換器100,來自交流電 壓源101提供的交流電壓VAC經電磁干擾(Electro-Magnetic Interference; EMI)濾波器 102 及橋式 整流器 (bridge rectifier) 104濾波及整流後得到具有漣波的直流輸 入電壓Vi,耦合至變壓器TX的一次侧繞組(Primary winding)Lp,功率開關SW與變壓器TX的一次側繞組Lp 串聯,控制器106輸出脈寬調變信號vpwm切換功率開關 SW,以轉換輸入電壓Vi至變壓器TX的二次侧產生輸出 電壓Vo。電阻R3與變壓器TX的一次侧繞組Lp串聯,用 5 200824250 以偵測一次側繞組電流Ip,進而控制脈寬調變信號 的時序(timing)。為了調節輸出電壓Vo,穩壓調整器11〇 及光耦合器(optical coupler)108從變壓器TX的二次側取 迴授彳§號Vfb給控制器106 ’控制器1 〇6根據迴授作號 調節脈寬調變信號Vpwm的責任週期,因而穩定輪出 電壓Vo。 圖2顯示圖1中脈寬調變信號vpwm、一次側繞組電BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching power converter, and more particularly to a load variation compensation circuit for a switching power converter. [Prior Art] A switched power converter can produce a regulated output voltage with a smaller size and better performance. Switched power converters with a transformer-coupled architecture, such as flyback converters and forward converters, whose power output is isolated from the power input by a transformer, while the power switch is Located on the primary side of the transformer. Pulse Width Modulation (PWM) is a way for a switching power converter to regulate the output voltage. It detects the difference between the output voltage and the reference value to determine the duty cycle of the power switch. ). For example, considering the flyback converter 100 shown in FIG. 1, the AC voltage VAC from the AC voltage source 101 is filtered and rectified by an Electro-Magnetic Interference (EMI) filter 102 and a bridge rectifier 104. Then, a DC input voltage Vi having a chopper is obtained, coupled to the primary winding Lp of the transformer TX, the power switch SW is connected in series with the primary winding Lp of the transformer TX, and the controller 106 outputs a pulse width modulation signal vpwm switching power. The switch SW generates an output voltage Vo by converting the input voltage Vi to the secondary side of the transformer TX. The resistor R3 is connected in series with the primary winding Lp of the transformer TX, and the primary winding current Ip is detected by 5 200824250, thereby controlling the timing of the pulse width modulation signal. In order to adjust the output voltage Vo, the regulator regulator 11 and the optical coupler 108 retrieve the authorization Vfb from the secondary side of the transformer TX to the controller 106 'controller 1 〇 6 according to the feedback number The duty cycle of the pulse width modulation signal Vpwm is adjusted, thereby stabilizing the turn-off voltage Vo. Figure 2 shows the pulse width modulation signal vpwm and the primary side winding of Figure 1.
Ip及^^次侧繞組電流Is的波形圖’其中波形2〇〇表干 脈寬調變信號Vpwm,波形202表示一次侧繞組電流Ip, 波形204表示二次側繞組電流Is。在脈寬調變信號vpwm 的責任期間(on-duty period)Ton,功率開關SW導通,_次 侧繞組電流Ip從〇逐漸增加,一次侧繞組Lp因此儲存能 量 aLpXIt 1 VI Γ -Lp(—xTony 2 LpWaveform diagram of Ip and ^^ secondary winding current Is' where waveform 2 is a dry pulse width modulation signal Vpwm, waveform 202 represents primary winding current Ip, and waveform 204 represents secondary winding current Is. During the on-duty period Ton of the pulse width modulation signal vpwm, the power switch SW is turned on, the _ secondary winding current Ip is gradually increased from 〇, and the primary winding Lp thus stores energy aLpXIt 1 VI Γ -Lp (-xTony 2 Lp
Lp 公式 其中’ Ιρκ為一次侧繞組電流Ip的峰值(peak value),V1為 夂侧繞組Lp上的跨壓。在脈寬調變信號Vpwm的非責 住期間(off-duty period)Toff,功率開關SW關閉,儲存在 一次侧繞組Lp的能量傳遞到二次側繞組Ls,因此二次侧 繞組電流Is從峰值ISK逐漸減少到〇。二極體D1用來整流 ’電容Co被充電產生輸出電壓Vo。在非責任期間Toff, 變壓器TX的二次側消耗能量 200824250 V〇xI〇xToff+I〇2xR〇xToff+IsxVfxT〇ff 公式 2 其中,I〇為輸出電流,大小等於二次侧繞組電流Is的平均 值’ Ro為^次側的輸出阻抗,Vf為二極體D1的順向偏壓 (forward voltage)。在公式2中,VoxIoxToff為負載得到的 能量,其餘則為二次侧的耗損能量。 變壓器TX的一次侧另有辅助繞組(auxiliary winding)Laux,用來產生直流電壓VCC當作控制器106的 電源。實際上一次侧繞組Lp儲存的能量係傳遞給二次侧 繞組Ls及一次侧的輔助繞組Laux,但是輔助繞組Laux 消耗的能量非常小,故可以忽略不計。讓公式1等於公式 2再除以Toff可得 V〇xIo+I〇2xR〇+IsxVf = |x^x|^-f 公式 3 又因為二次側繞組Ls上的跨壓 V2=Vo+I〇xR〇+Vf 公式 4 且電流1〇為電流Is的平均值,故可將電流1〇視為電流is ,因此根據公式3及公式4可得 7 200824250 公式5 lro ir T D V41 1 VI Ton 1 V2=Vo+I〇xR〇+Vf=-x—x-—x— 2 Lp Toff Io 由公式5可知,當負載電流Io因為負載增加而增加時,二 次側繞組Ls上的跨壓V2及輸出電壓Vo都將下降,反之 則上升。 在反驰轉換器100中,從變壓器TX的二次側取得輸 出電壓反饋信號(output voltage feedback signal)可以提供 * 精準的輸出電壓調節,卻必定增加控制系統的複雜度和成 本。改用一次侧迴授電路取得輸出電壓反饋信號可以減少 控制系統的複雜度和成本,但是必定造成精準調節的困難 度提高。美國專利公開號第2003/0128018號、第 2004/0052095號及第2006/0050539號使用複雜的運算在 一次側迴授系統中’來達成精準的輸出電壓調節。但是這 些技術需要較大且較複雜的電路,會增加電路尺寸及成本 _ ,對於許多精準度要求不高的應用而言並不合適。 【發明内容】 本發明的目的之一,在於提出一種切換式電源轉換器 _ 的負載變動補償電路,其具有低成本的優勢。 - 本發明之切換式電源轉換器的負載變動補償電路,用 來監視一誤差信號,在該誤差信號達到該一臨界值時,調 整一輸出電壓反饋#號對一輸出電壓偵測信號的比例,該 誤差信號及一脈寬調變信號因而改變,使該電源轉換器之 200824250 輸出電壓能穩定在預定之變動範圍内。 【實施方式】 圖3顯示應用本發明的第一實施例,在反驰轉換器300 中,來自交流電壓源302提供的交流電壓VAC經EMI濾波 器304及橋式整流器306產生具有漣波的直流輸入電壓Vi ,耦合至變壓器TX的一次侧繞組Lp,功率開關SW與變 壓器TX的一次侧繞組Lp串聯,PWM產生器314產生脈 寬調變信號Vpwm切換功率開關SW,將輸入電壓Vi轉換 為輸出電壓Vo。 輔助繞組Laux在變壓器TX的一次侧用來债測二次侧 的輸出電壓Vo,其繞組電流laux經二極體D2整流,對電 容C1充電產生偵測信號VD。如前所述,使用一次侧的輔 助繞組Laux來偵測輸出電壓Vo是習知技術。輔助繞組 Laux上的跨壓 V3=Vf2+VD 公式 ό 其中,電壓Vf2為二極體D2的順向偏壓。假設繞組Lp、 Ls及Laux的匝數比為nl : n2 : n3,則二次側繞組電壓 V2=(n2/n3)xV3=NxV3 公式 7 其中,N為二次侧繞組Ls對辅助繞組Laux的匝數比。電 9 200824250 阻R1及R2組成的分壓器對偵測信号虎ν〇分壓產生輸出電 壓反饋信號 VE1=VDx[R2/(R1+R2)] 公式 8 誤差放大器312的反相輸入端耦合輸出電壓反饋信號VE1 ,非反相輸入端耦合參考信號VREF1,誤差放大器312放 大二者的差值產生誤差信號COMP。電阻R0與一次侧繞 • 組Lp串聯,偵測一次側繞組電流Ip產生電流偵測信號cS ,PWM產生器314根據電流偵測信號cs及誤差信號 COMP決定脈寬調變信號Vpwm的時序與責任週期。使用 PWM產生器314根據電流偵測信號CS及誤差信號COMP 產生脈寬調變信號Vpwm也是習知技術。 負載變動補償電路310監視誤差信號COMP以調整該 輸出電壓反饋信號VE1對該偵測信號VD的比例。在負戴 φ 變動補償電路310中,電阻R3及電晶體3104串聯在誤差 放大器312的反相輸入端VE1及接地GND之間,電阻R5 及電晶體3106串聯在比較器3102的反相輸入端及接地 GND之間,電阻R4耦合在電壓VR2與比較器3102的反 * 相輸入端之間,比較器3102的非反相輸入端耦合誤差信 ^ 號COMP,比較器3102藉由比較誤差信號COMP及其反 相輸入端上的臨界信號VREF2以導通或關閉電晶體3104 及 3106。 公式8可改寫為 200824250 VD=VElx[l+(Rl/R2)] 公式 9 由於經負迴授穩定後,輸出電壓反饋信號VE1將等於參考 信號VREF1,因此可得 VD=VREF1X [ 1 +(R1 /R2)] 公式 10 圖4顯示圖3中轉換器300的負載電流i〇變化時輸出 電壓Vo及誤差信號COMP的波形圖,其中波形402表示 輸出電壓Vo,波形404表示誤差信號COMP。當負載上升 時,負載電流1〇上升,輸出電壓Vo下降,如波形402所 示,而電壓V2、偵測信號\^)及輸出電壓反饋信號\^£1 也都隨之下降,因而使得誤差信號COMP上升,如波形 404所示。在誤差信號COMP尚未高於臨界信號vrEF2 時,電晶體3104及3106為關閉狀態,此時臨界信號 公式11 VREF2-VR2 當負載電流1〇上升至1〇2時,誤差信號COMP超越臨界 信號VREF2,比較器3102因輸出端轉態而導通電晶體 3104及3106,造成電阻R3與電阻R2並聯,因此輪出電 壓反饋信號變成 11 200824250 YEl=VDx[(R2//R3)/(Rl+(R2//R3))] 公式 12 其中,R2//R3表示電阻R2及R3並聯的等效電阻值。因 此,在電晶體3104導通後,造成輸出電壓反饋信號¥£1 短暫性微小降低,進而導致誤差信號COMP微小升高,如 波形404所示,脈寬調變產生器314偵測該誤差信號COMP 微小升高後,則提高該脈寬調變信號Vpwm的責任週期, 二次侧繞組電壓V2隨即提升,根據公式5,輸出電壓Vo 也因而提升。 從另一方面來看,經負迴授穩定後,輸出電壓反饋信號 VE1將回到VREF1的準位,此時公式10變成 VD - VREFlx[l+(Rl/(R2//R3))] 公式 13 從公式13可知,偵測信號VD也因電阻R2及R3的並聯 而上升至較高的值。假設二極體D1及D2具有相同的順向 偏壓,即Vf=Vf2,根據公式5、公式6及公式7可得Lp Formula where ' Ιρκ is the peak value of the primary winding current Ip, and V1 is the crossover voltage on the side winding Lp. In the off-duty period Toff of the pulse width modulation signal Vpwm, the power switch SW is turned off, and the energy stored in the primary side winding Lp is transferred to the secondary side winding Ls, so the secondary side winding current Is is peaked ISK is gradually reduced to 〇. The diode D1 is used for rectification. The capacitor Co is charged to generate an output voltage Vo. During the non-responsible period Toff, the secondary side of the transformer TX consumes energy 200824250 V〇xI〇xToff+I〇2xR〇xToff+IsxVfxT〇ff Equation 2 where I〇 is the output current and the magnitude is equal to the average of the secondary winding current Is The value 'Ro is the output impedance of the secondary side, and Vf is the forward voltage of the diode D1. In Equation 2, VoxIoxToff is the energy obtained by the load, and the rest is the energy of the secondary side. The primary side of the transformer TX has an auxiliary winding Laux for generating a DC voltage VCC as the power source for the controller 106. Actually, the energy stored in the primary side winding Lp is transmitted to the secondary side winding Ls and the primary side auxiliary winding Laux, but the energy consumed by the auxiliary winding Laux is very small and can be ignored. Let Equation 1 be equal to Equation 2 and divide by Toff to get V〇xIo+I〇2xR〇+IsxVf = |x^x|^-f Equation 3 and because of the cross-over voltage on the secondary winding Ls V2=Vo+I〇 xR〇+Vf Equation 4 and the current 1〇 is the average value of the current Is, so the current 1〇 can be regarded as the current is, so it can be obtained according to Equation 3 and Equation 4 200824250 Equation 5 lro ir TD V41 1 VI Ton 1 V2 =Vo+I〇xR〇+Vf=-x—x-—x— 2 Lp Toff Io It can be seen from Equation 5 that when the load current Io increases due to an increase in load, the voltage across the secondary winding Ls and the output V2 and output The voltage Vo will drop, otherwise it will rise. In the flyback converter 100, obtaining an output voltage feedback signal from the secondary side of the transformer TX provides * accurate output voltage regulation, but necessarily increases the complexity and cost of the control system. Switching to the primary feedback circuit to obtain the output voltage feedback signal can reduce the complexity and cost of the control system, but it will certainly increase the difficulty of precise adjustment. U.S. Patent Publication Nos. 2003/0128018, 2004/0052095, and 2006/0050539 use sophisticated calculations in a primary side feedback system to achieve precise output voltage regulation. However, these techniques require larger and more complex circuits that increase circuit size and cost _ and are not suitable for many applications where accuracy is not critical. SUMMARY OF THE INVENTION One object of the present invention is to provide a load variation compensation circuit of a switching power converter, which has the advantage of low cost. - the load variation compensation circuit of the switching power converter of the present invention is configured to monitor an error signal, and adjust an output voltage feedback # to an output voltage detection signal when the error signal reaches the threshold value, The error signal and a pulse width modulation signal are thus changed to stabilize the 200824250 output voltage of the power converter within a predetermined range of variation. [Embodiment] FIG. 3 shows a first embodiment to which the present invention is applied. In the flyback converter 300, an AC voltage VAC supplied from an AC voltage source 302 generates a DC having a chopper via an EMI filter 304 and a bridge rectifier 306. The input voltage Vi is coupled to the primary side winding Lp of the transformer TX, the power switch SW is connected in series with the primary side winding Lp of the transformer TX, and the PWM generator 314 generates a pulse width modulation signal Vpwm to switch the power switch SW to convert the input voltage Vi into an output. Voltage Vo. The auxiliary winding Laux is used on the primary side of the transformer TX to measure the output voltage Vo of the secondary side, and the winding current laux is rectified by the diode D2 to charge the capacitor C1 to generate the detection signal VD. As described above, it is a conventional technique to use the primary side auxiliary winding Laux to detect the output voltage Vo. The voltage across the auxiliary winding Laux V3 = Vf2 + VD Equation ό where the voltage Vf2 is the forward bias of the diode D2. Assuming that the turns ratio of the windings Lp, Ls and Laux is nl : n2 : n3, the secondary winding voltage V2 = (n2 / n3) x V3 = NxV3 Equation 7 where N is the secondary winding Ls to the auxiliary winding Laux Turn ratio. Electricity 9 200824250 Resistor R1 and R2 voltage divider pair detection signal Tiger ν〇 divided voltage to produce output voltage feedback signal VE1=VDx[R2/(R1+R2)] Equation 8 Error amplifier 312 inverting input coupling output The voltage feedback signal VE1, the non-inverting input is coupled to the reference signal VREF1, and the error amplifier 312 amplifies the difference between the two to generate an error signal COMP. The resistor R0 is connected in series with the primary side winding group Lp, and detects the primary side winding current Ip to generate a current detecting signal cS. The PWM generator 314 determines the timing and responsibility of the pulse width modulation signal Vpwm according to the current detecting signal cs and the error signal COMP. cycle. It is also a conventional technique to generate the pulse width modulation signal Vpwm based on the current detection signal CS and the error signal COMP using the PWM generator 314. The load variation compensation circuit 310 monitors the error signal COMP to adjust the ratio of the output voltage feedback signal VE1 to the detection signal VD. In the negative wear φ variation compensation circuit 310, the resistor R3 and the transistor 3104 are connected in series between the inverting input terminal VE1 of the error amplifier 312 and the ground GND, and the resistor R5 and the transistor 3106 are connected in series at the inverting input terminal of the comparator 3102 and Between the ground GND, the resistor R4 is coupled between the voltage VR2 and the inverse* phase input of the comparator 3102, the non-inverting input of the comparator 3102 is coupled with the error signal COMP, and the comparator 3102 compares the error signal COMP and The critical signal VREF2 on its inverting input turns on or off the transistors 3104 and 3106. Equation 8 can be rewritten as 200824250 VD=VElx[l+(Rl/R2)] Equation 9 Since the output feedback signal VE1 will be equal to the reference signal VREF1 after the negative feedback is stabilized, VD=VREF1X [1 +(R1 / R2)] Equation 10 FIG. 4 is a waveform diagram showing the output voltage Vo and the error signal COMP when the load current i〇 of the converter 300 of FIG. 3 is changed, wherein the waveform 402 represents the output voltage Vo, and the waveform 404 represents the error signal COMP. When the load rises, the load current increases by 1〇, and the output voltage Vo decreases, as shown by waveform 402, and the voltage V2, the detection signal \^), and the output voltage feedback signal \^£1 also decrease, thus causing the error. Signal COMP rises as indicated by waveform 404. When the error signal COMP is not higher than the threshold signal vrEF2, the transistors 3104 and 3106 are turned off, and the critical signal formula 11 VREF2-VR2 when the load current 1〇 rises to 1〇2, the error signal COMP exceeds the critical signal VREF2, The comparator 3102 conducts the transistors 3104 and 3106 due to the output state transition, causing the resistor R3 to be connected in parallel with the resistor R2, so the turn-off voltage feedback signal becomes 11 200824250 YEl=VDx[(R2//R3)/(Rl+(R2// R3))] Equation 12 where R2//R3 represents the equivalent resistance value of the resistors R2 and R3 in parallel. Therefore, after the transistor 3104 is turned on, the output voltage feedback signal ¥£1 is temporarily reduced slightly, and the error signal COMP is slightly increased. As shown by the waveform 404, the pulse width modulation generator 314 detects the error signal COMP. After a slight rise, the duty cycle of the pulse width modulation signal Vpwm is increased, and the secondary side winding voltage V2 is then increased. According to Equation 5, the output voltage Vo is thus increased. On the other hand, after the negative feedback is stabilized, the output voltage feedback signal VE1 will return to the level of VREF1, and the formula 10 becomes VD - VREFlx[l+(Rl/(R2//R3))] Equation 13 As can be seen from Equation 13, the detection signal VD also rises to a higher value due to the parallel connection of the resistors R2 and R3. Assume that the diodes D1 and D2 have the same forward bias voltage, that is, Vf=Vf2, which can be obtained according to Equation 5, Equation 6, and Equation 7.
Vo=VDxN+(N-l)Vf-I〇xRo 公式 14Vo=VDxN+(N-l)Vf-I〇xRo Formula 14
由公式14可知,當負載電流1〇增加時輸出電壓Vo將減 小。參照圖4,當負載電流1〇由1〇0上升至1〇2時,輸出 電壓Vo下降AV,如上所述,因電阻R2及R3並聯,V2 提升,而讓偵測信號VD也上升,導致輸出電壓Vo上升AV 12 200824250 抵消因負載電流I〇增加所造成的下降。將公式13減去公 式10可得偵測信號VD.的變化量 A VD=VREF1X (R1 /R3) 公式 15 由公式15得知,偵測信號VD的變化量八乂0與電阻111 及R3以及參考信號VREF1有關,因此可以藉由選取適當 的電阻R1及R3以及參考信號VREF1使公式16中的 VDxN完全抵消I〇xR〇造成的衰減,使該電源轉換器之輸 出電壓Vo能穩定在預定之變動範圍av之内。 當負載電流1〇減少時,例如由1〇3降至Ιοί,由於先 前已導通電晶體3106,故此時比較器3102的反相輸入端 的臨界信號 VREF2=VR2 x [R5/(R4+R5)] 公式 16 小於先前的臨界值VR2。當負載電流i〇降至1〇2時,比較 器3102的輸出並沒有轉態,而要等負載電流1〇再下降至 1〇1時,誤差信號COMP才會小於臨界信號VREF2,造成 比較器3102的輸出再轉態使電晶體31〇4及3106關閉, 因而導致誤差信號COMP及輸出電壓Vo微小下降,自此 ,臨界信號VREF2又回復為VR2,而偵測信號VD也回 復如公式12所示。此磁滯設計可以避免雜訊干 擾,進一步優化性能。 13 200824250 在此實施例中’為了方便說明及理解,口杜_ 録負7K —個参 载補償單元,實際上,負載變動補償電路31〇可^ 只 多個負載補償單元,每一個負載補償單元皆耦人至^括^ 大器312的反相輸入端νΈ 1,且所有負載補幹留_ · 二 、 币貝早元的臨界As can be seen from Equation 14, the output voltage Vo will decrease as the load current 1〇 increases. Referring to FIG. 4, when the load current 1〇 rises from 1〇0 to 1〇2, the output voltage Vo falls AV. As described above, since the resistors R2 and R3 are connected in parallel, V2 is boosted, and the detection signal VD is also raised, resulting in an increase in the detection signal VD. The output voltage Vo rises AV 12 200824250 to offset the drop caused by the increase in load current I〇. Subtracting Equation 13 from Equation 10 gives the amount of change in the detection signal VD. A VD=VREF1X (R1 /R3) Equation 15 It is known from Equation 15 that the variation of the detection signal VD is 乂0 and the resistances 111 and R3 and The reference signal VREF1 is related, so that the VDxN in Equation 16 can completely cancel the attenuation caused by I〇xR〇 by selecting appropriate resistors R1 and R3 and the reference signal VREF1, so that the output voltage Vo of the power converter can be stabilized at a predetermined value. The range of variation is within av. When the load current 1〇 decreases, for example, from 1〇3 to Ιοί, since the crystal 3106 has been previously energized, the critical signal of the inverting input of the comparator 3102 is VREF2=VR2 x [R5/(R4+R5)] Equation 16 is smaller than the previous threshold VR2. When the load current i〇 drops to 1〇2, the output of the comparator 3102 does not change state, and when the load current 1〇 falls to 1〇1, the error signal COMP is less than the critical signal VREF2, resulting in a comparator. The output re-rotation state of 3102 turns off the transistors 31〇4 and 3106, so that the error signal COMP and the output voltage Vo decrease slightly. Since then, the critical signal VREF2 returns to VR2, and the detection signal VD also returns as in Equation 12. Show. This hysteresis design eliminates noise interference and further optimizes performance. 13 200824250 In this embodiment, 'for convenience of explanation and understanding, the port _ negative 7K is a load compensation unit. In fact, the load variation compensation circuit 31 can only have multiple load compensation units, each load compensation unit. Both are coupled to the inverting input νΈ 1, of the large device 312, and all the load is dry and left _ · Second, the critical value of the currency
仏號具有不同的臨界值,例如,第一個負載補償單—的广 考電壓為VR2,而第二個負載補償單元的參考電壓為 ,如此,如同圖4的波形404所示,當誤差信號達 到第一個負載補償單元的參考電壓VR2時,誤差^號 C 〇 Μ P稍微拉高,在誤差信號c 〇 M p達到第二個負』= 單元的參考電壓VR3時,誤差信號COMP又再次稍微二 高,依此類推,每當誤差信號C0MP達到一個負载補償單 元的臨界值時,都將使誤差信號COMP稍微拉高。反之, 在誤差信號C0MP減小的過程中,也是依序觸發不同的負 載補償單元,而稍微拉低誤差信號COMP。 圖5顯示本發明的第二實施例,在反馳轉換器5〇〇中 ’除了負載變動補償電路510以外,其他元件與圖3所示 相同,不再贅述。負載變動補償電路510監視誤差信號 COMP以調整該輸出電壓反饋信號VE1對該偵測信號VD 的比例。在負載變動補償電路51〇中,電晶體5104及電 阻R3串聯在誤差放大器512的反相輸入端VE1及接地 GND之間,電阻r4與齊納二極體〇3串聯在誤差故大器 512的輪出C〇MP及接地GND之間,運算放大器51〇2的 非反相輪入端耦合齊納二極體D3的陽極,其反相輸入端 耦合電阻R3,其輸出端產生控制信號給電晶體5104的閘 200824250 極。齊納二極體D3在此作為一偏壓元件,本發明之偏壓 元件並不偈限為齊納二極體。 圖6顯示圖5中輸出電壓Vo及誤差信號(:〇]^?的波 形圖,其中波形602表示誤差信號COMP,波形604表示 輸出電壓Vo。當負載上升時,負載電流1〇上升,輸出電 _ 壓Vo下降,如波形604所示,二次侧繞組Ls上的跨壓 V2、偵測信號VD及輸出電壓反饋信號VE1也都隨之下降 ,因而使得誤差信號COMP上升,如波形602所示。當誤 • 差信號COMP大於齊納二極體D3的崩潰電壓VZ時,運 算放大器5102的非反相輸入端之電壓Vl=COMP-VZ,運 算放大器5102因而導通電晶體5104,根據負迴授之虛短 路(virtual short)原理,運算放大器5102的反相輸入端之電 壓將等於VI之電壓,因此流經電阻R3之電流IR3為 IR3=(COMP-VZ)/R3 公式 17 • 由於崩潰電壓VZ為定值,因此電流IR3的變化量正比於 誤差信號COMP的變化量。如同第一實施例之推導,本實 施例之偵測信號VD在電晶體5104關閉時可表示為如公式 - 9所示,偵測信號VD在電晶體5104導通時可表示為 VD=VE1X [ 1 +(R 1 /R2)]+IR3 x R1 公式 18 將公式17代入公式18後,可得 15 200824250 VD=VE1x[1+(R1/R2)]+[(COMP.VZ)/R3]xR1 公式 19 將公式19減去公式9可得偵測信號VD在電晶體5l〇4導 通前後的變化量 AVD=(Ri/R3)x(COMP-VZ) 公式 20 從公式20可知,偵測信號VD的變化量AVD與誤差信號 _ COMP成正比。再根據公式14,偵測信號VD的增加$以 抵消輸出電壓Vo因負載電流1〇所造成的衰減,又因誤蓋 4吕5虎COMP正比於負載電流1〇,因此,適當地選取沾隊 R1及R3可以使輸出電壓Vo保持在一穩定值,如波形604 所示。 在本發明的第二實施例中,當電晶體5104導通後’ 該偵測信號VD對該輸出電壓反饋信號VE1的比例玎由公 φ 式丨9進一步推導為 [1+(R1/R2)]+[(COMP-VZ)/R3]x[R1/VREF1],因誤差信號 COMP正比於負載電流1〇,因此該輸出電壓反饋信號VE1 對该偵測信號VD的比例係一變動值,若負載電流1〇持續 - 增加,適當地選取電阻R1及R3可以使輸出電壓ν〇保持 - 在*穩定值。 如以上的實施例所揭示的,本發明的負载變動補償電 路及方法只運用了少數的元件及簡單的電路,在誤差信號 COMP達到臨界值時調整該輸出電壓反饋信號vei對該偵 200824250 測信號VD的比例,該誤差信號COMP因而改變,該PWM 產生器314再根據該誤差信號COMP之變化調整該脈寬調 變信號Vpwm,使該電源轉換器之輸出電壓Vo能穩定在預 定之變動範圍之内。The apostrophe has a different threshold, for example, the first load compensation meter has a wide test voltage of VR2, and the second load compensation unit has a reference voltage, and as such, as shown by waveform 404 of FIG. 4, the error signal When the reference voltage VR2 of the first load compensation unit is reached, the error ^C 〇Μ P is slightly pulled high. When the error signal c 〇M p reaches the second negative 』= unit reference voltage VR3, the error signal COMP is again Slightly two high, and so on, each time the error signal COMP reaches a critical value of the load compensation unit, the error signal COMP will be pulled slightly higher. Conversely, in the process of decreasing the error signal C0MP, different load compensation units are also sequentially triggered, and the error signal COMP is slightly pulled down. Fig. 5 shows a second embodiment of the present invention. The components other than the load variation compensation circuit 510 in the flyback converter 5 are the same as those shown in Fig. 3 and will not be described again. The load variation compensation circuit 510 monitors the error signal COMP to adjust the ratio of the output voltage feedback signal VE1 to the detection signal VD. In the load variation compensation circuit 51A, the transistor 5104 and the resistor R3 are connected in series between the inverting input terminal VE1 of the error amplifier 512 and the ground GND, and the resistor r4 is connected in series with the Zener diode 〇3 in the error amplifier 512. Between the C〇MP and the ground GND, the non-inverting wheel of the operational amplifier 51〇2 is coupled to the anode of the Zener diode D3, the inverting input is coupled to the resistor R3, and the output of the operational amplifier generates a control signal to the transistor. The gate of 5104 is 200824250 pole. The Zener diode D3 is here a biasing element, and the biasing element of the present invention is not limited to a Zener diode. 6 shows a waveform diagram of the output voltage Vo and the error signal (: 〇)^ in FIG. 5, wherein the waveform 602 represents the error signal COMP, and the waveform 604 represents the output voltage Vo. When the load rises, the load current rises and the output current is increased. _ The voltage Vo drops. As shown by the waveform 604, the voltage across the secondary winding Ls, the detection signal VD, and the output voltage feedback signal VE1 also decrease, thereby causing the error signal COMP to rise, as shown by the waveform 602. When the error difference signal COMP is greater than the breakdown voltage VZ of the Zener diode D3, the voltage Vl of the non-inverting input terminal of the operational amplifier 5102 is COMP-VZ, and the operational amplifier 5102 is thus energized to the crystal 5104, according to the negative feedback The principle of virtual short, the voltage at the inverting input of the operational amplifier 5102 will be equal to the voltage of VI, so the current IR3 flowing through the resistor R3 is IR3=(COMP-VZ)/R3 Equation 17 • Due to the breakdown voltage VZ For the fixed value, the amount of change of the current IR3 is proportional to the amount of change of the error signal COMP. As the derivation of the first embodiment, the detection signal VD of the present embodiment can be expressed as shown in the formula -9 when the transistor 5104 is turned off. Detection letter No. VD can be expressed as VD=VE1X when the transistor 5104 is turned on [1 +(R 1 /R2)]+IR3 x R1 Equation 18 After substituting the formula 17 into the formula 18, 15 200824250 VD=VE1x[1+(R1 /R2)]+[(COMP.VZ)/R3]xR1 Equation 19 Subtracting Equation 9 from Equation 9 gives the amount of change in the detection signal VD before and after the transistor 5l〇4 is turned on AVD=(Ri/R3)x( COMP-VZ) Equation 20 It can be seen from Equation 20 that the amount of change AVD of the detection signal VD is proportional to the error signal _ COMP. According to Equation 14, the increase of the detection signal VD is $ to offset the output voltage Vo due to the load current. The resulting attenuation is also due to the error of 4 55 tiger COMP proportional to the load current 1 〇, therefore, the appropriate selection of squeegee R1 and R3 can maintain the output voltage Vo at a stable value, as shown by waveform 604. In the second embodiment, when the transistor 5104 is turned on, the ratio of the detection signal VD to the output voltage feedback signal VE1 is further derived from the public φ 丨9 as [1+(R1/R2)]+[( COMP-VZ)/R3]x[R1/VREF1], because the error signal COMP is proportional to the load current 1〇, the ratio of the output voltage feedback signal VE1 to the detection signal VD is a variable value, if the load The current 1 〇 is continuously increased, and the appropriate selection of the resistors R1 and R3 can maintain the output voltage ν - - at a stable value. As disclosed in the above embodiments, the load variation compensation circuit and method of the present invention utilize only a small number of The component and the simple circuit adjust the ratio of the output voltage feedback signal vei to the detection signal 24D of the 200824250 when the error signal COMP reaches a critical value, and the error signal COMP is thus changed, and the PWM generator 314 further determines the COMP according to the error signal COMP. The pulse width modulation signal Vpwm is adjusted to vary so that the output voltage Vo of the power converter can be stabilized within a predetermined variation range.
17 200824250 【圖式簡單說明】 圖1係習知的反馳轉換器; 圖2顯示圖1中脈寬調變信號、一次侧繞組電流及二 次侧繞組電流的波形圖, 圖3顯示應用本發明的第一實施例; 圖4顯示圖3中的轉換器在負載變化時,負載電流、 輸出電壓及誤差信號的波形圖; 圖5顯示應用本發明的第二實施例;以及 圖6顯示圖5中的轉換器在負載變化時,負載電流、 輸出電壓及誤差信號的波形圖。 【主要元件符號說明】 100 反馳轉換器 101 交流電壓源 102 EMI濾波器 104 橋式整流器 106 控制器 108 光搞合器 110 穩壓調整器 200 脈寬調變信號的波形 202 一次侧繞組電流的波形 204 二次側繞組電流的波形 300 反馳轉換器 302 交流電壓源 200824250 304 EMI濾波器 306 橋式整流器 310 負載變動補償電路 3102 比較器 3104 電晶體 3106 電晶體 312 誤差放大器 314 PWM產生器17 200824250 [Simple description of the diagram] Figure 1 is a conventional flyback converter; Figure 2 shows the waveform of the pulse width modulation signal, the primary winding current and the secondary winding current in Figure 1, Figure 3 shows the application A first embodiment of the invention; FIG. 4 is a waveform diagram showing load current, output voltage and error signals of the converter of FIG. 3 when the load changes; FIG. 5 shows a second embodiment to which the present invention is applied; The waveform of the load current, output voltage and error signal of the converter in 5 when the load changes. [Main component symbol description] 100 Reverse converter 101 AC voltage source 102 EMI filter 104 Bridge rectifier 106 Controller 108 Light combiner 110 Regulator adjuster 200 Pulse width modulation signal waveform 202 Primary side winding current Waveform 204 Secondary Side Winding Current Waveform 300 Reverse Converter 302 AC Voltage Source 200824250 304 EMI Filter 306 Bridge Rectifier 310 Load Variation Compensation Circuit 3102 Comparator 3104 Transistor 3106 Transistor 312 Error Amplifier 314 PWM Generator
402 輸出電壓的波形 404 誤差信號的波形 500 反驰轉換器 510 負載變動補償電路 5102 運算放大器 5104 電晶體 602 誤差信號的波形 604 輸出電壓的波形 19402 Output voltage waveform 404 Error signal waveform 500 Reverse converter 510 Load variation compensation circuit 5102 Operational amplifier 5104 Transistor 602 Error signal waveform 604 Output voltage waveform 19