TW200824057A - Semiconductor package and display apparatus - Google Patents

Semiconductor package and display apparatus Download PDF

Info

Publication number
TW200824057A
TW200824057A TW096136896A TW96136896A TW200824057A TW 200824057 A TW200824057 A TW 200824057A TW 096136896 A TW096136896 A TW 096136896A TW 96136896 A TW96136896 A TW 96136896A TW 200824057 A TW200824057 A TW 200824057A
Authority
TW
Taiwan
Prior art keywords
substrate
terminals
liquid crystal
semiconductor wafer
film substrate
Prior art date
Application number
TW096136896A
Other languages
Chinese (zh)
Other versions
TWI361476B (en
Inventor
Tatsuya Katoh
Satoru Kudose
Tomokatsu Nakagawa
Toshiya Tsukao
Original Assignee
Sharp Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Kk filed Critical Sharp Kk
Publication of TW200824057A publication Critical patent/TW200824057A/en
Application granted granted Critical
Publication of TWI361476B publication Critical patent/TWI361476B/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985Flexible insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05568Disposition the whole external layer protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05573Single external layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • H01L2224/1412Layout
    • H01L2224/1413Square or rectangular array
    • H01L2224/14132Square or rectangular array being non uniform, i.e. having a non uniform pitch across the array
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • H01L2224/1412Layout
    • H01L2224/1413Square or rectangular array
    • H01L2224/14133Square or rectangular array with a staggered arrangement, e.g. depopulated array
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • H01L2224/1412Layout
    • H01L2224/1415Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/14152Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry being non uniform, i.e. having a non uniform pitch across the array
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • H01L2224/1412Layout
    • H01L2224/14177Combinations of arrays with different layouts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00013Fully indexed content
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01057Lanthanum [La]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Wire Bonding (AREA)

Abstract

In a tape carrier type semiconductor package having an interposer substrate, connection terminals and wiring are provided on the interposer substrate and upsizing of a semiconductor package incident to upsizing of the interposer substrate is inevitable as the number of connection terminals increases. The inventive semiconductor package where a semiconductor chip is connected with a film substrate through the interposer substrate, characterized in that the semiconductor chip is provided with a plurality of terminals respectively on two opposing sides and connected, on the interposer substrate, while being shifted from the center of the interposer substrate to the side of one of two sides having a fewer terminals.

Description

200824057 九、發明說明: 【發明所屬之技術領域】 本發明係關於半導體封裝體及使用其之顯示裝置。尤 其,係關於經由互連基板,連接ic晶片與薄膜基板之帶載 型半導體封裝體及使用其之顯示裝置。 【先前技術】 近年’伴隨搭載半導體裝置之電子機器的高功能化,達 成半導體裝置小型化及積體化,並開發各種類型的半導體 封裝體。該半導體封裝體之一係提案帶載型半導體封裝 體’其係稱為TCP(Tape Carrier Package··帶載封裝體)或 COF(Chip On Film :薄膜上晶片)。 TCP半導體封裝體係在薄膜基材上具有由銅箔等的金屬 圖案所形成之引線之封裝體,將1C晶片覆晶連接而安裝於 從形成於薄膜基材之穿通孔(裝置孔)突出引線前端而形成 之飛線。薄膜基材具柔軟性,故可凹折,且可多端子微間 距化,並可以既存的覆晶接合技術對應,從而多用於代表 液晶顯示裝置之薄型顯示裝置的驅動器IC用封裝體。 COF半導體封裝體不具有如以往之TCP半導體封裝體的 飛線,其具有以薄膜基材支持引線之構造。因此,可使用 更薄的布線材(銅箔),再者,其係可形成微間距引線之封 裝體技術’因半導體封裝體小型化及積體化的要求,近年 使用情況很多。 此外,COF半導體封裝體的形態之一係有具如圖9所示 的互連基板(中間基板)之C0F半導體封裝體(參照專利文獻 I25226.doc 200824057 υ。該形態之c〇f半導體封裝體31藉由在一個半導體封裝 體中内藏互連基板33(中間基板),並在封裝體内部進行ic 晶片32與互連基板33之連接,可高密度地安裝半導體元 件。 • #者’ I導體封裝體’例如,如同液晶顯示裝置的,藉 由伴隨所搭載電子機器高性能化之IC晶片的輸出入端子多 * 接腳化,有進一步要求微間距化之傾向。 φ [專利文獻1]曰本國公開專利公報「特開2004-207556號 公報(公開日:2004年7月22日)」 【發明内容】 具有如上述的互連基板之帶載型半導體封裝體中,在互 連基板上設置連接端子及布線,但因連接端子數增加,而 有以下問題:無法避免伴隨互連基板大型化之半導體封裝 體大型化。 再者,因互連基板,例如係由矽等半導體材料所形成, • 故有無法避免互連基板大型化所造成之成本增加的問題。 尤其,1C晶片的輸入端子數與輸出端子數不同時,互連 基板的端子數少之側的互連基板空間相冑於端子數多之側 * 的互連基板空間,大於所需,而構成半導體封裝體大型化 . 之要因。 因此,本發明之目的在於提供帶載型半導體封裝體,其 可配置連接端子及布線,而不需將互連基板大型化為必要 以上。 尤其,本發明之目的在於提供帶載型半導體封裝體,其 125226.doc 200824057 在ic晶片的輸入端子數與輸出端子數不同時,可配置連接 端子及布線,而不需將互連基板大型化為必要以上。 本發明之第一局面之半導體封裝M,其係半導體晶片經 由互連基板而連接於薄膜基板者,其特徵係:半導體晶片 的中心位置與互連基板的中心位置不同。 本發明之第二局面之半導體封裝體,其係半導體晶片經 . 由互連基板而連接於薄膜基板者,其特徵係:半導體晶片 籲 至少於相對的兩邊分別具有複數端子,再者,於互連基 板,從互連基板中心偏移連接於相對的兩邊中端子數少的 一方側。另外,也可在相對的兩邊以外之邊配置端子。 本發明之第三局面之半㈣封裝體,其係半導體晶片經 由互連基板而連接於薄膜基板者,其特徵係:半導體晶片 至少於相對的兩邊分別具有複數端子,互連基板至少於相 對的兩邊分別具有連接於薄膜基板之薄模基板連接端子, 亚在薄膜基板連接端子内側具有複數半導體晶片連接端 • 子,其係與配置於半導體晶片相對的兩邊之複數端子連 接,互連基板相對的兩邊各自之薄膜基板連接端子與半導 體晶片連接端子之距離,在半導體晶片連接端子的端子數 * 少者係比另一方短。 . 本發明之第四局面之半導體封裝體,其係半導體晶片經 由互連基板而連接於薄膜基板者,其特徵係:半導體晶片 至少於相對的兩邊分別具有複數端子,薄膜基板具有裝置 孔’且半導體晶片位於裝置孔内;再者,裝置孔相對的兩 邊各自之半導體晶片端面與裝置孔端面之距離,在前述半 125226.doc 200824057 導體晶片相對的兩邊中端子數少者係比另—方短。 此外’本發明之半導體封裝體,其特徵係:: 曰200824057 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor package and a display device using the same. In particular, it relates to a tape-type semiconductor package in which an ic wafer and a film substrate are connected via an interconnect substrate, and a display device using the same. [Prior Art] In recent years, with the increase in the functionality of electronic devices equipped with semiconductor devices, semiconductor devices have been miniaturized and integrated, and various types of semiconductor packages have been developed. One of the semiconductor packages is a tape-type semiconductor package, which is called a TCP (Tape Carrier Package) or a COF (Chip On Film). The TCP semiconductor package system has a package of a lead formed of a metal pattern such as copper foil on a film substrate, and the 1C wafer is flip-chip bonded and mounted on a lead wire protruding from a through hole (device hole) formed in the film substrate. And the flying line formed. Since the film substrate is flexible, it can be folded and folded, and can have a multi-terminal micro-interval, and can be used in a driver IC package for a thin display device of a liquid crystal display device. The COF semiconductor package does not have a flying wire of a conventional TCP semiconductor package, and has a structure in which a lead is supported by a film substrate. Therefore, a thinner wiring material (copper foil) can be used, and further, a package body technology capable of forming fine pitch leads can be used in recent years due to the demand for miniaturization and integration of semiconductor packages. Further, one of the forms of the COF semiconductor package is a COF semiconductor package having an interconnection substrate (intermediate substrate) as shown in FIG. 9 (refer to Patent Document No. 2525.doc 200824057 υ. This form of c〇f semiconductor package By mounting the interconnection substrate 33 (intermediate substrate) in one semiconductor package and connecting the ic wafer 32 and the interconnection substrate 33 inside the package, the semiconductor element can be mounted at a high density. • #者' I In the case of a liquid crystal display device, for example, a liquid crystal display device has a tendency to be finely pitched by an input/output terminal of an IC chip with high performance in mounting an electronic device. φ [Patent Document 1] Japanese Laid-Open Patent Publication No. 2004-207556 (Publication Date: July 22, 2004). SUMMARY OF THE INVENTION In a tape-type semiconductor package having an interconnect substrate as described above, on an interconnect substrate Although the number of connection terminals is increased, the number of connection terminals is increased, and there is a problem that the size of the semiconductor package which is increased in size of the interconnection substrate cannot be avoided. If it is formed of a semiconductor material such as germanium, there is a problem that the cost of the interconnect substrate is unavoidable. In particular, when the number of input terminals of the 1C chip is different from the number of output terminals, the number of terminals of the interconnect substrate is small. The space of the interconnect substrate on the side of the interconnect substrate is larger than the number of interconnects on the side of the number of terminals*, which is larger than necessary, and constitutes a factor for increasing the size of the semiconductor package. Therefore, the object of the present invention is to provide a packaged semiconductor package. The body can be configured to connect the terminals and the wiring without increasing the size of the interconnect substrate. In particular, the object of the present invention is to provide a load-carrying type semiconductor package, which is 125226.doc 200824057 at the input terminal of the ic chip. When the number is different from the number of output terminals, the connection terminals and the wiring can be arranged without increasing the size of the interconnection substrate. The semiconductor package M of the first aspect of the present invention is a semiconductor wafer connected via an interconnection substrate. In the case of a film substrate, the feature is that the center position of the semiconductor wafer is different from the center position of the interconnect substrate. a package, which is a semiconductor wafer connected to a film substrate by an interconnect substrate, wherein the semiconductor wafer has a plurality of terminals respectively on at least opposite sides, and further, on the interconnect substrate, from the center of the interconnect substrate The offset is connected to one side of the opposite sides in which the number of terminals is small. Alternatively, the terminals may be arranged on the opposite sides of the opposite sides. In the third aspect of the present invention, the package (four) is a semiconductor wafer via an interconnect substrate. The film substrate is characterized in that: the semiconductor wafer has a plurality of terminals on at least opposite sides thereof, and the interconnect substrate has a thin-die substrate connection terminal connected to the film substrate at least on opposite sides thereof, and is disposed inside the film substrate connection terminal. a plurality of semiconductor wafer connection terminals are connected to a plurality of terminals disposed on opposite sides of the semiconductor wafer, and the distance between the film substrate connection terminals of the opposite sides of the substrate and the semiconductor wafer connection terminals is at a semiconductor wafer connection terminal The number of terminals * is less than the other. A semiconductor package according to a fourth aspect of the present invention, wherein the semiconductor wafer is connected to the film substrate via the interconnection substrate, wherein the semiconductor wafer has a plurality of terminals at least on opposite sides, and the film substrate has a device hole' The semiconductor wafer is located in the hole of the device; further, the distance between the end faces of the semiconductor wafers on opposite sides of the device hole and the end face of the device hole is shorter than the other ones in the opposite sides of the opposite half of the conductor chip 125226.doc 200824057 . Further, the semiconductor package of the present invention has the following features:

片相對的兩邊中的一邊西己罟5坐 曰E 、遭甲的邊配置至+導體晶片之輸入信號娃 子,並在另一邊配置來自半導體 儿 干虻饈日曰片之輸出信號端子。 再者,本發明之半導體封裝體,其特徵係:輸出信 子的端子數比輸入信號端子的端子數多。 , 又’本發明之半導體封裝體,其 所構成。 互運基板由矽One of the opposite sides of the sheet is placed on the side of the hexagram 曰E, the edge of the armor is placed on the input signal of the +conductor chip, and the output signal terminal from the semiconductor chip is placed on the other side. Furthermore, the semiconductor package of the present invention is characterized in that the number of terminals of the output signal is larger than the number of terminals of the input signal terminal. Further, the semiconductor package of the present invention is constructed. Mutual transport substrate

此外,本發明之半導體封裝體,其特徵係:半導體晶片 為液晶驅動器。 本發明之顯示裝置,其特徵係:具有上述任一半導體 裝體。 根據本發明之半導體封裝體,可配置連接端子及布線, 而不會使互連基板過度大型化。 此外,可抑制用於互連基板之高價矽等的半導體材料 量,並可抑制成本增加。 再者本發明之其他目的、特徵及優點藉由以下所示之 η己載§可充分明白。又,本發明之利益藉由參照附圖之以 下說明當可明白。 【實施方式】 以下’參照圖說明本發明之實施形態。另外,在此,以 採用有本發明之半導體封裝體之液晶驅動器封裝體為例進 行說明。 (實施形態1) 125226.doc 200824057 圖1係本發明實施形態1之液晶驅動器封裝體的平面圖。 圖2係從切斷面線A-A’觀看圖1所示之液晶驅動器封裝體的 剖面圖。再者,圖3係液晶驅動器2與互連基板3之連接的 說明圖。以下,參照圖1、圖2及圖3,針對液晶驅動器封 裝體的概略構成進行說明。 本實施形態之液晶驅動器封裝體1係c〇F(chip 〇n FUm :薄膜覆晶封裝)半導體封裝體,至少具有液晶驅動 器2(半導體晶片)、互連基板3及薄膜基板4,液晶驅動器2 係經由互連基板3而連接薄膜基板4。此外,在液晶驅動器 2、互連基板3及薄膜基板4之間填充密封樹脂5,並補強· 固疋各個之間的連接部。在此,密封樹脂5 一般係稱為填 充材’可使用絕緣性樹脂(例如,環氧樹脂、矽樹脂、聚 醯亞胺樹脂等)。 液晶驅動器2係至少具備一個以上的液晶驅動電路(未圖 示),以驅動液晶顯示裝置。因此,在液晶驅動器,在與 互連基板相對之面(以下,稱為下面)係設置用以輸入圖像 資料信號等之圖像信號輸入用連接端子6及用以輸出液晶 驅動信號之驅動信號輸出用連接端子7。液晶驅動電路數 因所搭載之液晶顯示裝置而異,並無限制。 互連基板3係由半導體材料,最好係由矽所構成。在互 連基板3上係形成設於液晶驅動器2下面之圖像信號輸入用 連接端子6與驅動信號輸出用連接端子7及用以覆晶安裝之 液晶驅動器連接端子8a(輸入側)· 8b(輸出側)。再者,在 與設有液晶驅動器連接端子8a· 8b之面相同面内,從液晶 125226.doc -10· 200824057 驅動器連接端子8a· 8b設置布線11,再於該布線u的前端 部13上經由薄膜基板連接端子1〇a· 1补而連接薄膜基板 4 〇 薄膜基板4係具有裝置孔9,其用以收容液晶驅動器2, 在裝置孔9周邊部設置互連基板3的薄膜基板連接端子 l〇a(輸入側)· 10b(輸出侧)之連接端子。連接端子間距係 對應互連基板3上的布線前端部13上的薄膜基板連接端子 間距(35 μιη以上),可與互連基板3相連接。 在薄膜基板4,從互連基板3的薄膜基板連接端子1〇a · l〇b設置用以與液晶顯示裝置(未圖示)相連接之布線、 及用以與圖像輸入控制部(未圖示)相連接之布線12a。再 者,在薄膜基板4,除了與互連基板3之連接部以外,設置 絕緣性銲錫光阻14(熱性電鍍材),以從灰塵或水保護設於 薄膜基板4之布線,並形成難以引起短路等缺陷之構成。 此外,溥膜基板4上的布線12a· 12b最好係銅箔,利用 蒸鍍、蝕刻或印刷等方法,形成布線圖案。尤其,布線不 限於銅箔時,印刷之形成係簡單而良好。再者,薄膜基板 4係使用聚醯亞胺(PI)或聚對苯二甲酸乙烯酯等有機 薄膜等的可撓性高的素材,以易於彎曲加工。 其-人,參知、圖3,進一步詳細說明液晶驅動器2與互連基 板3之連接及互連基板3與薄膜4之連接。 在此,從設於互連基板3之液晶驅動器連接端子“ · “ 延伸之布㈣係隨著靠近與薄膜基板4相連接之前端和 而擴大該布線間隔。具體表示之,液晶驅動器連接端子此 125226.doc • 11 · 200824057 的間距係25 μιη以下,但布線11的前端部13的間距可為35 μπι以上。如此,藉由中介互連基板3,可將1C製程水準的 微間距變換為薄膜基板水準的電極間距。因此,薄膜基板 的薄膜及布線,可使用習知之材料,且有關該安裝方法, 可使用既有的技術。 在液晶驅動器2與互連基板3之連接,為對應微間距,可 使用比較硬且融點高的金屬或合金製凸塊。例如,可適用 使用有金(An)凸塊之Au-Au接合。藉此,可抑制凸塊變 形’因可解決相鄰凸境間的接觸問題,故可縮小端子間距 直到25 μπι左右,可使液晶驅動器多輸出化。 另一方面,互連基板3與薄膜基板(未圖示)之連接,可 為具比與液晶驅動器2之連接端子廣的間距,例如35〜丨〇〇 μπι左右的間距之端子間連接。以互連基板3的布線丨i的前 端部13的薄膜基板連接端子10a · 1〇b的八11凸塊與施於薄膜 基板4上的布線12a · 12b前端部之錫與金-錫共晶連接進行 連接。此外,不形成如同Au凸塊之高價的連接電極,可適 用使用有異方性導電薄膜(ACF : Anis〇tr〇pic c〇nductiveFurther, the semiconductor package of the present invention is characterized in that the semiconductor wafer is a liquid crystal driver. A display device of the present invention is characterized by comprising any of the above semiconductor packages. According to the semiconductor package of the present invention, the connection terminals and the wiring can be arranged without excessively increasing the size of the interconnection substrate. Further, the amount of semiconductor material for high-priced germanium or the like for interconnecting substrates can be suppressed, and an increase in cost can be suppressed. Further objects, features, and advantages of the present invention will be apparent from the following description. Further, the benefits of the present invention will become apparent when the following description is made with reference to the accompanying drawings. [Embodiment] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Here, a liquid crystal driver package using the semiconductor package of the present invention will be described as an example. (Embodiment 1) 125226.doc 200824057 Fig. 1 is a plan view showing a liquid crystal driver package according to Embodiment 1 of the present invention. Fig. 2 is a cross-sectional view showing the liquid crystal driver package shown in Fig. 1 as viewed from the cut surface line A-A'. Further, Fig. 3 is an explanatory view showing the connection of the liquid crystal driver 2 and the interconnect substrate 3. Hereinafter, a schematic configuration of a liquid crystal driver package will be described with reference to Figs. 1, 2, and 3. The liquid crystal driver package 1 of the present embodiment is a semiconductor package of at least a liquid crystal driver 2 (semiconductor wafer), an interconnect substrate 3, and a thin film substrate 4, and a liquid crystal driver 2 The film substrate 4 is connected via the interconnect substrate 3. Further, a sealing resin 5 is filled between the liquid crystal driver 2, the interconnect substrate 3, and the film substrate 4, and the connection portion between the respective portions is reinforced and fixed. Here, the sealing resin 5 is generally referred to as a filler. An insulating resin (for example, an epoxy resin, an anthracene resin, a polyimide resin, or the like) can be used. The liquid crystal driver 2 is provided with at least one or more liquid crystal driving circuits (not shown) for driving the liquid crystal display device. Therefore, in the liquid crystal driver, an image signal input connection terminal 6 for inputting an image data signal or the like and a drive signal for outputting a liquid crystal drive signal are provided on a surface opposite to the interconnection substrate (hereinafter referred to as a lower surface). Output connection terminal 7. The number of liquid crystal drive circuits varies depending on the liquid crystal display device mounted, and is not limited. The interconnect substrate 3 is made of a semiconductor material, preferably of germanium. The image signal input connection terminal 6 and the drive signal output connection terminal 7 provided on the lower surface of the liquid crystal driver 2 and the liquid crystal driver connection terminal 8a (input side) 8b for flip chip mounting are formed on the interconnect substrate 3. Output side). Further, in the same plane as the surface on which the liquid crystal driver connection terminals 8a and 8b are provided, the wiring 11 is provided from the liquid crystal 125226.doc -10·200824057 driver connection terminals 8a and 8b, and the front end portion 13 of the wiring u is provided. The film substrate 4 is connected via the film substrate connection terminal 1A·1. The film substrate 4 has a device hole 9 for housing the liquid crystal driver 2, and a film substrate connection of the interconnection substrate 3 is provided at the periphery of the device hole 9. Terminal l〇a (input side) · 10b (output side) connection terminal. The connection terminal pitch is connected to the interconnection substrate 3 in correspondence with the film substrate connection terminal pitch (35 μm or more) on the wiring front end portion 13 on the interconnection substrate 3. In the film substrate 4, a wiring for connecting to a liquid crystal display device (not shown) and a picture input control portion are provided from the film substrate connection terminals 1a, 1b of the interconnection substrate 3 ( The wiring 12a that is connected is not shown. Further, in addition to the connection portion with the interconnect substrate 3, the film substrate 4 is provided with an insulating solder resist 14 (hot plate material) to protect the wiring provided on the film substrate 4 from dust or water, and is difficult to form. Causes the formation of defects such as short circuits. Further, it is preferable that the wirings 12a and 12b on the enamel film substrate 4 are made of a copper foil, and a wiring pattern is formed by a method such as vapor deposition, etching, or printing. In particular, when the wiring is not limited to the copper foil, the formation of printing is simple and good. Further, the film substrate 4 is made of a highly flexible material such as an organic film such as polyimine (PI) or polyethylene terephthalate, and is easily bent. The connection between the liquid crystal driver 2 and the interconnection substrate 3 and the connection between the interconnection substrate 3 and the film 4 will be further described in detail. Here, the cloth (4) extending from the liquid crystal driver connection terminal provided on the interconnect substrate 3 is enlarged in accordance with the front end of the film adjacent to the film substrate 4. Specifically, the pitch of the liquid crystal driver connection terminal is 125 μm or less, but the pitch of the front end portion 13 of the wiring 11 may be 35 μπ or more. Thus, by interposing the substrate 3, the micro pitch of the 1C process level can be converted into the electrode pitch of the film substrate level. Therefore, a conventional material can be used for the film and wiring of the film substrate, and an existing technique can be used for the mounting method. In connection with the interconnection of the liquid crystal driver 2 and the interconnection substrate 3, a metal or alloy bump which is relatively hard and has a high melting point can be used for the corresponding fine pitch. For example, an Au-Au joint using gold (An) bumps can be applied. Thereby, the bump deformation can be suppressed. Since the contact problem between adjacent bumps can be solved, the terminal pitch can be reduced to about 25 μπι, and the liquid crystal driver can be outputted more. On the other hand, the connection between the interconnect substrate 3 and the film substrate (not shown) may be a terminal having a wider pitch than the connection terminal of the liquid crystal driver 2, for example, a pitch of about 35 to 丨〇〇 μπι. The eleventh 11th bump of the film substrate connection terminal 10a·1〇b of the front end portion 13 of the wiring 丨i of the interconnection substrate 3 and the tin and gold-tin of the front end portion of the wiring 12a·12b applied to the film substrate 4 The eutectic connection is made to connect. In addition, a high-priced connection electrode such as an Au bump is not formed, and an anisotropic conductive film (ACF: Anis〇tr〇pic c〇nductive) can be used.

Film)或異方性導電膠(ACP : Anisotropic Conductive Paste) 之整個接合。 再者,藉由採用如同ACF/ACP接合,因在連接之電極不 需突起電極,故可期待互連基板3的步驟簡化。 其次,洋細說明互連基板上液晶驅動器2的連接位置。 圖4係對應表示液晶驅動器封裝體的平面圖(圖”與剖面 圖(圖2)的部分構成品,又,從剖面觀之,表示液晶驅動器 125226.doc -12- 200824057 2的中心線B與互連基板的中心線c之圖。 參照圖4,互連基板3上的液晶驅動器2係以將液晶驅動 器2的短邊中心線b形成於比互連基板3的短邊中心線c左 側(輸入側)之方式而設置。且以端子間的距離定義時,液 晶驅動器2係設於互連基板3上,以使從圖像信號輸入用連 接端子6(或液晶驅動器連接端子8a)至薄膜基板連接端子 ^ 1〇a之距離L1比驅動信號輸出用連接端子7(液晶驅動器連 馨 接端子8b)至薄膜基板連接端子i〇b之距離L2短。 或從裝置孔9與位於其中之液晶驅動器2之關係來看,液 晶驅動器2與互連基板3係設於薄膜基板4上,以使液晶驅 動器2的端面與前述裝置孔端面之距離在與液晶驅動器相 對之兩邊中圖像^號輸入用連接端子6(或液晶驅動器連接 端子8a)側L3中比驅動信號輸出用連接端子7(液晶驅動器 連接端子8b)側L4短。 液晶驅動器2係以下構成:為對應所搭載之液晶顯示裝 肇置的高微細化,要求多輸出化,輸出端子數比輸入端子數 多。因此,在互連基板3設置布線時,在端子數(布線數)多 的輸出侧,與輸入側相比,必須準備用以間距變換之充分 • 區域。 ‘因此,藉由上述構成,在互連基板3的液晶驅動器輸出 側,可分割更多的區域。此外,輸入側中,因端子數(布 線數)少,故用以間距變換的區域最好比輸出侧小。因 此,藉由在輸入側分割比輸出側區域小的區域,可有效的 使用互連基板上的區域,並可避免互連基板3的大型化。 125226.doc η 200824057 在此,詳細說明互連基板上的布線圖案,並說明端子數 (布線數)很多者’為間距變化而必須有大區域之理由。圖 5(a) · (b)係表不^一種互連基板上之布線圖案的部分圖。 互連基板(半導體基板)上的布線斜線部(相對於互連基板 至薄膜基板之直線部而傾斜設置的布線圖案)係相對於直 線部而以45度角配置(設計規則)。再者,本實施形態中, 布線寬係5 μιη,布線間隔係2 μπι,為使布線寬比布線間隔Film) or the entire joint of an anisotropic conductive paste (ACP: Anisotropic Conductive Paste). Further, by using the ACF/ACP bonding, since the electrodes are not required to be bumped at the electrodes to be connected, the step of interconnecting the substrates 3 can be expected to be simplified. Next, the details of the connection position of the liquid crystal driver 2 on the interconnect substrate will be described. 4 is a partial view showing a plan view (FIG.) and a cross-sectional view (FIG. 2) of the liquid crystal driver package, and further showing the center line B of the liquid crystal driver 125226.doc -12-200824057 2 and the mutual cross-section. Referring to FIG. 4, the liquid crystal driver 2 on the interconnect substrate 3 is formed to form the short side center line b of the liquid crystal driver 2 to the left side of the short side center line c of the interconnect substrate 3 (input The liquid crystal driver 2 is provided on the interconnect substrate 3 so as to be defined from the image signal input connection terminal 6 (or the liquid crystal driver connection terminal 8a) to the film substrate. The distance L1 of the connection terminal ^1〇a is shorter than the distance L2 between the drive signal output connection terminal 7 (the liquid crystal driver connection terminal 8b) and the film substrate connection terminal i〇b. Or from the device hole 9 and the liquid crystal driver located therein 2, the liquid crystal driver 2 and the interconnect substrate 3 are disposed on the film substrate 4 such that the distance between the end surface of the liquid crystal driver 2 and the end face of the device hole is the image input on both sides opposite to the liquid crystal driver. Connection end The sub-6 (or the liquid crystal driver connection terminal 8a) side L3 is shorter than the drive signal output connection terminal 7 (liquid crystal driver connection terminal 8b) side L4. The liquid crystal driver 2 is configured to correspond to the mounted liquid crystal display device. The number of output terminals is larger than the number of input terminals. Therefore, when wiring is provided on the interconnect substrate 3, the output side with a large number of terminals (number of wires) must be compared with the input side. A sufficient area for the pitch conversion is prepared. Therefore, with the above configuration, more areas can be divided on the output side of the liquid crystal driver of the interconnect substrate 3. Further, the number of terminals (number of wirings) in the input side Therefore, the area for pitch conversion is preferably smaller than the output side. Therefore, by dividing the area smaller than the output side area on the input side, the area on the interconnection substrate can be effectively used, and the interconnection substrate 3 can be avoided. 125226.doc η 200824057 Here, the wiring pattern on the interconnect substrate will be described in detail, and the reason why the number of terminals (the number of wires) is large must be large for the pitch change. Fig. 5 (a ) (b) A partial view of a wiring pattern on an interconnect substrate. A diagonal portion of the wiring on the interconnect substrate (semiconductor substrate) (inclined with respect to a straight portion of the interconnect substrate to the film substrate) The wiring pattern is arranged at an angle of 45 degrees with respect to the straight portion (design rule). In the present embodiment, the wiring width is 5 μm and the wiring interval is 2 μm, so that the wiring width is wider than the wiring interval.

大’在凹折布線而設置之處(直線部與斜線部之交點,以 下稱為交點)中,必須錯開交點而設置布線,以使布線者 不相接觸。 因此,考慮如圖5所示的二種布線圖案。因一同錯開交 點而設有布線,故伴隨端子數(布線數)變多,距離。及。 亦變長,必須在互連基板上形成更多用以布線間距變換的 區域。 因此,互連基板上,在端子數(布線數)很多的輸出側, 與端子數少的輸入側相比,為間距變換,必須形成更大的 區域。 此外’伴隨液晶驅動器的多輸出化’考慮如圖6所示的 輸出端子圖案。如圖3所示,藉由排列一行輸出端子,藉 由將輸出端子排列成千鳥狀,在必須形成比布線部分大二 電極寬之端子部,因鄰接的端子者不會相干涉,故可進一 步微間距化’藉此可避免液晶驅動器的大型化。In the case where the recessed wiring is provided (the intersection of the straight portion and the oblique portion, hereinafter referred to as the intersection), the wiring must be staggered so that the wiring is not in contact. Therefore, consider two wiring patterns as shown in FIG. Since the wiring is provided by staggering the intersection, the number of terminals (the number of wirings) is increased and the distance is increased. and. It also becomes longer, and more areas for wiring pitch conversion must be formed on the interconnect substrate. Therefore, on the interconnect substrate, the output side having a large number of terminals (the number of wirings) has a larger pitch than the input side with a small number of terminals. Further, the output terminal pattern shown in Fig. 6 is considered in conjunction with the multi-output of the liquid crystal driver. As shown in FIG. 3, by arranging one row of output terminals, by arranging the output terminals in a thousand bird shape, it is necessary to form a terminal portion which is wider than the wiring portion by the second electrode, and since the adjacent terminals do not interfere, it is possible to further Micro-pitching 'This makes it possible to avoid an increase in the size of the liquid crystal driver.

I25226.doc 使採用該種千鳥狀驅動信號輸出用連接端子7的圖 ° 乂用本^明之構成’其係使液晶驅動器2在互連 -14- 200824057 基板3上錯開輸人侧而設置。因本發明的輸出端子數比輸 入端子數愈多,其效果越佳,故在對應有多輸出化之布線 數多的千鳥狀端子圖案中特別有效。 再者,伴隨液晶驅動器的多輸出化,也可使互連基板3 上的布線前端部13、與薄膜基板連接端子1〇a · 1〇b相連接 之薄膜基板4的前端部形成千鳥狀圖案。(未圖示) 又’藉由將液晶驅動器2在互連基板3上錯開輸入側而設 置,如圖4所示,在基板間產生不同長度的間隔l3(輸入 側)及間隔L4(輸出側)。液晶驅動器封裝體丨的製程方面, 分別連接液晶驅動器2、互連基板3及薄膜基板4後,在其 間填入密封樹脂5,但因注入密封樹脂5,必須有某種程度 大小的間隔。亦即,液晶驅動器2與薄膜基板4之間隔必須 保持某種程度,但間隔L4中,因可確保可盡量注入密封樹 脂5的間隔,故即使一間隔的間隔L3很窄,也可實現樹脂 注入。因此,與液晶驅動器輸入側的薄膜基板之間隔變窄 之本實施形態,對半導體封裝體的小型化有效。 上述之例中,配置於互連基板兩邊之複數端子係分別分 成輸入用及輸出用,但並不侷限於此。例如,伴隨輸出用 端子的增加,可將輸入側的部分區域設定在輸出側的端子 區域。藉由該構成,從輸入側將布線圍在部分輸出側而設 於互連基板上。因此,可進一步有效活用互連基板上的命 間’並可避免半導體封裝體大型化。 (實施形態2) 實施形態1中,係以CtOF液晶驅動器封裝體為例而說 125226.doc -15- 200824057 明,但本發明也可適用TCP半導體封裝體。實施形態2係 說明使用有本發明之TCP液晶驅動器封裝體。 圖7係對應實施形態1之說明所使用圖4之圖,其表示 TCP液晶驅動器封裝體21的平面圖與剖面圖,並表示各構 成構件的位置關係。 參照圖7,本實施形態之TCP液晶驅動器封裝體21係以 下構成:液晶驅動器22經由經由互連基板23而連接薄膜基 板24。但是,以下之點係與COF半導體封裝體不同:薄膜 基板24係具有突出於裝置孔之飛線25,互連基板23與薄膜 基板2 4係經由飛線2 5,從形成有薄膜基板2 4的布線之面的 背面接合。 本實施形態中,係使用本發明,其係有效活用互連基板 上的區域,並避免半導體封裝體大型化。與應實施形態1 之COF液晶驅動器封裝體相同,互連基板23上的液晶驅動 器22係以將液晶驅動器22的中心線D形成比互連基板23的 中心線E左侧(輸入侧)之方式而設置。且以端子間的距離 定義之’液晶驅動器22係設於互連基板23上,以使圖像信 號輸入用連接端子26(或液晶驅動器連接端子28a)至薄膜基 板連接端子30a之距離L5比驅動信號輸出用連接端子27(或 液晶驅動器連接端子28 b)直到薄膜基板連接端子30b之L6 短。 藉由形成本構成,在互連基板23上可有效活用供輸出端 子側間距變換之區域,其結果,可配置連接端子及布線, 而不用互連基板23大型化為必要以上。 125226.doc -16- 200824057 (實施形態3) 圖8係表示本實施形態之液晶g§ _ 风日日顯不骏置(顯示裝置)50構 成的概略圖。液晶顯示裝置5〇係目| & 川係具備實施形態1之液晶驅 動器封裝體1及液晶面板4 0,液$啦知 4文日日驅動器封裝體1係安裝於 液晶面板40。藉此,液晶驅動器封裝體⑽液晶驅動器. 動液晶面板40的掃描線4卜另外’液晶顯示裝置⑽也可具 備實施形態2之液晶驅動器封裝體21,以取代液晶驅動器 封裝體1。I25226.doc The configuration of the connection terminal 7 for the thousand bird-shaped drive signal output is made by the configuration of the present invention, which is provided such that the liquid crystal driver 2 is shifted from the input side to the substrate 3 of the interconnection -14-200824057. Since the number of output terminals of the present invention is larger than the number of input terminals, the effect is more excellent, and therefore it is particularly effective in a thousand bird-shaped terminal pattern corresponding to a large number of wirings having a large number of outputs. Further, with the multi-output of the liquid crystal driver, the tip end portion of the wiring substrate 13 on the interconnect substrate 3 and the film substrate 4 connected to the film substrate connecting terminal 1a, 1b can be formed into a bird shape. pattern. (not shown) Further, by providing the liquid crystal driver 2 on the interconnect substrate 3 with the input side shifted, as shown in FIG. 4, intervals 13 (input side) and intervals L4 (output side) of different lengths are generated between the substrates. ). In the process of the liquid crystal driver package, the liquid crystal driver 2, the interconnect substrate 3, and the film substrate 4 are respectively connected, and the sealing resin 5 is filled therebetween. However, the sealing resin 5 is injected with a certain interval. In other words, the distance between the liquid crystal driver 2 and the film substrate 4 must be kept to some extent. However, in the interval L4, since the interval at which the sealing resin 5 can be injected as much as possible is ensured, resin injection can be realized even if the interval L3 is narrow. . Therefore, the present embodiment in which the distance from the thin film substrate on the input side of the liquid crystal driver is narrowed is effective for downsizing the semiconductor package. In the above example, the plurality of terminals disposed on both sides of the interconnect substrate are divided into input and output, respectively, but are not limited thereto. For example, with the increase of the output terminal, the partial area on the input side can be set in the terminal area on the output side. With this configuration, the wiring is provided on the interconnect substrate from the input side around the partial output side. Therefore, the life on the interconnect substrate can be further effectively utilized and the semiconductor package can be prevented from being enlarged. (Embodiment 2) In the first embodiment, a CtOF liquid crystal driver package is exemplified as 125226.doc -15-200824057, but the present invention is also applicable to a TCP semiconductor package. Embodiment 2 describes the use of the TCP liquid crystal driver package of the present invention. Fig. 7 is a plan view and a cross-sectional view showing the TCP liquid crystal driver package 21, showing the positional relationship of the respective constituent members, in accordance with Fig. 4, which is used in the description of the first embodiment. Referring to Fig. 7, the TCP liquid crystal driver package 21 of the present embodiment is configured such that the liquid crystal driver 22 is connected to the film substrate 24 via the interconnect substrate 23. However, the following points are different from the COF semiconductor package: the film substrate 24 has a flying wire 25 protruding from the device hole, and the interconnect substrate 23 and the film substrate 24 are formed by the flying wire 25 from the thin film substrate 2 The back side of the wiring is joined. In the present embodiment, the present invention is used in which the area on the interconnect substrate is effectively utilized and the size of the semiconductor package is prevented from increasing. Similarly to the COF liquid crystal driver package of Embodiment 1, the liquid crystal driver 22 on the interconnection substrate 23 is formed such that the center line D of the liquid crystal driver 22 is formed on the left side (input side) of the center line E of the interconnection substrate 23. And set. And the 'liquid crystal driver 22' defined by the distance between the terminals is provided on the interconnect substrate 23 so that the image signal input connection terminal 26 (or the liquid crystal driver connection terminal 28a) is connected to the film substrate connection terminal 30a by a distance L5 ratio drive. The signal output connection terminal 27 (or the liquid crystal driver connection terminal 28b) is short until L6 of the film substrate connection terminal 30b. By forming this configuration, the area for the output terminal side pitch conversion can be effectively utilized on the interconnection substrate 23. As a result, the connection terminals and the wiring can be arranged without increasing the size of the interconnection substrate 23. 125226.doc -16- 200824057 (Embodiment 3) Fig. 8 is a schematic view showing a configuration of a liquid crystal g§_wind day display device (display device) 50 of the present embodiment. In the liquid crystal display device, the liquid crystal driver package 1 and the liquid crystal panel 40 of the first embodiment are provided, and the liquid crystal panel 40 is mounted on the liquid crystal panel 40. Thereby, the liquid crystal driver package (10) liquid crystal driver. The scanning line 4 of the liquid crystal panel 40. Alternatively, the liquid crystal display device (10) may be provided with the liquid crystal driver package 21 of the second embodiment instead of the liquid crystal driver package 1.

本說明書中,係以液晶驅動器為例而說明,但使用有互 連基板之帶載型半導體封裝體,也可適用本說明。此外, 不限於半導體晶片的輸出端子數比輸入端子數多之半導體 封裝體’用以收容相對的兩邊所配置端子數不同之半導體 晶片之半導體封裝體,也可適用本說明。 另外,本次所揭示之實施形態的所有點係例示,並非有 所侷限。本發明之技術範圍依申請專利範圍而劃定,且咅 圖包含申請專利m圍之記載等的意義^圍内的所有^ 更0 【圖式簡單說明】 圖Η系本發明實施形態i之半導體封裝體的平面圖。 圖2係本發明實施形態1之半導體封裝體的剖面圖。 S係表示本發明實施形悲1之半導體封裝體之半導體晶 片與互連基板的連接圖。 圖4係表示本發明實施形態1之半導體封裝體之半導體晶 片與互連基板的連接位置關係圖。 125226.doc -17- 200824057 圖5(a)、(b)係表示互連基板上之布線圖案的部分圖。 圖6係表示本發明實施形態〗之半導體封裝體之半導體晶 片與互連基板的連接圖。 圖7係表示本發明實施形態2之半導體封裝體之半導體晶 片與互連基板的連接位置關係圖。 圖8係表示本發明實施形態3之液晶顯示裝置構成的概略 圖。 圖9係專利文獻1所記載之COF半導體封裝體的剖面圖。 【主要元件符號說明】 1 2 3 4 5 6 7 8a 8b 9 10a 10b 11 12a 12b 液晶驅動器封裝體 液晶驅動器 互連基板 薄膜基板 密封樹脂 圖像信號輸入用連接端子 驅動信號輸出用連接端子 液晶驅動器連接端子(輸入) 液晶驅動器連接端子(輸出) 裝置孔 薄膜基板連接端子(輸入) 薄膜基板連接端子(輸出) 布線(互連基板) 布線(薄膜基板·輸入) 布線(薄膜基板·輸出) 125226.doc -18- 200824057 13 布 14 銲 21 液 22 液 線&端部(互連基板) 錫光阻 晶驅動器封裝體(TCP) 晶驅動益In the present specification, a liquid crystal driver is taken as an example, but the present invention can also be applied to a tape-type semiconductor package having an interconnect substrate. Further, the present invention is not limited to the semiconductor package in which the number of output terminals of the semiconductor wafer is larger than the number of input terminals, and the semiconductor package for accommodating the semiconductor chips having different numbers of terminals disposed on opposite sides. In addition, all the points of the embodiments disclosed herein are not limited. The technical scope of the present invention is defined in accordance with the scope of the patent application, and the drawings include all the meanings of the meanings of the patent application, etc. [Comprehensive description of the drawings] Figure Η The semiconductor of the embodiment i of the present invention A plan view of the package. Fig. 2 is a cross-sectional view showing a semiconductor package according to a first embodiment of the present invention. S is a connection diagram of a semiconductor wafer and an interconnect substrate of a semiconductor package of the present invention. Fig. 4 is a view showing a connection positional relationship between a semiconductor wafer and an interconnection substrate of the semiconductor package according to the first embodiment of the present invention. 125226.doc -17- 200824057 FIGS. 5(a) and (b) are partial views showing a wiring pattern on an interconnect substrate. Fig. 6 is a view showing a connection between a semiconductor wafer and an interconnect substrate of a semiconductor package according to an embodiment of the present invention. Fig. 7 is a view showing a connection positional relationship between a semiconductor wafer and an interconnection substrate of a semiconductor package in accordance with a second embodiment of the present invention. Fig. 8 is a schematic view showing the configuration of a liquid crystal display device according to a third embodiment of the present invention. FIG. 9 is a cross-sectional view of the COF semiconductor package described in Patent Document 1. [Main component symbol description] 1 2 3 4 5 6 7 8a 8b 9 10a 10b 11 12a 12b Liquid crystal driver package liquid crystal driver interconnection substrate film substrate sealing resin image signal input connection terminal drive signal output connection terminal liquid crystal driver connection Terminal (input) Liquid crystal driver connection terminal (output) Device hole film substrate connection terminal (input) Film substrate connection terminal (output) Wiring (interconnect substrate) Wiring (film substrate/input) Wiring (film substrate/output) 125226.doc -18- 200824057 13 cloth 14 welding 21 liquid 22 liquid line & end (interconnect substrate) tin photoresist driver package (TCP) crystal drive benefits

23 互連基板 24 薄膜基板 25 26 28a 28 b 30a 30b 31 飛線 圖像信號輸入用連接端子 驅動信號輸出用連接端子 液晶驅動器連接端子(輸入) 液晶驅動器連接端子(輸出) 薄膜基板連接端子(輸入) 薄膜基板連接端子(輸出) 半導體封裝體 32 1C晶片 33 40 互連基板 液晶面板 41 掃描線 5 0 液晶顯示裝置(顯示裝置) 125226.doc -19-23 Interconnect substrate 24 Film substrate 25 26 28a 28 b 30a 30b 31 Flying line image signal input connection terminal drive signal output connection terminal LCD driver connection terminal (input) LCD driver connection terminal (output) Film substrate connection terminal (input Film substrate connection terminal (output) Semiconductor package 32 1C wafer 33 40 Interconnect substrate liquid crystal panel 41 Scan line 5 0 Liquid crystal display device (display device) 125226.doc -19-

Claims (1)

200824057 十、申請專利範圍: L 一種半導體封裝體’其係半導體晶片經由互連基板而連 接於薄膜基板者,其特徵係: 述半‘體晶片的中心位置與前述互連基板的中心位 置不同。200824057 X. Patent Application Range: L A semiconductor package, in which a semiconductor wafer is connected to a film substrate via an interconnection substrate, is characterized in that the center position of the half-body wafer is different from the center position of the interconnection substrate. —種半導體封裝體’其係半導體晶片經由互連基板而連 接於薄膜基板者,其特徵係: 别述半導體晶片至少於相對的兩邊分別具有複數端 子; 再2,於前述互連基板,從前述互連基板中心偏移連 接於W述相對的兩邊中端子數少的一方側。 3. 一種半導體封裝體,其係半導體晶片經由互連基板而連 接於薄膜基板者,其特徵係: 别述半‘體晶片至少於相對的兩邊分別具有複數端 子; 月’J述互連基板至少於相對的兩邊分別具有連接於前述 薄膜基板之薄膜基板連接端子,並在前述薄膜基板連接 端子内側具有複數何體晶#連接料,其係與配置於 W述半導體晶片相對的兩邊之複數端子連接; 1Γ述互連基板相對的兩邊各自之前述薄膜基板連接端 子與前述半導體晶片連接端子之㈣,在前述半導體晶 片連接端子的端子數少者係比另一方短。 4. -種料體封錢’其料導體晶片㈣互連基板而連 接於薄膜基板者,其特徵係·· 125226.doc 200824057 兩邊分別具有複數端 前述半導體晶片至少於相對的 子; 前述薄膜基板具有裝置孔 述裝置孔内; 1前述半導體晶片位於前 • #者’前述裝置孔之相對的兩邊各自之前述半導體晶 片端面與前述裝置孔端面之距離,在前述半導體晶片相 對的兩邊中端子數少者係比另一方短。 籲5.如請求項2至4中任一項之半導體封裝體,其中在前述半 導體晶片相對的兩邊中的一邊配置至前述半導體晶片之 輸入信號端子,並在另—邊配置來自前述半導體晶片之 輸出信號端子。 3长項5之半導體封裝體’其中前述輸出信號端子的 端子數比前述輸入信號端子的端子數多。 7·如請求項丨至4中任一項之半導體封裝體,其中前述互連 基板係由矽所構成。 • 8.如請求項丨至4中任一項之半導體封裝體,其中前述半導 體晶片係液晶驅動器。 9· 一種顯示裝置,其特徵係:具有半導體封裝體,其係半 導體晶片經由互連基板而連接於薄膜基板,且前述半導 體晶片的中心位置與前述互連基板的中心位置不同。 125226.doca semiconductor package in which a semiconductor wafer is connected to a film substrate via an interconnect substrate, wherein: the semiconductor wafer has a plurality of terminals on at least opposite sides thereof; and further, in the interconnect substrate, from the foregoing The center of the interconnect substrate is shifted to the side of the two sides where the number of terminals is small. 3. A semiconductor package, wherein the semiconductor wafer is connected to the film substrate via the interconnect substrate, wherein: the semi-body wafer has a plurality of terminals at least on opposite sides; Each of the opposite sides has a film substrate connection terminal connected to the film substrate, and has a plurality of body material interconnects on the inner side of the film substrate connection terminal, and is connected to a plurality of terminals disposed on opposite sides of the semiconductor wafer; (4) of each of the film substrate connection terminals on the opposite sides of the interconnect substrate and the semiconductor wafer connection terminal, the number of terminals of the semiconductor chip connection terminal is shorter than the other. 4. - The material body seals the money conductor wafer (4) interconnects the substrate and is connected to the film substrate, and the characteristics thereof are: 125226.doc 200824057 has a plurality of ends of the semiconductor wafer at least opposite to each other; the film substrate Having the device aperture in the device aperture; 1 the semiconductor wafer is located on the opposite sides of the device hole, the distance between the end surface of the semiconductor wafer and the end surface of the device hole, the number of terminals in the opposite sides of the semiconductor wafer is small The person is shorter than the other. The semiconductor package according to any one of claims 2 to 4, wherein one of the opposite sides of the semiconductor wafer is disposed to an input signal terminal of the semiconductor wafer, and is disposed on the other side from the semiconductor wafer. Output signal terminal. In the semiconductor package of the term "5", the number of terminals of the output signal terminal is larger than the number of terminals of the input signal terminal. The semiconductor package of any one of claims 4 to 4, wherein the aforementioned interconnect substrate is composed of germanium. The semiconductor package of any one of claims 4 to 4, wherein the semiconductor wafer is a liquid crystal driver. A display device comprising: a semiconductor package, wherein the semiconductor wafer is connected to the film substrate via an interconnection substrate, and a center position of the semiconductor wafer is different from a center position of the interconnection substrate. 125226.doc
TW096136896A 2006-10-04 2007-10-02 Semiconductor package and display apparatus TWI361476B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006273306A JP4837513B2 (en) 2006-10-04 2006-10-04 Semiconductor package manufacturing method and display device manufacturing method

Publications (2)

Publication Number Publication Date
TW200824057A true TW200824057A (en) 2008-06-01
TWI361476B TWI361476B (en) 2012-04-01

Family

ID=39268369

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096136896A TWI361476B (en) 2006-10-04 2007-10-02 Semiconductor package and display apparatus

Country Status (3)

Country Link
JP (1) JP4837513B2 (en)
TW (1) TWI361476B (en)
WO (1) WO2008041507A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5589462B2 (en) * 2010-03-16 2014-09-17 カシオ計算機株式会社 Semiconductor device and manufacturing method of semiconductor device
JP6237315B2 (en) * 2014-02-18 2017-11-29 セイコーエプソン株式会社 Liquid discharge head and liquid discharge apparatus

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996021948A1 (en) * 1995-01-13 1996-07-18 Seiko Epson Corporation Semiconductor device, tape carrier package, and display panel module
JP3985016B2 (en) * 1997-10-31 2007-10-03 沖電気工業株式会社 Semiconductor device
JP3967263B2 (en) * 2002-12-26 2007-08-29 セイコーインスツル株式会社 Semiconductor device and display device
JP4689202B2 (en) * 2004-07-07 2011-05-25 ルネサスエレクトロニクス株式会社 Driving device and display device

Also Published As

Publication number Publication date
JP2008091790A (en) 2008-04-17
WO2008041507A1 (en) 2008-04-10
JP4837513B2 (en) 2011-12-14
TWI361476B (en) 2012-04-01

Similar Documents

Publication Publication Date Title
JP4271435B2 (en) Semiconductor device
TW473950B (en) Semiconductor device and its manufacturing method, manufacturing apparatus, circuit base board and electronic machine
US7109575B2 (en) Low-cost flexible film package module and method of manufacturing the same
JP2002083922A (en) Semiconductor device and its manufacturing method, and circuit board and electronic equipment
US6521483B1 (en) Semiconductor device, method of manufacture thereof, circuit board, and electronic device
JP2002083897A (en) Semiconductor device and manufacturing method thereof and, circuit board and electronic apparatus
JP2007048812A (en) Semiconductor device
US7508073B2 (en) Wiring board, semiconductor device using the same, and method for manufacturing wiring board
JP2006073925A (en) Semiconductor device
US8338965B2 (en) Semiconductor chip and semiconductor device, and method for manufacturing semiconductor device
JP2008135486A (en) Semiconductor device and semiconductor package
US7247936B2 (en) Tape circuit substrate having wavy beam leads and semiconductor chip package using the same
TW200824057A (en) Semiconductor package and display apparatus
US6853080B2 (en) Electronic device and method of manufacturing the same, and electronic instrument
US7279794B2 (en) Semiconductor device and electronic device, and methods for manufacturing thereof
US11830803B2 (en) Chip-on-film package having redistribution pattern between semiconductor chip and connection terminal
JP2004087936A (en) Semiconductor device, manufacturing method thereof, and electronic appliance
US20240014221A1 (en) Semiconductor package and package module including the same
US7042069B2 (en) Semiconductor device and method of manufacturing same, wiring board, electronic module, and electronic instrument
US6720205B2 (en) Electronic device and method of manufacturing the same, and electronic instrument
JP2004214373A (en) Semiconductor device with bumps and its packaging method
JP2007036283A (en) Semiconductor device
JP2010251566A (en) Wiring board, semiconductor device, semiconductor module, and method of manufacturing the module
JP2009049154A (en) Semiconductor device, packaging structure, electrooptical device, and electronic equipment
JP2004177578A (en) Electronic module