200822208 九、發明說明 【發明所屬之技術領域】 本發明是關於適於用來製造例如液晶顯示裝置等的半 導體裝置的半導體裝置之製造方法、半導體裝置之製造裝 置、電腦記憶媒體及記憶有處理程式之記憶媒體。 【先前技術】 過去以來，在半導體裝置的製程中，進行所要部位的 蝕刻時，大多是採用使用藥液的濕式蝕刻、及使用氣體的 乾式蝕刻。乾式蝕刻已知有：例如讓蝕刻氣體的電漿產生 ，藉由該電漿的作用來進行蝕刻之電漿蝕刻等。 例如液晶顯示裝置之非晶質矽TFT (薄膜電晶體）的 製程等，係在將金屬膜予以蝕刻來形成閘極、源極以及汲 極的步驟、將非晶質矽膜等予以蝕刻來形成島形構造的步 驟、形成通道的步驟中等，適當地使用濕式鈾刻及乾式鈾 刻。此外，大多是的情況，濕式蝕刻主要用於金屬膜的蝕 刻步驟。另外，還已知有：在上述的蝕刻步驟之間，利用 氧氣及含有氟的氣體之混合氣體進行灰化，除去半導體層 周緣部的***層，以改善電流特性的技術（例如，參考曰 本專利文獻1 )。 另外，上述液晶顯示裝置之非晶質矽TFT的製程，進 展成：移往使用呈段狀地形成的抗飩遮罩，讓遮罩數減少 之省遮罩處理。該省遮罩處理，係藉由將呈段狀形成之抗 蝕遮罩灰化到中途來變更該形狀，當作2種遮罩來使用， 200822208 可以減少1次遮罩形成步驟。 進而，依照在使用上述呈段狀形成的抗蝕遮罩的步驟 ，進行2次濕式鈾刻步驟及2次乾式飩刻的方法，將第2 次的濕式蝕刻步驟置換成乾式蝕刻，能夠藉由配線寬度、 通道長度等之控制性的提升；濕式藥液之使用成本的降低 •，步驟的減少等，達到提升生產性和良品率。 然而，將進行過1次乾式蝕刻的金屬膜，之後經由乾 式触刻來予以蝕刻，會在進行濕式蝕刻鈾時與飩刻液相接 觸，因而會有形成在金屬膜的緣部（露出部）之變質層， 在乾式蝕刻時未被蝕刻，成爲殘渣餘留著，對之後的步驟 造成不良影響，或對裝置特性造成不良影響的問題。例如 ，會有在源極-汲極間存在有上述的殘渣，導致源極-汲 極間電短路的事態。 專利文獻1 :日本專利特開2 0 0 5 — 7 2 4 4 3號公報 【發明內容】 <發明所欲解決之課題> 如以上所述，習知的技術所存在的課題爲：具有將金 屬模予以濕式蝕刻的步驟、及之後再將該金屬膜予以乾式 蝕刻的步驟的情況，濕式蝕刻時曝露在藥液中之金屬膜的 側面所形成的變質層，會在乾式蝕刻時未被蝕刻而變成殘 渣呈圍籬狀殘留著，對之後的步驟造成不良影響，還會對 裝置特性造成不良影響。 本發明係爲了要解決上述課題而提案，其目的係提供 -6- 200822208 具有將金屬膜予以濕式蝕刻的步驟、及之後具有將該金屬 膜予以乾式蝕刻的步驟的情況，可以減少：在濕式蝕刻步 驟中被形成在金屬膜上之變質層的殘渣導致對之後的步驟 所造成的不良影響和對裝置特性所造成的不良影響，又可 以穩定地製造良質的半導體裝置的半導體裝置之製造方法 、半導體裝置之製造裝置、電腦記憶媒體及記憶有處理程 式之記憶媒體。 <用以解決課題之手段> 本發明申請專利範圍第1項所述的半導體裝置之製造 方法’是一種具有：將被形成在基板上的金屬膜在濕式蝕 刻步驟中予以鈾刻之後，再將前述金屬膜予以乾式飩刻之 乾式蝕刻步驟的半導體裝置之製造方法，特徵爲：在前述 乾式餓刻步驟之前，進行：將在前述濕式蝕刻步驟中被形 成在前述金屬膜上之變質層予以除去之變質層除去步驟。 本發明申請專利範圍第2項所述的半導體裝置之製造 方法，如同申請專利範圍第1項所述的半導體裝置之製造 方法，其中，將前述基板收容在處理腔室（chainber)內，不 從前述處理腔室內搬出前述基板，持續持執行前述變質層 除去步驟及前述乾式蝕刻步驟。 本發明申請專利範圍第3項所述的半導體裝置之製造 方法’是一種具有：將被形成在基板上的金屬膜經由抗蝕 遮罩在濕式蝕刻步驟中予以蝕刻之後，再將前述金屬膜予 以乾式蝕刻之乾式蝕刻步驟的半導體裝置之製造方法其特 200822208 徵爲：具備有以下的步驟：將前述抗蝕遮罩的一部分予以 灰化變更前述抗蝕遮罩的形狀之灰化步驟、及將在前述濕 式蝕刻步驟中被形成在前述金屬膜上之變質層予以除去之 變質層除去步驟、及經由在前述灰化步驟中變更形狀之前 述抗飩遮罩，將前述金屬膜予以乾式鈾刻之乾式蝕刻步驟 〇 本發明申請專利範圍第4項所述的半導體裝置之製造 方法，如同申請專利範圍第3項所述的半導體裝置之製造 方法，其中，將前述基板收容在處理腔室內，不從前述處 理腔室內搬出前述基板，持續執行前述灰化步驟及前述變 質層除去步驟及前述乾式蝕刻步驟。 本發明申請專利範圍第5項所述的半導體裝置之製造 方法，是一種具有：將被形成在基板上的金屬膜經由抗蝕 遮罩在濕式飩刻步驟中予以蝕刻之後，再將前述金屬膜予 以乾式蝕刻之乾式蝕刻步驟的半導體裝置之製造方法其特 徵爲··具備有以下的步驟：經由前述抗鈾遮罩’將前述金 屬膜之下層的非晶質矽膜予以乾式蝕刻之第1乾式蝕刻步 驟、及將前述抗蝕遮罩的一部分予以灰化變更前述抗蝕遮 罩的形狀之灰化步驟、及將在前述濕式蝕刻步驟被形成在 前述金屬膜上的變質層予以除去之變質層除去步驟、及經 由在前述灰化步驟中變更形狀之前述抗蝕遮罩’將前述金 屬膜予以乾式蝕刻之第2乾式蝕刻步驟、及經由在前述灰 化步驟中變更形狀之前述抗蝕遮罩’將前述非晶質矽膜予 以乾式蝕刻之第3乾式餓刻步驟。 -8- 200822208 本發明申請專利範圍第6項所述的半導體 方法，如同申請專利範圍第5項所述的半導體 方法，其中，將前述基板收容在處理腔室內， 理腔室內搬出前述基板，持續執行前述第1乾 、及前述灰化步驟、及前述變質層除去步驟、 乾式餓刻步驟、及前述第3乾式蝕刻步驟。 本發明申請專利範圍第7項所述的半導體 方法，是一種具有：具有：將被形成在基板上 由抗蝕遮罩在濕式蝕刻步驟中予以蝕刻之後， 屬膜予以乾式鈾刻之乾式蝕刻步驟的半導體裝 法其特徵爲：具備有以下的步驟：將前述抗蝕 分予以灰化變更前述抗鈾遮罩的形狀之灰化步 前述濕式蝕刻步驟中被形成在前述金屬膜上的 除去之變質層除去步驟、及經由在前述灰化步 狀之前述抗飩遮罩，將前述金屬膜之下層的非 以乾式鈾刻之第1乾式蝕刻步驟、及經由在前 中變更形狀之前述抗蝕遮罩，將前述金屬膜予 之第2乾式蝕刻步驟、及經由在前述灰化步驟 之前述抗蝕遮罩，將前述非晶質矽膜予以乾式 乾式鈾刻步驟。 本發明申請專利範圍第8項所述的半導體 方法，如同申請專利範圍第7項所述的半導體 方法，其中，利用前述第1乾式蝕刻步驟，將 的一部分予以乾式蝕刻。 _ S之製造 裝置之製造 不從前述處 式蝕刻步驟 及前述第2 裝置之製造 的金屬膜經 再將前述金 置之製造方 遮罩的一部 驟、及將在 變質層予以 驟中變更形 晶質矽膜予 述灰化步驟 以乾式蝕刻 中變更形狀 鈾刻之第3 裝置之製造 裝置之製造 前述金屬膜 -9- 200822208 本發明申請專利範圍第9項所述的半導體裝置之製造 方法，如同申請專利範圍第7或8項所述的半導體裝置之 製造方法，其中，將前述基板收容在處理腔室內，不從前 述處理腔室內搬出前述基板，持續執行前述灰化步驟、及 前述變質層除去步驟、及前述第1乾式蝕刻步驟、及前述 第2乾式鈾刻步驟、及前述第3乾式蝕刻步驟。 本發明申請專利範圍第1 〇項所述的半導體裝置之製 造方法，如同申請專利範圍第1至9項中任一項所述的半 導體裝置之製造方法，其中，使用含有SF6及Cl2的混合 氣體、或含有SF6及02的混合氣體之電漿，進行前述變 質層除去步驟。 本發明申請專利範圍第1 1項所述的半導體裝置之製 造方法，申請專利範圍第1至1 〇項中任一項所述的半導 體裝置之製造方法，其中，前述金屬膜爲鋁或該合金膜、 鉬或該合金膜、鋁或該合金膜與鉬或該合金膜的層積膜中 的任何一種。 本發明申請專利範圍第1 2項所述的半導體裝置之製 造裝置，其特徵爲，具備有：收容基板之處理腔室、及將 處理氣體供應至前述處理腔室內之處理氣體供應手段、及 將從前述處理氣體供應手段所供應的前述處理氣體予以電 漿化來處理前述基板之電漿產生手段、及控制成在前述處 理腔室內執行申請專利範圍第1至11項中任一項所述的 半導體裝置之製造方法之控制部。 本發明申請專利範圍第1 3項所述的電腦記憶媒體， -10- 200822208 是一種記憶有在電腦上執行動作的控制程式之電腦記憶媒 體，其特徵爲：前述控制程式係控制半導體裝置的製造裝 置，以使其於執行時施行申請專利範圍第1至1 1項中任 一項所述的半導體裝置之製造方法。 本發明申請專利範圍第1 4項所述的記憶有處理程式 之記憶媒體，用以控制執行：將被形成在基板上的金屬膜 在濕式蝕刻步驟中予以蝕刻過後再將前述金屬膜予以乾式 餓刻之乾式蝕刻步驟的半導體裝置之製造裝置，其特徵爲 :前述處理程式在前述乾式蝕刻步驟之前，具備有將在前 述濕式蝕刻步驟中被形成在前述金屬膜上的變質層予以除 去之變質層除去步驟。 [發明效果] 依據本發明，提供當具有金屬膜進行濕式蝕刻的步驟 、及之後該金屬膜進行乾式蝕刻的步驟的情況，可以減少 :在濕式蝕刻步驟被形成在金屬膜上之變質層的殘渣導致 對之後的步驟所造成的不良影響、及對裝置特性所造成的 不良影響，又可以穩定地製造優質的半導體裝置的半導體 裝置之製造方法、半導體裝置之製造裝置、電腦記憶媒體 及記憶有處理程式之記憶媒體。 【實施方式】 以下，參考圖面來說明本發明的實施形態。第1圖爲 擴大表示本實施形態的半導體裝置之製造方法的基板1 00 -11 - 200822208 之剖面構成。第2圖爲表示本實施形態之作爲半導體裝置 之製造裝置之電漿鈾刻裝置的構成。首先，參考第2圖來 說明電漿鈾刻裝置的構成。 電漿蝕刻裝置1係由反應性離子蝕刻（RIE )裝置所 構成，該反應性離子蝕刻（RIE )裝置則是使處理腔室2 內產生處理氣體的電漿，析出電漿中的離子來與該處理腔 室2內所配置的基板1 00產生作用，以進行蝕刻。另外， 該處理腔室2內，並不侷限於進行電漿蝕刻，也可以進行 後述的變質層除去步驟和灰化步驟等。 可氣密地封閉內部之處理腔室2形成爲角筒形狀，在 該處理腔室2內設有被支持在向上下配置之2種絕緣性支 撐構件3a、3b之載置台3。然後，在該載置台3上載置液 晶顯示裝置用的玻璃基板等的基板1 〇〇。載置台3連接著 高頻電源4，從該高頻電源4來對載置台3供應特定頻率 (例如，1 3 ·5 6 MHz )的高頻電力。 處理腔室2的頂棚部設有對向電極5，該對向電極5 爲接地電位。對向電極5具有多數個穿孔5 a，以朝向基板 1 〇〇呈噴淋狀地供應從這些穿孔5a供應到氣體入口 6之處 理氣體的方式構成。氣體入口 6連接著氣體供應管7。進 而，該氣體供應管7經由閥8、質量流量控制器9連接著 處理氣體供應源1 〇。從處理氣體供應源1 〇供應特定的處 理氣體。 處理腔室2的底部連接著排氣管11，該排氣管1 1連 接著排氣裝置12。排氣裝置12具備有渦輪分子泵等的真 -12- 200822208 空泵，以可將處理腔室2內抽真空至特定的減壓雰圍爲止 的方式構成。另外，處理腔室2的側壁部設有閘閥1 3，在 該閘閥13張開的狀態下，從相鄰的承載室（load-lock )( 未圖示），將基板100予以搬入和搬出。 上述構成的電漿蝕刻裝置1係藉由控制部60來統籌 控制該動作。該控制部60設有具備CPU來控制電漿蝕刻 裝置1的各部位之製程控制器6 1、及使用者界面62、及 記憶部63。 使用者界面62係由爲使製程管理者方便管理電漿鈾 刻裝置1而進行指令的輸入操作之鍵盤、或以可視化來顯 示電漿蝕刻裝置1的運作狀況之顯示器等所構成。 記憶部63中儲存著記憶有經由控制製程控制器6 1以 實現電漿鈾刻裝置1所執行的各種處理用的控制程式（軟 體）或處理條件數據之程式。然後，因應於需求，依照來 自使用者界面62的指示等，製程控制器6 1執行從記憶部 6 3所叫出的任意程式，在製程控制器61的控制下，進行 電漿蝕刻裝置1所要進行的處理。另外，控制程式或處理 條件數據等的程式，也能夠使用被儲存在電腦可讀取的電 腦記憶媒體（例如，硬碟、CD、軟碟、半導體記憶體等） 等的狀態的程式、或者由其他的裝置，透過例如專線隨時 傳送經由上線來使用程式。 藉由上述構成的電漿蝕刻裝置1來對基板1 0 0進行電 漿鈾刻等的電漿處理的情況，首先閘閥1 00張開後，基板 100則從承載室（未圖示）辦入處理腔室2內，載置在載 -13- 200822208 置台3上。接著閘閥1 3關閉，藉由排氣裝置1 2，將處理 腔室2內抽真空至特定的真空度爲止。 之後’閥8張開，從處理氣體供應源丨〇所供應的特 定氣體’藉由質量流量控制器9，調整該流量，並通過處 理氣體供應管7、氣體入口 6，導入到處理腔室2內。 然後’處理腔室2內的壓力維持在特定的壓力，並且 特定頻率的高頻電力從高頻電源4施加給載置台3。藉由 此方式’處理氣體解離而在處理腔室2內產生電漿，並且 析出該電漿中的離子，到達被處理基板i 00，進行電漿蝕 刻等的電漿處理。 然後，特定的電漿處理結束，則停止高頻電力的供應 和處理氣體的供應，依照與上述的順序相反的順序，從處 理腔室2內搬出基板1〇〇。 其次，液晶顯示裝置之非晶質矽TFT的製造方法，作 爲本實施形態的半導體裝置之製造方法，參考第1圖來進 行說明。第1圖爲以模式來表示本實施形態中之基板1 00 的剖面構成。如第1 ( a )圖所示，由透明玻璃基板所組成 的基板1 00上，首先形成由金屬膜所組成的閘極1 02，該 金屬膜則是使用由光阻劑所組成的遮罩，進行蝕刻（濕式 蝕刻）來形成爲特定形狀。 其次，除去遮罩1 〇 1之後，如第1 ( b )圖所示，由下 側起依序形成絕緣膜1〇3、a — Si膜（非晶質膜）104、n + a— Si膜105、金屬膜1〇6，在金屬膜106的上面，形成呈 段狀的抗蝕遮罩1 〇7。金屬膜可以使用例如A1或該合金膜 -14- 200822208 、Mo或該合金膜、Mo或該合金/ A1或該合金的層積膜、 Mo或該合金/ A1或該合金/ Mo或該合金的層積膜等。 其次，如第1 ( c )圖所示，將呈段狀形成的抗蝕遮罩 1 07作爲遮罩，經由濕式蝕刻來將金屬膜予以餓刻，之後 進行：將、n + a — Si膜105、a — Si膜104予以乾式蝕刻來 形成島形部分之灰化步驟。上述的濕式蝕刻步驟，會在與 濕式触刻用的藥液相接觸之金屬膜1 0 6的緣部（露出部） ，形成變質層（推測主要是氧化物）1 0 8。 其次，如第1 ( d )圖所示，進行··將呈段狀形成的抗 蝕遮罩1 07灰化到中途之半灰化步驟。 之後，如第1 (e)圖所示，進行除去變質層108之變 質層除去步驟。該變質層除去步驟係使用含有SF6及Cl2 的混合氣體、或是使用含有sf6及〇2的混合氣體，作爲 處理氣體，利用該電漿來進行。使用含有sf6及C12的混 合氣體來作爲處理氣體的情況，Cl2的流量例如爲 100〜150 seem，ch與SF6的流量比例如爲5/1〜15/1， 壓力例如爲6.65〜13.3 Pa，高頻的電力爲0.58〜0.86 W/ cm2程度。另外，使用含有SF6及〇2的混合氣體來作爲處 理氣體的情況，處理條件的一個例子：SF6/ 〇2 = 50// 50 seem，壓力= 2.66 Pa，高頻電力= 〇·58 〜W / cm2。 之後，如第1(d)圖所示，將半灰化之呈段狀形成的抗 飩遮罩1 0 7作爲遮罩，經由乾式鈾刻來將金屬膜1 0 6、η + a — S i膜1 0 5、a — S i膜1 04的一部分予以蝕刻，形成通道 109 ° -15- 200822208 然後，上述步驟之後，進行形成鈍化膜和形成使用第 3抗蝕遮罩的接觸孔之鈾步驟、形成ITO膜和形成使用第 4抗蝕遮罩的像素電極之蝕刻步驟，製造液晶顯示裝置。 如以上所述，本實施形態，因經由變質層除去步驟來 除去濕式鈾刻所產生的金屬膜之變質層1 0 ’所以可以減輕 變質層1 0 8的殘渣導致對之後的步驟所造成的不良影響、 及對裝置特性所造成的不良影響。 相對於此，不施行變質層除去步驟的情況’如第4圖 所示，在濕式蝕刻導致在金屬膜106形成變質層的狀 態下（a )，接著進行半灰化步驟，呈段狀形成的抗鈾遮 罩107則會收縮（shrink)，金屬膜1〇6的一部分因而露 出（b )。然後，在該狀態下進行金屬膜1 〇6的乾式鈾刻 步驟，藉此在露出部分形成突刺形狀，只有外側的變質層 1 〇 8 (殘渣）會呈圍籬狀地殘留著（c )。該圍籬狀的殘渣 如同第4 ( c )圖的上部（上面圖）所示形成爲框狀’故會 有發生源極-汲極間的電短路等的情況。 上述實施形態中，將呈段狀形成的抗蝕遮罩1 07作爲 遮罩，以以下的條件，進行經由濕式蝕刻（鈾刻液=磷酸 +醋酸+硝酸）來將金屬膜1 06予以鈾刻之後的一連串步 驟。 即是使用SF6與Cl2的混合氣體，進行：將n+ a - Si 膜105、a — Si膜104予以乾式蝕刻來形成島形部分之島 形裝蝕刻步驟，再使用02氣體，進行··將呈段狀形成的 抗蝕遮罩1 07灰化到中途之半灰化步驟。之後’以處理氣 -16- 200822208 體 Cl2/SF6=150/10 seem，壓力= 10.64 Pa，局頻電力 = 0.58〜0.86 W/Cm2的條件，進行除去變質層1〇8的變 質層除去步驟。然後，將半灰化之呈段狀形成之抗蝕遮罩 107作爲遮罩，金屬膜106中，Mo膜使用的Cl2及02的 混合氣體來進行蝕刻，A1膜使用BC13及Cl2的混合氣體 來進行蝕刻，再使用Cl2及SF6的混合氣體來將n+ a— Si 膜105、a — Si膜104的一部分予以蝕刻，形成通道1〇9。 該結果，可以將變質層的殘渣所導致之突刺形狀或圍 籬狀的構造物等不會產生之良好狀態的薄膜電晶體予以製 造出來。此外，在使用上述一連串之段狀形成的電晶體的 步驟中，最初的濕式蝕刻以後的步驟係藉由第2圖所示的 電漿蝕刻裝置1來實施。此時，一經將基板1 〇〇收容到腔 室2內之後，依序變更處理氣體等的處理條件，藉由此方 式，不必取出基板1 00就可以進行處理。因而，比中途進 行濕式飩刻的情況還要更良好的效率且可以在短時間內進 行處理。 其次，參考第3圖來說明其他的實施形態。如第3 ( a )圖所示，在由透明玻璃基板所組成的基板1 〇〇，首先形 成由使用由光阻劑所組成的遮罩1 〇 1進行蝕刻（濕式鈾刻 )形成爲特定形狀的金屬膜所組成之閘極1 〇2。 其次，除去遮罩1 〇 1之後，如第3 ( b )圖所示，由下 側起依序形成絕緣膜103、a— Si膜（非晶質膜）104、Π + a— Si膜105、金屬膜106，在金屬膜106，在金屬膜106 的上面形成呈段狀形成抗鈾遮罩1 07。金屬膜可以使用例 -17- 200822208 如A1或該合金膜、Mo或該合金膜、Mo或該合金/A1或 該合金的層積膜、Mo或該合金/ A1或該合金/ Mo或該合 金的層積膜等。 其次，如第3 ( c )圖所示，將呈段狀形成的抗鈾遮罩 107作爲遮罩，藉由濕式鈾刻來將金屬膜1〇6予以触刻。 此步驟是要在經濕式蝕刻過之金屬膜1 〇6的緣部形成變質 層 1 08。 其次，如第3 ( d )圖所示，進行：只將呈段狀形成的 抗蝕遮罩1 07灰化到中途來變更該形狀之半灰化步驟。 之後、與上述過的實施形態同樣的方式，進行除去變 質層1 0 8的變質層除去步驟，然後，將n + a - S i膜1 0 5、a - Si膜1 04予以蝕刻來形成島形部分，再經由乾式鈾刻， 將金屬膜106、n+a— Si膜105、a — Si膜104的一部分予 以鈾刻，形成通道109。此外，也可以在將n + a 一 Si膜 105、a — Si膜104予以乾式蝕刻來形成島形部分時，依照 金屬膜的種類來將通道部分之金屬膜的一部分予以蝕亥[(。 與前述過的實施形態不同處則是本實施形態中換成半 灰化步驟及島形蝕刻步驟，不過半灰化步驟之後進@變、質 層除去步驟，可以獲得與前述過的實施形態同樣@ /效|。 另外，本實施形態中，若是變質層除去步驟使用Ch/ 的話，可以使用這系列的氣體來將n + a — Si膜1〇5、a — si 膜1 (Η予以蝕刻，所以可以持續執行島形蝕刻步驟，又可 以實質上減少步驟數。 -18- 200822208 【圖式簡單說明】 第1圖爲以模式來表示本發明的實施形態之基板的剖 面構成之圖。 第2圖爲表示本發明的實施形態之半導體裝置的製造 裝置的槪略構成之圖。 第3圖爲以模式來表示本發明的其他實施形態之基板 的剖面構成之圖。 第4圖爲以模式來表示習知技術中基板的上面和剖面 的構成之圖。 【主要元件符號說明】 100 :基板 101 :遮罩 102 :閘極 103 :絕緣膜 104 ： a- Si 膜 105 ： n + a — Si 膜 106 :金屬膜 107 :呈段狀形成的抗蝕遮罩 108 :變質層 109 :通道 -19-[Technical Field] The present invention relates to a method of manufacturing a semiconductor device suitable for manufacturing a semiconductor device such as a liquid crystal display device, a device for manufacturing a semiconductor device, a computer memory medium, and a memory processing program. Memory media. [Prior Art] In the past, in the process of manufacturing a semiconductor device, when etching a desired portion, wet etching using a chemical liquid and dry etching using a gas are often used. Dry etching is known, for example, by plasma generation of an etching gas, plasma etching by etching by the action of the plasma, and the like. For example, a process of an amorphous germanium TFT (thin film transistor) of a liquid crystal display device is performed by etching a metal film to form a gate, a source, and a drain, and etching an amorphous germanium film or the like to form an amorphous germanium film or the like. The steps of the island structure, the steps of forming the channels are medium, and wet uranium engraving and dry uranium engraving are suitably used. Further, in most cases, wet etching is mainly used for the etching step of the metal film. Further, a technique in which ashing is performed by a mixed gas of oxygen gas and a gas containing fluorine to remove a ridge layer on the peripheral portion of the semiconductor layer to improve current characteristics between the above-described etching steps is known (for example, reference to transcript) Patent Document 1). Further, the process of the amorphous germanium TFT of the above liquid crystal display device is carried out by moving to an anti-caries mask formed in a segment shape to reduce the number of masks. This masking treatment is performed by changing the shape by ashing the resist mask formed in a segment shape to the middle, and it is used as two types of masks. The 200822208 can reduce the mask forming step once. Further, in accordance with the step of using the above-described resist mask formed in a segment shape, the wet uranium engraving step and the second dry etching step are performed twice, and the second wet etching step is replaced by dry etching. By improving the controllability of the wiring width, the length of the channel, etc.; reducing the use cost of the wet chemical solution, and reducing the number of steps, the productivity and yield are improved. However, the metal film which has been subjected to dry etching once, and then etched by dry etching, is in contact with the etching liquid phase during wet etching of uranium, and thus is formed at the edge of the metal film (exposed portion). The altered layer is not etched during dry etching, and remains as a residue, which adversely affects subsequent steps or adversely affects device characteristics. For example, there may be a situation in which the above-mentioned residue exists between the source and the drain, resulting in an electrical short between the source and the drain. [Patent Document 1] Japanese Patent Laid-Open Publication No. Hei 2 0 0 5 - 7 2 4 3 3 SUMMARY OF THE INVENTION <Problems to be Solved by the Invention> As described above, the conventional technique has a problem of having The step of wet etching the metal mold and the step of dry etching the metal film later, the altered layer formed on the side surface of the metal film exposed to the chemical liquid during wet etching, during dry etching The residue is left in the form of a fence without being etched, which adversely affects the subsequent steps and adversely affects the characteristics of the device. The present invention has been made to solve the above problems, and an object thereof is to provide a step of wet etching a metal film from -6 to 200822208 and a step of dry etching the metal film thereafter, which can be reduced: in wet A method of manufacturing a semiconductor device in which a residue of a deteriorated layer formed on a metal film in an etching process causes adverse effects on subsequent steps and adverse effects on device characteristics, and which can stably manufacture a good semiconductor device , a manufacturing device for a semiconductor device, a computer memory medium, and a memory medium in which a processing program is stored. <Means for Solving the Problem> The method of manufacturing a semiconductor device according to the first aspect of the present invention is characterized in that the metal film formed on the substrate is uranium-etched in the wet etching step And a method of manufacturing a semiconductor device in which the metal film is subjected to dry etching in a dry etching step, characterized in that, before the dry-type etching step, the film is formed on the metal film in the wet etching step. The metamorphic layer removal step to remove the metamorphic layer. The method of manufacturing a semiconductor device according to the first aspect of the invention, wherein the substrate is housed in a processing chamber (chainber) The substrate is carried out in the processing chamber, and the modified layer removing step and the dry etching step are continuously performed. The method of manufacturing a semiconductor device according to claim 3 of the present invention is characterized in that the metal film formed on the substrate is etched in a wet etching step via a resist mask, and then the metal film is further removed. A method for manufacturing a semiconductor device for dry etching in a dry etching process is characterized in that the method includes: a step of ashing a part of the resist mask to change a shape of the resist mask; and The step of removing the altered layer formed by the altered layer formed on the metal film in the wet etching step, and the step of removing the modified uranium mask by changing the shape in the ashing step The method of manufacturing a semiconductor device according to the invention of claim 4, wherein the substrate is housed in a processing chamber, The substrate is not carried out from the processing chamber, and the ashing step and the modified layer removing step are continuously performed. And the dry etching step. A method of manufacturing a semiconductor device according to claim 5, wherein the metal film formed on the substrate is etched in a wet etching step via a resist mask, and then the metal is further removed A method of manufacturing a semiconductor device in which a dry etching step of a film is dry-etched is characterized in that: the first step of dry etching the amorphous germanium film under the metal film via the anti-uranium mask a dry etching step, an ashing step of ashing a part of the resist mask to change a shape of the resist mask, and removing a modified layer formed on the metal film in the wet etching step a modified layer removing step, a second dry etching step of dry etching the metal film by the resist mask having a shape changed in the ashing step, and the resist having a shape changed by the ashing step Mask A third dry hungry step of dry etching the amorphous tantalum film. The semiconductor method according to claim 5, wherein the substrate is housed in a processing chamber, and the substrate is carried out in the processing chamber, and continues The first dry and the ashing step, the modified layer removing step, the dry etching step, and the third dry etching step are performed. The semiconductor method according to claim 7 of the present invention is characterized in that: the method comprises: dry etching of a film which is to be dry uranium engraved after being etched by a resist mask in a wet etching step on a substrate The semiconductor package according to the step of the present invention is characterized in that the step of: ashing the resist portion to change the shape of the uranium-resistant mask; and removing the resist formed on the metal film in the wet etching step a step of removing the altered layer, and a first dry etching step of the underlying metal film that is not dry uranium engraved through the anti-caries mask in the ashing step, and the aforementioned resistance by changing the shape in the front In the etch mask, the metal film is subjected to a second dry etching step and the amorphous ruthenium film is subjected to a dry dry uranium etching step via the resist mask in the ashing step. The semiconductor method according to claim 7, wherein the semiconductor method according to claim 7 is characterized in that a part of the semiconductor method is dry-etched by the first dry etching step. The manufacture of the manufacturing apparatus of the S is not a step of masking the metal film produced by the above-described etching process and the second device, and then changing the shape of the metal layer. The method for producing a semiconductor device according to the ninth aspect of the present invention is the method for producing a semiconductor device according to the ninth aspect of the present invention. The method of manufacturing a semiconductor device according to claim 7 or 8, wherein the substrate is housed in the processing chamber, the substrate is not carried out from the processing chamber, and the ashing step and the altered layer are continuously performed. The removing step, the first dry etching step, the second dry uranium etching step, and the third dry etching step. The method of manufacturing a semiconductor device according to any one of claims 1 to 9, wherein a mixed gas containing SF6 and Cl2 is used. Or the slurry containing the mixed gas of SF6 and 02, and the step of removing the altered layer. The method of manufacturing a semiconductor device according to any one of claims 1 to 1, wherein the metal film is aluminum or the alloy. A film, molybdenum or the alloy film, aluminum or any one of a laminated film of the alloy film and molybdenum or the alloy film. The apparatus for manufacturing a semiconductor device according to claim 12, further comprising: a processing chamber for accommodating the substrate; and a processing gas supply means for supplying the processing gas into the processing chamber; a plasma generating means for treating the substrate by plasma-treating the processing gas supplied from the processing gas supply means, and controlling to perform the method according to any one of claims 1 to 11 in the processing chamber. A control unit of a method of manufacturing a semiconductor device. The computer memory medium according to claim 13 of the present invention is a computer memory medium for storing a control program for performing an operation on a computer, characterized in that the control program controls the manufacture of the semiconductor device. The device is a method of manufacturing a semiconductor device according to any one of claims 1 to 11. The memory medium having the processing program described in claim 14 is used for controlling the execution: the metal film formed on the substrate is etched in the wet etching step, and then the metal film is dried. In the apparatus for manufacturing a semiconductor device which is subjected to a dry etching process, the processing program includes a modified layer which is formed on the metal film in the wet etching step before the dry etching step. Metamorphic layer removal step. [Effect of the Invention] According to the present invention, it is possible to reduce the deterioration layer formed on the metal film in the wet etching step in the case where the metal film is subjected to the wet etching step and the metal film is subjected to the dry etching step. The residue causes a bad influence on the subsequent steps and adverse effects on the characteristics of the device, and a method for manufacturing a semiconductor device capable of stably manufacturing a high-quality semiconductor device, a device for manufacturing the semiconductor device, a computer memory medium, and a memory There is a memory medium for processing programs. [Embodiment] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Fig. 1 is a cross-sectional view showing the substrate 1 00 -11 - 200822208 showing the method of manufacturing the semiconductor device of the present embodiment. Fig. 2 is a view showing the configuration of a plasma uranium engraving apparatus as a manufacturing apparatus of a semiconductor device of the present embodiment. First, the configuration of the plasma uranium engraving apparatus will be described with reference to Fig. 2. The plasma etching apparatus 1 is constituted by a reactive ion etching (RIE) apparatus which generates a plasma of a processing gas in the processing chamber 2 and deposits ions in the plasma. The substrate 100 disposed in the processing chamber 2 acts to etch. Further, in the processing chamber 2, plasma etching is not limited, and a modified layer removing step, an ashing step, and the like which will be described later may be performed. The processing chamber 2, which can hermetically seal the inside, is formed in a rectangular tube shape, and the processing chamber 2 is provided with a mounting table 3 supported by two kinds of insulating supporting members 3a and 3b arranged upward and downward. Then, a substrate 1 such as a glass substrate for a liquid crystal display device is placed on the mounting table 3. The high frequency power supply 4 is connected to the mounting table 3, and high frequency power of a specific frequency (for example, 1 3 · 5 6 MHz) is supplied to the mounting table 3 from the high frequency power supply 4. The ceiling portion of the processing chamber 2 is provided with a counter electrode 5 which is at a ground potential. The counter electrode 5 has a plurality of perforations 5a formed to supply the gas supplied from the perforations 5a to the gas inlets 6 in a shower-like manner toward the substrate 1. The gas inlet 6 is connected to the gas supply pipe 7. Further, the gas supply pipe 7 is connected to the process gas supply source 1 via the valve 8 and the mass flow controller 9. A specific process gas is supplied from the process gas supply source 1 . The bottom of the processing chamber 2 is connected to an exhaust pipe 11 which is connected to the exhaust unit 12. The exhaust unit 12 is provided with a true -12-200822208 air pump such as a turbo molecular pump, and is configured to evacuate the inside of the processing chamber 2 to a specific decompression atmosphere. Further, a gate valve 13 is provided in a side wall portion of the processing chamber 2, and the substrate 100 is carried in and out from an adjacent load-lock (not shown) while the gate valve 13 is opened. The plasma etching apparatus 1 having the above configuration is controlled by the control unit 60 to coordinate the operation. The control unit 60 is provided with a process controller 61 including a CPU for controlling each part of the plasma etching apparatus 1, a user interface 62, and a memory unit 63. The user interface 62 is constituted by a keyboard for inputting an instruction for facilitating management of the plasma uranium apparatus 1 by a process manager, or a display for visually displaying the operation state of the plasma etching apparatus 1. The memory unit 63 stores therein a program for storing control programs (software) or processing condition data for controlling various processes executed by the plasma uranium engraving device 1 via the control process controller 61. Then, in response to an instruction from the user interface 62, the process controller 61 executes an arbitrary program called from the memory unit 63, and under the control of the process controller 61, performs the plasma etching apparatus 1. Processing carried out. Further, a program for controlling a program or processing condition data or the like can also use a program stored in a state of a computer readable medium (for example, a hard disk, a CD, a floppy disk, a semiconductor memory, etc.) or the like. Other devices can be used to transmit programs via the online line at any time through, for example, a dedicated line. In the plasma etching apparatus 1 having the above configuration, the plasma processing such as plasma uranium engraving is performed on the substrate 100. First, after the gate valve 100 is opened, the substrate 100 is loaded from the carrying chamber (not shown). The processing chamber 2 is placed on the stage 3 of the carrier-13-200822208. Then, the gate valve 13 is closed, and the inside of the processing chamber 2 is evacuated to a specific degree of vacuum by the exhaust unit 12. Then, the valve 8 is opened, and the specific gas supplied from the processing gas supply source ' is adjusted by the mass flow controller 9, and is introduced into the processing chamber 2 through the processing gas supply pipe 7, the gas inlet 6, Inside. Then, the pressure in the processing chamber 2 is maintained at a specific pressure, and high-frequency power of a specific frequency is applied from the high-frequency power source 4 to the stage 3. In this manner, the treatment gas is dissociated to generate plasma in the processing chamber 2, and ions in the plasma are deposited, and the substrate to be processed i 00 is subjected to plasma treatment such as plasma etching. Then, when the specific plasma processing is completed, the supply of the high-frequency power and the supply of the processing gas are stopped, and the substrate 1 is carried out from the processing chamber 2 in the reverse order to the above-described order. Next, a method of manufacturing an amorphous germanium TFT of a liquid crystal display device will be described with reference to Fig. 1 as a method of manufacturing the semiconductor device of the present embodiment. Fig. 1 is a cross-sectional view showing the structure of the substrate 100 in the present embodiment in a pattern. As shown in the first (a) diagram, on the substrate 100 composed of a transparent glass substrate, a gate electrode 102 composed of a metal film is first formed, and the metal film is a mask composed of a photoresist. Etching (wet etching) is performed to form a specific shape. Next, after the mask 1 〇 1 is removed, as shown in the first (b), the insulating film 1 〇 3, a — Si film (amorphous film) 104, n + a — Si are sequentially formed from the lower side. The film 105 and the metal film 1〇6 are formed in a segmented resist mask 1〇7 on the upper surface of the metal film 106. The metal film may use, for example, A1 or the alloy film-14-200822208, Mo or the alloy film, Mo or the alloy / A1 or a laminated film of the alloy, Mo or the alloy / A1 or the alloy / Mo or the alloy Laminated film, etc. Next, as shown in Fig. 1(c), the resist mask 107 formed in a segment shape is used as a mask, and the metal film is hungry by wet etching, and then: n + a - Si The film 105, a - the Si film 104 is dry etched to form an island portion ashing step. In the above-described wet etching step, a modified layer (presumably mainly an oxide) 1 0 8 is formed at the edge (exposed portion) of the metal film 106 which is in contact with the liquid phase for wet etching. Next, as shown in Fig. 1 (d), the half-ashing step of ashing the anti-corrosion mask 07 formed in a segment shape to the middle is performed. Thereafter, as shown in Fig. 1(e), a step of removing the altered layer of the altered layer 108 is performed. This altered layer removal step is carried out using a mixed gas containing SF6 and Cl2 or a mixed gas containing sf6 and cesium 2 as a processing gas. When a mixed gas containing sf6 and C12 is used as the processing gas, the flow rate of Cl2 is, for example, 100 to 150 seem, and the flow ratio of ch to SF6 is, for example, 5/1 to 15/1, and the pressure is, for example, 6.65 to 13.3 Pa, which is high. The frequency of the power is about 0.58~0.86 W/cm2. Further, in the case of using a mixed gas containing SF6 and 〇2 as a processing gas, an example of processing conditions is SF6 / 〇2 = 50 / / 50 seem, pressure = 2.66 Pa, high frequency power = 〇 · 58 〜 W / Cm2. Thereafter, as shown in Fig. 1(d), the semi-ashed anti-small mask 101 formed in a segment shape is used as a mask, and the metal film 1 0 6 , η + a - S is dried by dry uranium engraving. A portion of the i film 1 0 5, a — S i film 104 is etched to form a channel 109 ° -15- 200822208. Then, after the above steps, a uranium is formed which forms a passivation film and forms a contact hole using the third resist mask. In the steps of forming an ITO film and forming an electrode electrode using the fourth resist mask, a liquid crystal display device was produced. As described above, in the present embodiment, since the altered layer 10' of the metal film generated by the wet uranium engraving is removed by the modified layer removing step, the residue of the altered layer 108 can be reduced to cause the subsequent steps. Adverse effects, and adverse effects on device characteristics. On the other hand, in the case where the modified layer removing step is not performed, as shown in FIG. 4, in the state in which the modified layer is formed in the metal film 106 by wet etching (a), the half-ashing step is followed to form a segment. The anti-uranium mask 107 will shrink, and a portion of the metal film 1〇6 is thus exposed (b). Then, in this state, the dry uranium engraving step of the metal film 1 〇 6 is performed, whereby a spur shape is formed in the exposed portion, and only the outer metamorphic layer 1 〇 8 (residue) remains in a fence shape (c). The fence-like residue is formed into a frame shape as shown in the upper part (above) of Fig. 4(c), so that an electric short circuit between the source and the drain may occur. In the above embodiment, the resist mask 107 formed in a segment shape is used as a mask, and the metal film 106 is subjected to uranium by wet etching (uranium engraving = phosphoric acid + acetic acid + nitric acid) under the following conditions. A series of steps after engraving. That is, using a mixed gas of SF6 and Cl2, an island-shaped etching step of forming an island-shaped portion by dry etching the n+ a-Si film 105 and the a-Si film 104, and using 02 gas, The segment-formed resist mask 107 is ashed to the mid-half ashing step. Thereafter, the removal step of removing the altered layer 1〇8 was carried out under the conditions of a treatment gas of -16 - 200822208, Cl2 / SF6 = 150/10 seem, pressure = 10.64 Pa, and local frequency power = 0.58 to 0.86 W/cm 2 . Then, the semi-ashing resist mask 107 formed in a segment shape is used as a mask, and the metal film 106 is etched by a mixed gas of Cl2 and 02 used for the Mo film, and the A1 film is mixed with BC13 and Cl2. Etching is performed, and a part of the n+ a-Si film 105 and the a-Si film 104 is etched using a mixed gas of Cl2 and SF6 to form a channel 1〇9. As a result, a thin film transistor which does not have a good state such as a spur shape or a fence-like structure due to the residue of the altered layer can be produced. Further, in the step of using the above-described series of segments formed of transistors, the steps after the first wet etching are carried out by the plasma etching apparatus 1 shown in Fig. 2. At this time, after the substrate 1 is accommodated in the chamber 2, the processing conditions of the processing gas and the like are sequentially changed, whereby the processing can be performed without taking out the substrate 100. Therefore, it is more efficient than the case of wet engraving in the middle and can be processed in a short time. Next, other embodiments will be described with reference to Fig. 3. As shown in Fig. 3(a), the substrate 1 made of a transparent glass substrate is first formed to be formed by etching (wet uranium engraving) using a mask 1 〇1 composed of a photoresist. The gate of the shape of the metal film is 1 〇2. Next, after the mask 1 〇 1 is removed, as shown in the third (b), the insulating film 103, the a-Si film (amorphous film) 104, and the Π + a-Si film 105 are sequentially formed from the lower side. The metal film 106 is formed on the metal film 106 to form an anti-uranium mask 1 07 in a segment shape. As the metal film, for example, -17-200822208 such as A1 or the alloy film, Mo or the alloy film, Mo or the alloy/A1 or a laminated film of the alloy, Mo or the alloy / A1 or the alloy / Mo or the alloy may be used. Laminated film, etc. Next, as shown in Fig. 3(c), the anti-uranium mask 107 formed in a segment shape is used as a mask, and the metal film 1〇6 is inscribed by wet uranium engraving. This step is to form a metamorphic layer 108 on the edge of the wet-etched metal film 1 〇6. Next, as shown in Fig. 3(d), the half-ashing step of changing the shape is performed by ashing only the resist mask 107 formed in a segment shape to the middle. Thereafter, in the same manner as in the above-described embodiment, the step of removing the altered layer of the altered layer 108 is performed, and then the n + a - S i film 1 0 5 and the a - Si film 104 are etched to form an island. The shaped portion is further etched into a portion of the metal film 106, the n+ a-Si film 105, and the a-Si film 104 by dry uranium engraving to form a channel 109. Further, when the n + a - Si film 105 and the a - Si film 104 are dry-etched to form an island-shaped portion, a part of the metal film of the channel portion may be etched according to the type of the metal film [(. The difference in the above-described embodiment is that the half-ashing step and the island-shaped etching step are replaced in the present embodiment. However, after the half-ashing step, the step of changing and the layer removing step can be obtained in the same manner as the above-described embodiment. In the present embodiment, if Ch/ is used for the modified layer removal step, the n + a - Si film 1 〇 5 and the a - sia film 1 can be etched using this series of gases. The island etching step can be continuously performed, and the number of steps can be substantially reduced. -18- 200822208 BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view showing a cross-sectional structure of a substrate according to an embodiment of the present invention in a pattern. 3 is a schematic view showing a schematic configuration of a substrate for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 3 is a view showing a cross-sectional configuration of a substrate according to another embodiment of the present invention. A diagram showing the configuration of the upper surface and the cross section of the substrate in the prior art. [Description of main components] 100: Substrate 101: Mask 102: Gate 103: Insulating film 104: a-Si film 105: n + a - Si film 106: Metal film 107: a resist mask 108 formed in a segment shape: a metamorphic layer 109: channel-19-