TW200822030A

TW200822030A - New integrated DC/DC converter applied to LCD

Info

Publication number: TW200822030A
Application number: TW95142147A
Authority: TW
Inventors: Shyh-Shin Liang; Yung-Yu Tsai
Original assignee: Chi Mei Optoelectronics Corp
Priority date: 2006-11-14
Filing date: 2006-11-14
Publication date: 2008-05-16
Also published as: TWI348673B

Abstract

The invention discloses an integrated DC/DC converter. In addition to provide working voltages of the source drivers of a LCD, the integrated DC/DC converter combines a digital control interface, for generating a common voltage output, and what regulars the Gamma voltage. The power-adapting element is used to receive a digital signal from a timing controller of the LCD. A DAC of the integrated DC/DC converter transforms the digital signal into a common voltage and outputs it as an electric field reference level of the LCD. The timing controller reads a predetermined data in a memory in advance and the integrated DC/DC converter generates the predetermined value of the common voltage. After the common voltage is amended, a new predetermined data was stored back to the memory. The gray levels of the LCD are based on the Gamma voltage. The integrated DC/DC converter includes a LDO that adjusts a reference level of the Gamma voltage via a voltage-feedback. The LDO provides the source drivers stable terminal Gamma voltage appropriately.

Description

200822030200822030

二理綱弧·丄W3094PA 九、發明說明：【發明所屬之技術領域】本發明是有關於一種應用於液晶顯示器之新整合型直流轉換器，且特別是有關於一種結合了數位介面方式简整共同電壓及具有伽瑪電壓源穩壓電路之應用於液晶顯^ 示器之新整合型直流轉換器。【先前技術】TECHNICAL FIELD The present invention relates to a new integrated DC converter applied to a liquid crystal display, and in particular to a simplified digital interface method. A common integrated DC converter for liquid crystal displays with common voltage and gamma voltage source voltage regulator circuit. [Prior Art]

」液晶顯示器，特別是薄膜電晶體液晶顯示器（TFT LCD)，發展至今已經是非常成熟的產品，但為了追求高晝值、高品質同時能節省成本，所有的製造廠商仍舊致力於不斷地推出新的設計及生產方式。其中，共同電壓VC0M 及伽瑪電壓VGAM (Gamma Voltage)的設計方式，未來也會成為重要的研究課題。應用於液晶顯示器之直流轉換器的演進，從最早之單一組升壓輸出，並搭配外部的電荷PumP)電路以產生電壓VG0N及電壓VG0FF，到現在結合升降壓多組電源輸出，且同時包含閘極脈波（§ate pulse)調變之電源轉換元件。由於液晶分子必須以交流的方式來驅動’使得液晶電容内所儲存之電荷電壓沒有直流成份。若是液晶電容内所儲存之電荷電壓具有直流成份時，在影像上會造成殘影 (Image Sticking)與晝面閃爍（Flicker)，更嚴重者會造成液晶分子的電化學作用而產生解離，形成永久性的破 6 200822030Liquid crystal displays, especially thin film transistor liquid crystal displays (TFT LCDs), have been developed to date, but in order to pursue high value, high quality and cost savings, all manufacturers are still committed to continuously introducing new ones. Design and production methods. Among them, the design method of common voltage VC0M and gamma voltage VGAM (Gamma Voltage) will become an important research topic in the future. The evolution of the DC converter applied to the liquid crystal display, from the earliest single group boost output, and with the external charge PumP) circuit to generate the voltage VG0N and the voltage VG0FF, and now combined with the buck-boost multiple sets of power output, and at the same time contain the gate脉ate pulse modulation power conversion component. Since the liquid crystal molecules must be driven in an alternating manner, the charge voltage stored in the liquid crystal capacitor has no direct current component. If the charge voltage stored in the liquid crystal capacitor has a DC component, it will cause image sticking and flickering on the image. In the more serious case, the liquid crystal molecules will be electrochemically dissociated to form a permanent. Sexual break 6 200822030

三達編號：TW3094PA 壞0 共同電壓卿係域晶—ϋ之電場之參考準位，於理想的况中’ JE、負極性電壓驅動時應該使液晶顯示器穿透=相同的亮度，但是由於饋通（feed—浙⑽gh)的關係，使得原本儲存於液晶晝素電容内之電壓產生位準漂移，導致液晶正、負極性電壓失去平衡，因此必須調整共同電壓VC0M，使得液晶顯示器可以維持最佳效能。目前最為普遍的共同電壓VC0M設計方式是採用旋鈕式分壓電阻 (Potenti⑽eter)，請參照第1圖，其繪示乃傳統旋鈕式分壓電阻電路之電路圖。電阻H〜r3係形成一分壓電路，其中電阻r2係為一旋鈕式分壓電阻。共同電壓輸出之别會先經過由放大器1〇2所組成之射極隨耦器（f〇ii〇w emi tter) ’以增加共同電壓vc〇M之輸出推力。上述之旋鈕式分壓電阻電路的優點為簡單實用、價格超便宜（約新台幣1元），然而其精準度差，且必須採用人工調整。液晶顯示器製造過程中，會藉由特殊的影像使晝面閃爍，作業員再根據自己所見閃爍的程度，調整分壓電阻之旋紐，以改變共同電壓VC0M之值使閃爍程度降低至最低。然而，每個作業員對閃爍程度之感觀有異，故難以控制共同電壓VC0M之精雄度，所以調整後之共同電壓VC0M 未必是最佳值。此外，旋鈕式分壓電阻電路一般都是設計在液晶顯示器之面板背部，或是侧邊。一旦生產大尺寸液晶面板，則作業員要同時調整共同電壓VC0M及觀看閃爍程度時，就會產生調整;f便利性的問題。 7 200822030Sanda number: TW3094PA Bad 0 Common voltage Qing system crystal - the reference level of the electric field of the ,, in the ideal case 'JE, the negative voltage should drive the liquid crystal display to penetrate = the same brightness, but because of the feedthrough (Feed-Zhejiang (10) gh), the voltage stored in the liquid crystal capacitors is leveled, causing the positive and negative voltages of the liquid crystal to be out of balance. Therefore, the common voltage VC0M must be adjusted so that the liquid crystal display can maintain the best performance. . At present, the most common common voltage VC0M design method is a knob type voltage dividing resistor (Potenti (10) eter), please refer to Fig. 1, which is a circuit diagram of a conventional knob type voltage dividing resistor circuit. The resistors H to r3 form a voltage dividing circuit, wherein the resistor r2 is a knob type voltage dividing resistor. The common voltage output first passes through the emitter follower (f〇ii〇w emi tter) composed of the amplifier 1〇2 to increase the output thrust of the common voltage vc〇M. The above-mentioned knob type voltage dividing resistor circuit has the advantages of being simple and practical, and the price is extremely cheap (about NT$1), but its accuracy is poor and must be manually adjusted. During the manufacturing process of the liquid crystal display, the surface is flickered by a special image, and the operator adjusts the knob of the piezo-resistance according to the degree of flicker that he sees, so as to change the value of the common voltage VC0M to minimize the flicker. However, each operator has a different perception of the degree of flicker, so it is difficult to control the precision of the common voltage VC0M, so the adjusted common voltage VC0M is not necessarily the optimum value. In addition, the knob type voltage dividing resistor circuit is generally designed on the back of the panel of the liquid crystal display or on the side. Once a large-size liquid crystal panel is produced, the operator has to adjust the common voltage VC0M and the degree of flickering at the same time, which causes adjustment; f convenience. 7 200822030

二達繼號：iW3094PA 請參照第2圖，其緣示乃傳統採用數位調整元件以產生共同電壓VC0M的電路之之電路圖。第2圖中，電阻r4〜r5 組成一分壓電路，數位式電壓計數器201係用以產生共同包壓VC〇M’由輸出端0UT輸出，並經由放大器202所組成之射極⑨輸出至液晶顯示器内之多個源極驅動器。其原理係為藉由控制訊號Sc以控制數位式電壓計數器2〇1 内口及取（sink)電波之能力，進而改變電阻^^上之電壓之升降，因此可以利用數位調整的方式調整共同電壓之上升或下降。此外，電阻Rset可決賴輸出之共同電壓VC0M之最小值。由圖可以列出下列關係式：公式（1) 公式（2) V0UT(l/r4+ l/r5) = VADD/r4- lout Π = I〇ut+ 12 當電流lout改變時，使得電流12產生變化，進而改變在電阻r5上之跨壓之壓降。此外，於數位式電壓計數器2〇ι 内建有電子抹除式唯讀記憶體（EEPR〇M)(未繪示於圖），可紀錄凋整後之共同電壓。然而，上述之電路與傳統旋鈕式分壓電阻電路相比，雖然可以得到較精確之共同電壓 VC0M，但其所採用之數位式電壓計數器2〇1價格並不便宜’同時因應液晶顯示器不斷跌落的價格，此種設計方式未必符合成本上的考量。此外，液晶顯示器中之多個源極驅動器亦需要伽瑪電 >£ VGAM輸入’作為伽瑪曲線（Gamma curve)的準位。伽瑪曲線是指不同灰階與亮度的關係。把0到255灰階當x軸，亮度當y軸所得到之曲線即為伽瑪曲線。伽瑪曲線會直槔 8 200822030Erda: iW3094PA Please refer to Figure 2, which is a circuit diagram of a circuit that uses a digital adjustment component to generate a common voltage VC0M. In Fig. 2, the resistors r4 to r5 form a voltage dividing circuit, and the digital voltage counter 201 is used to generate a common voltage divider VC〇M' which is output from the output terminal OUT and output to the emitter 9 formed by the amplifier 202 to Multiple source drivers in a liquid crystal display. The principle is to control the signal voltage Sc to control the internal voltage of the digital voltage counter 2〇1 and to sink the electric wave, thereby changing the voltage rise and fall on the resistance ^^, so the common voltage can be adjusted by digital adjustment. Rise or fall. In addition, the resistance Rset can depend on the minimum value of the common voltage VC0M of the output. The following relationship can be listed by the figure: Equation (1) Formula (2) V0UT(l/r4+ l/r5) = VADD/r4- lout Π = I〇ut+ 12 When the current lout changes, the current 12 changes. In turn, the voltage drop across the voltage across resistor r5 is varied. In addition, an electronic erasing read-only memory (EEPR〇M) (not shown) is built into the digital voltage counter 2〇ι to record the common voltage after the fading. However, compared with the conventional knob type voltage dividing resistor circuit, the above-mentioned circuit can obtain a more accurate common voltage VC0M, but the digital voltage counter 2〇1 used by the circuit is not cheaper, and the liquid crystal display is continuously dropped. Price, this design approach may not be in line with cost considerations. In addition, multiple source drivers in a liquid crystal display also require gamma > £ VGAM input' as the level of the gamma curve. The gamma curve refers to the relationship between different gray levels and brightness. The 0 to 255 gray scale is the x-axis, and the curve obtained by the luminance as the y-axis is the gamma curve. The gamma curve will go straight 8 200822030

一®«m.rW3094PA 影，到液晶顯不器晝面上之漸層效果，因此直流轉換器必須提供-組相當穩定之伽瑪電壓。請參照第3圖，其繪示乃傳統伽瑪電壓源穩壓電路之電路圖。伽瑪電壓源穩壓電，卯1中，並难P%壓态（Shunt 仂r)D係為主要的穩A ®«m.rW3094PA shadow, the gradual effect on the surface of the liquid crystal display, so the DC converter must provide a fairly stable gamma voltage. Please refer to Figure 3, which shows the circuit diagram of the traditional gamma voltage source voltage regulator circuit. Gamma voltage source voltage regulator, 卯1, and difficult P% pressure state (Shunt 仂r) D system is the main stability

Ctg件’電阻r7〜r8決定了並聯穩壓器D之輸出電壓。電阻r6貫質上係作用為一限流電阻，若是電阻μ之值設計太低，會使得並聯穩壓器D通過太多電流，造成元件過熱 =當機甚至是燒毀。若是電阻r6之值設計太高，則無法麵1供源極驅動器足夠的伽瑪電壓。【發明内容】一有鑑於此，本發明的目的就是在提供一種應用於液晶顯不為之新整合型直流轉換器，除了提供液晶顯示器的源極驅動器之卫作電壓外，還結合了數位介面控制方式產生共同電壓VC0M輸出及伽瑪電壓（Ga_a v〇ltage)的穩壓設 5十方式。此電源轉換元件可接收液晶顯示器的時序控制器輪出的數位訊號’經由整合型直流轉換器内部的數位類比 $換器產生共同電壓VC0M輸出，作為液晶顯示器之電場參考準位。時序控制器會先讀取記憶體的預設資料，首先產生共同電堡VC0M的預設值，一旦共同電壓vc〇m經過修正後，新的電壓設定值也回存於記憶體内。伽瑪電堡是液晶顯示器灰階（gray level)的基準。此整合型直流轉換器内部包含一組低壓降穩壓器（LD0)，經 9 200822030 ^The Ctg device 'resistors r7 to r8 determine the output voltage of the shunt regulator D. The resistor r6 acts as a current limiting resistor. If the value of the resistor μ is too low, it will cause the shunt regulator D to pass too much current, causing the component to overheat = even crashing. If the value of resistor r6 is too high, it is not possible to provide sufficient gamma voltage for the source driver. SUMMARY OF THE INVENTION In view of the above, the object of the present invention is to provide a new integrated DC converter for liquid crystal display, which not only provides the voltage of the source driver of the liquid crystal display, but also combines the digital interface. The control method generates a voltage regulation setting of a common voltage VC0M output and a gamma voltage (Ga_a v〇ltage). The power conversion component can receive the digital signal rotated by the timing controller of the liquid crystal display. The common voltage VC0M output is generated by the digital analog converter inside the integrated DC converter as the electric field reference level of the liquid crystal display. The timing controller first reads the preset data of the memory, firstly generates the preset value of the common electric castle VC0M. Once the common voltage vc〇m has been corrected, the new voltage setting value is also stored in the memory. Gamma is the benchmark for the gray level of liquid crystal displays. This integrated DC converter contains a set of low-dropout regulators (LD0) internally, via 9 200822030 ^

二連編职I · iW3094PA 由電壓迴授輕伽瑪電壓源的參考準位，適時提供源極驅動器穩定的伽瑪端點電壓。根據本發明的目的，提出一種整合型直流轉換器應用於液晶顯不器，液晶顯示器包括時序控制器、吃憶體及多個源極驅動器。整合型直流轉換器包括脈衝寬度^ 控制電路、放大器、數位類比轉換器以及伽瑪高壓低壓降，器=寬度調變控制電路係用以產生多個源極驅動 ::二Si放大器形成射極隨耦器。數位類比轉換器記憶體，受時序控制器之控制並依據體所儲存之數位預設，以輸出共同電壓至放大盗。伽瑪高壓健降穩壓轉接至電壓。其中，萼人刑古法絲& w 丑称出弟兩〇直",L轉換器耦接至一分壓回路，依據弟-祕以輸出伽瑪電壓至此些源極驅動器。庠狄：5本毛明的目的，另提出-種液晶顯示器，包括時 V : 、記憶體、多個源極軸器以及整合型直流轉換 5§ : 口直机轉換器包括脈衝寬度調變控制電路、放大儲^位㈣轉換^以及伽瑪高壓低壓降穩壓器。記憶體個el:位預：電壓。脈衝寬度調變控制電路係用以產生多類/比^動S之卫作電壓。放大11形成射極隨搞器。數位押、器耦接至時序控制器及記憶體，受時序控制器之依據記憶體所儲存之數位預設電壓，以輸出共同電於φ #大器。伽瑪高壓低壓降穩壓器耦接至工作電壓，且 ^第-電壓。其中，整合型直流轉換器輕接至一分壓回依據第-電麈以輸出伽瑪電壓至此些源極驅動器。 200822030…Erlian I. iW3094PA uses the reference level of the voltage feedback light gamma voltage source to provide the stable gamma endpoint voltage of the source driver. In accordance with the purpose of the present invention, an integrated DC converter is proposed for use in a liquid crystal display including a timing controller, a memory device, and a plurality of source drivers. The integrated DC converter includes a pulse width ^ control circuit, an amplifier, a digital analog converter, and a gamma high voltage drop, and the width modulation control circuit is used to generate multiple source drivers: the two Si amplifiers form an emitter Coupler. The digital analog converter memory is controlled by the timing controller and preset according to the digital position stored by the body to output a common voltage to amplify the thief. The gamma high voltage step-down regulator is switched to voltage. Among them, the 萼人古法丝& w ugly called the two brothers straight, "L converter is coupled to a voltage divider circuit, according to the brother - secret to output gamma voltage to these source drivers.庠Di: 5 Maoming's purpose, another proposed liquid crystal display, including V:, memory, multiple source shafts and integrated DC conversion 5§: Straight machine converter including pulse width modulation control Circuit, amplified memory (four) conversion ^ and gamma high voltage low dropout regulator. Memory El: Bit Pre: Voltage. The pulse width modulation control circuit is used to generate a multi-class/specific S voltage. Zoom in 11 to form an emitter follower. The digitizer is coupled to the timing controller and the memory, and is subjected to a digital preset voltage stored by the timing controller according to the memory, so that the output is common to the φ# large device. The gamma high voltage low dropout regulator is coupled to the operating voltage and ^ volt-voltage. Wherein, the integrated DC converter is lightly connected to a voltage-dependent voltage to output the gamma voltage to the source drivers. 200822030...

一* J.W3094PA 為讓本發明之上述目的、特徵、和優點能更明顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說明如下：【實施方式】本發明係提供一種應用於液晶顯示器之新整合型直流轉換器，搭配時序控制器之數位訊號與轉合型直流轉換器内部之數位類比轉換器，產生共同電壓VC0M輸出，具有精準及快速調整的優點。整合型直流轉換器内建之伽瑪高壓低壓降穩壓器可以提供源極驅動器穩定的伽瑪參考電壓，具有節省電路元件的優點。請參照第4圖，其繪示乃依照本發明較佳實施例之具有整合型直流轉換器之液晶顯示器之部份示意圖。液晶顯示器400，例如為一薄膜電晶體液晶顯示器（TFT LCD)，包括時序控制器402、記憶體404、整合型直流轉換器406 以及多個源極驅動器4121〜412η。整合型直流轉換器406 係包括脈衝寬度調變控制電路（PWM IC)408、伽瑪高壓低壓降穩壓器（Gamma HVLDO)410、數位類比轉換器（DAC)412 以及放大器414。記憶體404實質上係為一電子抹除式唯讀記憶體（EEPROM)。脈衝寬度調變控制電路408係經由一整流電路，包括電容C、電感L及整流二極體，用以產生源極驅動器 4121〜412η之工作電壓。時序控制器402除了負責源極驅動器4121〜412η及閘極驅動器（未繪示於圖）之訊號控制 11 200822030…The above-mentioned objects, features, and advantages of the present invention will become more apparent from the following detailed description. The utility model provides a new integrated DC converter applied to a liquid crystal display, which is matched with a digital signal converter of a digital signal of a timing controller and a DC converter of a switching type to generate a common voltage VC0M output, which has the advantages of precise and rapid adjustment. The built-in gamma high-voltage low-dropout regulator of the integrated DC converter provides a stable gamma reference voltage for the source driver, saving board components. Referring to Figure 4, there is shown a partial schematic view of a liquid crystal display having an integrated DC converter in accordance with a preferred embodiment of the present invention. The liquid crystal display 400 is, for example, a thin film transistor liquid crystal display (TFT LCD), and includes a timing controller 402, a memory 404, an integrated DC converter 406, and a plurality of source drivers 4121 to 412n. The integrated DC converter 406 includes a pulse width modulation control circuit (PWM IC) 408, a gamma high voltage drop voltage regulator (Gamma HVLDO) 410, a digital analog converter (DAC) 412, and an amplifier 414. Memory 404 is essentially an electronic erasable read only memory (EEPROM). The pulse width modulation control circuit 408 includes a capacitor C, an inductor L and a rectifying diode via a rectifying circuit for generating operating voltages of the source drivers 4121 to 412n. The timing controller 402 is responsible for the signal control 11 200822030 of the source drivers 4121 to 412 η and the gate drivers (not shown).

一«W3//L * xWj094PA 外，還具有共同電壓VC0M之數位控制介面。記憶體404 利用外部燒錄的方式，儲存數位預設電壓，亦即為共同電壓VC0M之預設準位。當系統運作時，時序控制器402透過數位資料傳輸之方式先讀取記憶體404所儲存之數位預設電壓，並將數位預設電壓傳遞給數位類比轉換器412，經由放大器414所組成之射極隨耦器，輸出共同電壓VC0M 以作為液晶顯示器400之電場之參考準位。數位類比轉換器412接收一高位準電壓VH及一低位準電壓VL。高位準電壓VH及一低位準電壓VL係由一分壓電路設定，分壓電路包括電阻R1〜電阻R3。電阻R1之第一端耦接至一地電壓，電阻R2之第一端耦接至電阻R1之第二端，電阻R3之第一端耦接至電阻R2之第二端，電阻 R3之第二端耦接至工作電壓VADD。電阻R1〜R3使得電阻 R2之第一端具有低位準電壓VL，且使得電阻R3之第一端具有高位準電壓VH。因此，此分壓電路可以限制共同電壓VC0M之調整範圍，亦即共同電壓VC0M之電壓位準係小於高位準電壓VH 且大於低位準電壓VL。若假設數位類比轉換器412係為η 位元，η為正整數，則時序控制器402可以控制數位類比轉換器412以每個位階電壓差Vstep調整共同電壓V⑶Μ，位階電壓差Vstep如下列之公式（3)所示，係為高位準電壓VH及低位準電壓VL之差除以2n。In addition to a «W3//L* xWj094PA, there is also a digital control interface with a common voltage VC0M. The memory 404 stores the digital preset voltage by means of external programming, that is, the preset level of the common voltage VC0M. When the system is in operation, the timing controller 402 reads the digital preset voltage stored in the memory 404 by digital data transmission, and transmits the digital preset voltage to the digital analog converter 412, and is formed by the amplifier 414. The pole follower outputs a common voltage VC0M as a reference level of the electric field of the liquid crystal display 400. The digital analog converter 412 receives a high level voltage VH and a low level voltage VL. The high level voltage VH and the low level voltage VL are set by a voltage dividing circuit, and the voltage dividing circuit includes a resistor R1 to a resistor R3. The first end of the resistor R1 is coupled to a ground voltage, the first end of the resistor R2 is coupled to the second end of the resistor R1, the first end of the resistor R3 is coupled to the second end of the resistor R2, and the second end of the resistor R3 The terminal is coupled to the operating voltage VADD. The resistors R1 to R3 have the first end of the resistor R2 having the low level voltage VL and the first end of the resistor R3 having the high level voltage VH. Therefore, the voltage dividing circuit can limit the adjustment range of the common voltage VC0M, that is, the voltage level of the common voltage VC0M is smaller than the high level voltage VH and greater than the low level voltage VL. If the digital analog converter 412 is assumed to be an n-bit and η is a positive integer, the timing controller 402 can control the digital-to-digital converter 412 to adjust the common voltage V(3) 以 with each step voltage difference Vstep. The step voltage difference Vstep is as follows. (3) shows the difference between the high level voltage VH and the low level voltage VL divided by 2n.

Ystep=(VH~VL)/ 2n 公式（3) 請參照第5圖，其繪示乃依照本發明較佳實施例之時 12Ystep=(VH~VL)/ 2n Formula (3) Please refer to FIG. 5, which is illustrated in accordance with a preferred embodiment of the present invention.

fW3094PA 200822030 序控制器402之示意圖。時序控制器4〇2包括上行/下行 a十數器4 0 21及數位介面4 0 2 2。上行/下行計數器$ 〇 21係用以接收控制訊號Control，據以決定以m個位階電壓差 Vstep調整該共同電壓VC0M，m為小於2n之正介面體係_至上行/下行計數器4G2i及數位類比轉換器412，使得數位類比轉換器412心個位階電壓差 Vstep調整共同電壓vc〇M。政取大優點是省去共同電壓V⑽的設計電路’所以不爲要分壓雷u日數器，而依舊可以提0^不需要額外的數位式電壓計合型直流轉換器_之2=及低位準電壓制採用整改變共同電壓VC0M之可阻㈣3來歧，故可任意以準確的贼㈣當叫同雙侧值。齡類轉= 位·其與時序控制器4〇2間之對應關係位階 ~ j·.·· ·. ----— 由時序控制i 0 00000000 1 ---- 00000001 2 ^ 00000010 3 . 00000011 4 --—^ 00000100 入數位類比轉換器輸出fW3094PA 200822030 Schematic diagram of the sequence controller 402. The timing controller 4〇2 includes an up/down a ten-digit 4 0 21 and a digital interface 4 0 2 2 . The up/down counter $ 〇 21 is used to receive the control signal Control, and accordingly, the common voltage VC0M is adjusted by m steps voltage difference Vstep, m is a positive interface system less than 2n _ to the up/down counter 4G2i and the digital analog conversion The 412 is such that the digital analog converter 412 adjusts the common voltage vc 〇 M by a step voltage difference Vstep. The advantage of political acquisition is that the design circuit of the common voltage V(10) is omitted. Therefore, it is not necessary to divide the voltage of the U-day, but it can still be raised. No additional digital volt-amplifier DC converter is needed. The low-level quasi-voltage system adopts the whole change of the common voltage VC0M, which can be dissipated (four) 3, so that the exact thief (four) can be called the same double-sided value. Age class = bit · its corresponding relationship with the timing controller 4〇2 ~ j·.···. ----- controlled by timing i 0 00000000 1 ---- 00000001 2 ^ 00000010 3 . 00000011 4 ---^ 00000100 into the digital analog converter output

VoVo

Vo+lx(VH-VLV128 Vo+2x(VH-VL)/128Vo+lx(VH-VLV128 Vo+2x(VH-VL)/128

Vo+3x(VH-VL)/128Vo+3x(VH-VL)/128

Vo + 4x(VH~VL)/128 200822030, .Λ£ΛΥΙ«3{/Ιι * 丄 \ 125 11111101 ^〇+125x(VH-VL)/128 126 11111110 Vo+126x(VH-VL)/128 127 11111111 Vo+127x(VH-VL)/128 表 1 如果記憶體404初始設定之數位預設電壓不符合實際需求，可以透過外部之控制訊號Control做調整。當共同電壓VC0M經過調校後，一樣可以透過外部控制將共同電壓VC0M之值再一次回存於記憶體404内，下次開機時，就不必再做調整。整合型直流轉換器406中，伽瑪高壓低壓降穩壓器 (GammaHVLDO)410，係耦接至工作電壓VADD，且輸出第一電壓VREF，第一電壓VREF係為伽瑪高壓低壓降穩壓器410 内部之固定參考電壓。其中，整合型直流轉換器406係輕接至一分壓回路，依據第一電壓VREF以輸出伽瑪電壓VGAM 至源極驅動器4121〜412η。分壓回路決定伽瑪電壓vgAM之輸出準位，分壓回路包括電阻R4〜R5，電阻R4之第一端搞接至地電壓，電阻R5之第一端耦接至電阻之第二端及伽瑪高壓低壓降穩壓器410,電阻R5之第二端耦接至伽瑪高壓低壓降穩壓器410,且電阻旧之第一端係具有第一電壓VREF。因此，藉由分壓回路之運作，電阻肋之第二端具有伽瑪電壓VGAM且輸出伽瑪電壓VGM至源極驅動器 4121〜412η。此外，所輸出之伽瑪電壓VGM亦可以視實際使用情況藉由另外的電阻RGl〜RGn+1所形成之多分壓電 200822030Vo + 4x(VH~VL)/128 200822030, .Λ£ΛΥΙ«3{/Ιι * 丄\ 125 11111101 ^〇+125x(VH-VL)/128 126 11111110 Vo+126x(VH-VL)/128 127 11111111 Vo+127x(VH-VL)/128 Table 1 If the preset voltage of the initial setting of the memory 404 does not meet the actual demand, it can be adjusted by the external control signal Control. When the common voltage VC0M is calibrated, the value of the common voltage VC0M can be once again stored in the memory 404 through external control, and the next time the power is turned on, it is not necessary to make adjustments. In the integrated DC converter 406, a gamma high voltage low dropout regulator (GammaHVLDO) 410 is coupled to the operating voltage VADD and outputs a first voltage VREF, and the first voltage VREF is a gamma high voltage low dropout regulator. 410 Fixed reference voltage inside. The integrated DC converter 406 is connected to a voltage dividing circuit to output a gamma voltage VGAM to the source drivers 4121 to 412n according to the first voltage VREF. The voltage dividing circuit determines the output level of the gamma voltage vgAM, the voltage dividing circuit includes the resistors R4 R R5, the first end of the resistor R4 is connected to the ground voltage, and the first end of the resistor R5 is coupled to the second end of the resistor and the gamma The high voltage low dropout regulator 410, the second end of the resistor R5 is coupled to the gamma high voltage low dropout regulator 410, and the first end of the resistor has a first voltage VREF. Therefore, by the operation of the voltage dividing circuit, the second end of the resistance rib has a gamma voltage VGAM and outputs a gamma voltage VGM to the source drivers 4121 to 412n. In addition, the output gamma voltage VGM can also be formed by another resistor RG1~RGn+1 according to actual use. 200822030

—^^rznym'jjju， TW3094PA 路而调正成不同值之伽瑪端點電壓Μ卜跑，此即為各灰階之伽瑪端點電壓。 ™ D〇t^ ίΓ例巾所提供之伽碼高壓低壓降穩壓器（Gamma )41G係不同於—般所指之低壓差線性穩壓器 ⑽X未繪示於圖）’―般之低壓差線性穩_係提供時 402及多個驅動^件所使用之數位電源，輸出電 : 1’5V〜Vin-(K5V’而伽瑪高壓低壓降穩壓器 (Ga職HVLDOMi 0則為提供伽瑪電壓之電源。薄膜電晶體〔液晶顯示器所需之伽瑪電壓大約在7〜9V之間，不同於一般之9V〜13V，所以伽瑪高壓低壓降穩壓器的製程耐壓須高於一般的低壓差線性穩壓器，因此稱之為高壓低壓差線性穩壓器（HVLD0)。本實施例所揭露之採用伽瑪高壓低壓降穩壓器（GammaMLDOMK)之電路架構，電壓容易調整，同時可以節省板材佈線面積，伽瑪電壓VGM端之電壓值計异方式為公式（4)。 VGAM=(1+R5/R4)VREF 公式⑷ …本發明上述實施例所揭露之應用於液晶顯示器之新整合型直流轉換器，係可接收時序控制器所輪出之數位押制訊號’藉以調整共同電壓VC0M。此外，白碼電壓VGAf 產生方式，可穩定的提供源極驅動器伽瑪端點電壓，避免受到工作電壓VADD之漣波（ripple)影響。特別是數位介面的共同電壓VC0M調整方式，可以杜絕傳統人=調整^ 缺失，未來如能搭配自動化機台，更可以做到自動調整共同電壓VC0M之功能，極具實用性。 15 200822030—^^rznym'jjju, TW3094PA is tuned to a different value of the gamma endpoint voltage, which is the gamma endpoint voltage of each gray level. The gamma high-voltage drop-down regulator (Gamma) 41G provided by TM D〇t^ Γ Γ 不同于不同于不同于不同于 41 41 41 41 41 41 41 41 41 41 41 41 41 41 41 41 41 41 41 41 41 41 41 41 41 41 41 41 41 41 41 41 41 41 41 41 Linear stability _ provides the digital power supply used by 402 and multiple drive components, output power: 1'5V~Vin-(K5V' and gamma high voltage low dropout regulator (Ga HVLDOMi 0 provides gamma Voltage power supply. Thin film transistor [The gamma voltage required for liquid crystal display is about 7~9V, which is different from the general 9V~13V, so the process withstand voltage of gamma high voltage low dropout regulator must be higher than the general low voltage. The differential linear regulator is called a high voltage low dropout linear regulator (HVLD0). The circuit structure of the gamma high voltage low dropout regulator (GammaMLDOMK) disclosed in this embodiment makes the voltage easy to adjust and saves The wiring area of the board, the voltage value of the gamma voltage VGM terminal is calculated by the formula (4). VGAM=(1+R5/R4)VREF Formula (4) The new integrated type of the liquid crystal display disclosed in the above embodiment of the present invention DC converter, which can receive the timing controller The digital control signal 'to adjust the common voltage VC0M. In addition, the white code voltage VGAf generation mode can stably provide the source driver gamma endpoint voltage to avoid the ripple effect of the working voltage VADD. Especially The common voltage VC0M adjustment method of the digital interface can eliminate the traditional people = adjustment ^ missing, if you can match the automatic machine in the future, you can automatically adjust the function of the common voltage VC0M, which is very practical. 15 200822030

一。剛肌一’W3094PA 綜上所述，雖然本發明已以一較佳實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍内，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。One. Rigid Muscles - 'W3094PA In summary, although the present invention has been disclosed above in a preferred embodiment, it is not intended to limit the invention. It will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

20082203 0TW3094PA 【圖式簡單說明】第1圖繪示傳統旋鈕式分壓電阻電路之電路圖。第2圖繪示傳統採用數位調整元件以產生共同電壓 V⑶Μ的電路之電路圖。第3圖繪示傳統伽瑪電壓源穩壓電路之電路圖。第4圖繪示依照本發明較佳實施例之具有整合型直流轉換器之液晶顯示器之部份示意圖。第5圖繪示依照本發明較佳實施例之時序控制器402 之示意圖。 17 200822030 ^20082203 0TW3094PA [Simple description of the diagram] Figure 1 shows the circuit diagram of a conventional knob type voltage divider resistor circuit. Fig. 2 is a circuit diagram showing a conventional circuit using a digital adjustment element to generate a common voltage V(3). Figure 3 is a circuit diagram of a conventional gamma voltage source voltage regulator circuit. 4 is a partial schematic view of a liquid crystal display having an integrated DC converter in accordance with a preferred embodiment of the present invention. FIG. 5 is a schematic diagram of a timing controller 402 in accordance with a preferred embodiment of the present invention. 17 200822030 ^

—· TWj094PA 【主要元件符號說明】 102、202、414 :放大器 201 :數位式電壓計數器 301 :伽瑪電壓源穩壓電路 4 0 0 ·液晶顯不為 402 :時序控制器 404 :記憶體 406 :整合型直流轉換器 408 :脈衝寬度調變控制電路 410 :伽瑪高壓低壓降穩壓器 412 :數位類比轉換器 4021 :上行/下行計數器 4022 :數位介面 4121〜412η :源極驅動器 rl〜r7、R1 〜R5、RG1 〜RGn+Ι ··電阻 C :電容、 D:並聯穩壓器 18—· TWj094PA [Description of main component symbols] 102, 202, 414: Amplifier 201: Digital voltage counter 301: Gamma voltage source voltage regulator circuit 4 0 0 • Liquid crystal display is not 402: Timing controller 404: Memory 406: Integrated DC converter 408: Pulse width modulation control circuit 410: Gamma high voltage low dropout regulator 412: Digital analog converter 4021: Up/down counter 4022: Digital interface 4121~412η: Source driver rl~r7, R1 ~ R5, RG1 ~ RGn + Ι · · Resistor C: Capacitor, D: shunt regulator 18

Claims

W3094PA 200822030, 十、申請專利範圍： 1. 一種整合型直流轉換器，係應用於—液晶顯吊态，該液晶顯示器係包括一時序控制器、一記憶體及: 個源極驅動器，該整合型直流轉換器包括：“嘎麩一脈衝寬度調變控制電路，係用以產生該些源極器之工作電壓； +動一放大|§ ’係形成一射極隨岸禺器；一數位類比轉換器（DAC)，係耦接至該時序控制器及該記憶體，受該時序㈣H之控籠依據該記憶體所儲存之一數位預設電壓，以輸出一共同電壓”⑶们至該放大器；以及一伽瑪咼壓低壓降穩壓器（Gamma HVLD0)，係耦接至工^電壓（VADD)，且輸出_第_電壓（VREF); ★其中，該整合型直流轉換器係耦接至一分壓回路，依，該第f：屋以輪出一伽瑪電壓⑽M)至該些源極驅動 m /·如申明專利範圍第1項所述之整合型直流轉換 :J數位類比轉換器係接收-高位準電壓(VH)及-低位準電壓㈤’該共同電壓之電壓位準係小於該高位準電壓 ^ “低位準電壓，且該共同電壓係經由該放大器所形射極輸出，以料該液晶顯示器之電場之翏考準位。器，1.中如中請專利範圍第2項所述之整合型直流轉換數位類比轉換器係為一 η位元之數位類比轉 19 200822030 一适/i冊m , aW3094PA ' 換器，η為正整數，該時序控制器可以控制該數位類比轉換器以一位階電壓差調整該共同電壓，該位階電壓差係為該高位準電壓及該低位準電壓之差除以2η。 4. 如申請專利範圍第3項所述之整合型直流轉換器，該時序控制器包括：一上行/下行計數器，係用以接受一控制訊號，據以決定以m個位階電壓差調整該共同電壓，m為小於2η之正整數；以及一數位介面，係耦接至該上行/下行計數器及該數位類比轉換器，使得該數位類比轉換器以m個位階電壓差調整該共同電壓。 5. 如申請專利範圍第2項所述之整合型直流轉換器，其中該數位類比轉換器係耦接至一分壓電路，該分壓電路包括：一第一電阻，該第一電阻之第一端係耦接至一地電壓；一第二電阻，該第二電阻之第一端係耦接至該第一電阻之第二端；以及一第三電阻，該第三電阻之第一端係耦接至該第二電阻之第二端，該第三電阻之第二端係耦接至該工作電壓；其中，該第一電阻、該第二電阻及該第三電阻使得該第二電阻之第一端具有該低位準電壓，且使得該第三電阻之第一端具有該高位準電壓。 6. 如申請專利範圍第1項所述之整合型直流轉換 20 200822030„ ——,/WliU ^// Li — r r ^ ^ * Λ. Λ. Λ, 器，其中該記憶體係為一電子抹除式唯讀記憶體 (EEPROM)。 7. 如申請專利範圍第1項所述之整合型直流轉換器，其中該分壓回路包括：一第四電阻，該第四電阻之第一端係耦接至該地電壓；一第五電阻，該第五電阻之第一端係耦接至該第四電阻之第二端及該伽瑪高壓低壓降穩壓器，該第五電阻之第二端係耦接至該伽瑪高壓低壓降穩壓器，且該第五電阻之第一端係具有該第一電壓；因此，該第五電阻之第二端具有該伽瑪電壓（VGAM) 且輸出該伽瑪電壓至該些源極驅動器。 8. 如申請專利範圍第7項所述之整合型直流轉換器，該伽瑪電壓更經由一多分壓電路而輸出複數個伽瑪端點電壓至該些源極驅動器。 9. 如申請專利範圍第1項所述之整合型直流轉換器，其中該液晶顯示器係為一薄膜電晶體液晶顯示器（TFT LCD)。 10. —種液晶顯示器，包括：一時序控制器；一記憶體，係儲存一數位預設電壓；複數個源極驅動器；以及一整合型直流轉換器，包括：一脈衝寬度調變控制電路，係用以產生該些源 21 200822030 —〜二…：W3094PA 極驅動器之工作電壓；一放大器，係形成一射極隨耦器；一數位類比轉換器（DAC)，係耦接至該時序控制器及該記憶體，受該時序控制器之控制並依據該數位預設電壓，以輸出一共同電壓（V⑶M)至該放大器；；及一伽瑪高壓低壓降穩壓器（Gamma HVLD0)，係耦接至一工作電壓（VADD)，且輸出一第一電壓（VREF); 其中’該整合型直流轉換器係I禺接至一分壓回路，依據該第一電壓以輸出一伽瑪電壓（VAGM)至該些源極驅動器。 11·如申請專利範圍第1〇項所述之液晶顯示器，該數位類比轉換II係接收—高位準電壓⑽及—低位準電 [(VL) It共同電壓之電壓位準係小於該高位準電壓且大於該低位準，且該共同係經由該放大ϋ所形成之該射極_器而輸出，以作為該液晶顯示器之電場之準仿。 7 7 12.如申請專利範圍第π項所述之液晶顯示器，其、~數位類比轉換益係為一 η位元之數位類比轉換器， η為正整數，該時序控制器可以控制該數位類比轉換器以 4 I1白電[差5胃整該共同電壓，該位階電歷差係準電壓及該低鱗電敎差除以。门位 Μ請專利範圍第12項之液晶顯時序控制器包括： ^ 上行/下仃計數器，係用以接收一控制訊號，據以 22 W3094PA 200822030 決定以m個位階電壓差調整該共同電壓，m為小於2n之正整數；以及一數位介面，係耦接至該上行/下行計數器及該數位類比轉換器，使得該數位類比轉換器以m個位階電壓差調整該共同電壓。 14. 如申請專利範圍第11項所述之液晶顯示器，其中該數位類比轉換器係耦接至一分壓電路，該分壓電路包括：一第一電阻，該第一電阻之第一端係耦接至一地電壓；一第二電阻，該第二電阻之第一端係耦接至該第一電阻之第二端；以及一第三電阻，該第三電阻之第一端係耦接至該第二電阻之第二端，該第三電阻之第二端係耦接至該工作電壓；其中，該第一電阻、該第二電阻及該第三電阻使得該第四電阻之第一端具有該低位準電壓，且使得該第五電阻之第一端具有該高位準電壓。 15. 如申請專利範圍第10項所述之液晶顯示器，其中該記憶體係為一電子抹除式唯讀記憶體（EEPR0M)。 16. 如申請專利範圍第10項所述之液晶顯示器，其中該分壓回路包括：一第四電阻，該第四電阻之第一端係耦接至該地電壓；一第五電阻，該第五電阻之第一端係耦接至該第四電 23 'W3094PA 200822030 阻之第二端及該伽瑪高壓低壓降穩壓器，該第五電阻之第二端係耦接至該伽瑪高壓低壓降穩壓器，且該第五電阻之第一端係具有該第一電壓；因此，該第五電阻之第二端具有該伽瑪電壓（VGAM) 且輸出該伽瑪電壓至該些源極驅動器。 17. 如申請專利範圍第16項所述之液晶顯示器，該伽瑪電壓更經由一多分壓電路而輸出複數個伽瑪端點電壓至該些源極驅動器。 18. 如申請專利範圍第10項所述之液晶顯示器，該液晶顯示器係為一薄膜電晶體液晶顯示器（TFT LCD)。 24W3094PA 200822030, X. Patent application scope: 1. An integrated DC converter is applied to a liquid crystal display. The liquid crystal display includes a timing controller, a memory and a source driver. The integrated type The DC converter comprises: "bronze-pulse width modulation control circuit for generating the working voltage of the source devices; + moving one amplification|§ 'forming an emitter-to-shore converter; a digital analog conversion The DAC is coupled to the timing controller and the memory, and is controlled by the timing (4) H according to a predetermined voltage stored in the memory to output a common voltage "3) to the amplifier; And a gamma voltage drop low voltage drop regulator (Gamma HVLD0) coupled to the voltage (VADD) and output _ _ voltage (VREF); ★ wherein the integrated DC converter is coupled to a voltage divider circuit, according to the f: the house to rotate a gamma voltage (10) M) to the source drive m / · as described in the scope of claim 1 integrated DC conversion: J digital analog converter Receive - high level voltage (VH) and - The level voltage (5) 'the voltage level of the common voltage is less than the high level voltage ^" low level voltage, and the common voltage is output through the emitter of the amplifier to measure the electric field of the liquid crystal display 1. The integrated DC-converting analog-to-digital converter described in item 2 of the patent scope is an η-bit digital analogy. 19 200822030 yi/i volume m , aW3094PA ' converter, η As a positive integer, the timing controller can control the digital analog converter to adjust the common voltage by a one-order voltage difference, wherein the difference between the high level voltage and the low level voltage is divided by 2η. The integrated DC converter of the third aspect of the patent, the timing controller includes: an uplink/downstream counter for receiving a control signal, and determining to adjust the common voltage by m rank voltage differences, where m is a positive integer less than 2η; and a digital interface coupled to the up/down counter and the digital analog converter, such that the digital analog converter adjusts by m steps voltage difference 5. The integrated voltage converter of claim 2, wherein the digital analog converter is coupled to a voltage divider circuit, the voltage divider circuit comprising: a first resistor, The first end of the first resistor is coupled to a ground voltage; a second resistor, the first end of the second resistor is coupled to the second end of the first resistor; and a third resistor, the first The first end of the third resistor is coupled to the second end of the second resistor, and the second end of the third resistor is coupled to the operating voltage; wherein the first resistor, the second resistor, and the third The resistor causes the first end of the second resistor to have the low level voltage, and the first end of the third resistor has the high level voltage. 6. As described in the scope of claim 1, the integrated DC conversion 20 200822030 „, /WliU ^// Li — rr ^ ^ * Λ. Λ. Λ, 器, where the memory system is an electronic erase 7. The integrated read-only memory (EEPROM). The integrated DC converter of claim 1, wherein the voltage dividing circuit comprises: a fourth resistor, the first end of the fourth resistor is coupled a voltage to the ground; a fifth resistor, the first end of the fifth resistor is coupled to the second end of the fourth resistor and the gamma high voltage low dropout regulator, the second end of the fifth resistor Is coupled to the gamma high voltage low dropout regulator, and the first end of the fifth resistor has the first voltage; therefore, the second end of the fifth resistor has the gamma voltage (VGAM) and outputs the The gamma voltage is applied to the source drivers. 8. The integrated DC converter of claim 7, wherein the gamma voltage further outputs a plurality of gamma terminal voltages via a multi-divider circuit to The source drivers. 9. Integrated DC conversion as described in claim 1 The liquid crystal display is a thin film transistor liquid crystal display (TFT LCD). 10. A liquid crystal display comprising: a timing controller; a memory for storing a digital preset voltage; a plurality of source drivers; And an integrated DC converter, comprising: a pulse width modulation control circuit for generating the source 21 200822030 - 2 ...: W3094PA pole driver operating voltage; an amplifier forming an emitter follower a digital analog converter (DAC) coupled to the timing controller and the memory, controlled by the timing controller and based on the digital preset voltage to output a common voltage (V(3)M) to the amplifier; And a gamma high voltage low dropout regulator (Gamma HVLD0) coupled to an operating voltage (VADD) and outputting a first voltage (VREF); wherein the integrated DC converter is connected to a voltage dividing circuit, according to the first voltage, to output a gamma voltage (VAGM) to the source drivers. 11. The liquid crystal display according to claim 1, wherein Digital analog conversion II system receiving - high level voltage (10) and - low level quasi-electricity [(VL) It common voltage voltage level is less than the high level voltage and greater than the low level, and the common system is formed by the amplification The emitter is outputted as a quasi-simulation of the electric field of the liquid crystal display. 7 7 12. The liquid crystal display according to the πth aspect of the patent application, wherein the ~ digital analog conversion system is an n-bit The digital analog converter, η is a positive integer, the timing controller can control the digital analog converter to 4 I1 white electricity [difference 5 stomach complete the common voltage, the level electric history difference standard voltage and the low scale electric power difference Divide. The liquid crystal display timing controller of the 12th item of the patent scope includes: ^ Up/down counter, which is used to receive a control signal, and according to 22 W3094PA 200822030, the common voltage is adjusted by m step voltage difference, m a positive integer less than 2n; and a digital interface coupled to the up/down counter and the digital analog converter such that the digital analog converter adjusts the common voltage by m steps voltage difference. 14. The liquid crystal display according to claim 11, wherein the digital analog converter is coupled to a voltage dividing circuit, the voltage dividing circuit comprising: a first resistor, the first resistor The end is coupled to a ground voltage; a second resistor, the first end of the second resistor is coupled to the second end of the first resistor; and a third resistor, the first end of the third resistor The second end of the third resistor is coupled to the operating voltage; wherein the first resistor, the second resistor, and the third resistor cause the fourth resistor The first end has the low level voltage, and the first end of the fifth resistor has the high level voltage. 15. The liquid crystal display of claim 10, wherein the memory system is an electronic erasable read only memory (EEPROM). The liquid crystal display of claim 10, wherein the voltage dividing circuit comprises: a fourth resistor, the first end of the fourth resistor is coupled to the ground voltage; a fifth resistor, the first The first end of the fifth resistor is coupled to the second end of the fourth electric 23 'W3094PA 200822030 and the gamma high voltage low dropout regulator, and the second end of the fifth resistor is coupled to the gamma high voltage a low voltage drop regulator, and the first end of the fifth resistor has the first voltage; therefore, the second end of the fifth resistor has the gamma voltage (VGAM) and outputs the gamma voltage to the sources Extreme drive. 17. The liquid crystal display of claim 16, wherein the gamma voltage further outputs a plurality of gamma terminal voltages to the source drivers via a multi-divider circuit. 18. The liquid crystal display of claim 10, wherein the liquid crystal display is a thin film transistor liquid crystal display (TFT LCD). twenty four