200820431 九、發明說明： 【發明所屬之技術領域】 /本發明係有關於-種紅外線熱影像陣列模組，其係特猶關於紅外線 熱影像陣列模組驗證架構與製造方法。 【先前技術】 / 著必須滿足各種熱像應用的特殊需求，在陣列感測模組材料的選 擇、最佳化元件結構設計與提升熱影像解析度及偵檢度，過去十多年來均 為開發高品質之紅外線熱影像陣舰組並盼望達到之目的。舉例來說：_ 曰本Masalkar等人（US 20020088943A1)，針對感測架構中多重量子井 製程架構的改進與簡化製程之步驟提出，可有效提升感測元件的檢測效 率，在2004年，美國jeffrey B· Bart〇n等人（us 2〇_6i〇56ai)，提出 • ~化銦基板下糊新設計之近紅外光偵檢架構與提出針對模组製程改進方 法用於偵檢陣列架構上；2〇〇5年美瞒chael G· Engel_ (us 20050HM_A1 )等人針對大紐高解析度可見光與近紅外光陣列型影像 感測器模組架構提出改良性架構，同年Frederick E.⑽等人（仍 2〇〇50_遞），首:欠如量子點紅外線鮮面陣舰減合⑽減號讀 取電路架構之熱影像應用。 總括絲，由於熱像模組開發需要各種不料業領域賊人員，例如， 一個完整紅外線熱影像陣列模組’包含：感測树陣列蠢晶與設計需要物 理、光電材料、材料蟲晶專長，陣列式光訊號讀取積體電路⑽c)單元 需要積體電路設計、類比數位電子專長及熱顯像校正電路需要邏輯電路與 紛象電路設計專長，整體模組最佳整合與偵錯需要影像系統驗證專長人 ，。之前’整合技術開發時，只在侧專業_專長躺巾進行局部性能 最佳化驗證’並無提出一套具體紅外線影像感測模組驗證流程與其結構製 作整合方法。 力@此’本發明針對上述問題而提出-種紅外線熱影像陣列模組驗證 架構與製造方法，不僅可改善傳統熱影像_材料、異#接合與顯像之架 5 200820431 構^製作流程之缺點，又可顧在不關影像制材料、異質接合與顯像 之木構與製作流程，並提升開發各種熱像陣列模組中之偵錯效率，可解決 上述之問題。 【發明内容】 制、生本务^主要目的，在於提供—種紅外線熱影像陣舰組驗證架構與 衣w方法，其提升陣列感測模組性能及偵錯效率。 、 制、^之#目的’在於提供—種紅外線熱影像陣列模組驗證架構與 衣以方法，其有效降低研發之成本。 &树對紅外線熱影像陣列模組驗證架構與製造方法，其包含一埶 格ΐ組Γ格設計、蟲晶與光學物性驗證，須先進行蟲晶參數校正；驗證合 二貼：單乙型感測元件製程與變溫光電量測驗證，實際蟲晶完成 日:rr同軸導線或低雜訊號線導出，經過低溫 後即itr-ΓΪ 、響應賴、碰度校正，合格此驗證 規才夂“ rtr車列製程及其光電均勻度驗證’不合格則返回熱像模組 陣歹^程及ΓΓΪ光學物性驗證重新驗證；而合格後，繼續進行該焦平面 試區域進行日立雷二吏 型茶數進行陣列製作'，之後，選定測 讀出積體電^二與磨驗=格此即進行一焦平面陣列與訊號 晶與光學物性驗證重新驗證。n…不&格則返回熱像模組規格設計、磊 驗證，將間平面^平面_與峨讀出龍電路貼合與磨薄製程 組進行先積體電路進行銦貼合，以感測陣舰 系統）驗證，不合才夂則返巫f Ο進仃熱影像品質整合測試（含光機 最佳驅動與控制輸出夂杳、、貝正& “ °式（含光機系統）驗證，調制 ’ ’以進彳Τ模組熱f彡像品質分析與測定；合格此驗 6 200820431 進行-熱影像陣列模組雛型，不合格則返回焦平面陣解峨 和體-¾路貼合與磨薄製程驗證重新驗證。 ” 貝』 =格後，繼續進行該熱影像陣列模組雛型，係利用銦柱貼 平面感測陣列接合，每陣列單元内的光電流 ^歹^ =經訊號輸出端送至感測器緩衝板模組與影 侧物獅型。如此，可姆列感· 性月b，細短偵檢模組之驗證期程。 【實施方式】 兹為使貴審查委員對本發·結構雜及職成之功效有更進—步 之瞭线’謹佐以較佳之實施例及配合詳細之說明，說明如後： s 弟士圖其為本發明之紅外線熱影像陣列模組驗證架構之流程 ί先:H *發明包含—熱賴域格設計、蟲晶與光學物性驗證1〇， 交正；而—感測波段利用短、中、長紅外線吸收波段； :感雜雜外線穿透基板⑽選擇感測模組之品紐劣，即影響接收波 =紅外線牙透率，-底端高摻雜接觸層副，紅外線 Γ率；—本質層或空乏層⑽，吸收、紅外線之厚度與 λΙ、’影響1子效率與感測元件暗電流值；一能障阻騎別，影 二感，件本質阻抗，以符合高注人光電流效率、_树暗電流值、操 作溫度下活化m端隸f摻雜觸層112，影響_接觸特性與光 電子流輸出之效率。 上迷驗證合格後，即進行一單乙型感測元件製程與變溫光電量測验證 ^貫際蟲晶完成導熱膠關試絕緣，而以金線經由_導線或低雜訊號 線導出，經過低溫變溫與變壓量測其暗電流、暗電阻、響應頻譜、偵檢度 权正’合格此驗證後即進行一焦平面陣列製程及其光電均勾度驗證汕，不 口 t則返回熱像杈組規格設計、遙晶與光學物性驗證重新驗證；而合格 200820431 後，繼續進行遠焦平面陣列製程及其光電均勻度驗證3〇，以符合設定之感 測元件規格’進行焦平面障列製程，而製作流程為使用之單乙型參數進行 陣列製作’之後，選定職區域進行暗電流均勻度測試，合格此驗證後即 進行-焦平祕顺訊號讀出麵電路貼合與磨薄製程驗證4G，不合格則 返回熱像模組規格設計、磊晶與光學物性驗證1〇重新驗噔。 合格後，繼續進行·、平鱗__如频f賴合錢薄製程 驗證40 ’將間平面感測模組與訊號讀出積體電路進行姻貼合，以便使感測 陣列模組進行光電訊號轉換；-訊號取樣與保持單元418，儲存於積分電容 1〇2〇，即感測之訊號/雜訊比（S/N比）輸入至_注入單元412;該注入單 元412，注入積分電容翻電荷訊號輸出至輸出端；一放大器模组單元， 訊號增益放大；-行414與列416多工選擇器單元，感測單元位置循序揭 ^ -時序生成控制單满，由主時序概控制讀取與訊號積分時間，合 證彳_行熱品f整合戦（含桃知驗證Μ，不合格則 返回焦平面陣列製程及其光電均勻度驗證30重新驗證。 合格後，繼續進行該熱影像品質整合 制:!直，，二===調 =光之齡模 面驅動模組…顯像處理電路模组526，處理_ 處理器522 ’控制整個指令與影像訊號輸出，並連社主^月/久 後即進杆一赦旦/你咕 I埂、，'口主控電腦，合格此驗證 積_二:::=:=則返-平面陣列與· 行式與 使列412與彳情6乡工験序_ 钟分電容膽訊號， 像處理系統内進辟像理虎輸出而达至感測器緩衝板模組524與影 …5錢里’以完成熱影感測陣列模組離型即。 8 200820431 清-併參閱第二圖（a)，其為本發明之架構圖。由圖示可知，本發明 熱像模_格設計、蟲晶與光學物性驗證1()，係依據所設計之參數^ , 定義規格所需熱影像陣列模組中紅外線感測元件結構，其利用蠢晶與高溫 擴散设備，以分子束蠢晶法（M〇lecular Beam Epitaxy，眶）、金屬有機 氣相磊晶法（Metal Organic VapQF DepQsitiQn，MQ(：vd)— ，擴散爐（麵）純佳元件結難備对。若將紅外光徽層⑽設計成 量子侷限架構，如：量子井（Quantum Well)、量子點（如碰咖㈣感 測架構操作，則偏向以分子束蠢晶法或金屬有機氣減晶法之方式蠢晶。 反之，若以基體型（Bulk Type) P-N、P-I-N型態為主之感測架構，常 以分子束蟲晶法或金屬有機氣相屋晶;遞成長_丨層後，再高溫擴散爐 擴散出P層。而使用基板可為四族如：石夕（Si)、三五族如：咖、⑽， 其感測材料、週期架構與厚度分別為；Si/SizGel—z (z=〇.卜， l〇~4〇nm/l〜i〇nm，10〜50 個週期）、AlxGy—xAs/GaAs (χϋ〇·5， 10〜40nm/l〜l〇nm，10〜50個週期）、MxGal—心㈣如―咖鳩s (X-O·卜0· 5，y二〇· 1 〜〇· 3 ’ 10〜4〇nm/;i〜5nin/l〜10nm，10〜50個週期），而基 體型感測材料為InSb、MCT、InP，有I-本質層（厚度：0〜5//m)之卜卜碟 構，P極是利用HTD0擴散方式形成，p極擴散材料可為論化合物、如、^， 深度:1〜3"m 〇 田以刀子束视日日法、金屬有機氣相磊晶法或高溫擴散爐磊晶與擴散機 台成長所設計劇元件_前，必須先進行蠢晶參數校正，如：材料沉積 ^、週期架構完整性、結構結晶品質、極性與參雜濃度。上述為感測元件 板組架構之蠢晶架構設計流程、蠢晶參數驗證與感測元件架構。之後，截 取同-片感測凡件蟲晶片一部分（約晶片總面積1/4〜1/5)，進行單乙型感 測讀製程、光電特性制驗證2Q，主要確認實際i晶完減測元件架構 與所設計元件結構間的光電特性與品質差異。 在單乙型感測元件製程中，以光罩與實體元件製程線寬誤差<1〇%，進 行變温光《測驗證時，在10〜删κ下操作溫度誤差率<15%，得到光譜型態 200820431 均勻度薦，並調制適當的_水溶劑（内含腿值酸液：雙氧水：去離 子水=2〜5 : ：1〜2:5〜20)，蝕刻深度為元件層架構上層至產生電子_電洞層 間之厚度（約1〜lG//m)，目的為避免側向漏電流，若為平面式（ρι-加e) 定義元件區域製程，可用於高溫擴散p—極（擴散深度在G 5〜5卵），再以 表面研磨方式（1〜5/zm粒徑之氧化紹：去離子水=1:2〜5)，研磨至 〇· 25〜2卵，形成最適當之p—極區域，非元件區域為卜本質層可阻止側向溢 散（Lateral Spreading )電流，而將光電流侷限流經元件主架構層至接 觸電極區，以達到最大量子效率。 之後，可選擇以電聚化學氣相沉積法（pl_EnhanceChemical200820431 IX. INSTRUCTIONS: [Technical field to which the invention pertains] / The present invention relates to an infrared thermal image array module, which relates to an infrared thermal image array module verification architecture and a manufacturing method. [Prior Art] / Must meet the special needs of various thermal imaging applications, in the selection of array sensing module materials, optimized component structure design and improved thermal image resolution and detection, for the past ten years or more Develop high-quality infrared thermal imaging fleets and look forward to achieving their goals. For example: _ MaMasalkar et al. (US 20020088943A1), proposed for the improvement of the multi-quantum well process architecture in the sensing architecture and the simplification of the process steps, can effectively improve the detection efficiency of the sensing components, in 2004, the United States jeffrey B. Bart〇n et al. (us 2〇_6i〇56ai) proposed a near-infrared light detection architecture based on the new design of the indium substrate and proposed a module process improvement method for the detection array architecture; In the following year, Frederick E. (10) et al. Still 2〇〇50_ hand), first: owing to the thermal imaging application of the quantum structure of the quantum dot infrared fresh-faced ship reduction (10) minus the reading circuit architecture. The total wire, because the development of thermal imaging modules requires a variety of thieves in the industry, for example, a complete infrared thermal image array module 'includes: sensing tree arrays and design needs physical, optoelectronic materials, material insect crystal expertise, array Optical signal reading integrated circuit (10) c) unit requires integrated circuit design, analog digital expertise and thermal imaging correction circuit requires logic circuit and framing circuit design expertise, overall module optimal integration and debugging requires image system verification Expertise,. In the previous 'integrated technology development, only the side professional _ specialty lie lying for local performance optimization verification' did not propose a specific infrared image sensing module verification process and its structural integration method. The present invention is directed to the above problems and proposes an infrared thermal image array module verification architecture and manufacturing method, which can not only improve the shortcomings of the traditional thermal image_material, different #joining and developing frame 5 200820431 It can also solve the above problems by not considering the wood structure and production process of image material, heterojunction and development, and improving the debugging efficiency in developing various thermal image array modules. SUMMARY OF THE INVENTION The main purpose of the system is to provide an infrared thermal image array verification framework and a clothing w method, which improves the performance of the array sensing module and the debugging efficiency. The purpose of the system is to provide a verification framework and a clothing method for the infrared thermal image array module, which effectively reduces the cost of research and development. & tree verification framework and manufacturing method for infrared thermal image array module, which includes a 埶 ΐ group design, insect crystal and optical property verification, must first correct the crystal parameters; verify the second paste: single type Sensing component process and variable temperature photoelectric measurement verification, the actual insect crystal completion date: rr coaxial wire or low noise signal line is exported, after low temperature, itr-ΓΪ, response Lai, touch correction, qualified this verification rule 夂 "rtr The train process and its photoelectric uniformity verification 'returned to the thermal image module array and the optical property verification to re-verify; and after passing the test, continue to carry out the focal plane test area for the number of Hitachi Leiji type tea Array production ', after that, select and read the integrated product and the test = then perform a focal plane array and signal crystal and optical property verification and re-verification. n... not & check the thermal image module specifications Design, Lei verification, the plane plane ^ plane _ and 峨 read the dragon circuit and the thin process group for the first integrated circuit for indium bonding, to sense the array ship system) verification, if not, then return to the witch Ο进仃影Quality integration test (including the best drive and control output of the optical machine, 正, &;; " ° type (including optical system) verification, modulation ' 'to enter the 彳Τ module thermal image quality analysis and determination; Qualified for this test 6 200820431 - The prototype of the thermal image array module, if it fails, return to the focal plane array solution and the body -3⁄4 way and the thin process verification and re-verification. "Bei" = after the grid, continue the heat The prototype of the image array module is bonded by an indium pillar-mounted planar sensing array, and the photocurrent in each array unit is sent to the sensor buffer board module and the shadow side lion type through the signal output end. , Kumli sense, sex month b, the verification period of the short detection module. [Embodiment] In order to make your review board have a more advanced line of the efficacy of the hair, structure and occupational skills The following is a description of the preferred embodiment and the detailed description of the following: s 彼 士 其 为本 为本 为本 为本 为本 为本 为本 为本 红外线 红外线 红外线 红外线 红外线 红外线 红外线 红外线 红外线 红外线 : : : : : : : : : : : : : H H H H H Insect crystal and optical property verification 1〇, cross-positive; and – sensing band Use short, medium and long infrared absorption bands; : The interfering external line penetrates the substrate (10) to select the sensing module, which affects the received wave = infrared tooth penetration rate, - the bottom end is highly doped contact layer pair, infrared Γ rate; - essence layer or vacant layer (10), absorption, infrared thickness and λ Ι, 'influence 1 sub-efficiency and sensing element dark current value; one obstacle barrier riding, shadow two sense, piece intrinsic impedance, in line with high Injecting photocurrent efficiency, _tree dark current value, and operating m temperature to activate f-doped contact layer 112, affecting the contact characteristics and the efficiency of photoelectron flow output. After the verification is passed, a single type B feeling is performed. Test component process and variable temperature photoelectric measurement verification ^ 贯 虫 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶The response spectrum and the detection degree right are qualified. After this verification, a focal plane array process and its photoelectricity check is performed. If no, then return to the thermal image group specification design, and the remote crystal and optical property verification are verified. ; and qualified 200820431 Continue to perform the far-focus planar array process and its photoelectric uniformity verification 3〇, in order to meet the set sensing component specifications 'to perform the focal plane barrier process, and the production process is to use the single-type parameter for array production', then select The dark current uniformity test is carried out in the service area, and the verification is carried out after the verification. The circuit of the Jiaoping secret signal reading surface is combined with the thinning process verification 4G. If it fails, the specification of the thermal image module is returned, and the epitaxial and optical properties are returned. Verify that 1〇 is re-examined. After passing the test, continue to carry out the flat scale __ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The signal conversion and the signal sampling and holding unit 418 are stored in the integrating capacitor 1〇2〇, that is, the sensed signal/noise ratio (S/N ratio) is input to the injection unit 412; the injection unit 412 is injected with the integration capacitor. Turning the charge signal output to the output; an amplifier module unit, signal gain amplification; - line 414 and column 416 multiplexer unit, sensing unit position sequence - ^ timing generation control single full, read by master timing control Take the signal integration time, the certificate 彳 _ hot item f integration 戦 (including Tao Zhi verification Μ, if it fails, return to the focal plane array process and its photoelectric uniformity verification 30 re-verification. After passing the test, continue the thermal image quality Integration system:! Straight,, two === adjustment = light age die surface drive module... development processing circuit module 526, processing _ processor 522 'control the entire command and video signal output, and even the main body ^ month / After a long time, you will enter the club for a while. , 'portal master computer, qualified this verification product _ two:::=:= then return-plane array and · line and make column 412 and lyric 6 township order _ clock minute capacitance bile signal, like processing system The internal input is like the Ricoh output and reaches the sensor buffer board module 524 and the shadow...5 money to complete the thermal imaging array module release. 8 200820431 Clear - and refer to the second picture (a) It is the architecture diagram of the present invention. It can be seen from the figure that the thermal image module of the present invention, the crystal and the physical property verification 1 (), according to the designed parameters ^, define the required thermal image array module Mid-infrared sensing element structure, which utilizes stray crystal and high-temperature diffusion equipment, Molecular Beam Epitaxy, metal organic vapor phase epitaxy (Metal Organic VapQF DepQsitiQn, MQ(:vd) ) - , the diffusion furnace (face) pure good component is difficult to prepare. If the infrared light layer (10) is designed into a quantum confinement structure, such as: Quantum Well (quantum well), quantum dots (such as touch coffee (four) sensing architecture operation, It is biased toward silencing by molecular beam or metal organic gas reduction. Bulk Type PN, PIN type-based sensing architecture, often by molecular beam crystallization method or metal organic gas phase house crystal; after growing _ 丨 layer, then high temperature diffusion furnace diffuses out P layer. The substrate can be of four groups such as: Shi Xi (Si), three or five families such as: coffee, (10), the sensing material, periodic structure and thickness are respectively; Si / SizGel - z (z = 〇. Bu, l 〇 ~ 4 〇nm/l~i〇nm, 10~50 cycles), AlxGy-xAs/GaAs (χϋ〇·5, 10~40nm/l~l〇nm, 10~50 cycles), MxGal-heart (four) such as Curry s (XO·Bu 0·5, y 〇 〇 1 ~ 〇 · 3 '10~4〇nm/; i~5nin/l~10nm, 10~50 cycles), while the base type sensing material is InSb, MCT, InP, there is an I-essential layer (thickness: 0~5//m), the P-pole is formed by HTD0 diffusion, and the p-polar diffusion material can be a compound, such as ^, depth. :1~3"m Putian uses the knife to view the Japanese and Japanese methods, metal organic vapor phase epitaxy or high-temperature diffusion furnace epitaxy and diffusion machine design of the drama component _ before, must first perform the stupid crystal parameter correction, such as : material deposition ^, periodic architecture integrity, Quality crystal structure, the polarity of the doping concentration. The above is the silo architecture design flow of the sensing component board set architecture, the stupid crystal parameter verification and the sensing component architecture. After that, the same-chip sensing part of the worm chip (about 1/4~1/5 of the total wafer area) is intercepted, and the single-b type sensing read process and the photoelectric characteristic system verification 2Q are performed, mainly confirming the actual i-crystal reduction test. The difference in photoelectric characteristics and quality between the component structure and the designed component structure. In the process of the single-b type sensing element, the temperature error of the process is determined by the error of the line width error of the mask and the physical component <1〇%, and the temperature error rate is <15% when the test is verified. Spectral type 200820431 uniformity recommended, and modulate the appropriate _ water solvent (including leg acid: hydrogen peroxide: deionized water = 2 ~ 5 : : 1 ~ 2: 5 ~ 20), etching depth is the upper layer of the component layer architecture To the thickness of the electron-hole layer (about 1~1G//m), in order to avoid lateral leakage current, if the planar region (ρι-plus e) defines the component region process, it can be used for high-temperature diffusion p-pole ( The depth of diffusion is in G 5~5 eggs), and then by surface grinding method (1~5/zm particle size oxidation: deionized water = 1:2~5), grinding to 〇·25~2 eggs, forming the most appropriate In the p-polar region, the non-element region is a layer that prevents lateral flow of current, and the photocurrent is limited to flow through the main structural layer of the device to the contact electrode region to achieve maximum quantum efficiency. After that, you can choose electro-chemical vapor deposition (pl_EnhanceChemical)
De輝t〇n，PECVD)(基板溫度介於咖〜5_)、光化學沉積法（ρι_ Vapor Depositor!，PVD)(基板溫度介於8〇〜2〇(rc)、離子濺鍍（一般使 用He、Ar離子鈍性氣體）、或加熱蒸錢法成長氧切⑽X)或氮化碎 (SiNx)，當作感測元件之表面披覆層116，厚度介於％〜咖服，再以化學 離子乾式法（Reactive IQn Etching，RIE)或濕侧法（氟化氫：去離 子[Buffer HF:DI water:卜5:20)定義出半導體接觸金屬區，而此類 感測元件上114與下1010電極區使用的接觸金屬材質，若為N型可為纪⑽) 1 〜20nm/鉻（Cr) 1 〜20nm/金鍺合金（Au/Ge) 50〜3⑽nm/金（Au) 5〇 3〇〇咖， P型可為鈀（Pd) 1〜20nm/鉻（Cr) 1〜20nm/金鈹合金（Au/@e)或鋅（Zn) 50〜300而/金（Au) 50〜300nm，可使用熱蒸錢、電子搶加溫蒸錢或離子_ 進行金屬電極製作。 快速退火（Rapid Thermal Annealing，RTA)製程是形成於較佳之半 導體與金屬間之歐姆接觸，加溫穩定溫度與時間分別介於35〇 5〇〇它， 15〜6〇Sec，加溫溫度斜率1〇〇〜2(TC/Sec。若為平台式（Mesa)定義感測元 件區域製程，除了利用光罩顯影定義蝕刻區，蝕刻區域深度必須超過下端 高摻雜極性區厚度之1/3〜1/2之間，其餘製程均以平面式相同。在針對量= 井感測元件_製程，必須在平台式定義感·件區域製程之後增加=期 性光柵結構，其結構為1維長條狀或2維方形或菱形型態，光栅間距及高度 200820431 介於卜5//m與1〇〜5_ιι之間侧方法與平台式制定義區域製程方式相 同。以上為單乙型感測元件製程主要步驟，其目的是要利耻製程參數作 為之後焦平面陣列架構製作之參考參數。 / 完成單乙型感測元件架構後，以導熱膠貼在測試絕緣基座上（如·氧 化銘載台基座），將金線上下訊號端引出，放入循環式液態氮低溫變2 空腔體中，再將端子pin訊號線經由饋通線（feedthr〇ugh)介面經由同轴 導線或低雜訊訊號線導出，經過低溫變溫與變壓量測其暗電流、暗電阻、 響應頻譜（如：以FTIR光譜分析儀··入射光源、進行傅立葉頻域^矣得到 魏光譜分布；健訊電赫大器：進行賴狀、訊號感峨與增益放 人）、偵檢度校正（如：黑體輻射源：校正叮⑺光源強度；鎖相放大器： 同步调k光電雜制電壓峨娜），經過以上光電物理參數量測與驗證 後，右料合所訂之制兀件規格，如：訊號雜訊比、光響應波段、響廉 度、债檢度、暗電流、暗微分電阻，同片感測蠢晶片其餘3/4〜4/5晶片:積 則使用陣列型光罩。 貝 之後，直接進行鮮面陣聽程，以每單位碰單元均勻度線寬誤差 <10%，光轉應巾總光電流均勻度>75%，而製作流程使闕單乙型參數為 主進行陣列製作，最後加上;^件測試區進行暗電流均勻度測試13，若為利 用低能隙感測材料所製作之感測_，如録化銦、汞麟，必須在感測陣 列表面以電漿、紫外光輔助汽相沉積、或加熱真空沉積等方式成長如：氧 化石夕或氮化石夕等鈍化膜（passivation layer)(厚度介於5〇.〜3〇〇隨之間^ 或以旋轉塗佈方式彼覆聚合物層（厚度介於Q 5〜之間）於陣列層上， 主要目的是防止表面受外界水氣或污染物滲透，造成表面雜質能階增加形 成側向暗電流，而影響感測品質。 淆一併芩閱第二圖（b)，其為本發明之架構圖。由圖示可知，隨之， 上、下金屬電極端上成長銦柱118 (高度介於3〜12，，底部面積小於金屬 電極區）’利用壓應力與平板加溫方式（溫度介於9G〜·。C)，達到鋼枉 近熔點瞬間時，與訊號讀出積體電路進行銦貼合（Indiumbonding)，接 200820431 著進行灌膠固化製程（如· Pnl ^ 訊號讀出積體電路架構。在^中贿水合物負）’而完成完整焦平面陣列與 讀出積體電路單-絲職錄_鮮面陣列與訊號 轉換’其架構為每個晝素單元對庫 =:為先“賴取 電容轉阻放大式注入擷取訊卢_ ;， 錢，人、閘極調變、 列感測元件架構與訊號讀出=/望能增加利用焦平面陣 成之切應鳩之目的減爾組帽度，並適度釋放研磨所造 在灌膠製程時’先將感測元件陣列與訊號讀出積體電路姓 如：丙mi it s ’至纽置8〜12小日輪翻有機溶液 殘存鮮面_额“上之賴光阻與 =麵小取後’旷併參閱第三圖，類似如單乙型感測晶片，先 1著於細細腳晶絲座上。基座上的打線接魏財式辦於隹^ 與訊號讀出積體電路内的感測轉換輸出訊號7〇、電源訊號72、時脈 =心驅織人輸出I/_#b74、操作溫度檢_號顺職二極體訊號 參閱第四圖，其為本發明之方塊圖。由圖示可知，完成後，再進行至 ^溫真技冷腔中5G2 ’先進行時序驅動程序51G，目的是供給焦平面陣 ^拉組正常工作狀態，使輸出訊號維持正常工作模式，此時利用數位示波 益截取感測器緩衝板模組（S_r Buffer B〇ard) 524内的影像類比 ，，以確認其要求輸出訊號規格。之前’測試室溫下之焦平面陣列與:號 項出積體電路接合阻值訊號畫面，目的初步了解接合狀況，再將溫度設定" 於待驗證紅外線熱影像陣顺組之適當溫度操作細，此操作溫度ςς絕 對凯氏溫度40〜3眶之間。當溫度在此設定溫度敎約至少15分鐘彳^，進= 調整外加模組操作偏壓512，而機至跨接在感測元件之偏壓絕對侧8介 於黯至4V間；配合調整訊號讀出積體電路内積分時間使其介於ι〇㈣c至 12 200820431 32msec之間；訊號轉阻放大暨補償5〇4與緩衝增益5〇6功能端賴後級放大與 補偏電路而定，當社重要_參數均調為使得影像感嶋組觀測單辦 段溫區背景下，原始影像訊號在顯示螢幕為灰階層次。 同時’以讀1§繼續監測影像輸丨端訊號，使其顯示出對溫度變化 較大之動態值，此顯像處理系統電路板（Vide〇 p職ssing加㈣汹 中’也設計具有訊號類比/數位轉換514、訊號資料處理儲存與介面控制 516、可程式型時序内建518、可程式電源供應電路52〇，而主時序也可絲由 VME bus傳輸鏈由電腦供給’整個控制指令與影像訊號輸出架構也可由防咖 介面，連結主控電腦中控制處理點22之阶I/F介面卡作為指令（ 與M)功能。織再裝置紅外線光學鏡頭至感測模組前焦距處（f#介於) 1. 5〜3· 5) ’熱影像整合測試（含光機系統）驗證5〇進行調制參數微調，最 後進行低溫與高溫區段兩點影像訊號線性補償，以校正其動態影像均勾度。 請參閱第五圖，其為本發明之立體圖。如圖所示，然而，影像調^程 序几成後，便確㉙完成紅外線熱影像陣賴組製作中，焦面感測陣列之焦 平面陣列與訊號讀出積體電路模組是域測模組背面接光圓雄收紅外 線光訊號8G2，讀域體電路讀取電路晶㈣8是以喊讀出積體電 路上光電流輸人端806，藉由銦㈣合方式魅域鱗狀辭面陣列接 合’每_單元⑽光電猶存至積分電容翻訊賴由耶順行多工器 812依序純號輸㈣814送至制驗衝板模組524錢像處理***電路 模組526内進行影像訊號處理等程序；低溫操作之鮮面陣列魏制冷器控 制溫度介於4(Μ5_)·5Κ，縣内部真空勤介於1GE_5|2耐:間， 經兩點均⑽祕品質爾後鄕縣面均皱观，F__檢單福 作率>95%，最後便完成一組熱影像模組雛型6〇。 ' 綜上所述，本發明之紅外線熱影像陣列模組驗證架構與製造方法，其 包含有熱絲減格輯、I晶與光學物性驗證，須先進行蠢晶參數校正； 其在感測波段湘短、中、長紅外線吸收波段；合格後，進行單乙型感測 元件製程與變溫光«測驗證，妓晶完成感測元件以低溫變溫與變壓量 200820431 ，卩卩繼例物邮細_證，進 =暗，均物収，不合格則返回熱像模組規格 麟重Γ證；合格後，繼續進行職平面_與《如積體祕占1 模組與訊號讀出積體電路進行銦貼合轉換 =',酬树、平轉顺觀紅糊細簡驗證。 輸出參數分析與測定；不;;證’調制最佳驅動與控制 別 、、員進仃δ亥熱影像陣列模組雛型，# _^貼=與鮮__接合，完成飾断顺_型。’、 本㈣係貫為-具有新穎性、進步性及可供產業利用者，應符 1利法所規定之專利申請要件無疑’爰依法提出發 ^ 口 ^ 早日賜准專利，至感為禱。 Τ月祈鈞局 明士二述：’僅為本發明之’佳實施例而已’並非用來限定本笋 f㈣’舉凡依本發”請專利範圍所述之形狀、構造、特徵2 神所為之均等變化與修飾，均應包括於本發明之㈣專利範_。 1 【圖式簡單說明】 ，-圖為本發明之紅外線熱影像陣順組之流程圖； 2—圖（a)為本發明之紅外線熱影像陣列模組之架構圖； I圖、b)為本發明之紅外線熱影像陣列模組之架構圖； ★第三圖為本發明之紅外線熱影像_模組之平面圖； f四圖為本發明之紅外線熱影像_模組之方塊圖；及 第五圖為本發明之紅外線熱影像陣列模組之立體圖。 【主要元件符號說明】 10 熱像模組規格設計、磊晶與光學物性驗證 200820431 20 單乙型感測元件製程與變溫光電量測驗證 30 焦平面陣列製程及其光電均勻度驗證 40 焦平面陣列與訊號讀出積體電路貼合與磨薄製程驗證 50 影像整合測試（含光機系統）驗證 60 熱影像陣列模組雛型完成 102 模組紅外線穿透基板 104 底端高摻雜接觸層 106 紅外線吸收層 108 本質層 110 能障阻擋層 112 頂端高雜質摻雜接觸層 114 上電極區 116 感測元件表面絕緣彼覆層 118 銦柱 1010 下電極區 1012 輸出致能P-MOSFET電晶體 1014 輸出與復置切換P-MOSFET電晶體 、 1016 調整感測元件偏壓P-MOSFET電晶體 1018 復置致能N-MOSFET電晶體 1020 積分電容 1022 選擇致能端點 1024 偏壓注入端點 1026 復置端點 1028 負端端點 1030 訊號輸出端 412 注入單元 15 200820431 414 行多工器 416 列多工器 418 行取樣保持與放大電路單元 420 時序生成單元 422 時序生成控制單元 424 線時序 426 主時序 428 行選擇淳 2110行復置埠 2111列選擇琿 2112列復置埠 2113 A通道輸出端 2114 B通道輸出端 70 通道輸出端點 72 偏壓與電源端點 74 時序端點 76 晶片溫度感測二極體輸出端點 78 測試感測輸出模組端點 502 低溫真空致冷腔 524 感測器緩衝板模組 504 訊號轉阻放大與補償 506 緩衝增益功能 508 影像晶片核組時序與偏Μ驅動核組 510 時序生成模組 512 偏壓建立模組 526 影像處理電路模組 514 類比數位轉換電路 16 200820431 516 518 520 522 802 804 806 808 810 812 814 輸出影像資料訊號處理與控制電路 可程式時脈生成電路 可程式電源供應電路 控制處理器 紅外光訊號射入 感測模組背面接光區 訊號讀出積體電路上之光電流輸入端 訊號讀出積體電路之言買取電路晶片 列多工器 行多工器 訊號輸出端 17Dehui t〇n, PECVD) (substrate temperature between coffee ~ 5 _), photochemical deposition (ρι_ Vapor Depositor!, PVD) (substrate temperature between 8 〇 ~ 2 〇 (rc), ion sputtering (usually used) He, Ar ion blunt gas), or heating steaming method, oxygen cutting (10) X) or nitriding (SiNx), as the surface coating layer 116 of the sensing element, the thickness is between % and GI, and then chemical Reactive IQn Etching (RIE) or wet side method (hydrogen fluoride: Deionization [Buffer HF: DI water: Bu 5:20) defines the semiconductor contact metal region, and such sensing elements are on the 114 and lower 1010 electrodes. Contact metal material used in the area, if it is N type can be Ji (10)) 1 ~ 20nm / chromium (Cr) 1 ~ 20nm / gold-bismuth alloy (Au / Ge) 50 ~ 3 (10) nm / gold (Au) 5 〇 3 〇〇 〇〇 , P type can be palladium (Pd) 1~20nm / chromium (Cr) 1~20nm / gold bismuth alloy (Au / @e) or zinc (Zn) 50 ~ 300 and / gold (Au) 50 ~ 300nm, can be used Hot steaming, electronic grabbing, warming steam or ion _ for metal electrode fabrication. The Rapid Thermal Annealing (RTA) process is formed by the ohmic contact between the preferred semiconductor and the metal. The temperature and time of the heating are between 35〇5〇〇, 15~6〇Sec, and the temperature gradient is 1 〇〇~2 (TC/Sec. If the sensing device area process is defined for the platform type (Mesa), in addition to using the mask development to define the etched area, the etched area depth must exceed 1/3~1 of the thickness of the lower highly doped polarity region. Between /2, the rest of the process is the same in the plane. In the case of the quantity = well sensing component _ process, the gradual grating structure must be added after the platform-type sensible component area process, and its structure is 1 dimension long strip Or 2D square or diamond shape, grating spacing and height 200820431 Between 5//m and 1〇~5_ιι The side method is the same as the platform type defined area. The above is the main type of single sensing element process. The purpose of the step is to be ashamed of the process parameters as a reference parameter for the fabrication of the focal plane array structure. / After completing the single-type sensing element structure, the thermal conductive adhesive is applied to the test insulating base (eg, seat), The lower signal end of the gold wire is taken out, placed in a circulating liquid nitrogen low temperature change 2 cavity, and then the terminal pin signal line is exported through the feed line (feedthr〇ugh) interface via the coaxial wire or the low noise signal line. The dark current, dark resistance, and response spectrum are measured by low temperature variable temperature and variable pressure measurement (for example, FTIR spectrum analyzer · · incident light source, Fourier frequency domain ^ 矣 to obtain Wei spectrum distribution; Jianxun electric hexagram: conduct Lai Shape, signal sense and gain release), detection degree correction (such as: black body radiation source: correction 叮 (7) light source intensity; lock-in amplifier: synchronous adjustment k photoelectric heterogeneous voltage 峨 Na), after the above photoelectric physical parameters measurement After verification, the specifications of the right parts, such as: signal noise ratio, optical response band, soundness, debt inspection, dark current, dark differential resistance, and the same film sensing stray chip 3/ 4~4/5 wafer: the product uses the array type reticle. After the shell, directly perform the fresh face array listening process, with the uniformity of the line width error per unit touch unit <10%, the total photocurrent uniformity of the light transfer towel >75%, and the production process makes the single-type parameter For the main array production, and finally; ^ test area for dark current uniformity test 13, if the use of low energy gap sensing materials made of sensing _, such as recorded indium, mercury, must be in the sensing array The surface is grown by means of plasma, ultraviolet light-assisted vapor deposition, or vacuum deposition, such as: passivation layer such as oxidized stone or nitrite (thickness is between 5〇.~3〇〇) Or spin coating the polymer layer (between Q 5 and the thickness) on the array layer, the main purpose is to prevent the surface from being infiltrated by external moisture or contaminants, causing the surface impurity level to increase to form a lateral dark Current, which affects the quality of the sensing. Confused with reference to the second figure (b), which is the architectural diagram of the present invention. As can be seen from the figure, the indium pillars 118 are grown on the upper and lower metal electrode ends (the height is between 3 and 12, and the bottom area is smaller than the metal electrode region). The compressive stress and the flat plate heating method are used (the temperature is between 9 G and 〜 · C), in the instant of reaching the near melting point of the steel shovel, indium bonding with the signal reading integrated circuit, and then performing the potting curing process (such as · Pnl ^ signal reading integrated circuit structure) ^ 中 brib hydrate negative) 'and complete the complete focal plane array and read the integrated circuit single-wire job record _ fresh surface array and signal conversion' its architecture for each pixel unit pair library =: first Capacitance resistance amplification injection into the signal _;, money, people, gate modulation, column sensing component architecture and signal reading = / hope to increase the use of focal plane matrix to achieve the purpose of the reduction group Hat degree, and moderate release of the grinding process in the potting process, 'first the sensing element array and the signal reading integrated circuit surname: C mi it s ' to the new 8~12 small day turn over the organic solution residual fresh noodles _Amount "on the light barrier and = face after taking small" and see the third picture, similar For example, a single-type sensing wafer is first placed on a fine-footed wire holder. The wiring on the pedestal is connected to the Wei Cai-style office in the 隹^ and the signal-sensing readout integrated circuit in the sense conversion output signal 7〇, power signal 72, clock = heart drive weaver output I / _ # b74, operating temperature Check the _ number of the secondary diode signal, see the fourth figure, which is a block diagram of the present invention. It can be seen from the figure that after completion, the 5G2' in the cold body of the temperature system is first subjected to the timing driver 51G, and the purpose is to supply the normal working state of the focal plane array to maintain the normal operation mode of the output signal. The digital analogy is used to intercept the image analogy in the sensor buffer board module (S_r Buffer B〇ard) 524 to confirm the required output signal specification. Before 'testing the focal plane array at room temperature and the number of the integrated circuit circuit to block the resistance signal screen, the purpose is to understand the joint condition, and then set the temperature to the appropriate temperature of the infrared thermal image array to be verified. This operating temperature is between 40 and 3 凯 absolute Kelvin temperature. When the temperature is at this set temperature for about at least 15 minutes, the input voltage adjustment 512 is adjusted, and the machine is connected across the absolute side of the biasing element of the sensing element 8 between 黯 and 4V; The integration time in the integrated circuit is read to be between ι〇(4)c and 12200820431 32msec; the signal transimpedance amplification and compensation 5〇4 and the buffer gain 5〇6 function depend on the post-amplification and complementing circuit, The important _ parameters of the agency are adjusted so that the original image signal is displayed in the background of the temperature range of the image sensing group. At the same time, 'reading 1 § continues to monitor the image transmission end signal to show the dynamic value of the temperature change. The imaging processing system board (Vide〇p job ssing plus (4) 汹中' is also designed with signal analogy / digital conversion 514, signal data processing and interface control 516, programmable timing built-in 518, programmable power supply circuit 52, and the main timing can also be supplied by the computer from the VME bus transmission chain 'entire control command and image The signal output architecture can also be used as an instruction (and M) function by connecting the I/F interface card of the control processing point 22 in the main control computer. The ray re-installation infrared optical lens to the front focal length of the sensing module (f#介于) 1. 5~3· 5) 'The thermal image integration test (including the optical system) verifies 5〇 to fine-tune the modulation parameters, and finally linearly compensates the two-point image signal in the low temperature and high temperature sections to correct the dynamic image degree. Please refer to the fifth figure, which is a perspective view of the present invention. As shown in the figure, however, after the image adjustment process is completed, the infrared thermal image array is completed. The focal plane array and the signal readout integrated circuit module of the focal plane sensing array are domain-testing. The back side of the group receives the infrared light signal 8G2, and the read domain circuit reads the circuit crystal (4). 8 is to read the photocurrent input terminal 806 on the integrated circuit, and the infra-red (four) combination mode is used. Bonding 'Every _ unit (10) photoelectric still stored to the integral capacitor splicing Lai yue shun multiplexer 812 in order to send the pure number (four) 814 to the inspection plate module 524 money processing system circuit module 526 for video signals Processing and other procedures; low temperature operation of the fresh surface array Wei refrigerator control temperature is between 4 (Μ5_)·5Κ, the county internal vacuum is between 1GE_5|2 resistance: between, after two points (10) secret quality, then the county is wrinkled View, F__ check the rate of good work > 95%, and finally complete a set of thermal imaging module prototype 6 〇. In summary, the infrared thermal image array module verification architecture and manufacturing method of the present invention includes a hot wire subtractive series, I crystal and optical physical property verification, and must be first corrected for stray crystal parameters; The short, medium and long infrared absorption bands of Xiang; after passing the test, the process of single-type sensing element and the variable temperature light are measured and verified, and the sensing element is finished with low temperature and variable pressure. 200820431 _ card, enter = dark, average receipt, if it is unqualified, return to the thermal image module specification Lin heavy Γ certificate; after passing, continue to work plane _ and "such as the accumulation of secrets 1 module and signal reading integrated circuit Indium bonding conversion = ', reward tree, flat turn and red paste simple verification. Output parameter analysis and measurement; no;; proof 'modulation of the best drive and control,, member of the 仃 亥 亥 热 影像 影像 image array module, # _ ^ paste = with fresh __ joint, complete the cut _ type . ', this (four) is consistent - has novelty, progressive and available for industrial use, should be in accordance with the provisions of the patent application requirements of the law, undoubtedly '爰 提出 提出 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ . Τ月钧钧局明士二述: 'Only the 'best embodiment of the present invention' is not intended to limit the shape, structure, and characteristics of the bamboo shooter f (four) ' 凡 凡 according to the scope of the patent. Equivalent changes and modifications shall be included in the (4) patent model of the present invention. 1 [Simple description of the drawing], - Figure is a flow chart of the infrared thermal imaging array of the present invention; 2 - Figure (a) is the present invention The architecture diagram of the infrared thermal image array module; I diagram, b) is the architecture diagram of the infrared thermal image array module of the present invention; ★ the third diagram is the plan view of the infrared thermal image_module of the present invention; The block diagram of the infrared thermal image_module of the present invention; and the fifth figure is a perspective view of the infrared thermal image array module of the present invention. [Description of main component symbols] 10 thermal image module specification design, epitaxy and optical properties Verification 200820431 20 Single-B type sensing component process and variable-temperature photoelectric measurement verification 30 Focal plane array process and its photoelectric uniformity verification 40 Focal plane array and signal reading integrated circuit bonding and thinning process verification 50 Image integration test (including optical system) verification 60 thermal image array module prototype complete 102 module infrared penetrating substrate 104 bottom high doped contact layer 106 infrared absorption layer 108 intrinsic layer 110 energy barrier layer 112 top high impurity doping contact Layer 114 Upper electrode region 116 Sensing element surface insulation coating 118 Indium pillar 1010 Lower electrode region 1012 Output enabled P-MOSFET transistor 1014 Output and reset switching P-MOSFET transistor, 1016 Adjusting sensing component bias P - MOSFET transistor 1018 reset enable N-MOSFET transistor 1020 integrating capacitor 1022 select enable terminal 1024 bias injection terminal 1026 reset terminal 1028 negative terminal 1030 signal output 412 injection unit 15 200820431 414 row Multiplexer 416 column multiplexer 418 row sample hold and amplify circuit unit 420 timing generation unit 422 timing generation control unit 424 line timing 426 main timing 428 row selection 淳 2110 row reset 埠 2111 column selection 珲 2112 column reset 埠 2113 A channel output 2114 B channel output 70 channel output terminal 72 bias and power supply terminal 74 timing end point 76 wafer temperature sensing diode Output Endpoint 78 Test Sensing Output Module Endpoint 502 Low Temperature Vacuum Cooling Chamber 524 Sensor Buffer Board Module 504 Signal Transimpedance Amplification and Compensation 506 Buffer Gain Function 508 Image Chip Core Group Timing and Hemiplegic Drive Core Set 510 Timing generation module 512 bias generation module 526 image processing circuit module 514 analog digital conversion circuit 16 200820431 516 518 520 522 802 804 806 808 810 812 814 output image data processing and control circuit programmable clock generation circuit programmable Power supply circuit control processor infrared light signal injection sensing module back light receiving area signal reading integrated circuit on the optical current input terminal signal reading integrated circuit words buy circuit chip array multiplexer row multiplexer Signal output 17