TW200816207A

TW200816207A - Memory circuits and malfunction protection methods thereof

Info

Publication number: TW200816207A
Application number: TW96135125A
Authority: TW
Inventors: Che-Yuan Jao
Original assignee: Mediatek Inc
Priority date: 2006-09-21
Filing date: 2007-09-20
Publication date: 2008-04-01
Also published as: CN101149975A; CN101149975B; TWI344152B

Abstract

Memory circuits capable of preventing false programming caused by power-up sequence are provided, in which a programmable unit comprises a plurality of programmable elements, a source bus coupled between an external programming voltage and the programmable elements, a switching unit connected between the external programming voltage and the source bus, comprising a control terminal, and a level shifter, shifting a voltage level of an enabling signal to a first power voltage from a second power voltage lower than the external programming voltage. When the second power voltage is not ready during power up, the level shifter sets the control terminal of the switching unit to a predetermined logic level such that the switching unit is turned off and the source bus is disconnected from the external programming voltage thereby preventing false programming.

Description

200816207 . 九、發明說明：【發明所屬之技術領域】本發明有關於一種記憶體電路’特別有關一種記憶體電路能夠避免由於電源啟動順序（P〇wer_up sequence) 導致的錯誤燒錄（false programming)。【先前技術】熔絲元件係廣泛地使用於半導體裝置中，用以記錄 f、晶片編號或序號。一般而言，為了將熔絲元件與半導體裝置中其它元件斷開，每個熔絲元件都會包含一個能夠被燒斷（即斷路）的熔絲。舉例而言，熔絲可以藉由雷射來照射直到它被斷路，或者藉由一個能夠散發足夠熱度的過電流來將其熔斷。藉由過電流將熔絲斷路與使用雷射不同，其甚至可以在半導體裝置被封裝後才執行，通常被稱作電燒錄（或電程式化；electrically programming)溶絲。此外，容許這種燒錄方式的熔絲係稱為電可燒錄熔 ( 絲或電可程式化溶絲，或簡稱為e-fuse，並且大部分的熔絲只能被燒錄一次，用以提供對應於高低阻抗狀態的狀態〇與狀態1，反者亦反。【發明内容】本發明係提供一種記憶體電路，包括一可燒錄單元、一開關元件以及位準調整器。可燒錄單元包括複數可燒錄元件；以及一電源匯流排，柄接於一外部燒錄電壓與可燒錄元件之間；一開關元件，連接於外部燒錄電 0758-A3255 lTWF;MTKI-06-358;yens 6 200816207 -塵與電源匯流排能信號的電壓位準1 位準調整器’用以將-致電虔，苴中；；由一弟二電源電壓調整至-第-電源、盾私着/、琶源電壓低於外部燒錄電壓，祐曰A币 :=過程中第二電源㈣尚未備妥時，位準:周」： 1=::之控制端設置於-既定邏輯位準，;吏；：疋件被截止，並且電卡使仔開關 -^ ^ ^ „ (faIse σ: ^ ^ 元，^電路，包括—電源供應單括複數可燒錄元件，二二二及一可燒錄單元，包電路，用以燒錄可㈣1 流排；以及一燒錄動器，接至可燒錄二及亚ΐ燒錄電路包括複數驅一第-電源電麼所供ΐ。;及:弟一位準調整器由至少電壓，當電源啟動、晶ρ Λ #迅源電壓係低於外部燒錄 /隹 k矛壬中第一電源電壓尚未備委日士筮 :位:調整器係將其輪出端設置=:、二弟準，使得燒錄電路中之驅^ 2疋邏輯位避免錯誤燒錄。 θ被不此（disabled)，以便本發明亦提供—種記憶體其令記憶體電路係包括複數、動：：護方法，及—感測電路，莩動柞 70 % 70牛、一 k錄電路以可燒錄元件與一外整器用以耦接至開關元件：：之間’6又置-弟-位準調過程中第二電源電摩尚未：f制：；以及當電源啟動設置於-第—邏輯位〜’將開關兀件之控制端位準，使得開關元件被截止，並且電〇758.A32551TWF;MTKI-〇6.358· yens 200816207 . 源匯流排會與外部燒錄電壓斷開。本發明亦提供一種誤動作保護方法，其包括當一核心電壓尚未備妥時，切斷來自可燒錄元件之一外部燒錄電壓。並且當上述核心電壓備妥時，根據一致能信號控制上述外部燒錄電壓和上述可燒錄元件間之連結。為了讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉一較佳實施例，並配合所附圖示，作詳細說明如下： f K : 【實施方式】第1圖係為一記憶體電路之一實施例。如圖所示，記憶體電路100包括一電可燒錄單元11〇(例如e-fuse bank)、一感測電路112以及一燒錄電路114。電可燒錄單元110包括複數熔絲元件，並且每一個熔絲元件具有用以被燒斷的熔絲（即Rf〇、Rfl〜Rfn)以及用以作為電流源的NMOS電晶體（即TO、T1〜Τη)。熔絲RfO〜Rfn係可、為自對準石夕化物之覆晶電阻（salicide polysilicon resistor)，而MOS電晶體TO〜Τη係可為薄閘極裝置（thin gate device)或厚閘極裝置（thick gate device)。參考熔絲 Rref亦耦接至感測電路112,用以區別未燒斷的熔絲與燒斷的熔絲。感測電路112係藉由欲感測的位址ADD<0:n> 以及一讀取致能信號RE，啟動讀取的動作並輸出比較後的資料 DATA<0:n>。燒錄電路114係措由欲燒錄的位址ADD<0:n〉J^及 0758-A32551TWF;MTKI-06-358;yens 8 200816207 一燒錄致能信號PE，燒錄電可燒錄單元110中對應之熔絲。熔絲RfO〜Rfn皆藉由一電源匯流排111以及一電阻 RP，耦接至一外部燒錄電壓EPS，例如一熔絲電源（fuse source)或一電源電壓。由於在燒錄過程中需要穩定且穩態的電流，因此由外部燒錄電壓EPS到電源匯流4非111 之電流路徑的電阻值要保持在儘可能的低。若電流源（即 NMOS電晶體T0〜Τη)皆由電壓輸入/輸出裝置（即厚閘極裝置）所實現，感測電路112與燒錄電路114則可能需要使用多個電源電壓以及能夠將核心電源位準信號轉換成輸入/輸入電源位準信號的複數位準調整器。第2圖係為一感測電路之一實施例。如圖所示，感測電路112包括複數個位準調整器（統稱LS12)、複數及閘AG00〜AGOn以及複數感測器SA0〜SAn。位準調.整器 LS12係耦接至一核心電源電壓VDD_CORE以及一輸入/ 輸出（I/O)電源電壓VDD_IO，用以將欲感測的位址 ADD<0:n>以及讀取致能信號RE，由核心電源電壓位準的信號調整至I/O電源電壓位準的信號。感測器 SA0〜SAn各耦接至一對應之熔絲以及參考熔絲Rref，而及閘AG00〜AGOn係用以根據位址ADD<0:n>，驅動感測器SA0〜San，藉以輸出比較後的資料。第3圖係為一燒錄電路之一實施例。如圖所示，燒錄電路114包括複數個位準調整器（統稱LS14)以及複數及閘AGIO〜AGln。位準調整器LS14係耦接至一核心電源電壓VDD—CORE以及一輸入/輸出（I/O)電源電壓 075 8-A3 25 51TWF;MTKI-06-3 5 8 ;yens 9 200816207 VDD—ΙΟ，用以將欲燒錄的位址ADD<0:n>以及燒錄致能信號PE，由核心電源電壓位準的信號調整成I/O電源電壓位準的信號。每個及閘AGIO〜AGln係作為一驅動器，並且連接一對應之熔絲以及參考熔絲Rref。當接吹到來自位準調整器LS14之燒錄致能信號PE時，及閑 AGIO〜AGln係根據位址ADD<0:n>將溶絲燒斷。然而，若使用串接的電源調整器（regulator)，將报有可能產生如第4圖中所示之電源啟動順序。舉例而言，200816207. IX. Description of the Invention: [Technical Field] The present invention relates to a memory circuit that is particularly related to a memory circuit capable of avoiding false programming due to a power-up sequence (P〇wer_up sequence) . [Prior Art] Fuse elements are widely used in semiconductor devices for recording f, wafer number or serial number. In general, in order to disconnect a fuse element from other elements in a semiconductor device, each fuse element will contain a fuse that can be blown (i.e., broken). For example, the fuse can be illuminated by a laser until it is broken, or it is blown by an overcurrent that is capable of dissipating sufficient heat. Breaking the fuse by overcurrent is different from using a laser, which can even be performed after the semiconductor device is packaged, commonly referred to as electrically programmed (solving). In addition, the fuse that allows this burning method is called electric burnable melting (filament or electrically programmable melting wire, or simply e-fuse, and most of the fuse can only be burned once, with The present invention provides a memory circuit including a programmable unit, a switching element, and a level adjuster. The recording unit includes a plurality of combinable components; and a power bus bar, the handle is connected between an external programming voltage and the recordable component; and a switching component is connected to the external programming power 0758-A3255 lTWF; MTKI-06- 358;yens 6 200816207 -The voltage level of the dust and power busbar signal level 1 level adjuster' is used to - call 虔, 苴中;; adjust the power supply voltage from one brother to the second - power supply, shield private /, 琶 source voltage is lower than the external programming voltage, 曰曰 A currency: = in the process when the second power supply (four) is not ready, level: week": 1 =:: the control terminal is set at - the established logic level, ;吏;: The condition is cut off, and the card is turned on -^ ^ ^ „ (faIse σ: ^ ^ Yuan, ^ circuit, including - power supply unit including a plurality of combustible components, 22 and a programmable unit, packet circuit for burning (4) 1 stream row; and a burning recorder, connected to burnable Recorded two and Aachen programming circuits include a multi-driver-first power supply.; and: a bit of a quasi-regulator consists of at least voltage, when the power is activated, crystal Λ 迅 #迅源电压系 is lower than external burning Recording / 隹k spears in the first power supply voltage has not been prepared for the Japanese 筮筮: bit: adjuster is set to its wheel end =:, second brother, so that the drive circuit in the programming circuit 2 疋 logic bit to avoid errors θ is disabled, so that the present invention also provides a memory for the memory circuit including complex, dynamic: protection method, and - sensing circuit, 柞 70% 70 cattle, one The k-recording circuit is coupled to the switching element by a burnable component and an external device:: the second power supply during the '6-set-different-bit calibration process has not yet been: f system:; and when the power is turned on Set to - the - logic bit ~ 'the control terminal level of the switch element, so that the switching element is cut off, and the electricity 758.A32551TWF; MTKI-〇6.358· yens 200816207. The source busbar is disconnected from the external programming voltage. The present invention also provides a method of malfunction protection, which includes cutting off the burnable when a core voltage is not ready. One of the components externally burns the voltage, and when the core voltage is ready, the connection between the external programming voltage and the flammable component is controlled according to a uniform energy signal. To achieve the above and other objects, features, and The advantages can be more clearly understood. A preferred embodiment will be described below in detail with reference to the accompanying drawings. f K : [Embodiment] FIG. 1 is an embodiment of a memory circuit. As shown, the memory circuit 100 includes an electrically recordable unit 11 (eg, an e-fuse bank), a sensing circuit 112, and a programming circuit 114. The electrically recordable unit 110 includes a plurality of fuse elements, and each of the fuse elements has a fuse to be blown (ie, Rf 〇, Rfl 〜 Rfn) and an NMOS transistor (ie, TO, used as a current source). T1 ~ Τη). The fuses RfO~Rfn can be self-aligned salicide polysilicon resistors, and the MOS transistors TO~Τ can be thin gate devices or thick gate devices (thin gate devices) Thick gate device). The reference fuse Rref is also coupled to the sensing circuit 112 for distinguishing between the unbaked fuse and the blown fuse. The sensing circuit 112 starts the reading operation and outputs the compared data DATA<0:n> by the address ADD<0:n> to be sensed and a read enable signal RE. The programming circuit 114 is determined by the address to be burned ADD<0:n>J^ and 0758-A32551TWF; MTKI-06-358; yens 8 200816207, a burn-in enable signal PE, and a burnable electric burnable unit The corresponding fuse in 110. The fuses RfO Rfn are coupled to an external programming voltage EPS, such as a fuse source or a power supply voltage, via a power bus bar 111 and a resistor RP. Since a stable and steady current is required during the programming process, the resistance value of the current path from the external programming voltage EPS to the power supply sink 4 is kept as low as possible. If the current sources (ie, NMOS transistors T0~Τη) are implemented by voltage input/output devices (ie, thick gate devices), sensing circuit 112 and programming circuit 114 may require multiple supply voltages and the ability to The power level signal is converted into a complex level regulator of the input/output power level signal. Figure 2 is an embodiment of a sensing circuit. As shown, the sensing circuit 112 includes a plurality of level adjusters (collectively LS12), complex and gates AG00~AGOn, and complex sensors SA0~SAn. The LS12 is coupled to a core supply voltage VDD_CORE and an input/output (I/O) supply voltage VDD_IO for the address to be sensed ADD<0:n> and read enable Signal RE, a signal that is adjusted to the I/O supply voltage level by a signal at the core supply voltage level. The sensors SA0~SAn are each coupled to a corresponding fuse and a reference fuse Rref, and the gates AG00~AGOn are used to drive the sensors SA0~San according to the address ADD<0:n> Comparative information. Figure 3 is an embodiment of a programming circuit. As shown, the programming circuit 114 includes a plurality of level adjusters (collectively referred to as LS14) and a complex AND gate AGIO~AGln. The level adjuster LS14 is coupled to a core power supply voltage VDD_CORE and an input/output (I/O) power supply voltage 075 8-A3 25 51TWF; MTKI-06-3 5 8 ; yens 9 200816207 VDD-ΙΟ, The signal ADD<0:n> to be burned and the burn enable signal PE are used to adjust the signal of the core power supply voltage level to the signal of the I/O power supply voltage level. Each of the gates AGIO~AGln serves as a driver and is connected to a corresponding fuse and a reference fuse Rref. When the burn-in enable signal PE from the level adjuster LS14 is received, the idle AGIO~AGln is blown according to the address ADD<0:n>. However, if a serial power regulator is used, it is possible to generate a power-on sequence as shown in Fig. 4. For example,

電源電壓VDD—IO(例如3.3V)係超前於外部燒錄電墨 EPS(例如2·5ν)以及核心電源電壓VDD一CORE(例如 1.0V)。因此，當I/O電源電壓VDD—10備妥（ready)時，核心電源電壓VDD一CORE還是無效的（尚未備妥），此日卞外部燒錄電壓EPS可為任何值，使得在週期τΐ中電可焯錄單元110係處於一個未知的狀態。此情況將可能導致未預期或錯誤的燒錄動作。於某些實施例中，可燒錄單元110中之NMOS電曰曰體（即T0〜Τη)係由薄閘極裝置所實現，所以感測電路與燒錄電路114只需要核心電源電壓VDD一CORE，故其位準調整器皆可以略除。然而，此等實施例仍然需要維持外部燒錄電壓EPS與核心電源電壓VDD一CORE的電场啟始順序，使得核心電源電壓VDD—CORE必須比外部捧錄電壓EPS更早備妥（ready)，以避免未預期或錯誤锋= 的動作。為了避免這些情況，本發明更提供一些能夠避免未 0758-A32551TWF;MTKI-06-358;yens 10 200816207 - 預期或錯誤燒錄的動作之記憶體電路的實施例。第5圖係為一記憶體電路之另一實施例。如圖所示，記憶體電路100”包括一電可燒錄單元110”、一感測電路112”、一燒錄電路114”、一開關元件116、一位準調整器LS16、一靜電放電（ESD)保護電路118、一電源供應單元120以及一電阻RP，，。舉例而言，記憶體電路1〇〇，，係可為非易失性記憶體、電可燒錄記憶體（electrical programmable memory)、一次燒錄唯讀記憶體（once time 〔 programmable read only memory ; OTP ROM)，但不限定於此。電源供應單元120用以提供外部燒錄電壓EPS(例如一熔絲電源或一電源電壓）至電可燒錄單元11〇”。電可燒錄單元110”係包括複數熔絲元件，每個熔絲元件包括一個用以被燒斷之炼絲（例如RfO、Rf 1〜Rfn)以及一個作為電流源之NM0S電晶體（例如TO、T1〜Τη)。舉例而言，炼絲RfO〜Rfn係可為自對準石夕化物之覆晶電阻（salicide polysilicon resistor)，而 MOS 電晶體 T0〜Τη ‘ 係可為薄閘極裝置（thin gate device)或厚閘極裝置（thick gate device)。參考熔絲Rref亦耦接至感測電路}丨2”，用以區別未燒斷的熔絲與燒斷的熔絲，並且溶絲Rf〇〜Rfn 和Rref是透過一電源匯流排111”和電阻Rp”連接到一外部燒錄電壓EPS。電可燒錄單元110”係可為一非易失性且電可燒錄的單元，例如e-fuse bank、快閃記憶體、一次燒錄型記憶單元，但不限定於此。感測電路112”與燒錄電路114”係與第2圖、第3圖 0758-A3255 lTWF;MTKI-06-358;yens 11 200816207 -中所示之感測電路112與燒錄電路114相似，差别在於當包源啟動過程中核心電源電壓vdD-C〇re尚未備妥日才位準凋整為LS17與LS18能夠將其輸出端設置於— 既疋邏輯位準’使得感測電路112，，中之感測器SA〇〜SAn 與燒錄包路114’中之驅動器皆會被禁能（以祕⑷。舉例而言，位準調整器LS17係耦接於讀取致能信唬RE與感測電路112”之及閘AG〇〇〜AG〇n之間，用以當電源啟動過程中核心電源電壓VDD_c〇RE尚未備妥 <日守’將及閘AG〇〇〜AGOn之輸入端皆設置到一既定邏輯位準’使得感測電路112”之感測器sa〇〜SAn都會被禁能，以便避免電源啟始順序導致錯誤的讀取動作。類似地，位準調整器LS18係耦接於燒錄致能信號pE與燒錄電路 114”之及閘AGIO〜AGln之間，用以當電源啟動過程中核心電源電壓VDD一CORE尚未備妥時，將及閘ag 10〜AG 1 η 之輸入端皆設置到一既定邏輯位準，使得燒錄電路114，，，會被禁能，以便避免電源啟始順序導致錯誤的燒錄動作。反a之’當I/O電源電壓VDD_IO與核心電源電壓乂00」301^皆備妥時，位準調整器1^16〜1^18係用以將外部燒錄電壓致能信號EPSJEN、讀取致能信號rE以及燒錄致能信號PE由核心電源電壓位準的信號調整至輸入輸出電源電壓位準的信號，以便分別控制開關元件 116、感測電路112”中之感測器SA0〜SAn以及燒錄電路 114”中之及閘AGIO〜AGln(即驅動器）。要注意的是，當電可燒錄單元110”中之NMOS電晶 0758-A3255 lTWF;MTKI-06-358;yens 12 200816207 - 體TO〜Τη係由厚閘極裝置（I/O裝置）所實現時，則需要一組位準調整器LS17，用以調整感測電路112”中位址（信號）八00<0:!1>與讀取致能信號RE。同樣地，需要一組位準調整器LS18，用以調整燒錄電路114”中位址（信號）八00<0:!1>與燒錄致能信號PE。開關元件116係耦接於外部燒錄電壓EPS與電阻 RP”之間，用以根據位準調整器LS16之輸出，選擇性地將外部燒錄電壓EPS與電源匯流排111”斷開。舉例而 f 言，開關元件116係可為主動元件，例如MOS電晶體、雙載子電晶體（BJT)、接面場效型電晶體（JFET)，但不限定於此。位準調整器LS16係耦接於外部燒錄電壓致能信號 EPS_EN與開關元件116之控制端之間，用以選擇性地將外部電源電壓EPS與電可燒錄單元110”斷開。舉例而言，當I/O電源電壓VDD_IO與核心電源電壓VDD—CORE 皆備妥(ready)時，位準調整器LS16係用以將外部燒錄電 I 壓致能信號EPS_EN由核心電源電壓位準的信號調整至輸入輸出電源電壓位準的信號，以便控制開關元件116 連接外部燒錄電壓EPS至電可燒錄單元110”，俾以對電可燒錄單元110”進行燒錄或感測（讀取）。反言之，當電源啟動過程中核心電源電麼VDD_CORE尚未備女時’位準調整器LS16會將開關元件116之控制端設置至一既定邏輯位準，使得開關元件116會截止，所以電可燒錄單元110”中之電源匯流排111”會與外部燒錄電壓EPS斷 075 8-A325 51 TWF;MTKI-06-3 5 8 ;yens 13 200816207 ，開，藉以避免錯誤的燒錄動作。舉例而言，位準調整器LS 16〜LS18係可藉由交流耦合（AC coupling)、來自一外部電路之一控制信號、藉由一電阻性元件放電或其組合的方式來其輸出端設置於一既定邏輯位準。靜電放電保護電路118係連接開關元件 116與電阻RP”，用以避免靜電放電事件的損害。第6圖係為一位準調整器之一實施例。如圖所示，位準調整器21A係根據一輸入信號IN_C0RE，產生輸出 f 信號0UT_I0與0UTB_I0,並且位準調整器21A包括一第一邏輯單元16、一第二邏輯單元18、兩個驅動器23 與25，以及一反相器INV1。第一邏輯單元16係由I/O 電源電壓VDD_I0所供電，而第二邏輯單元18係由核心電源電壓VDD_C0RE所供電。舉例而言，第一邏輯單元 16係包括一栓鎖單元12以及一差動對14，而第二邏輯單元18包括一反相器INV0，其中栓鎖單元12包括交叉耦接至PM0S電晶體ΜΡ0與MP1，而差動對14包括兩 ( 個NM0S電晶體ΜΝ0與MN1。於某些實施例中，栓鎖單元12亦可包括兩個交叉耦接至反相器。由核心電源電壓VDD_C0RE供電之反相器INV0係用以將輸入信號 IN_C0RE轉換成一反相信號INB+C0RE。在某些實施例中，栓鎖單元12中的電晶體是由薄閘極裝置所實施，而位準調整器21A中的電晶體則是由厚閘極裝置所實施。若輸入信號IN—CORE為高位準時，反相信號 INB_C0RE會為低位準，所以NM0S電晶體ΜΝ0與MN1 0758-A32551TWF;MTKI-06-358;yens 14 200816207 曰刀別為‘通輿截止。當nmos電晶體mno導通時， PMOS包日日歧之閘極會被拉低至接地電壓gND，於是PMOS電尹挪人 . 曰體MPI會接著導通。因此，輸入信號〇υτ ίο 與〇trrft \ 冲— ΤΒ-10會分別為高位準與低位準。此時，即點N1與Ν2係可視為用以輸出輸出信號OUT 10盥〇UTB-IO之輪出端。 —”The power supply voltage VDD-IO (for example, 3.3V) leads the externally-printed ink EPS (for example, 2·5ν) and the core power supply voltage VDD-CORE (for example, 1.0V). Therefore, when the I/O power supply voltage VDD-10 is ready, the core power supply voltage VDD_CORE is still invalid (not yet ready), and the external programming voltage EPS can be any value on this day, so that the period τΐ The CLP recorder unit 110 is in an unknown state. This condition may result in an unexpected or erroneous burning action. In some embodiments, the NMOS capacitors (ie, T0~Τη) in the programmable unit 110 are implemented by a thin gate device, so the sensing circuit and the programming circuit 114 only need the core power supply voltage VDD. CORE, so its level adjuster can be omitted. However, these embodiments still need to maintain the electric field starting sequence of the external programming voltage EPS and the core power supply voltage VDD-CORE, so that the core power supply voltage VDD_CORE must be ready earlier than the external holding voltage EPS, To avoid unexpected or false front = action. In order to avoid these situations, the present invention further provides some embodiments of memory circuits that are capable of avoiding the actions of 0758-A32551TWF; MTKI-06-358; yens 10 200816207 - expected or erroneous programming. Figure 5 is another embodiment of a memory circuit. As shown, the memory circuit 100" includes an electrical burnable unit 110", a sensing circuit 112", a programming circuit 114", a switching element 116, a level regulator LS16, and an electrostatic discharge ( ESD) protection circuit 118, a power supply unit 120, and a resistor RP, . For example, the memory circuit can be a non-volatile memory, an electrically programmable memory, or a read-only memory (once time [programmable read only memory; OTP ROM), but is not limited to this. The power supply unit 120 is configured to provide an external programming voltage EPS (for example, a fuse power supply or a power supply voltage) to the electrically recordable unit 11A. The electrically programmable unit 110 includes a plurality of fuse elements, each of which is melted. The wire member includes a wire for being blown (for example, RfO, Rf 1 to Rfn) and an NMOS transistor (for example, TO, T1 to Τη) as a current source. For example, the RfO~Rfn system can be a salicide polysilicon resistor, and the MOS transistor T0~Τη can be a thin gate device or thick. Thick gate device. The reference fuse Rref is also coupled to the sensing circuit}丨2” for distinguishing between the unblowed fuse and the blown fuse, and the dissolved wires Rf〇 Rfn and Rref are transmitted through a power bus bar 111” and The resistor Rp" is connected to an external programming voltage EPS. The electrically programmable unit 110" can be a non-volatile and electrically recordable unit, such as an e-fuse bank, a flash memory, a single-burning type. Memory unit, but is not limited to this. The sensing circuit 112" and the programming circuit 114" are similar to the sensing circuit 112 shown in FIG. 2, FIG. 3, 0758-A3255, TWF; MTKI-06-358; yens 11 200816207 -, and the programming circuit 112 is similar to the programming circuit 114. The difference is that during the startup of the packet source, the core power supply voltage vdD-C〇re is not ready yet, and the LS17 and LS18 can set their output terminals to the ?? logic level' so that the sensing circuit 112, The driver in the sensor SA〇~SAn and the burnout packet 114' will be disabled (secret (4). For example, the level adjuster LS17 is coupled to the read enable signal RE and Between the sense circuit 112" and the gate AG〇〇~AG〇n, when the core power supply voltage VDD_c〇RE is not ready during the power-on process, the input terminal of the gate AG〇〇~AGOn All of the sensors sa〇~SAn are set to a predetermined logic level so that the sensing circuit 112 is disabled, so as to avoid erroneous read operations caused by the power supply sequence. Similarly, the level adjuster LS18 is Coupling between the programming enable signal pE and the gates AGIO~AGln of the programming circuit 114" for starting the power supply process When the core power supply voltage VDD_CORE is not ready, the input terminals of the gates ag 10~AG 1 η are all set to a predetermined logic level, so that the programming circuit 114,, will be disabled to avoid the power supply start. The sequence causes an incorrect burning action. When the 'I/O power supply voltage VDD_IO and the core power supply voltage 乂00' 301 are all ready, the level adjuster 1^16~1^18 is used to burn the outside. The recording voltage enable signal EPSJEN, the read enable signal rE, and the burn enable signal PE are adjusted by the signal of the core power supply voltage level to the signal of the input and output power voltage levels, so as to respectively control the switching element 116 and the sensing circuit 112. And the gates AG0~AGln (ie, the driver) in the sensor SA0~SAn and the programming circuit 114. It should be noted that the NMOS transistor 0758-A3255 lTWF in the electrically programmable unit 110"; MTKI-06-358;yens 12 200816207 - When the body TO~Τη is realized by a thick gate device (I/O device), a set of level adjusters LS17 is needed to adjust the position of the sensing circuit 112" Address (signal) 00 < 0: !1 > and read enable signal RE. Similarly, one is needed The level adjuster LS18 is used to adjust the address (signal) 00 <0:!1> and the burn-in enable signal PE in the programming circuit 114". The switching element 116 is coupled to the external programming voltage EPS and the resistor. Between the RPs, the external programming voltage EPS is selectively disconnected from the power busbar 111" according to the output of the level adjuster LS16. For example, the switching element 116 can be an active device such as a MOS transistor, a bi-carrier transistor (BJT), or a junction field effect transistor (JFET), but is not limited thereto. The level regulator LS16 is coupled between the external programming voltage enable signal EPS_EN and the control terminal of the switching element 116 for selectively disconnecting the external power supply voltage EPS from the electrically recordable unit 110". In other words, when the I/O power supply voltage VDD_IO and the core power supply voltage VDD_CORE are ready, the level regulator LS16 is used to set the externally-programmed electric I voltage enable signal EPS_EN from the core power supply voltage level. The signal is adjusted to a signal of the input/output power voltage level, so as to control the switching element 116 to connect the external programming voltage EPS to the electrically combable unit 110" to burn or sense the electrical burnable unit 110" (read In other words, when the core power supply VDD_CORE is not ready for female during power-on, the level regulator LS16 sets the control terminal of the switching element 116 to a predetermined logic level, so that the switching element 116 will be turned off. Therefore, the power bus bar 111" in the electric burner unit 110" will be disconnected from the external programming voltage EPS 075 8-A325 51 TWF; MTKI-06-3 5 8 ; yens 13 200816207, to avoid erroneous burning. Action. For example, bit The adjusters LS 16 LS LS 18 can be arranged at a predetermined logic level by means of AC coupling, control signals from one of the external circuits, discharge by a resistive element or a combination thereof. The ESD protection circuit 118 is connected to the switching element 116 and the resistor RP" to avoid damage from electrostatic discharge events. Figure 6 is an embodiment of a quasi-regulator. As shown, the level adjuster 21A generates output f signals OUT_I0 and OUTB_I0 according to an input signal IN_C0RE, and the level adjuster 21A includes a first logic unit 16, a second logic unit 18, and two drivers 23. With 25, and an inverter INV1. The first logic unit 16 is powered by the I/O supply voltage VDD_I0 and the second logic unit 18 is powered by the core supply voltage VDD_C0RE. For example, the first logic unit 16 includes a latch unit 12 and a differential pair 14, and the second logic unit 18 includes an inverter INV0, wherein the latch unit 12 includes a cross coupling to the PMOS transistor ΜΡ0. And MP1, and the differential pair 14 includes two (NM0S transistors ΜΝ0 and MN1. In some embodiments, the latch unit 12 may also include two cross-coupled to the inverter. Powered by the core supply voltage VDD_C0RE The inverter INV0 is used to convert the input signal IN_C0RE into an inverted signal INB+C0RE. In some embodiments, the transistor in the latch unit 12 is implemented by a thin gate device, and the level adjuster 21A The transistor in the middle is implemented by a thick gate device. If the input signal IN-CORE is high, the inverted signal INB_C0RE will be low, so NM0S transistor ΜΝ0 and MN1 0758-A32551TWF; MTKI-06-358; Yens 14 200816207 The knives are not wanted. When the nmos transistor mno is turned on, the gate of the PMOS packet will be pulled down to the ground voltage gND, so the PMOS power will be moved. The body MPI will then be turned on. Therefore, the input signal 〇υτ ίο and 〇trrft \冲—ΤΒ-10 will be high and low, respectively. At this time, the points N1 and Ν2 can be regarded as the output of the output signal OUT 10盥〇UTB-IO. —“

、、、"動為23係|馬接於I/O電源電塵vdd一 10與節 ? N1 ’用以當核心電源電壓VDD—C0RE尚未備妥犄使彳^J Nl上的電壓會與1/〇電源電壓VDD—〗〇匹配而第一驅動器25係耦接於節點N2與接地電壓gND 之，’用以备核心電源電壓VDD-CORE尚未備妥時，拉低節點上的電壓（或將節點N2上的電壓維持在低位準）。第一驅動器23係藉由PMOS電晶體MP2與NM〇S 電晶體MN2與MN3來實現，而第二驅動器乃係藉由 NMOS電晶體MN4與MN5來實現。 PMOS電晶體Mp2係包括汲極與源極耦接至電源电壓VDDj〇以及一閘極耦接至節點犯，意即pM〇s 膛晶體MP2係連接成一電容器。NM〇s電晶體包括一汲極耦接至節點N1、一閘極耦接至I/O電源電壓 VDD一 10，以及一源極端。在某些實施例中，位準調整器 21A可以只包含第一驅動器23而不包含第二驅動器乃: NM0S電晶體MN3係包括一汲極端耦接至Nm〇s 電晶體MN2之源極端以及一閘極端與一源極端一起耦接至接地電壓GND。NM0S電晶體MN4係包括一閘極耦接 0758-A32551TWF;MTKI-06-358;yens 15 200816207 - 至節點N2以及一汲極端與一源極端一起耦接至接地電壓GND，即NMOS電晶體MN4係連接成一電容器。NMOS 電晶體MN5係包括一汲極端耦接至節點N2以及一閘極端與一源極端一起耦接至接地電壓GND。換言之，NMOS 電晶體MN4與MN5係可示為去耦合電容器（decoupling capacitors) 〇由於寄生電容Cgd及或Cgb，節點N1上的電壓位準會追隨著I/O電源電壓VDD_I0,同時由於去耦合電容 ’ （即NMOS電晶體MN4與MN5)節點N2上的電壓位準會維持在低位準。因此，當電源啟動過程中核心電源電壓 VDD_C0RE未備妥時，輸出信號OUT_IO與OUTB_IO 會分別被設置於高位準與低位準。換言之，電源啟動過程中核心電源電壓VDD_C0RE未備妥時，由於位準調整器21A之輸出端可被設置於既定邏輯位準，因此位準調整器21A可用以實現第5圖中之位準調整器LS16、LS17 與 LS18〇 ^ 舉例而言，當電源啟動過程中核心電源電壓 VDD—CORE未備妥時，位準調整器LS16會輸出具有高位準之輸出信號〇UTB_IO及/或一具有低位準之輸出信號〇UT_I〇至開關元件116，使得電可燒錄單元110”與外部燒錄電壓EPS斷開，藉以避免未預期的或錯誤的燒錄動作。同樣地，當電源啟動過程中核心電源電壓 VDD_CORE未備妥時，位準調整器LS17會輸出具有低位準之輸出信號OUT_IO至感測電路112”中之及閘 0758-A32551TWF;MTKI-06-358;yens 16 200816207 - AG00〜AGOn，使得感測電路112”中之感測器SA0〜SAn 會被禁能。再者，當電源啟動過程中核心電源電壓 VDD_C〇RE未備妥時，位準調整器LS18會輸出具有低位準之輸出信號〇UT_IO至感測電路112”中之及閘 AGIO〜AGln，使得燒錄電路114”會被禁能。於某些實施例中，第一驅動器23亦可包括NMOS 電晶體MN2與MN3，但不包括PMOS電晶體MP2。於某些實施例中，第一驅動器23亦可包括PMOS電晶體 ’ MP2，但不包括NMOS電晶體MN2與MN3。於某些實施例中，第二驅動器25亦可包括NMOS電晶體MN4，但不包括NMOS電晶體MN5。於某些實施例中，第二驅動器25亦可包括NMOS電晶體MN5，但不包括NMOS 電晶體MN4。第7A圖係為開關元件之一實施例。如圖所示，開關元件116包括一 PMOS電晶體P1耦接於外部燒錄電壓 EPS與電阻RP”之間，以及一 NMOS電晶體N1耦接於耦 < 接於電阻RP”與接地電壓GND之間，其中MOS電晶體 P1與N1之控制端係一起耦接至位準調整器LS16之輸出端。當電源啟動過程中核心電源電壓VDD_CORE未備妥且輸出信號OUTBJO為高邏輯位準時，PMOS電晶體會被截止，而NMOS電晶體N1會導通。因此，外部燒錄電壓EPS會與電可燒錄單元110”中電源匯流排111”斷開，並且會被放電至接地端。換言之，當電源啟動過程中，無論外部燒錄電壓EPS為何，位準調整器LS16都會 075 8-A325 51 TWF;MTKI-06-3 5 8 ;yens 17 200816207 . 輸出輸出信號0UTB_I0將開關元件116關閉（截止）。當電源啟動過程中核心電源電麼VDD_CORE未備女時’外部燒錄電壓EPS會與電可燒錄單元110”斷開，因此可避免未預期的或錯誤的燒錄動作。, , , " Move for 23 Series | Horse connected to I / O power supply dust vdd a 10 and section? N1 ' used when the core power supply voltage VDD - C0RE is not ready, so that the voltage on the J ^ J Nl will be 1 / 〇 power supply voltage VDD - 〗〇 matching and the first driver 25 is coupled to the node N2 and the ground voltage gND, 'to prepare the core power supply voltage VDD-CORE is not ready, pull the voltage on the node (or The voltage on node N2 is maintained at a low level). The first driver 23 is implemented by PMOS transistors MP2 and NM〇S transistors MN2 and MN3, and the second driver is implemented by NMOS transistors MN4 and MN5. The PMOS transistor Mp2 includes a drain and a source coupled to the power supply voltage VDDj〇 and a gate coupled to the node, that is, the pM〇s 膛 crystal MP2 is connected as a capacitor. The NM〇s transistor includes a drain coupled to the node N1, a gate coupled to the I/O supply voltage VDD-10, and a source terminal. In some embodiments, the level adjuster 21A may include only the first driver 23 and not the second driver: the NMOS transistor MN3 includes a source terminal that is extremely coupled to the Nm〇s transistor MN2 and a The gate terminal is coupled to the ground voltage GND together with a source terminal. NM0S transistor MN4 includes a gate coupling 0758-A32551TWF; MTKI-06-358; yens 15 200816207 - to node N2 and a terminal and a source terminal are coupled to ground voltage GND, that is, NMOS transistor MN4 Connected into a capacitor. The NMOS transistor MN5 includes a terminal coupled to the node N2 and a gate coupled to a ground terminal GND together with a source terminal. In other words, the NMOS transistors MN4 and MN5 can be shown as decoupling capacitors. Due to the parasitic capacitance Cgd and or Cgb, the voltage level on the node N1 will follow the I/O supply voltage VDD_I0, and due to the decoupling capacitor. The voltage level at node N2 (ie NMOS transistors MN4 and MN5) will remain at a low level. Therefore, when the core power supply voltage VDD_C0RE is not ready during power-on, the output signals OUT_IO and OUTB_IO are set to the high and low levels, respectively. In other words, when the core power supply voltage VDD_C0RE is not ready during power-on, since the output of the level adjuster 21A can be set to a predetermined logic level, the level adjuster 21A can be used to achieve the level adjustment in FIG. For example, when the core power supply voltage VDD_CORE is not ready during power-on, the level regulator LS16 outputs a high level output signal 〇UTB_IO and/or one with low level. The output signal 〇UT_I〇 is switched to the switching element 116, so that the electrically burnable unit 110” is disconnected from the external programming voltage EPS to avoid an unexpected or erroneous burning operation. Similarly, the core power supply during the power-on process. When the voltage VDD_CORE is not ready, the level adjuster LS17 outputs a low level output signal OUT_IO to the sense circuit 112" and the gate 0758-A32551TWF; MTKI-06-358; yens 16 200816207 - AG00~AGOn, The sensors SA0~SAn in the sensing circuit 112" are disabled. Furthermore, when the core power supply voltage VDD_C〇RE is not ready during power-on, the level regulator LS18 will output low. The output signal 〇UT_IO to the gates AGIO~AGln in the sensing circuit 112", so that the programming circuit 114" is disabled. In some embodiments, the first driver 23 can also include the NMOS transistor MN2 and MN3, but does not include PMOS transistor MP2. In some embodiments, first driver 23 may also include PMOS transistor 'MP2, but does not include NMOS transistors MN2 and MN3. In some embodiments, second driver 25 may also include NMOS transistor MN4, but does not include NMOS transistor MN5. In some embodiments, second driver 25 may also include NMOS transistor MN5, but does not include NMOS transistor MN4. Figure 7A is a switch An embodiment of the device. As shown, the switching element 116 includes a PMOS transistor P1 coupled between the external programming voltage EPS and the resistor RP", and an NMOS transistor N1 coupled to the coupling. Between the RP" and the ground voltage GND, wherein the control terminals of the MOS transistors P1 and N1 are coupled to the output terminal of the level adjuster LS16. When the power supply is started, the core power supply voltage VDD_CORE is not ready and the output signal OUTBJO is High logic level, PMOS transistor It will be cut off, and the NMOS transistor N1 will be turned on. Therefore, the external programming voltage EPS will be disconnected from the power busbar 111" in the electrically recordable unit 110" and will be discharged to the ground. In other words, when the power is turned on In the process, regardless of the external programming voltage EPS, the level adjuster LS16 will be 075 8-A325 51 TWF; MTKI-06-3 5 8 ; yens 17 200816207 . The output output signal OUTB_I0 turns off the switching element 116 (off). When the core power supply is turned on during power-on, VDD_CORE is not ready for female. The external programming voltage EPS will be disconnected from the electrical burn-in unit 110, thus avoiding unexpected or erroneous programming.

當核心電源電壓VDD_CORE與I/O電源電壓皆備妥時，LS16會根據外部燒錄電壓致能信號EPS JEN，輸出輸出信號〇UTB_IO與〇UT_IO來控制開關元件116。換言之，於電源啟動完成後，開關元件116係根據外部燒 " 錄電壓致能信號EPS JEN，選擇性地將外部燒錄電壓EPS 連接至電可燒錄單元110”之電源匯流排111”。舉例而言，當輸出信號〇UTB_IO為低位準時，PMOS電晶體P1 會導通，NMOS電晶體N1會截止。因此，外部燒錄電壓 EPS會被連接至電可燒錄單元110”之電源匯流排111”，以便進行電可燒錄單元110”的燒錄或感測動作。如果當PMOS電晶體P1在截止狀態時，感測電路 112”不需要開關元件116的輸出電位接地，則NMOS電、晶體N1並非必要元件。也就是說，在某些實施例中，並不需要實施NMOS電晶體N1，而僅需要實施PMOS電晶體P1即可滿足。第7B圖係為開關元件之另一實施例。如圖所示，開關元件116”係與第7A圖中所示之開關元件116相似，其差別在於NMOS電晶體N2係耦接於外部燒錄電壓EPS 與電阻RP”之間。當電源啟動過程中核心電源電壓 VDD CORE未備妥時，如果輸出信號OUTB_IO與 0758-A3255 lTWF;MTKI-06-358;yens 18 200816207 OUT—10在係分 ^ PI與NM〇s $，設置於高位準與低位準，PMOS電晶體會導通。因此，外，體N2會被截止，而NMOS電晶體N1 之電源匯淹挪i °卩燒錄電壓EPS會與電可燒錄單元11〇，，動過程中核心$Ul斷開，並被放電至接地端。當電源啟電壓EPS會_源電壓VDD—⑶RE未備妥時，外部燒錄期的或錯誨的:可燒錄單元110’’斷開，因此可避免未預 NMOS電晶趲^錄動作。如果當PMOS電晶體P1和開關元件2在截止狀態時，感測電路112”不需要非必要元件。的輪出電位接地，則NMOS電晶體N1並施NMOS電曰曰〜就疋說’在某些實施例中，並不需要實 NMOS電晶辦體Μ〗，而僅需要實施PM〇s電晶體P1和第‘二即可滿足。所示，由於在弟5圖中記憶體電路之模擬結果。如圖未備妥時，铪兔源啟動過程中核心電源電壓VDD—CORE VDD 10用^出4唬〇UTB-10會追隨著1/0電源電壓開，所以在=將外部燒錄電壓EPS與電源匯流排1U，，斷二單元m二電源電M VDD-⑶_妥之前，電可燒丁包源匯流排111”上的電壓位準VBUS係保持在低位準，Μ π、\ ^ 故可避免未預期的或錯誤的燒錄動作。 h固係為位準調整器之另一實施例。如圖所示， m Μ 55 ο 1ΤΛ Μ 1 1 、、係與第6圖中所示之位準調整器21Α相似，、差別在於除去第一驅動器23並且第二驅動器25 係由開關元件60來實現。在某些實施例中，反相器 INV0中的電晶體是由薄閘極裝置所實施，而位準調整器〇758-A32551TWF;MTKI-06-358;yens 200816207 -21B中的其他電晶體則是由厚閘極裝置所實施。開關元件60係耦接於節點N2與接地電壓GND之間，並且受一個外部的電源啟始重置電路70之控制。當電源啟動過程中核心電源電壓VDD_CORE未備妥時，外部的電源啟始重置電路70會產生一控制信號SR來控制開關元件60，使得節點N2上的電壓位準會被拉低。當節點N2上的位準被開關元件60拉低時，PMOS電晶體ΜΡ0會導通，並且節點N1亦會被拉高至I/O電源電壓VDDJO。換言之， ’ 在核心電源電壓VDD—CORE未備妥時，輸出信號〇UTB_IO與OUT_IO會分別設置於高位準與低位準。當核心電源電壓VDD_CORE備妥時，電源啟始重置電路70會藉由控制信號SR將開關元件60截止，使得使用核心電源電壓VDD_CORE之反相器INV0會產生反相信號並取回對位準調整器21B的控制權。於某些實施例中，開關元件60係可由一主動元件來實現，例如MOS 電晶體、雙載子電晶體、接面場效型電晶體或其組合。 % 第10圖係為位準調整器之另一實施例。如圖所示，When the core power supply voltage VDD_CORE and the I/O power supply voltage are all ready, the LS16 controls the switching element 116 according to the external programming voltage enable signal EPS JEN and the output signals 〇UTB_IO and 〇UT_IO. In other words, after the power-on is completed, the switching element 116 selectively connects the external programming voltage EPS to the power busbar 111" of the electrically recordable unit 110" according to the externally-recorded voltage enable signal EPS JEN. For example, when the output signal 〇UTB_IO is low, the PMOS transistor P1 is turned on and the NMOS transistor N1 is turned off. Therefore, the external programming voltage EPS is connected to the power bus bar 111" of the electrically combable unit 110" for performing the burning or sensing action of the electrically combable cell 110". If the PMOS transistor P1 is off In the state, the sensing circuit 112" does not require the output potential of the switching element 116 to be grounded, and the NMOS, crystal N1 is not an essential component. That is, in some embodiments, it is not necessary to implement the NMOS transistor N1, but only the PMOS transistor P1 needs to be implemented. Figure 7B is another embodiment of a switching element. As shown, the switching element 116" is similar to the switching element 116 shown in FIG. 7A, with the difference that the NMOS transistor N2 is coupled between the external programming voltage EPS and the resistor RP". When the core power supply voltage VDD CORE is not ready during power-on, if the output signals OUTB_IO and 0758-A3255 lTWF; MTKI-06-358; yens 18 200816207 OUT-10 in the system ^ PI and NM〇s $, set in The high level and low level, the PMOS transistor will turn on. Therefore, the body N2 will be cut off, and the power supply of the NMOS transistor N1 will be flooded. The burn-in voltage EPS will be disconnected from the electrically combustible unit 11〇, and the core $Ul is disconnected and discharged. To the ground. When the power-on voltage EPS_source voltage VDD-(3)RE is not ready, the external programming period or the error: the burn-in unit 110'' is turned off, so that the unpre-NMOS transistor operation can be avoided. If the PMOS transistor P1 and the switching element 2 are in the off state, the sensing circuit 112" does not require an unnecessary component. The turn-out potential is grounded, and the NMOS transistor N1 is applied with an NMOS 曰曰~ In some embodiments, the real NMOS transistor is not required, and only the PM 〇s transistor P1 and the second '2' need to be implemented. As shown in the figure, the simulation result of the memory circuit in the figure 5 is shown. When the picture is not ready, the core power supply voltage VDD-CORE VDD 10 during the startup process of the Rex Rabbit source will be 4 唬〇 UTB-10 will follow the 1/0 power supply voltage, so the externally burned voltage EPS will be Before the power bus 1U, the second unit m two power supply M VDD-(3) _, the voltage level VBUS on the electric fire can only be kept at a low level, Μ π, \ ^ Unexpected or erroneous burning actions can be avoided. h is a further embodiment of a level adjuster. As shown, m Μ 55 ο 1ΤΛ Μ 1 1 , is similar to the level adjuster 21 所示 shown in FIG. 6, with the difference that the first driver 23 is removed and the second driver 25 is connected by the switching element 60. achieve. In some embodiments, the transistor in inverter INV0 is implemented by a thin gate device, while the level adjuster 〇758-A32551TWF; MTKI-06-358; other transistors in yens 200816207-21B It is implemented by a thick gate device. The switching element 60 is coupled between the node N2 and the ground voltage GND, and is controlled by an external power supply starting reset circuit 70. When the core power supply voltage VDD_CORE is not ready during power-on, the external power supply start reset circuit 70 generates a control signal SR to control the switching element 60 such that the voltage level at the node N2 is pulled low. When the level on node N2 is pulled low by switching element 60, PMOS transistor ΜΡ0 is turned on, and node N1 is also pulled high to I/O supply voltage VDDJO. In other words, when the core power supply voltage VDD_CORE is not ready, the output signals 〇UTB_IO and OUT_IO are set to the high level and the low level, respectively. When the core power supply voltage VDD_CORE is ready, the power supply start reset circuit 70 turns off the switching element 60 by the control signal SR, so that the inverter INV0 using the core power supply voltage VDD_CORE generates an inverted signal and retrieves the alignment level. Control of the regulator 21B. In some embodiments, switching element 60 can be implemented by an active element, such as a MOS transistor, a bipolar transistor, a junction field effect transistor, or a combination thereof. % Figure 10 is another embodiment of a level adjuster. as the picture shows,

位準調整器21C係與第6圖所示之位準調整器21A相似，其差別在於第二驅動器25由開關元件60來實現。在某些實施例中，反相器INV0中的電晶體是由薄閘極裝置所實施，而位準調整器21C中的其他電晶體則是由厚閘極裝置所實施。當電源啟動過程中核心電源電壓 VDD—CORE未備妥時，由於MOS電晶體MP2、MN2或 MN3的寄生電容Cgd或Cbg所導致的交流耦合（AC 0758-A32551TWF;MTKI-06-358;yens 20 200816207 -coupling)，節點N1上的電壓位準會追隨著I/O電源電壓 VDDJO，並且節點N2上的電壓位準會被開關元件60 拉低至接地端。換言之，當電源啟動過程中核心電源電壓VDD_CORE未備妥時，輸出信號OUTB_IO與OUT jO 會分別被設置於高位準與低位準。當核心電源電壓 VDD—CORE備妥時，外部的電源啟始重置電路70會藉由控制信號SR將開關元件60截止，使得使用核心電源電壓VDD_CORE之反相器INV0會產生反相信號並取回對位準調整器21C的控制權。第11圖係為位準調整器之另一實施例。如圖所示，位準調整器21D係與第6圖中所示之位準調整器21A相似，其差別在於第二驅動器25係由一電阻性元件62所實現，用以慢慢地拉低節點N2上的電壓位準。當電源啟動過程中核心電源電壓VDD—CORE未備B夺’由於^ MOS 電晶體MP2、MN2或MN3的寄生電容Cgd或Cbg所導致的交流輕合(AC coupling)，節點N1上的電壓位準會追隨著I/O電源電壓VDD_IO，並且節點N2上的電壓位準會藉由電阻性元件62慢慢地被拉低。換言之，當電源啟動過程中核心電源電壓VDD_CORE未備妥時，輸出信號 OUTB—10與OUT—10會分別被設置於高位準與低位準。舉例而言，若電阻性元件62具有足夠的阻值，於核心電源電壓VDD—CORE備妥時，它將可視為一個高阻抗。因此，當核心電源電壓VDD_CORE備妥時，使用核心電源電壓VDD—CORE之反相器INV0會產生反相信號，並取 0758-A32551TWF;MTKI-06-358;yens 21 200816207 回對位準調整器21D的控制才蘿凡件之一實施例。如圖所示The level adjuster 21C is similar to the level adjuster 21A shown in Fig. 6, with the difference that the second driver 25 is realized by the switching element 60. In some embodiments, the transistors in inverter INV0 are implemented by thin gate devices, while the other transistors in level adjuster 21C are implemented by thick gate devices. AC coupling due to parasitic capacitance Cgd or Cbg of MOS transistor MP2, MN2 or MN3 when the core supply voltage VDD_CORE is not ready during power-on (AC 0758-A32551TWF; MTKI-06-358; yens 20 200816207 -coupling), the voltage level on node N1 will follow the I/O supply voltage VDDJO, and the voltage level on node N2 will be pulled down to ground by switching element 60. In other words, when the core power supply voltage VDD_CORE is not ready during power-on, the output signals OUTB_IO and OUT jO are set to the high and low levels, respectively. When the core power supply voltage VDD_CORE is ready, the external power supply start reset circuit 70 turns off the switching element 60 by the control signal SR, so that the inverter INV0 using the core power supply voltage VDD_CORE generates an inverted signal and takes The control of the level adjuster 21C is returned. Figure 11 is another embodiment of a level adjuster. As shown, the level adjuster 21D is similar to the level adjuster 21A shown in FIG. 6, with the difference that the second driver 25 is implemented by a resistive element 62 for slowly pulling down The voltage level on node N2. When the power supply is started, the core power supply voltage VDD-CORE is not ready for B. The voltage level on the node N1 due to the AC coupling caused by the parasitic capacitance Cgd or Cbg of the MOS transistor MP2, MN2 or MN3. The I/O supply voltage VDD_IO will follow, and the voltage level at node N2 will be slowly pulled low by the resistive element 62. In other words, when the core power supply voltage VDD_CORE is not ready during power-on, the output signals OUTB-10 and OUT-10 are set to the high and low levels, respectively. For example, if the resistive element 62 has sufficient resistance, it will be considered a high impedance when the core supply voltage VDD-CORE is ready. Therefore, when the core power supply voltage VDD_CORE is ready, the inverter INV0 using the core power supply voltage VDD_CORE will generate an inverted signal, and take 0758-A32551TWF; MTKI-06-358; yens 21 200816207 back to the level adjuster One of the embodiments of the 21D control. as the picture shows

第12A圖係為電阻性元件電阻性元件62A係輕接於節黑占間，並且包括N個串聯源極。當電源啟動過程中核心電源電壓VDD—c〇RE未備妥日守，NMOS黾θθ體MNB會導通，使得節點N2上的電壓位準會被慢慢地拉低。因此，當1/〇電源電壓VDEli〇比核心電源電壓VDD—CORE早備妥時，輸出信號 OUTB J0會被第一驅動器23拉高，而輸出信號0UT_1〇會被電阻性元件62A慢慢地拉低。Fig. 12A is a resistive element. The resistive element 62A is lightly connected to the blackout interval and includes N series sources. When the core power supply voltage VDD_c〇RE is not ready during power-on, the NMOS 黾θθ body MNB will be turned on, so that the voltage level at node N2 will be slowly pulled low. Therefore, when the 1/〇 power supply voltage VDEli〇 is earlier than the core power supply voltage VDD_CORE, the output signal OUTB J0 is pulled high by the first driver 23, and the output signal OUT_1〇 is slowly pulled by the resistive element 62A. low.

第12B圖係為電阻性元件之另一實施例。如圖所示，電阻性元件62B係與第12A圖中所示之電阻性元件 62A相似，其差別在PMOS電晶體MPA1〜MPAN係由雙載子電晶體（BJTs)BTAl〜BTAN所取代，電阻性元件62B 之動作係與第12A圖中所示之電阻性元件62A相似，於此不再累述。第12C圖係為電阻性元件之另一實施例。如圖所示，電阻性元件62C係與第12A圖中所示之電阻性元件 62A相似，其差別在PMOS電晶體MPA1〜MPAN係由 NMOS電晶體MNA1〜MNAN所取代，每一個NMOS電晶體MNA1〜MNAN皆連接成二極體形式，即閘極耦接其 0758-A32551TWF;MTKI-06-358;yens 22 200816207 汲極。電阻性元件62C之動作係與第12A圖中所示之電阻性元件62A相似，於此不再累述。第12D圖係為電阻性元件之另一實施例。如圖所示，電阻性元件62C係與第12A圖中所示之電阻性元件 62A相似，其差別在NM〇s電晶體係耦接於電晶體ΜΡΑ0與MPA1〜MPAN之間，電阻性元件62D之動作係與第12A圖中所示之電阻性元件62a相似，於此不再累述。少於某此實施例中，位準調整器LS16、LS17與LS18 係可選擇性地移除。舉例而言，當電可燒錄單元〗1〇，，中之難OS f晶體係由薄閘極裝置所實現時，感測電路 u2與燒錄電路114”只需要核心電源電壓vdd_c〇re，因此位準調整器LS17與1^18可被移除。或者是說，當，可燒錄單元110，，中之咖⑽電晶體係由厚閘極裝置所實現時，感測電路112”與燒錄電路114”中之位準調整器了白由第6、9、10與π圖中所示之位準調整器jiA、 21C或21D來貫現。亦或是說，感測電路ία，，與燒錄電路114，，中之位準調整器可皆由第6、9、1〇與^ 圖中所示之位準調整器21A、21B、21C或21D來實現，但移除開關元件116與位準調整器LS16。見干由於本發明之記憶體電路可於電源啟動過程中核心電源電壓未備妥時，將外部燒錄電壓與電可燒錄單開」因此可以避免由於電源啟動順序所造成未預期錯誤的燒錄動作。、/ 、s _-A32551TWiT;MTKn358;yens 幻 200816207 雖然本發明已以較每以限定本發明，任何例揭路如上’然其並非用神和範圍内，當可作者’在不脫離本發明之精 =1II1® ^^ W4 — σ更動與潤飾，因此本發明之保 4粑圍田視後附之申請專利範圍所界定者為準。【圖式簡單說明】 ΐ:圖係為—記憶體電路之一實施例。 f圖係為-感测電路之一實施例。 f 3圖係為-燒錄電路之-實施例。第4圖係為第1圖中雕第5 Ri 甲、脰電路之模擬結果弟5圖係為一記憶體電路每楚a固/么认只知例。 f圖係為一位準調整器之-實施例。，7A圖係為開關元件之_實施例。 f 7B圖係為開關元件之另—實施例。弟8圖係為第5圖中記愔> Μ 電路之模擬結果。 ^圖係為位準調整器之另—實施例。第10圖係為位準調整器之另一每々弟II圖係為位準調整器之另—實施例。第12Α圖係為電阻性元件之一實施例。 f 12Β圖係為電阻性元件之另：實：例。弟12C圖係為電阻性元件之每 ^ 10ΤΛ _ ^ J 貝知例。弟12D圖係為電阻性元件之 —h 々—貫施例。【主要元件符號說明】 12 ··栓鎖單元； 14 ·兰壬 H•差動對； 0758-A3255 lTWF;MTKI-〇6-358; yens 24 200816207 16、18 :邏輯單元； 23、25 :驅動器； 62、62A〜62D :電阻性元件； 70 :電源啟始重置電路； 100、100” ：記憶體電路； 110、 110” ：電可燒錄單元； 111、 111” ：電源匯流排； 112、 112” ：感測電路；114、114” ：燒錄電路； 116、60 ··開關元件； 118 :靜電放電保護電路； 120 :電源供應單元； RP、RP” ：電阻；Figure 12B is another embodiment of a resistive element. As shown, the resistive element 62B is similar to the resistive element 62A shown in FIG. 12A, with the difference that the PMOS transistors MPA1 to MPAN are replaced by bi-carrier transistors (BJTs) BTAl to BTAN, and the resistors The action of the element 62B is similar to that of the resistive element 62A shown in Fig. 12A and will not be described again. Figure 12C is another embodiment of a resistive element. As shown, the resistive element 62C is similar to the resistive element 62A shown in FIG. 12A, with the difference that the PMOS transistors MPA1 MPPAAN are replaced by NMOS transistors MNA1 MNMNAN, each NMOS transistor MNA1 ~ MNAN are connected in the form of a diode, that is, the gate is coupled to its 0758-A32551TWF; MTKI-06-358; yens 22 200816207 bungee. The operation of the resistive element 62C is similar to that of the resistive element 62A shown in Fig. 12A and will not be described again. Figure 12D is another embodiment of a resistive element. As shown, the resistive element 62C is similar to the resistive element 62A shown in FIG. 12A, the difference being coupled between the transistor ΜΡΑ0 and MPA1~MPAN in the NM〇s electro-crystalline system, the resistive element 62D The action is similar to the resistive element 62a shown in Fig. 12A and will not be described again. In less than a certain embodiment, the level adjusters LS16, LS17 and LS18 are selectively removable. For example, when the hard-to-burn unit is 〇1, and the hard-to-OS f crystal system is implemented by the thin gate device, the sensing circuit u2 and the programming circuit 114" only need the core power voltage vdd_c〇re, Therefore, the level adjusters LS17 and 1^18 can be removed. Or, when the programmable unit 110, the medium (10) electro-crystal system is implemented by the thick gate device, the sensing circuit 112" and The level adjuster in the programming circuit 114" is whited by the level adjusters jiA, 21C or 21D shown in the sixth, ninth, tenth and π diagrams. Also, the sensing circuit ία, , and the leveling regulator 114, the level adjuster can be implemented by the level adjusters 21A, 21B, 21C or 21D shown in the sixth, ninth, first and second figures, but the switching elements are removed. 116 and the level adjuster LS16. See that the memory circuit of the present invention can open the external programming voltage and the electric burnable single when the core power supply voltage is not ready during the power-on startup. The burning action caused by the unexpected error in the order. , /, s _-A32551TWiT; MTKn358; yens illusion 200816207 Although the present invention has been described above in detail, any example is disclosed as above, but it is not intended to be used within the scope of the invention. Fine = 1II1 ® ^^ W4 - σ 改改改改改改改改改改改改改改改改改改改改改改改改改改改改改改改改改[Simple diagram of the diagram] ΐ: The diagram is an embodiment of a memory circuit. Figure f is an embodiment of a sensing circuit. The f 3 diagram is an example of a burn-in circuit. Figure 4 is the simulation result of the 5th Ri A and 脰 circuits in Fig. 1. The 5th picture is a memory circuit. The f-picture is an example of a quasi-regulator. The 7A diagram is an embodiment of a switching element. The f 7B diagram is another embodiment of the switching element. The brother 8 is the simulation result of the circuit in Fig. 5 . The figure is another embodiment of the level adjuster. Figure 10 is another embodiment of a level adjuster for each of the level II adjusters. Figure 12 is an embodiment of a resistive element. The f 12 diagram is another of the resistive components: real: examples. The 12C picture is a per- 10 ΤΛ _ ^ J of the resistive element. The 12D picture is a -h 々 - example of a resistive element. [Main component symbol description] 12 ··Latch unit; 14 · Lancome H•Differential pair; 0758-A3255 lTWF; MTKI-〇6-358; yens 24 200816207 16,18: Logic unit; 23, 25: Driver 62, 62A~62D: resistive component; 70: power supply start reset circuit; 100, 100": memory circuit; 110, 110": electric burnable unit; 111, 111": power bus; , 112": sensing circuit; 114, 114": programming circuit; 116, 60 · · switching element; 118: electrostatic discharge protection circuit; 120: power supply unit; RP, RP": resistance;

RfO、Rfl〜Rfn :熔絲；INV0〜INV1 ·•反相器； SA0〜SAn :感測器； AG00〜AGOn、AGIO〜AGln :及閘；RfO, Rfl~Rfn: fuse; INV0~INV1 ·• inverter; SA0~SAn: sensor; AG00~AGOn, AGIO~AGln: and gate;

Cgd、Cgb ··寄生電容；PE :燒錄致能信號； RE :讀取致能信號； EPS JEN :外部燒錄電壓致能信號； VDD_CORE :核心電源電壓； VDD—10 ·•輸入/輸出（I/O)電源電壓； IN_C〇RE ··輸入信號； OUT_IO、OUTB_IO :輸出信號； INB—CORE :反相信號；GND 接地電壓；Cgd, Cgb ··parasitic capacitance; PE: burn enable signal; RE: read enable signal; EPS JEN: external programming voltage enable signal; VDD_CORE: core supply voltage; VDD-10 • Input/output ( I/O) power supply voltage; IN_C〇RE ·· input signal; OUT_IO, OUTB_IO: output signal; INB-CORE: inverted signal; GND ground voltage;

Nl、N2 :節點； SR :控制信號； VBUS :電壓位準； LS12、LS14、LS16、LS17、LS18、21A〜21D :位準調整器； 0758-A32551TWF;MTKI-06-358;yens 25 200816207 TO 、 T1〜Τη ΜΡΑ1 〜ΜΡΑΝ ΜΝΑ1 〜ΜΝΑΝ : 、PI、Ν1 〜Ν2、ΜΡΟ〜ΜΡ2、、ΜΝΒ 、 ΜΤΑ1 〜ΜΤΑΝ 電晶體。 ΜΝΟ〜ΜΝ5、、ΒΤΒ 、 0758-A32551TWF;MTKI-06-358;yens 26Nl, N2: node; SR: control signal; VBUS: voltage level; LS12, LS14, LS16, LS17, LS18, 21A~21D: level adjuster; 0758-A32551TWF; MTKI-06-358; yens 25 200816207 TO , T1~Τη ΜΡΑ1 ~ΜΡΑΝ ΜΝΑ1 ~ΜΝΑΝ : , PI, Ν1 Ν2, ΜΡΟ~ΜΡ2, ΜΝΒ, ΜΤΑ1 ΜΤΑΝ ΜΤΑΝ transistor. ΜΝΟ~ΜΝ5, ΒΤΒ, 0758-A32551TWF; MTKI-06-358; yens 26

Claims

200816207 , 十、申請專利範圍： 1.一種記憶體電路，包括：一可燒錄單元（programmable unit)，包括：複數可燒錄元件；以及一電源匯流排，耦接於一外部燒錄電壓與上述可燒錄元件之間；一開關元件，耦接於上述外部燒錄電壓與上述電源匯流排之間，上述開關元件包括一控制端；以及 f 一位準調整器（level shifter)，用以將一致能信號的電壓位準由一第二電源電壓調整至一第一電源電壓，其中上述第二電源電壓低於上述外部燒錄電壓，並且當電源啟動過程中上述第二電源電壓尚未備妥（not ready) 時，上述位準調整器係將上述開關元件之控制端設置於一既定邏輯位準，使得上述開關元件被截止，並且上述電源匯流排會與上述外部燒錄電壓斷開，以便避免錯誤燒錄（false programming) 〇 l 2.如申請專利範圍第1項所述之記憶體電路，其中上述可燒錄元件各包括一熔絲。 3. 如申請專利範圍第1項所述之記憶體電路，其中上述記憶體電路係為一非易失性記憶體（nonvolatile memory) 〇 4. 如申請專利範圍第1項所述之記憶體電路，其中上述記憶體電路係為一電可燒錄記憶體（electronic programmable memory) 〇 0758-A32551TWF;MTKI-06-358;yens 27 200816207 上述二專:f圍第1項所述之記憶體電路，其十了^錄早兀係為一快閃記憶體。上、十、!·如申請專利範圍第1項所述之記憶體電路，其中上述弟-電源電壓係高於上述外部燒錄電壓。 Α上、=U利耗®第1項所述之記憶體電路，其中、第二電源電麼備妥(ready)時，上述位準調述致能信號之電壓位準由上述第二電源電壓口周正至上述弟一電源電壓。200816207, X. Patent application scope: 1. A memory circuit comprising: a programmable unit comprising: a plurality of programmable components; and a power bus coupled to an external programming voltage and a switching element coupled between the external programming voltage and the power busbar, the switching component includes a control terminal; and a f-level shifter for Adjusting a voltage level of the coincidence signal from a second power voltage to a first power voltage, wherein the second power voltage is lower than the external programming voltage, and the second power voltage is not ready during power startup (not ready), the level adjuster sets the control end of the switching element to a predetermined logic level, so that the switching element is turned off, and the power bus bar is disconnected from the external programming voltage, so that Avoid false programming (false programming) 〇l 2. The memory circuit described in claim 1, wherein the above can be burned Each element comprises a fuse. 3. The memory circuit according to claim 1, wherein the memory circuit is a nonvolatile memory 〇4. The memory circuit according to claim 1 The memory circuit is an electronic programmable memory 〇0758-A32551TWF; MTKI-06-358; yens 27 200816207 the above two special circuits: the memory circuit described in item 1 The tenth record is a flash memory. The memory circuit of claim 1, wherein the above-mentioned power supply voltage is higher than the external programming voltage. The memory circuit of the first item, wherein the second power supply is ready, the voltage level of the level modulation enable signal is from the second power supply voltage. The mouth is approaching the power supply voltage of the above brother.

/ k 8. 如中請專利範圍第1項所述之記憶體電路，其中 =电源啟動中上述第二電源電塵尚未備妥㈣咖办）日守’上述位準調整器係藉由交流輕合（Ac c〇upHng)將上述開關兀件之控制端設置於上述既定邏輯位準。 9. 如申明專利範圍第7項所述之記憶體電路，其中於二源啟動中上;4第二電源電壓尚未備妥時，當上述位準調整器係根據來自—外部電路之—控制信號，將上述開關元件之控制端設置於上述既定邏輯位準。 10.如申請專利範圍第7項所述之記憶體電路，其中於電源啟動中上述第二電源電壓尚未備妥時，當上述位準凋王。。係藉由父流輕合（Ac C0UpHng)以及來自一外部笔路之心·制彳5號’將上述開關元件之控制端設置於上述既定邏輯位準。 U· 一種記憶體電路，包括：私源供應單元’用以提供一外部燒錄電壓；以及一可燒錄單元，包括：〇758>A3255 lTWF;MTKI-〇6-358;yens 28 200816207 稷數可燒錄元件 %"小眠級辨；以及電路心，路’用以燒錄上述可燒錄元件，上述燒錄電路包括稷數驅動器耗接至上述 :位：調整器由至少一第-電源電厂堅所供電二= 弟一琶源電㈣低於上述外部燒錄電M =上述第一電源電壓尚未備妥時，上述；：位準：裔係將其輸出端設置於—第—既㈣輯位準，使得二驅動裔會被禁能（disabled)’以便避免錯誤燒錄。^ 勺括12二:，專利範圍第11項所述之記憶體電路，更 ^ 括感及U 路（sensing circuit)心 =述感測電路包括複數複數感卿-接至上錄凡件以及—第二位準調整器，當電源啟動中上述第疋電源電壓尚未備妥時，甲k弟— 端設置於一第二既定邏輯=: = ==其輪出上述感測器會被禁能。使-上述感測電路中之 13.如ί料難目帛12韻叙記憶包括： ^文 -開關元件，連接於上述外部燒錄電壓與上匯k排？，上述開關元件包括—控制端；以及、 -第三位準調整器，用以當電源啟動中上述第 _尚未傷妥時’將上述開關元件之控制端設置於：弟二既疋_位準’使得上述電源g流排與上述錄電壓斷開，以便避免錯誤燒錄。 ^ 14.如申請專利範圍第13項所述之記憶體電路，其 0758-A32551TWF;MTKI-06-358;yens 29 200816207 .2述每個可燒料件包括—炫絲以及—電晶體連接於上述電源匯流排與一接地電壓之間。 15:如申明專利範圍$ 13項所述之記憶體電路，苴上述弟一、第二、第三位準調整器係由上述源電壓以及一第二電源電摩所供電，其中上述第二電；ί 廢係南於上述外部燒錄電壓，當上述第：壓皆備妥時，上述第一、第二、电原电將-致能信號之電壓位準由上-：凋』係用以〔述第二電源。由上述弟-電源電壓調整至上 16.-種兄憶體電路之誤動作保護方法，其中上 =、體電路包括複數可燒錄元件、—燒㈣路以及—感測電路，上述誤動作保護方法包括·· ΰ又置開關兀件於上述可燒錄元件與一外部燒錚電壓之間； &不电置第位準凋整裔用以耦接至上述開關元件之一控制知’其令上述第一位準調整器係由一第一及 -包源電壓所供電，上述第二電源電壓係低於上一並且上述第一電源電壓高於上述外部燒錄電座，以及當電源啟動過程中上述第二電源·尚未備妥時，將上述開關元件之控制端設置於一第一邏輯位準，使得 f述開關元件被截止’並且上述電源匯流排會與上述外部燒錄電壓斷開。如申請專利範圍第16項所述之記憶體電路之誤〇758-A32551TWF；MTKI-06-358* yens 30 200816207 動作保護方法，更包括·· 哭盥陆力—準調整器於上述燒錄電路之複數驅動盗與-燒錄致能信號之間；以及 μ稷數駆動於電源啟動中上抽_ 述第二位準調整：-上源電壓尚未備妥時，將上準，使得上、f洚棘剧出端设置於一第二既定邏輯位干便传上述燒錄電路φ 中之上述驅動器會被禁能。 8 ·如申請專利範圍動作保護方法，更包括項所述之讀體電路之誤器與二二二f調整器於上述感測電路之複數感測、項取致此k號之間；以及於電源啟動中上述第二電源㈣尚未備边弟三位準調整器之輸出卜一準，使楫卜H、目丨干』出鳊5又置於一弟三既定邏輯位 α感測电路中之上述感測器會被禁能。 19.如申請專利範圍第18項所述之記憶體電路之誤作保濩方法，其中上述第一、、係藉由交流搞合或來自—外部二立丰调“、输出^又置於上述第一、第二、第三既定邏輯位準。 2〇·—種誤動作保護方法，其包括·· 當一核心電塵尚未備妥時’切斷來自可燒錄元件之外部燒錄電壓；以及當上述核心、縣備妥時’根據—致能信號控制上述邛燒錄電壓和上述可燒錄元件間之連結。 2!.如申請專利範圍帛2〇工貝所述之誤動作保護方法，更包括： 0758>A3255lTWF;MTKI-06-358; yens 31 200816207 . 當上述核心電壓尚未備妥時，設置一開關元件之控制端於一既定邏輯位準，使得外部燒錄電壓與上述可燒錄元件斷開。 22.如申請專利範圍第21項所述之誤動作保護方法，更包括：調整上述致能信號之電壓位準為一電源電壓；以及當上述核心電壓備妥時，提供上述電源電壓至上述開關元件的控制端，用以控制上述外部燒錄電壓和上述 # 可燒錄元件間之連結。 0758-A32551TWF;MTKI-06-358;yens 32/ k 8. The memory circuit described in item 1 of the patent scope, wherein = the second power supply dust in the power supply is not ready (4) coffee service) (Ac c〇upHng) sets the control end of the above switch component to the above-mentioned predetermined logic level. 9. The memory circuit according to claim 7 of the patent scope, wherein the second power supply voltage is not ready, and when the second power supply voltage is not ready, when the level regulator is based on the control signal from the external circuit. The control terminal of the switching element is set to the predetermined logic level. 10. The memory circuit according to claim 7, wherein the above-mentioned level is inferior when the second power supply voltage is not ready during power-on. . The control terminal of the above switching element is set to the predetermined logic level by the parent flow (Ac C0UpHng) and the heart from an external stroke. U. A memory circuit, comprising: a private source supply unit 'to provide an external programming voltage; and a programmable unit, comprising: 〇 758> A3255 lTWF; MTKI-〇6-358; yens 28 200816207 The burnable component %"small sleep level; and the circuit core, the road 'used to burn the above-mentioned burnable component, the above-mentioned programming circuit includes a number of drivers to be used to the above: bit: the adjuster consists of at least one - The power supply power plant is powered by two = the other one is the source of electricity (four) is lower than the above external burning power M = the above first power supply voltage is not ready, the above;: level: the system sets its output to - the first The (four) level of the standard, so that the two drivers will be disabled (disabled) in order to avoid false burning. ^ Spoon 12 2: The memory circuit described in Item 11 of the patent scope, the sense of the sense and the sensing circuit of the heart = the sense circuit includes a plurality of complex senses - connected to the record and - The two-position regulator, when the above-mentioned first power supply voltage is not ready in the power-on, the terminal is set to a second predetermined logic =: = == The above-mentioned sensor is disabled. Make--the above-mentioned sensing circuit 13. If it is difficult to see the 12 rhyme memory, including: ^ text - switching components, connected to the above external programming voltage and the upper row k? The switching element includes a control terminal, and a third level adjuster for setting the control end of the switching element to: when the power is activated, the third control terminal is set to: 'The above power source g current row is disconnected from the above recorded voltage to avoid erroneous burning. ^ 14. The memory circuit according to claim 13 of the patent application, which is 0758-A32551TWF; MTKI-06-358; yens 29 200816207.2, each of the burnable parts includes - the ray and the transistor are connected to The power bus is connected to a ground voltage. 15: The memory circuit of claim 13 wherein the first, second, and third level adjusters are powered by the source voltage and a second power supply, wherein the second power ; ί The waste is south of the above external programming voltage. When the above-mentioned first pressure is ready, the voltage levels of the first, second, and electrical primary-enable signals are used by the upper-: [The second power supply. The method for protecting the malfunction of the above-mentioned brother-power supply voltage to the above-mentioned 16-type brother-recalling circuit, wherein the upper=, the body circuit includes a plurality of programmable elements, the (four) way and the sensing circuit, and the above-mentioned malfunction protection method includes · ΰ ΰ 兀于于于于于于于于 & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & a quasi-regulator is powered by a first and a source voltage, the second supply voltage is lower than the previous one and the first power supply voltage is higher than the external burn-in battery, and when the power is activated When the second power source is not ready, the control terminal of the switching element is set to a first logic level such that the switching element is turned off and the power busbar is disconnected from the external programming voltage. For example, the error of the memory circuit described in claim 16 is 758-A32551TWF; MTKI-06-358* yens 30 200816207 The action protection method further includes: · Cry the Luli-quasi-regulator in the above-mentioned programming circuit The plural number drives the pirate and the burn-in enable signal; and the μ 稷駆于于电源电源电源 _ _ _ 第二第二第二第二第二第二第二第二第二第二第二第二第二第二第二第二第二第二第二第二第二第二第二第二第二第二第二第二第二第二第二The above-mentioned driver that is set in a second predetermined logic bit and passes through the above-mentioned programming circuit φ is disabled. 8 as claimed in the patent application scope protection method, further comprising the error device of the reading body circuit and the two-two f adjuster in the above-mentioned sensing circuit, the complex sensing, the item is obtained between the k number; In the power-on startup, the above-mentioned second power source (4) has not yet prepared the output of the three-position regulator of the younger brother, and the output of the three-level regulator is made to be placed in the first logical position α sensing circuit of the third brother. The above sensors will be disabled. 19. The method for protecting a memory circuit according to claim 18, wherein the first one is connected by an exchange or is derived from an external Erlifeng, and the output is placed in the above The first, second, and third predetermined logic levels. 2〇·- a malfunction protection method, including: · cutting off an external programming voltage from the recordable component when a core dust is not ready; When the above-mentioned core and county are ready, the connection between the above-mentioned squeezing voltage and the above-mentioned flammable components is controlled according to the enable signal. 2!. If the application scope is 帛2〇, the malfunction protection method described above, Including: 0758>A3255lTWF;MTKI-06-358; yens 31 200816207. When the above core voltage is not ready, the control terminal of a switching element is set to a predetermined logic level, so that the external programming voltage and the above flammable component are 22. The method for protecting a malfunction according to claim 21, further comprising: adjusting a voltage level of the enable signal to be a power supply voltage; and providing the power when the core voltage is ready The source voltage is connected to the control terminal of the switching element to control the connection between the external programming voltage and the # burner element. 0758-A32551TWF; MTKI-06-358; yens 32