TW200814135A - System and method for processing wafer - Google Patents

System and method for processing wafer Download PDF

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Publication number
TW200814135A
TW200814135A TW95133346A TW95133346A TW200814135A TW 200814135 A TW200814135 A TW 200814135A TW 95133346 A TW95133346 A TW 95133346A TW 95133346 A TW95133346 A TW 95133346A TW 200814135 A TW200814135 A TW 200814135A
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Taiwan
Prior art keywords
wafer
module
wafer processing
processing system
reflectance
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TW95133346A
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Chinese (zh)
Inventor
Yi-Huan Chung
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Applied Materials Inc
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Priority to TW95133346A priority Critical patent/TW200814135A/en
Publication of TW200814135A publication Critical patent/TW200814135A/en

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

A system for processing at least one wafer and a method for the processing the same are disclosed. The system is used for detecting the surface reflectivity of the wafer before processing at least one kind of fabrication. The system comprises a front module, a detecting module and at least one process module. The front module is used for accommodating the wafer. The detecting module is used for detecting the surface reflectivity of the wafer before processing the fabrication, so as to determine whether the wafer can be processed.

Description

200814135 九、發明說明 【發明所屬之技術領域】 本發明係有關於一種晶圓處理系統與方法,特別是 關於一種可預先進行偵錯感測的晶圓處理系統與方法。 【先前技術】 ▲ 2今半導體產業之製程設備開發主要著重於如何$ 高產能和降低成本,而所因應開發的製程設備例如隹$ 型設備(clusterT〇〇i)’其將相關的製程模組(例如::: 氣相沉積CVD、物理氣相沉積pVD或平坦化製程)整: 在同-機纟’使數個相關製程可在單一機台内完成,、; 少晶圓輸送時間和人工運逆過盘 提高潔淨度》 運一因而降低生產時間』 f入::内晶:ί理系統係先將適合處理的晶圓… m在=量快速地對複數批的晶圓進行製" 晶圓中有時可能會混入不適合處㈣ 有不明材料或結構,…對^ 處理糸、,先之真二[體或機構造成 潔淨度下降或設備損壞’造成設;::二而” 而導致整體製程良率下降和晶圓的:費成本的增加’進 【發明内容】 因此,本發明之一 方面係在於提供一種 圓處理系統 200814135 與方法,藉以預先偵測出不適合處理的晶圓,以避免晶圓 之耗費和設備之損壞,並提升製程良率和確保設備之二淨 度。 、 本發明之另一方面係在於提供一種晶圓處理系統與方 法,藉以使晶圓在預先偵錯後可在同一機台上進行多種製 程步驟,因而可提升生產效率。 根據本發明之一實施例,此晶圓處理系統至少包含有 前端模組、至少一製程模組及偵錯模組。前端模組係用以容 置至少一晶圓,製程模組係設置於前端模組之後段,用以對 此些晶圓進行製程步驟。偵錯模组係設置於前端模組與製程 模組之間,其中偵錯模組設有感測器,用以感測晶圓的表面 反射率,偵錯模組係以一預定表面反射率來作為判斷標準, 以判斷晶圓是否適合被製程模組所處理。 勹人又根據本發明之另一實施例,此晶圓處理方法至少 ^合·提供—晶圓;在進行至少—製程步驟前,積測晶圓之 "面反射率;以一預定表面反射率做為偵錯判斷標準,來判 斷晶圓是否適合被製程模組所處理。 口 口此本發明之晶圓處理系統與方法可在晶圓進行製 程步驟則’預先地由偵錯模組來偵測出是否為適合處理的晶 L 口而避免晶圓的不當耗費和設備損壞,進而提升整體製 程良率和潔淨度。 【實施方式】 明參知第1圖,其繪示依照本發明第一實施例之晶圓 6 200814135 處理糸統的俯視示意圖。本第一實施例的晶圓處理系統包 括··前端模組100、偵錯模組200、卡匣模組3〇〇、傳輸模 組400及製程模組5〇〇。前端模組ι〇〇係用以儲存晶圓6〇〇, 並使晶圓600依序地預先由偵錯模組200來感測是否為適合 處理的晶圓600。若偵錯模組200偵測為適合處理的,晶圓 600則可傳送至卡匣模組300内,再利用傳輸模組4〇〇來傳 輸晶圓600至製程模組500内,以進行相關的製程步驟。若 伯錯·模組200偵測為不適合處理的,晶圓6〇〇則可退回至前 端模組100内。 如第1圖所示,本第一實施例之前端模組1〇〇係與卡g 模組300形成組接,以傳送晶圓600至卡匣模組3⑽内。前 端模組100設有複數個卡匣110和前端機械臂120。每一此 些卡H 110内置放有複數片相同的晶圓600,因而晶圓6〇〇 可成批地儲放於前端模組100中,其中此些卡匣11〇内之晶 圓600係尚未由製程模組5〇〇處理的,或係已由製程模組 50〇處理完成而將進行下一相關製程步驟的。前端機械臂 12〇係對應於此些卡匣110設置,當晶圓6〇〇進行製程處理 時,前端機械臂120可取出卡匣110内之晶圓600,而預先 傳送至偵錯模組200來偵測是否為適合處理的晶圓6〇〇。當 晶圓600在由製程模組5〇〇處理完成後,前端機械臂 可由卡匣模組300内取出晶圓600,並傳送回卡匣11〇内, 以批次地運輸至另一製程設備機台(未繪示),進行下一相關 製程步驟處理 如第1圖所示,本第一實施例之偵錯模組2⑽係設置於 7 200814135 前端模'组⑽上,並電性連接前端模組1〇〇,以預先债測由 前端模組iOO之前端機械臂120所傳送的晶圓6〇〇。债錯模 組200設有感測器210(例如係光學感測器),以㉟測光線在 晶圓60G的表面反射率4中,彳貞錯模組係以—默表面反 .射率來作為偵錯判斷標準,藉由晶圓600的表面反射率是否 實質相等於此預定表面反射率,來判斷晶圓6〇〇是否為適合 處理的。因此’此預定表面反射率係對應於不同的製程步驟 而改變。 _ U施例中’晶圓_例如係在進行沉積—鶴金屬 層(未繪示)前預先進行债錯,此時,此預定表面反射率可 以没定為鎢金屬層的表面反射率,當晶圓600之表面反射 率實質相等於此預定反射率時,偵錯模組200即判斷晶圓 600係已沉積有鎢金屬層,而不適合進行處理。 在另一實施例中,晶圓600例如係在進行平坦化前預先 進行偵錯,其係對晶圓600上一材料層(未繪示)進行平坦 化,此時,此預定表面反射率可以設定為此材料層的表面 ⑩反射率,當晶圓600之表面反射率實質不相等於此預定反射 .率時,偵錯模組200即判斷晶圓600未具有此材料層,而不 適合進行處理。 如第1圖所示’本第一實施例之卡匣模組3⑽係與傳輸 模組400形成組接,以使傳輸模組4〇〇可由卡匣模組3⑽ 取出適合處理的晶圓600;或使已處理完成的晶圓600傳送 回卡ϋ模組300内。卡匣模組300設有輸入承載室31〇和輸 出承載室3 20,輸入承載室3 i 〇用以容放由前端模組1 〇〇所 8 200814135 二=複數片晶圓_(已通過預先備測,但尚未處理的), 載室320用以容放由傳輸模組4〇〇所傳輸的複數片之 日日i 600(已由製程模組5〇〇處理完成的)。 第1圖所不,本第一實施例之傳輸模組權係與卡匿 模組300和製程模組5〇〇形成έ且旅 々珉、、且接以使傳輸模組400可在BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer processing system and method, and more particularly to a wafer processing system and method that can perform error detection sensing in advance. [Prior Art] ▲ 2 The manufacturing process of the semiconductor industry today focuses on how to high-capacity and cost reduction, and the process equipment developed for this purpose, such as the “clusterT〇〇i”, which will be related to the process module. (Example::: Vapor Deposition CVD, Physical Vapor Deposition pVD or Flattening Process): In the same machine, several related processes can be completed in a single machine, and less wafer transfer time and labor Reversing the disk to improve the cleanliness. The first one reduces the production time. f In:: The inner crystal: The system is the first wafer that will be suitable for processing... m is rapidly and quantitatively applied to a plurality of wafers. In the wafer, sometimes it may be mixed into the unsuitable place. (4) There is an unknown material or structure, ... the treatment of 糸, first of the true two [body or mechanism caused by the decrease in cleanliness or equipment damage] caused by ::: two and The overall process yield is reduced and the cost of the wafer is increased: [Invention] Therefore, an aspect of the present invention is to provide a circular processing system 200814135 and a method for detecting a wafer that is unsuitable for processing in advance. avoid Wafer cost and equipment damage, and improve process yield and ensure equipment clarity. Another aspect of the present invention is to provide a wafer processing system and method whereby the wafer can be pre-detected. The plurality of processing steps are performed on the same machine, thereby improving production efficiency. According to an embodiment of the invention, the wafer processing system includes at least a front end module, at least one process module, and a debugging module. The system module is disposed at the rear of the front end module for performing the processing steps on the wafers. The debugging module is disposed between the front end module and the process module. The debugging module is provided with a sensor for sensing the surface reflectance of the wafer, and the debugging module uses a predetermined surface reflectance as a criterion to determine whether the wafer is suitable for being processed by the processing module. According to another embodiment of the present invention, the wafer processing method at least provides and supplies a wafer; and before performing at least a process step, the surface reflectance of the wafer is measured; reflection As a debugging judgment standard, it is judged whether the wafer is suitable for processing by the processing module. The wafer processing system and method of the present invention can be processed in the wafer by the 'pre-detection module. It is determined whether it is a suitable crystal port L to avoid improper consuming of the wafer and equipment damage, thereby improving the overall process yield and cleanliness. [Embodiment] FIG. 1 is a first view showing the first aspect according to the present invention. The wafer processing system of the first embodiment includes a front end module 100, a debugging module 200, a cassette module 3, and a transmission module 400. And a process module 5〇〇. The front end module is used to store the wafer 6〇〇, and the wafer 600 is sequentially sensed by the debug module 200 in advance to determine whether it is a suitable wafer 600. . If the debug module 200 detects that it is suitable for processing, the wafer 600 can be transferred to the cassette module 300, and then the transfer module 4 is used to transport the wafer 600 to the process module 500 for correlation. Process steps. If the erroneous module 200 detects that it is unsuitable for processing, the wafer 6 可 can be returned to the front end module 100. As shown in FIG. 1, the front end module 1 of the first embodiment is assembled with the card g module 300 to transfer the wafer 600 to the cassette module 3 (10). The front end module 100 is provided with a plurality of cassettes 110 and a front end mechanical arm 120. Each of the cards H 110 is internally provided with a plurality of identical wafers 600, so that the wafers 6 can be stored in the front-end module 100 in batches, wherein the wafers in the cassettes are The process that has not been processed by the process module 5〇〇, or has been processed by the process module 50〇, will proceed to the next related process step. The front end arm 12 is disposed corresponding to the plurality of cassettes 110. When the wafer 6 is processed, the front end arm 120 can take out the wafer 600 in the cassette 110 and transmit it to the debug module 200 in advance. To detect if it is a suitable wafer for processing. After the wafer 600 is processed by the process module 5, the front arm can be taken out of the cassette 600 by the cassette module 300 and transferred back into the cassette 11 to be transported by batch to another process device. The machine (not shown) performs the next related process step processing. As shown in FIG. 1, the debug module 2 (10) of the first embodiment is disposed on the 7 200814135 front-end module group (10), and is electrically connected to the front end. The module 1〇〇 pre-debts the wafer 6〇〇 transmitted by the front end of the front end module iOO. The faulty module 200 is provided with a sensor 210 (for example, an optical sensor) for measuring the surface light reflectance 4 of the wafer 60G by 35, and the error module is based on the surface acoustic radiation rate. As a debugging judgment criterion, whether or not the wafer 6 is suitable for processing is determined by whether or not the surface reflectance of the wafer 600 is substantially equal to the predetermined surface reflectance. Therefore, this predetermined surface reflectance changes corresponding to different process steps. _ U in the example of 'wafer _, for example, before the deposition - crane metal layer (not shown) before the debt error, at this time, the predetermined surface reflectivity can be determined as the surface reflectivity of the tungsten metal layer, when When the surface reflectance of the wafer 600 is substantially equal to the predetermined reflectance, the debug module 200 determines that the wafer 600 has been deposited with a tungsten metal layer and is not suitable for processing. In another embodiment, the wafer 600 is pre-detected, for example, before planarization, which planarizes a material layer (not shown) on the wafer 600. At this time, the predetermined surface reflectance can be The reflectivity of the surface 10 of the material layer is set. When the surface reflectance of the wafer 600 is substantially not equal to the predetermined reflectance rate, the debug module 200 determines that the wafer 600 does not have the material layer, and is not suitable for processing. . As shown in FIG. 1 , the cassette module 3 ( 10 ) of the first embodiment is assembled with the transfer module 400 so that the transfer module 4 can be taken out of the wafer 600 suitable for processing by the cassette module 3 ( 10 ); Or the processed wafer 600 is transferred back into the cassette module 300. The cassette module 300 is provided with an input carrying chamber 31〇 and an output carrying chamber 3 20, and the input carrying chamber 3 i is used for receiving by the front end module 1 8 200814135 2 = multiple wafers _ (has passed The test room 320 is used for receiving the daily data i 600 of the plurality of pieces transmitted by the transmission module 4 (which has been processed by the process module 5). In the first embodiment, the transmission module right of the first embodiment is formed with the card module 300 and the process module 5, and is connected to the transmission module 400.

卡ΙΕ模'组300和製程模、组·之間進行晶圓6〇〇的傳輸。傳 輸模組4〇0設有傳輸腔體410、傳輸機械臂420及隔離閘門 430。卡£模組·和製程模組_係分別設置於傳輸模組 4〇〇之傳輸腔體410的周圍,傳輸機械臂42〇係設置於傳輸 腔體41。内,其中傳輸腔體内例如係呈高度無塵狀態, 以隔絕污染物。隔離閘門43〇係設置於傳輸腔體41〇與製程 模組500之間’用以隔離傳輸腔體41〇與製程模組内所 使用之工作氣體(未繪示)。當晶圓6〇〇進行製程步驟時,傳 輸模組400之傳輸機械臂42〇係由卡昆模組3〇〇之輸入承載 室310内取出晶圓600’再傳輸至製程模組5〇〇内來進行製 程步驟。晶圓600在製程模組500内製程步驟完成後,傳輸 模組400之傳輸機械臂420即由製程模組5〇〇内取出晶圓 600,並傳輸回卡Ε模組300之輸出承載室32〇内來置放。 如第1圖所示,製程模組500係設置於傳輸模組4〇〇 之傳輸腔體410的周圍。製程模組5〇〇設有至少一製程腔體 510 ,在一實施例中,製程模組500係設有複數個製程腔體 5 10 ’母一製程腔體5 10分別係用以進行不同的製程步驟(例 如:化學氣相沉積CVD、物理氣相沉積pvd或平坦化製 程),其可對應各種的製程需求而選用不同的製程步驟。 9 200814135The transfer of the wafer 6 之间 between the cassette mode group 300 and the process mode and the group is performed. The transmission module 4〇0 is provided with a transmission cavity 410, a transmission robot 420 and an isolation gate 430. The card module and the process module are respectively disposed around the transmission cavity 410 of the transmission module 4, and the transmission robot 42 is disposed in the transmission cavity 41. Inside, the transfer chamber is, for example, highly dust-free to isolate contaminants. The isolation gate 43 is disposed between the transmission cavity 41 and the process module 500 to isolate the transmission chamber 41 and the working gas (not shown) used in the process module. When the wafer 6 is subjected to the process step, the transfer robot 42 of the transfer module 400 is taken out from the input carrying chamber 310 of the Kahn module 3 and then transferred to the process module 5〇〇. In-process process steps. After the processing steps of the wafer 600 in the process module 500 are completed, the transfer robot 420 of the transfer module 400 takes out the wafer 600 from the process module 5 and transfers it back to the output load chamber 32 of the cassette module 300. Put it inside. As shown in Fig. 1, the process module 500 is disposed around the transfer cavity 410 of the transfer module 4A. The process module 5 is provided with at least one process cavity 510. In an embodiment, the process module 500 is provided with a plurality of process chambers 5 10 'mother one process cavity 5 10 respectively for different Process steps (eg, chemical vapor deposition CVD, physical vapor deposition pvd, or planarization processes) that can be used to select different process steps for various process requirements. 9 200814135

請參照第1圖和第2圖,第2圖係緣示依照本發明第一 實施狀晶圓處理系統之谓錯模組的摘錯判斷流程圖。首 先’ W端模組100之前端機械f⑽隸序地傳送晶圓_ 至偵錯模組康之感測器21G來進行感測,當晶圓600被摘 錯模組200 #斷為適合處理時,即由前端機械冑12〇將晶圓 6〇〇傳送至卡E模組300内,以進一步傳輸至製程模組5〇〇 進行處m日圓_被感測為不適合處理時,則由前端機 械臂120將晶圓600退回至前端模組1〇〇内,接著,前端機 械臂120再由前端模組100内取出下一晶圓6〇〇來進行偵 測。因此,本第一實施例之晶圓處理系統可在晶圓6〇〇進行 製程步驟前,預先地由偵錯模組2〇〇來感測出是否為適合處 理的,以避免不明晶圓混入,而造成材料浪費和設備損壞, 因而本發明的晶圓處理系統可提升整體製程良率。 請參照第3圖,其繪示依照本發明第二實施例之晶圓 處理系統的俯視示意圖。相較第一實施例之卡匣模組3〇〇、 傳輸模組400及製程模組500,第二實施例係包括有第一卡 ϋ模組300a、第二卡匣模組3〇Ob、第一傳輸模組4〇〇a、第 二傳輪模組400b、第一製程模組500a及第二製程模組 5 00b。第一卡匣模組300a、第一傳輸模組400a及第一製程 模組500a係設置於前端模組1〇〇之後段,以處理由偵錯模 組200預先感測過的晶圓600。而第二卡匣模組300b、第二 傳輸模組400b及第二製程模組500b係設置於第一傳輸模組 4〇〇a之後段,藉以使在第一製程模組50〇a内完成一系列製 程步驟後的晶圓600可傳輸至第二製程模組500b内,來進 200814135 行另一系列製程步驟。因而第二實施例之晶圓處理系統與 方法可對晶圓600進行更多不同的相關製程步驟,因而增 加製程設備的使用度和減少生產時間。且可利用偵錯模組 2〇〇來避免不明之晶圓混入,因雨提升製程良率。Referring to Fig. 1 and Fig. 2, Fig. 2 is a flow chart showing the error determination of the error correction module of the wafer processing system according to the first embodiment of the present invention. First, the front end of the W-end module 100 mechanical f (10) sequentially transfers the wafer _ to the Detector Module 21G for sensing, when the wafer 600 is erroneously module 200 # is suitable for processing, That is, the front end mechanical 胄 12 〇 transports the wafer 6 至 into the card E module 300 for further transmission to the process module 5 〇〇 where m yen _ is sensed as unsuitable for processing, then the front end arm The wafer 600 is retracted into the front end module 1A. Then, the front end robot arm 120 takes out the next wafer 6 from the front end module 100 for detection. Therefore, the wafer processing system of the first embodiment can be sensed by the debug module 2 预先 before the process step of the wafer 6 to detect whether it is suitable for processing, so as to avoid the incorporation of unknown wafers. The wafer processing system of the present invention can improve the overall process yield, resulting in material waste and equipment damage. Please refer to FIG. 3, which is a top plan view of a wafer processing system in accordance with a second embodiment of the present invention. The second embodiment includes a first cassette module 300a and a second cassette module 3〇Ob, compared to the cassette module 3〇〇, the transmission module 400, and the process module 500 of the first embodiment. The first transmission module 4A, the second transmission module 400b, the first process module 500a, and the second process module 500b. The first cassette module 300a, the first transfer module 400a, and the first process module 500a are disposed in the subsequent stage of the front end module 1 to process the wafer 600 previously sensed by the debug module 200. The second cassette module 300b, the second transfer module 400b, and the second process module 500b are disposed in the subsequent stage of the first transfer module 4A, so that the first process module 50A is completed. The wafer 600 after a series of process steps can be transferred to the second process module 500b to enter another series of process steps in 200814135. Thus, the wafer processing system and method of the second embodiment can perform a number of different process steps on the wafer 600, thereby increasing the usability of the process equipment and reducing production time. The debug module can be used to avoid unintentional wafer incorporation and improve process yield due to rain.

由上述本發明之實施例可知,本發明之晶圓處理系統 與=法可在晶圓進行製程步驟前,預先地由偵錯模組來感 測疋否為適合處理的晶圓,以避免不明之晶圓混入所造成之 材料浪費和設備損壞的情形,因而提升整體製程良率。 雖^本發明已以實施例揭露如上,然其並非用以限定 習此技藝者,在不脫離本發明之精神和範圍 " 種之更動與潤飾,因此本發明之保護範圍卷視 後附之t請料所界^轉。 耗8^視 【圖式簡單說明】 第1圖係繪示根據本發明第 的俯視示意圖。 實施例之晶圓處理系 統According to the embodiment of the present invention, the wafer processing system and the method of the present invention can detect whether the wafer is suitable for processing by the debug module before the wafer is processed to avoid unclear. The wafer is mixed into the material waste and equipment damage, thus improving the overall process yield. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the scope of the invention, and the scope of protection of the present invention is attached thereto without departing from the spirit and scope of the invention. t Please ask the industry to turn around. Fig. 1 is a schematic plan view showing the first embodiment of the present invention. Embodiment wafer processing system

第2圖係繪示根據本 統 〇 統 之偵錯楔龟在剌齡θπ 弟一實梅例之晶圓處理 片租姨組在判斷晶圓 ^ , m ^ ^ 否適合處理的偵錯流程示意 弟3圖係繪示根據本笋 的俯視示意圖。 "一貝施例之晶圓處理 【主要元件符號說明】 1G():前端模組 120 :前端機械臂 11 200814135 200 :偵錯模組 300 :卡匣模組 3 00b ··第一卡匣模組 320 ··輸出承載室 400 ··傳輸模組 400b :第二傳輸模組 ‘ 420 :傳輸機械臂 500 :製程模組 • 500b :第二製程模組 600 :晶圓 2 10 :感測器 300a :第一卡匣模組 3 1 0 :輸入承載室 400a :第一傳輸模組 410 :傳輸腔體 430 :隔離閘門 500a :第一製程模組 510 :製程腔體 12Figure 2 is a schematic diagram showing the debugging process of the wafer processing film renting group according to the system of the θ θ π π π π π π π π π π The brother 3 shows a schematic view of the bird according to the plan. "One Baye Example Wafer Processing [Main Component Symbol Description] 1G(): Front End Module 120: Front End Manipulator 11 200814135 200: Debug Module 300: Card Module 3 00b ··First Card 匣Module 320 ··output carrier room 400 ··transmission module 400b: second transmission module '420: transmission robot 500: process module•500b: second process module 600: wafer 2 10: sensor 300a: first cassette module 3 1 0: input carrying room 400a: first transmission module 410: transmission cavity 430: isolation gate 500a: first process module 510: process chamber 12

Claims (1)

200814135 十、申請專利範圍 1 · 一種晶圓處理系統,至少包含: 一前端模組,用以容置至少一晶圓; 至少-製程模组,設置於該前端模組之後段,用 晶圓進行至少一製程步驟;以及 Λ -積錯模組’設置於該前端模組與該製程模組之間,直 中該偵錯模組設有-感測器,用以感測該晶圓之—表ς 率,㈣錯模組仙-預定反射率來做為偵錯·標準,备 該表面反射㈣實質㈣於該財反射率時,該彳貞錯模电二 判斷該晶圓係不適合被該至少_製程模組所處理。 2. 如中請專利範圍第Μ所述之晶圓處理系統, 該摘錯模組之該感測器係一光學式感測器。 ’、 3. 如中請專利範圍第!項所述之晶圓處理系統, 該至少一製程步驟包含一沉積步。 /、中 .如申明專利粑圍第3項所述之晶圓處理系統,1中 該沉積步驟係用以沉積一金屬層。 5. 如申請專利範圍第4項所述之晶圓處理系統,复中 該預疋反射率為該金屬層的反射率。 6. 如申請專利範圍第5項所述之晶圓處理系統,其中 13 200814135 該金屬層為一鎢金屬層。 二如::專利範圍第6項所述之晶圓處理“ 預疋反射率為該鎢金屬層的反射率。 8·如巾4專㈣圍第3項所述之晶κ處理系^ 儿積步驟為一化學氣相沉積步驟。 9·如申清專利範圍帛3項所述之晶圓處理系胡 Μ沉積步驟為一物理氣相沉積步驟。 10·如申睛專利範圍第1項所述之晶圓處理系έ 該至少-製程步驟包含一平坦化步驟,用以平坦化 11〜如中請專利範圍帛1G所述之晶圓處理系 該預疋反射率為該材料層在平坦化後的反射率。 一 12.如申睛專利範圍第1〇項所述之晶圓處理系 中該平坦化步驟為一化學機械研磨步驟。 U•一種晶圓處理系統,至少包含: 一前端模組,用以容置至少一晶圓; 至少一製程模組,設置於該前端模組之後段,用 ’其中 其中 ’其中 其中 一材料 統,其 統,其 以對該 14 200814135 晶圓進行至少一製程步驟;以及 一偵錯模組,設置於該前端模組舆該製程模組之間,其 中該偵錯模組設有一感測器,用以感測該晶圓之一表面反射 率,該偵錯模組係以一預定反射率來做為偵錯判斷標準,♦ 反射率係實質不㈣該預定反射率時,該㈣模組; 判斷該晶圓係不適合被該至少一製程模組所處理。200814135 X. Patent Application Range 1 · A wafer processing system comprising at least: a front end module for accommodating at least one wafer; at least a process module disposed at a later stage of the front end module and using a wafer At least one process step; and the 积-debug module is disposed between the front end module and the process module, and the debug module is provided with a sensor for sensing the wafer. Table ς rate, (4) wrong module sen - predetermined reflectivity as a debugging standard, prepared for the surface reflection (four) substantial (four) at the financial reflectivity, the erroneous mode 2 determines that the wafer system is not suitable for the At least _ process module processing. 2. The wafer processing system of claim 1, wherein the sensor of the error module is an optical sensor. ’, 3. Please ask for the scope of patents! The wafer processing system of claim 1, wherein the at least one process step comprises a deposition step. In the wafer processing system of claim 3, the deposition step is for depositing a metal layer. 5. The wafer processing system of claim 4, wherein the pre-turn reflectance is a reflectivity of the metal layer. 6. The wafer processing system of claim 5, wherein 13 200814135 the metal layer is a tungsten metal layer. For example: The wafer processing described in item 6 of the patent scope “pre-reflection reflectivity is the reflectivity of the tungsten metal layer. 8.························ The step is a chemical vapor deposition step. 9. The wafer processing system according to the scope of the patent application 帛 3 is a physical vapor deposition step. 10 · As stated in claim 1 The wafer processing system έ the at least-process step includes a planarization step for planarization 11~ the wafer processing system described in the patent scope 帛1G, the pre-reflection rate is after the material layer is flattened The flattening step is a chemical mechanical polishing step in the wafer processing system described in the first aspect of the patent application. U• A wafer processing system comprising at least: a front end module For accommodating at least one wafer; at least one process module is disposed at a later stage of the front end module, and one of the materials is used to perform at least one of the 14 200814135 wafers Process steps; and a debug module, Positioned between the front end module and the process module, wherein the debug module is provided with a sensor for sensing a surface reflectivity of the wafer, the debug module having a predetermined reflectivity As the detection criterion, ♦ the reflectivity is not (4) the predetermined reflectivity, the (four) module; determining that the wafer is not suitable for being processed by the at least one process module. H·如申請專利範圍第 中該至少一製程步驟包含一 料層。 13項所述之晶圓處理系統,其 平坦化步驟,用以平坦化一材 中二如申請專利範圍第13項所述之晶圓處理系統,其 以預疋反射率為該材料層的反射率。 八 16·如申請專利範圍第13項所述之晶圓處理系統,盆 “平坦化步驟為一化學機械研磨步驟。 /、、 ’、 1 7 ·如申5青專利範圍第 中該至少一製程牛=項所述之晶圓處理系統,其 I^驟包含一沉積步驟。 二專利範圍第13項所述之晶圓處理系 學氣相沉積步驟。 中該沉積步驟為一化 統,其 19·如申請專利範 圍第13項所述之晶圓處理系統,其 15 200814135 中該沉積步驟為一物理氣相沉積步驟。 2〇· —種晶圓處理方法,至少包含: 提供一晶圓; 在進行至少一製程步驟前,偵測該晶圓之一表面反射 率;以及 以一預定表面反射率做為偵錯判斷標準,來判斷該晶圓 是否適合被該至少一製程模組所處理,其中當該表面反射率 係貝貝相等於該預定反射率時,該晶圓係不適合被該至少一 製程模組所處理。 21. 如申請專利範圍第2〇項所述之晶圓處理方法,其 中該至少一製程步驟包含一沉積步驟。 22. 如申請專利範圍第21項所述之晶圓處理方法,其 中該沉積步驟係用以沉積一金屬層。 23·如申請專利範圍第22項所述之晶圓處理方法,其 中該預定反射率為該金屬層的反射率。 八 24·如申請專利範圍第22項所述之晶圓處理 中該金屬層為一鎢金屬層。 沄,某 25·如申請專利範圍第24項所述之晶圓處理方法,其 16 200814135 的反射率 中該預定反射率為該鎢金屬展 26·如申請專利範圍第 中該沉積步驟為一化學氣相 2 1項所述之晶眉處理方 沉積步驟。 法,其 27·如申請專利範圍第 中5亥沉積步驟為一物理氣相 21項所述之晶圓處理方法 沉積步驟。 ,其H. As in the scope of the patent application, the at least one process step comprises a layer. The wafer processing system of claim 13, wherein the flattening step is used to planarize a wafer processing system as described in claim 13 of the patent application, wherein the pre-reflection reflectance is a reflection of the material layer rate. 8.16. The wafer processing system according to claim 13 of the patent application scope, the "flattening step is a chemical mechanical polishing step. /,, ', 1 7 · The application of the at least one process of the claim 5 The wafer processing system described in the above clause comprises a deposition step. The wafer processing system vapor deposition step described in claim 13 of the patent scope. The deposition step is a chemical system, wherein The wafer processing system of claim 13, wherein the deposition step in 15 200814135 is a physical vapor deposition step. 2. A wafer processing method comprising at least: providing a wafer; Detecting a surface reflectance of the wafer before performing at least one process step; and determining whether the wafer is suitable for processing by the at least one process module by using a predetermined surface reflectance as a debugging criterion When the surface reflectance is equal to the predetermined reflectance, the wafer is unsuitable for being processed by the at least one process module. 21. The wafer processing method according to claim 2, The at least one process step includes a deposition step. The wafer processing method of claim 21, wherein the depositing step is to deposit a metal layer. The wafer processing method, wherein the predetermined reflectance is a reflectance of the metal layer. 824. The metal layer is a tungsten metal layer in the wafer processing described in claim 22 of the patent application. The wafer processing method according to claim 24, wherein the predetermined reflectance of the reflectance of 16 200814135 is the tungsten metal exhibit 26; as in the patent application, the deposition step is a chemical vapor phase 2 1 The method of depositing a crystal eyebrow processing method according to the item, wherein the method of depositing a wafer processing method according to the physical gas phase 21 is as described in the patent application scope. 28·如申請專利範圍第 中該至少一製程步驟包含一 2〇項所述之晶圓處理方法,其 平坦化步驟。 29· —種晶圓處理方法,至少包含: 提供一晶圓; 在進仃至少一製程步驟前,偵測該晶圓之一表面反射 率;以及 ^以一預定表面反射率做為偵錯判斷標準,來判斷該晶圓 疋否適合被該至少一製程模組所處理,其中當該表面反射率 係貝貝不同於該預定反射率時,該晶圓係不適合被該至少一 製程模組所處理。 30·如申請專利範圍第29項所述之晶圓處理方法,其 中該至少一製程步驟包含一平坦化步驟,用以平坦化一材 料層。 17 200814135 31. 如申請專利範圍第30項所述之晶圓處理方法,其 中該預定反射率為該材料層的反射率。 32. 如申請專利範圍第30項所述之晶圓處理系統,其 中該平坦化步驟為一化學機械研磨步驟。 33. 如申請專利範圍第29項所述之晶圓處理方法,其 中該至少一製程步驟包含一沉積步驟。 34. 如申請專利範圍第33項所述之晶圓處理方法,其 中該沉積步驟為一化學氣相沉積步驟。 3 5.如申請專利範圍第33項所述之晶圓處理方法,其 中該沉積步驟為一物理氣相沉積步驟。 1828. The method of claim </ RTI> wherein the at least one process step comprises the wafer processing method of claim 2, the planarizing step. The method of processing a wafer includes at least: providing a wafer; detecting a surface reflectance of the wafer before performing at least one process step; and determining a predetermined surface reflectance as a debugging a standard for determining whether the wafer is suitable for processing by the at least one process module, wherein when the surface reflectance is different from the predetermined reflectance, the wafer is not suitable for being processed by the at least one process module deal with. The wafer processing method of claim 29, wherein the at least one process step comprises a planarization step for planarizing a material layer. The wafer processing method of claim 30, wherein the predetermined reflectance is a reflectance of the material layer. 32. The wafer processing system of claim 30, wherein the planarizing step is a chemical mechanical polishing step. 33. The wafer processing method of claim 29, wherein the at least one process step comprises a deposition step. 34. The wafer processing method of claim 33, wherein the depositing step is a chemical vapor deposition step. 3. The wafer processing method of claim 33, wherein the depositing step is a physical vapor deposition step. 18
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