TW200813713A - Managing bad blocks in flash memory for electronic data flash card - Google Patents

Abstract

An electronic data flash card accessible by a host computer, includes a flash memory controller connected to a flash memory device, and an input-output interface circuit activated to establish a communication with the host. In an embodiment, the flash card uses a USB interface circuit for communication with the host. A flash memory controller includes an arbitrator for mapping logical addresses with physical block addresses, and for performing block management operations including: storing reassigned data to available blocks, relocating valid data in obsolete blocks to said available blocks and reassigning logical block addresses to physical block addresses of said available blocks, finding bad blocks of the flash memory device and replacing with reserve blocks, erasing obsolete blocks for recycling after relocating valid data to available blocks, and erase count wear leveling of blocks, etc. Furthermore, each flash memory device includes an internal buffer for accelerating the block management operations.

Description

200813713200813713

V 九、發明說明： 【發明所屬之技術領域】 本發明涉及電子資料快閃記憶體卡，更具體地說，是 關於電子資料快閃記憶體卡中快閃記憶體設備的快閃記 憶體塊控制的系統和方法。 【先前技術】V IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD The present invention relates to an electronic data flash memory card, and more particularly to a flash memory block for a flash memory device in an electronic data flash memory card. Control systems and methods. [Prior Art]

機检資料檔案通常存儲在軟碟中，或者通過需要口 令或者安全加密的網路傳送。機密文檔則通過安全封印發 迗。然而，口令、加密、安全封印都有可能遭到破壞（被 解雄、），從而給機密資料檔案和機密文檔帶來危險，導致 機密資訊被未授權存取。 隨著快閃記憶體技術變得越來越先進，快閃記憶體正 逐步取代在移動系統中作爲存儲介質的傳統磁片的地 位。和軟碟或磁性介質硬碟相比，快閃記憶體具有以下一 些顯著優點：高阻抗和低功率耗散。由於快閃記憶體的物 理尺寸小，更加有利於移動系統的發展。相應地，快閃記 憶體的發展也得益於其與移動系統的相容性和低功耗。 然而，快閃記憶體也有其固有限制。首先，已編程的 快閃記憶體單元必須經過擦除才能進行再次編程。同時， 快閃記憶體單元只有有限的使用壽命；即，快閃記憶體單Machine inspection data files are usually stored on a floppy disk or transmitted over a network that requires a password or secure encryption. Confidential documents are issued via a secure seal. However, passwords, encryption, and security seals can be compromised (distracted), posing a danger to confidential data files and confidential documents, resulting in unauthorized access to confidential information. As flash memory technology becomes more advanced, flash memory is gradually replacing the traditional magnetic disk as a storage medium in mobile systems. Flash memory has several significant advantages over floppy or magnetic media hard disks: high impedance and low power dissipation. Due to the small physical size of the flash memory, it is more conducive to the development of mobile systems. Accordingly, the development of flash memory has also benefited from its compatibility with mobile systems and low power consumption. However, flash memory also has its inherent limitations. First, the programmed flash memory unit must be erased to be reprogrammed. At the same time, the flash memory unit has a limited lifetime; that is, the flash memory unit

元在失效前只能進行有限次數的擦除操作。例如，NAND 快閃記憶體單元典型的最大擦除次數爲一 • ㈡馬次。相應 200813713 地，由於“寫入前擦除’’的特點，快閃記憶體存取速度較 慢’而且反復的擦除操作將會損壞快閃記憶體單元。 快閃記憶體設備的存儲單元陣列由典型的基本結構構 成，即分爲“磁區”或“頁面”，並由“磁區，，或“頁 面構成塊。一個磁區由5 12個位元組（小塊格式） 或2 112個位元組（大塊袼式）構成一個資料段，由i 6個 位元組或64個位元組構成一個備用段。一個塊由一組磁 區構成，例如：16、32、64或更多磁區，磁區數量根據具 • 體情況確定。如果其中某個磁區包含一個或多個無效存儲 單元（即，編程或擦除操作過程中，一個或多個存儲單元 無法實現既定的最小操作狀態），則認爲這是一個“壞” 塊。如果一個塊的全部存儲單元都功能完好，則認爲這是 一個“好”塊。 快閃記憶體設備可能一開始就有大量壞塊（例如， 10 Λ )此外，快閃§己憶體設備原來的好塊也可能在製造商 規定的使用壽命之内變成壞塊。這些壞塊將在快閃記憶體 _ 設備的寫入或擦除操作中表現出來。不幸的是，不斷增加 的壞塊發生率極大地降低了快閃記憶體系統的性能。 大部分快閃記憶體系統（例如，電子資料快閃記憶體 卡）同時使用多個快閃記憶體設備，並通過在多個快閃記 憶體設備陣列中搜索可用好塊的方法來解決壞塊問題。存 儲在壞塊中的有效資料（或分配給壞塊的資料）需要重新 分配或重新放置在一個或多個可用好塊中。傳統方法在系 統全部快閃記憶體設備中搜索具有可用好磁區的可用好 6 200813713 塊，在搜索過程中，典型的重新分配/重新放置過程包括— 個把資料傳輪外部緩衝區的過程（，存儲到快閃記憶體 設備之外）。如果找到了足夠數量的可用好磁區，再把該 資料寫回這些塊中。 Λ 上述傳統重新分配/重新放置過程可能會出現的一個 問題，即如果一個或多個快閃記憶體設備達到容量極限 (即，沒有剩餘可用好塊），則快閃記憶體系統必須繼續 搜索其他快閃記憶體設備，直到搜索到具有足夠數量的可 用好磁區的可用好塊。這可能導致外部緩衝區擁塞，從而 導致快閃記憶體系統的總體性能的降低。 快閃記憶體設備中可用好塊的數量隨著快閃記憶體設 備存儲里越來越接近容量和過期（無效）塊數量的增加而 減少。過期塊是指包含過期磁區的好塊，過期磁區是指存 儲過有負料而該資料又被更新過的磁區。資料被更新後， 過期貝料仍保留在過期磁區中，被更新資料則被寫入新磁 品該新磁^即成爲包含有效資料的有效磁區。有效資料 匕括被更新資料和未被更新資料。相應地，過期塊數量將 隨著文件修改或刪除而增加。 過期塊通常通過“垃圾回收”操作迴圈使用。在“垃 圾回收”操作過程中，過期塊將被擦除以便再次執行寫入 操作。過期塊可能同時包含過期資料和有效資料。有效資 料必須在過期塊被擦除前複製到可用好塊中。在垃圾回收 操作中’過期塊中的有效資料將複製到外部缓衝區，然後 執行可用好塊搜索程式，在全部快閃記憶體設備中搜索和 7 200813713The element can only perform a limited number of erase operations before it fails. For example, a typical NAND flash memory cell has a maximum number of erasures of one (two) horses. Corresponding to 200813713, due to the "scratch before writing" feature, the flash memory access speed is slower' and repeated erase operations will damage the flash memory cell. Memory cell array of flash memory device It consists of a typical basic structure, which is divided into "magnetic regions" or "pages" and consists of "magnetic regions," or "page blocks. One magnetic region consists of 5 12 bytes (small block format) or 2 112 A byte (large block) forms a data segment consisting of i 6 bytes or 64 bytes forming a spare segment. A block consists of a set of magnetic regions, for example: 16, 32, 64 or More magnetic regions, the number of magnetic regions is determined according to the physical condition. If one of the magnetic regions contains one or more invalid memory cells (ie, one or more memory cells cannot be achieved during a program or erase operation) The minimum operating state) is considered to be a "bad" block. If all the memory cells of a block are functionally intact, then this is considered a "good" block. Flash memory devices may have a lot of bad at first. Block (for example, 10 Λ) In addition, the original good block of the flash memory device may also become a bad block within the lifetime specified by the manufacturer. These bad blocks will be displayed in the flash memory_device write or erase operation. Unfortunately, the increasing incidence of bad blocks greatly reduces the performance of flash memory systems. Most flash memory systems (for example, electronic data flash memory cards) use multiple flash memory devices simultaneously. And solve the bad block problem by searching for a good block in the array of multiple flash memory devices. The valid data stored in the bad block (or the data allocated to the bad block) needs to be reassigned or relocated in one Or a plurality of available good blocks. The traditional method searches for all available flash memory devices in the system with available good magnetic regions. In the search process, the typical redistribution/relocation process includes - The process of transferring the external buffer (storage to the flash memory device). If a sufficient number of available magnetic regions are found, write the data back to these blocks.可能 A problem that may arise with the above traditional redistribution/relocation process, that is, if one or more flash memory devices reach the capacity limit (ie, no good blocks remain available), the flash memory system must continue to search. Other flash memory devices until a good number of available blocks with a sufficient number of available magnetic regions are searched. This may cause external buffer congestion, resulting in a reduction in the overall performance of the flash memory system. The number of available blocks decreases as the number of blocks in the flash memory device storage gets closer to the capacity and the number of expired (invalid) blocks. The expired block is a good block containing the expired magnetic area, and the expired magnetic area is stored. The magnetic area has the negative material and the data has been updated. After the data is updated, the expired material remains in the expired magnetic area, and the updated data is written into the new magnetic product, which becomes the valid data. Effective magnetic area. Valid information includes updated and unupdated data. Accordingly, the number of expired blocks will increase as files are modified or deleted. Expired blocks are usually looped through the "garbage collection" operation. During the “garbage collection” operation, the expired block will be erased to perform the write operation again. An expired block may contain both expired and valid data. Valid data must be copied to the available blocks before the expired block is erased. In the garbage collection operation, the valid data in the 'expired block' will be copied to the external buffer, and then the available good block search program will be searched for in all flash memory devices and 7 200813713

定位可用好塊。一旦可用好塊搜索成功，外部緩衝區中的 有效資料將被複製回可用好塊中。和重新分配/重新放置過 程相同，傳統的垃圾回收操作也可能發生外部緩衝區擁塞 問題’導致快閃記憶體系統總體性能的降低。 另一個壞塊解決方案爲包括塊替換過程的“損耗平 衡操作。在該操作中，有效資料將從一個塊向另一個塊 轉移’從而使資料分佈更加均勻。然而，該操作同樣包括 外部緩衝區操作和多個設備中可用好塊的搜索操作過 程。如上所述，該操作也可能導致外部緩衝區擁塞，導致 快閃冗憶體系統總體性能的降低。 通吊傳、统方法沒有解決在多個快閃記憶體設備中搜 索可用好塊所需的附加處理時間的問題，並且這些問題目 前還沒有—個很好的解決方案。已知㈣決方㈣ 解決搜索㈣中外部緩祕潛在的擁塞問題n 限制都將影響壞塊管理、垃圾回收和損耗平衡的效率， 因此’我們需要一套改進的快閃記憶體控制系統和方 。广糸和方法必須能解決處理壞塊、崎回收和損耗 平衡過程中可用好塊搜索所需處理時間的問題。同時，、 系統和方法必須簡單可行、成本合理並且可以备= 術方便地實現。本發”目的就是要解決 “技 【發明内容】 本發明主要針對包含快 3氏閃彡己憶體設備的電子資 記憶體卡、指紋感測器、輪 、科〖夬閃 翰入/輸出介面電路和處理單元。 8 200813713 電子資料快閃記憶體卡可通過主機（外部電腦）存取，例 如個人電腦，筆記本電腦或其他電子主機設備。由於電子 貝料快閃圯憶體卡的便攜性和耐用性，個人資料可以用加 密形式存儲在快閃記憶體設備中，這樣只有通過諸如卡身 上的指紋感測n之類的安全措施才能存取，確保不被未授 權人員誤用。Positioning is available in good blocks. Once the available good block search is successful, the valid data in the external buffer will be copied back to the available good blocks. As with the redistribution/replacement process, traditional garbage collection operations can also suffer from external buffer congestion problems, resulting in a reduction in overall performance of the flash memory system. Another bad block solution is the "loss-balance operation of the block replacement process, in which valid data is transferred from one block to another" to make the data distribution more uniform. However, this operation also includes an external buffer. Operation and multi-device search operation process of good block. As mentioned above, this operation may also cause external buffer congestion, resulting in a decrease in the overall performance of the flash memory system. The problem of additional processing time required to search for available blocks in a flash memory device, and these problems are not yet a good solution. Known (4) The solution (4) Solve the potential congestion of external mitigation in search (4) Problem n restrictions will affect the efficiency of bad block management, garbage collection and wear leveling, so 'we need an improved flash memory control system and method. The vast and method must be able to solve the bad block, the recovery and loss. The problem of processing time required for good block search in the balancing process. At the same time, the system and method must be simple and feasible, cost-combined And the invention can be conveniently implemented. The purpose of the present invention is to solve the problem. The present invention is mainly directed to an electronic memory card, a fingerprint sensor, a wheel, and a device including a fast flash memory device.夬 夬 翰 入 入 入 输出 8 8 8 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 The portability and durability of the flash memory card, the personal data can be stored in the flash memory device in encrypted form, so that it can be accessed only by security measures such as fingerprint sensing n on the card body, ensuring that it is not Unauthorized personnel misuse.

本發明中，快閃記憶體控制器作爲處理單元的一部分 =快閃記憶體設備的操作。處理單元與快閃記憶體設備 快二：出介面電路相連接。快閃記憶體控制器邏輯包括 爲快二：體類型演算法，用於檢測該快閃記憶體設備是否 將快閃:己憶體控制器邏輯所支援的快閃記憶體類型。通過 儲在、隱體檢測凟算法代碼動態部分連同機密資料存 體卡唯^個快閃記憶體設備中，不但電子資料快閃記憶 記=::體，)的大小可以降低，而且新的快閃 中快閃記憶體體調整而僅需調整存儲於快閃記憶體 援。這樣既降低1檢測演异法代碼的動態部分即可被支 間。 _ 了總體成本又和消除了不必要的開發時 根據本發明另一個實施 的處理覃；π 寬子貝枓快閃記憶體卡 編程模式、資 下二個工作狀態下··可 枓頊取模式、重定模式。當處理i _步#τ 編程模式時，虚师0 — 田羼理早7G處於可 处理早疋啟動輪入/ 機的機密資料拎奢 ；輪出"面電路接收來自主 中。當處理、 ’、儲存在快閃記憶體設備 处理早％處於資料讀取模式 丁 處理早兀啟動輸入 9 200813713 /輸出介面電路把資料檔案傳輸到主機中。 資料重定模式時，資料栲崇r 田处里早70處於 兮“ 案（以及參考用指紋資料）將從 該快閃記憶體設備中被擦除。 针）將攸 ’二本發明實施方案中中，處理單元爲-個微處理哭， 该微處理器可以是8〇51、8〇52 8〇2 时In the present invention, the flash memory controller is part of the processing unit = the operation of the flash memory device. Processing unit and flash memory device Fast 2: The interface of the interface is connected. The flash memory controller logic includes a fast type 2: body type algorithm for detecting whether the flash memory device will flash: the type of flash memory supported by the memory controller logic. Through the stored and hidden detection 凟 algorithm code dynamic part together with the confidential data storage card only ^ flash memory device, not only the size of the electronic data flash memory =:: body,) can be reduced, and the new fast Flash flash memory body adjustment and only need to adjust the memory stored in the flash memory. This reduces the dynamic portion of the 1 detection algorithm and can be branched. _ The overall cost and the elimination of unnecessary development according to another embodiment of the present invention; π wide sub-beak flash memory card programming mode, under the two working states · · capture mode , re-mode. When processing the i_step#τ programming mode, the virtual master 0—Tian Lili 7G is in the process of handling the confidential information of the early starter/intake; the round-out "face circuit reception comes from the main. When processing, ', stored in the flash memory device processing is early in the data read mode D processing early start input 9 200813713 / output interface circuit to transfer the data file to the host. When the data is re-determined, the data will be erased from the flash memory device in the field (the reference fingerprint data) will be erased. The needle will be used in the embodiment of the invention. The processing unit is crying for a micro-processing, the microprocessor can be 8〇51, 8〇52 8〇2

或數位信號處理n (DSP)。 RM、MIPS 在本發明貝知方案中’輸入’輸出（I USB ^ 0 I ®冤路才木Or digital signal processing n (DSP). RM, MIPS 'input' output in the invention of the present invention (I USB ^ 0 I ® 才路才木

T六rxj記憶體設備^T six rxj memory device ^

主機之間採用批量僂輪f RnTΛ u A ) 速傳輸資料。由3 Β Ο T傳輸的命令、資祖、 、枓狀恶不但依賴於默認控制終端Μ 遞依賴於批量終端點，所 πτ Μ ΰυΓ協定是一種比CBI協j 更加高效而且快速的傳輸協定。The host uses a batch f wheel f RnTΛ u A ) to transfer data. The commands, ancestors, and scorpions transmitted by 3 Β Ο T depend not only on the default control terminal, but also on the batch termination point. The πτ Μ ΰυΓ protocol is a more efficient and fast transmission protocol than the CBI protocol.

在本發明另一個實施方案中，電子資料快閃記憶體卡 (或：他决閃β己憶體系統）包含帶有處理器的快閃記憶體 控制器’該處理器負責和系統連接的多個快閃記憶體設備 的塊管理操作。這些塊管理操作包括壞塊識別、過期塊回 收二損耗平衡操作。本發明中，處理器利用來自仲裁邏輯 的貝料，在塊管理操作中，把可用好塊搜索限制在某個特 定的快閃記憶體設備中’而不像傳統方法那樣在全部快閃 記憶體設備中進行搜d外，在某個快閃記憶體設備中 搜索可用好塊4 ’處理||將利用該快閃記憶體設備的内部 緩衝區儲存有效資料。通過把可用好塊搜索限制在一個特 疋决閃δ£憶體⑨備中’並使用指定快閃記憶體設備的内部 200813713 緩衝區，本發明可減少可用好塊搜索時間並消除對外邱緩 衝區使用的需要，從而可以避免外部緩衝區擁夷， 友 ^ 提向傳 統快閃記憶體糸統的性能。相應地，塊管理操作的速声將 有顯著提高。 X: 【實施方式】 參看圖1，根據本發明實施方案，電子資料快閃記憶 體卡10可通過介面匯流排13、讀卡器12或其他介面機= (圖中未示）被外部電腦（主機）9存取，電子資料快閃 記憶體卡10包括卡身i、處理單元2、一個或多個快閃記 憶體設備3、指紋感測器4、輸入/輸出介面電路5、可選 顯示單元6、可選電源（例如’電池）7、可選功能鍵广 快閃記憶體設備3安裝於卡身}上， 卜牙1上以已知方式儲存 了-個或多個資料檔案、參考口令以及通過掃描,電子資料 快閃記憶體卡㈣一個或多個授權用戶指紋獲得的參考 指纹資料。只有授權用戶能存取所儲存的資料標案。該資 料檔案可以爲圖片文件或文字檔案。 、 指紋感測器4安裝於卡身1上， ρ弓々_触上 通過知描電子資料快 閃圮憶體卡10的用戶指紋產生 播 ^ d^^ ^ 日紋知描資料。指紋感測 器4可參考本發明人共同擁 能力的積體電路卡”，專利號爲、6=利帶有指紋識別 m ^ j, ., ^ … 547，130，本發明採 用該專利的技術方案。t诚护 置-陆上述扣紋感蜊器專利包括一個掃描 陣列，該陣列定義了指紋掃描區域。〆纹播π勺 括通過掃描相應的掃描單元陣料日㈣描-貝料包 早夕〗線而獲得的大量掃描線 11 200813713 育料。掃描單元陣列線按照行和列的方式進行掃描◊各掃 描單元若檢測到持卡人指紋脊則産生第—邏輯信號，若檢 測到指紋持卡人指紋穀則産生第二邏輯信號。 輸入/輸出介面電路5安裝於卡身丨上，啟動後，介面 匯流排13或讀卡器12通過適當的插口建立和主機9之間 的通訊。在本發明的一個實施方案中，輸入/輸出介面電路 5包含一個咖、…禮八或RS232介面電路和控制邏輯 結構，可與連接至或安裝於主機9的插口相連。在另一個 #實施方案中’輸入/輸出介面電路5包含SD介面電路、MMC 介面電路、CF介面電路、MS介面電路、pci_Exp⑽介 面電路、介面電路、SATA彳面電路，這些電路通過 介面匯流排13或讀卡器12和主機9連接。 处里單元2女裝於卡身1上，通過卡身1上的導電線 路與與快閃記憶體設備3、指紋感測器4和輸入/輸出介面 電路5連接。在本發明的一個實施方案中，處理單元2可 採：英代爾公司的8051、8052《8〇286微處理器。在其 _ 貝轭方案中，處理單元2採用RISc、A·、皿?8或其 7數位信號處理器（DSP)。本發明中，處理單元2至少受 儲存在快閃s己憶體設備3中的程式控制，這樣處理單 2 2可以通過選擇在以下三種模式下工作：⑴可編程模 '在該杈式下，處理單元2啟動輸入/輸出介面電路5 接收來自主機9的資料檔案和參考指紋資料，並把資料檔 $和參考指紋資料儲存在快閃記憶體設備3中；（2 )資料 靖取杈式：在該模式下，處理單元2啟動輸入/輸出介面電 12 200813713 路5把存儲於快閃記憶 ο ψ . r 」T的貝枓檔案傳輸到主柢 _’（3)貧料重定模式：在該模式下，資料 和參考 才日紋資料將從快閃士产# ' 、U己隱體，又備3中擦除。操 主機9 通過介面匯流排η七冷本 乍中 發送寫入卜 和輸人/輪出介面電路5 =和項取請求到電子資料快閃記憶體卡ι〇上的處 "二：2,處理單元2通過快閃記憶體控制器（圖中未示) ::或：個快閃記憶體設備3讀取或向其寫入資料。在 /明的-個實施方案中’爲了進一步確保安全一旦檢 、'子儲於决閃δ己憶體設備3的資料樓案自上一次授權存 ::超過了預設的時間極限，處理單元2將自動啓動重定 操作。 一可選電源7安裝於卡身1上，並與卡纟1上的處理單 和其他相關單元相連，爲其提供電源。 、力犯鍵8女裝於卡身1上，並與處理單元2連接， :過選擇可使處理單元2工作於編程、資料讀取或資料重 一模式功此鍵8可用於輸入處理單元2的口令。處理單 二 料的口令和存儲在快閃記憶體設備3中的參考口 進仃比#又’右輪入口令和參考口令一致，則啓動電子資 閃記憶體卡i 0的授權操作。 並心•員示單元6安裝於卡身1上，與處理單元2相連 發又二控制，用於顯示與主機9之間交換的資料檔案以及 '子貝料快閃記憶體卡1〇的操作狀態。 雜卡：的大部分優點:首先’電子資料快閃記憶 、 谷里大，所以資料傳輸方便；其次，由於指 13 200813713 = ::::電子資料快閃記憶體卡只允許授權人員存取 卡上儲存的賢料檔案，從而提高了安全性。 本發明其他特點和優點如下。 ::爲本發明優選實施方案的電子資料快閃記憶體卡 方框圖’丨中省略了指紋感測器和相關用戶識別程式 二二4 了降低集成成本，，電子資料快閃記憶體卡i〇a包 括：個尚度集成的處理單元2A、輸入/輸出介面電路5A 和快閃記憶體控制器21。輸入/輸出介面電路从包括一個 收發器模組列介面引擎塊、資料緩衝器、暫存器和中 斷邏輯。輸入/輸出介面電路5A和内部匯流排相連，使輸 矜„出”面電路5 A各個單元都能和快閃記憶體控制器21 的各單元通訊。快閃記憶體控制@ 21包括一個微處理器 单元、唯讀記憶體（R0M)、RAM、快閃記憶體控制器邏 輯、錯誤校正代碼邏輯、通用輸入/輪出（GPI〇)邏輯。 在本發明的一個實施方案中，Gpi〇邏輯和數個led相 連，用於狀態指示，例如：電源良好，快閃記憶體讀取/ 寫入中等，或和其他I/O設備相連，快閃記憶體控制器2 1 和一個或多個快閃記憶體設備3相連。 在本實施方案中，主機9A設有功能鍵8A ,在電子資 料〖夬閃記憶體卡1 〇 A操作過程中，通過介面匯流排或讀卡 器和處理單元2 A連接。功能键8 A用於選擇電子資料快閃 尤憶體卡10 A的工作模式：編程、資料讀取或資料重定模 式。功能鍵8A同時可用于向主機9A輸入口令。處理單元 2A把輪入的口令和存儲在快閃記憶體設備3中的參考口 14 200813713 令進行比較，若輸人π令和參考口令—致，則㈣電子資 料快閃記憶體卡10Α的授權操作。 同時在本實施方案中，主機9Α設有顯示單元6八，在 =電子資料快閃記憶體卡1GA的過程中，通過介面匯流 排或讀卡II與處理單S2A連接。單元从用於顯示盘主機 :狀父態換的資料播案以及電子資料快閃記憶體卡i〇A的操 圖3爲處理單元2A的詳細框圖。電子資料快閃記憶 元設有功率調^仏用於向-個或多個處理單 _供電。電源根據電子資料快閃記憶體卡 疋不同的要求提供不同電壓的電源。電”（圖中未干） ==高電源穩定性。電子資料快閃記憶體卡i〇A設有 重疋電路23,用於向處理單元2八 重定電路23向全部單元重疋㈣。上電後， 穩定… 信號。當内部電壓達到 " 後，撤銷重定信號，由電阻器和電容5| Γ 1S1 Φ去 示）俘埒4电谷(圖中未 心時?Γ 調整，電子資料快閃記憶體卡 〇A R時包括—個石英晶體振蕩 單元2A内的PLL提供基頻。 ”“)，向處理 在本發明的實施方案中，輸入/ 定電路上方 甸出”面電路5A、重 疋電路23、功率調節器22被集 2A内。土含錄古巷丄一 1刀杲成在處理單元 &種鬲集成度大大減少了所需的咖BB 製造成本。 而的工間、複雜度和 緊被性和成本對移動設備至關重 的電子資料快閃記憶體卡。現代Ic封"匕這裏所涉及 裒T从在一個1C封 15 200813713In another embodiment of the present invention, the electronic data flash memory card (or: his flashback beta memory system) includes a flash memory controller with a processor that is responsible for the connection with the system. Block management operations for flash memory devices. These block management operations include bad block identification, expired block recovery, and two wear leveling operations. In the present invention, the processor utilizes the material from the arbitration logic to limit the available good block search to a particular flash memory device in the block management operation 'instead of all flash memory as in the conventional method. In the device to search for, in a flash memory device search for a good block 4 'processing|| will use the internal buffer of the flash memory device to store valid data. By limiting the available block search to a special flash memory and using the internal 200813713 buffer of the specified flash memory device, the present invention can reduce the available block search time and eliminate the use of the external buffer. The need to avoid external buffers, friends ^ to the performance of traditional flash memory. Accordingly, the speed of the block management operation will be significantly improved. X: Embodiments Referring to FIG. 1, an electronic data flash memory card 10 can be externally connected via an interface bus 13, a card reader 12, or other interface machine (not shown) according to an embodiment of the present invention ( Host 9 access, electronic data flash memory card 10 includes card body i, processing unit 2, one or more flash memory devices 3, fingerprint sensor 4, input / output interface circuit 5, optional display Unit 6, optional power supply (such as 'battery) 7, optional function key wide flash memory device 3 mounted on the card body, on the tooth 1 stored in a known manner - one or more data files, reference Password and reference fingerprint data obtained by scanning, electronic data flash memory card (4) one or more authorized user fingerprints. Only authorized users can access the stored data standard. The data file can be an image file or a text file. The fingerprint sensor 4 is mounted on the card body 1, and the ρ 々 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The fingerprint sensor 4 can refer to the integrated circuit card of the inventor of the present invention. The patent number is 6, 6= with fingerprint identification m ^ j, ., ^ 547, 130, and the invention adopts the technology of the patent. The scheme of the above-mentioned buckle-sensing device includes a scanning array, which defines a fingerprint scanning area. The 〆 播 播 通过 通过 通过 扫描 扫描 扫描 扫描 扫描 扫描 扫描 扫描 扫描 扫描 扫描 扫描 扫描 扫描 扫描 扫描 扫描 扫描 扫描 扫描 扫描A large number of scanning lines obtained in the eve of the line 11 200813713. The scanning unit array lines are scanned in rows and columns. Each scanning unit generates a first logic signal if a cardholder fingerprint ridge is detected, and if a fingerprint is detected, The card person fingerprint valley generates a second logic signal. The input/output interface circuit 5 is mounted on the card body, and after startup, the interface bus bar 13 or the card reader 12 establishes communication with the host computer 9 through an appropriate socket. In one embodiment of the present invention, the input/output interface circuit 5 includes a coffee, ... or RS232 interface circuit and control logic structure that can be connected to a jack that is connected to or mounted to the host 9. In another #implementation In the scheme, the input/output interface circuit 5 includes an SD interface circuit, an MMC interface circuit, a CF interface circuit, an MS interface circuit, a pci_Exp(10) interface circuit, an interface circuit, and a SATA port circuit, and these circuits pass through the interface bus 13 or the card reader 12 The unit 2 is connected to the main body 2. The unit 2 is attached to the card body 1, and is connected to the flash memory device 3, the fingerprint sensor 4, and the input/output interface circuit 5 through a conductive line on the card body 1. In one embodiment of the invention, the processing unit 2 can take the 8051, 8052 "8 〇 286 microprocessor of the Intel Corporation. In its _ yoke scheme, the processing unit 2 uses RISc, A ·, Dish 8 or Its 7-digit signal processor (DSP). In the present invention, the processing unit 2 is controlled by at least a program stored in the flash memory device 3, so that the processing unit 2 2 can be operated by selecting the following three modes: (1) Programmable Mode 'In this mode, the processing unit 2 activates the input/output interface circuit 5 to receive the data file and reference fingerprint data from the host 9 and stores the data file $ and the reference fingerprint data in the flash memory device 3 ;(2) capital In this mode, the processing unit 2 activates the input/output interface power 12 200813713 Road 5 Transfers the Bellow files stored in the flash memory ο r . r ”T to the main 柢 _'(3) poor Material re-setting mode: In this mode, the data and reference data will be erased from Flash Player #', U-Hidden, and 3. The host computer 9 sends a write buffer and an input/round interface circuit 5 through the interface bus η7 coldbook, and a request to the electronic data flash memory card ι〇2: 2, The processing unit 2 reads or writes data to the flash memory controller (not shown) :: or : a flash memory device 3 . In the embodiment of the invention, in order to further ensure the safety of the inspection, the data of the sub-storage device has been stored since the last time: exceeds the preset time limit, the processing unit 2 will automatically start the re-operation. An optional power source 7 is mounted to the card body 1 and is coupled to a processing unit and other associated units on the cassette 1 to provide power thereto. The key 8 is placed on the body 1 and connected to the processing unit 2: the selection can cause the processing unit 2 to operate in the programming, data reading or data re-mode mode. The key 8 can be used to input the processing unit 2 Password. The password for processing the single material and the reference port stored in the flash memory device 3 coincide with the #又' right wheel entry command and the reference password, and the authorization operation of the electronic flash memory card i 0 is started. The centering member unit 6 is mounted on the card body 1, and is connected to the processing unit 2 for two-fold control, for displaying the data file exchanged with the host computer 9 and the operation of the 'sub-battery flash memory card 1'. status. Miscellaneous card: Most of the advantages: First of all, 'electronic data flash memory, large valley, so the data transmission is convenient; secondly, because the finger 13 200813713 = :::: electronic data flash memory card only allows authorized personnel to access the card The storage of the sages file, which improves security. Other features and advantages of the invention are as follows. :: The electronic data flash memory card block diagram of the preferred embodiment of the present invention omits the fingerprint sensor and related user identification program. The lower the integration cost, the electronic data flash memory card i〇a The utility model comprises: a processing unit 2A integrated with an input, an input/output interface circuit 5A and a flash memory controller 21. The input/output interface circuitry includes a transceiver module column interface engine block, data buffer, scratchpad, and interrupt logic. The input/output interface circuit 5A is connected to the internal bus bar so that each unit of the output circuit 5A can communicate with each unit of the flash memory controller 21. Flash Memory Control @ 21 includes a microprocessor unit, read-only memory (R0M), RAM, flash memory controller logic, error correction code logic, and general-purpose input/round-out (GPI〇) logic. In one embodiment of the invention, the Gpi〇 logic is connected to a plurality of LEDs for status indication, such as: good power, flash memory read/write, etc., or connected to other I/O devices, flashing The memory controller 2 1 is connected to one or more flash memory devices 3. In the present embodiment, the main unit 9A is provided with a function key 8A which is connected to the processing unit 2A through the interface bus or card reader during the operation of the electronic data flash memory card 1 〇 A. Function key 8 A is used to select the flash of the electronic data. The working mode of the memory card 10 A: programming, data reading or data re-setting mode. The function key 8A can also be used to input a password to the host 9A at the same time. The processing unit 2A compares the entered password with the reference port 14 200813713 stored in the flash memory device 3, and if the input π command and the reference password are used, then (4) the authorization of the electronic data flash memory card 10Α operating. At the same time, in the present embodiment, the host unit 9 is provided with a display unit 6-8. In the process of = electronic data flash memory card 1GA, it is connected to the processing unit S2A through the interface bus or card II. The unit 3 is a detailed block diagram of the processing unit 2A from the data broadcast for displaying the disk host: the parental state and the electronic data flash memory card i〇A. The electronic data flash memory unit is provided with a power adjustment unit for supplying power to one or more processing units. The power supply provides power for different voltages according to the different requirements of the electronic data flash memory card. Electric" (not shown in the figure) == high power supply stability. The electronic data flash memory card i〇A is provided with a reset circuit 23 for resetting the processing unit 2 to the all-unit (4). After the electric power, stabilize... signal. When the internal voltage reaches ", the re-reset signal is cancelled, and the resistor and capacitor 5| Γ 1S1 Φ are shown to capture the 4 electric valley (the picture is not in the heart? Γ adjustment, electronic data is fast The flash memory card 〇AR includes a PLL in the quartz crystal oscillating unit 2A to provide a fundamental frequency. ""), in the embodiment of the present invention, the input/fixed circuit is over the "face" circuit 5A, The circuit 23 and the power conditioner 22 are integrated in the 2A. The soil contains the ancient alleys and one knives in the processing unit & the integration of the species greatly reduces the cost of manufacturing the required coffee BB. The labor, complexity, and tightness of the flash memory card are critical to mobile devices. Modern Ic seal "匕 involved here 裒T from a 1C seal 15 200813713

元件。例如，輸 混合信號 .混合電路，可與處理單元集 重定電路和功率調節器爲類 集成到MCP (多晶片封裝） 1C技術本質上允許同時集成類比和數位電 路口此更兩度的集成技術可納入處理單元模具中， 包括輸入/輸出介面電路5A、快閃記憶體控制器Η、重定 ❿ 電路23和功率調節器22。 在優選的實現方案中，通過利用多晶片封裝技術或混 合信號IC技術，實現處理單元2、輸入/輸出介面電路5、 功率調即器22和重定電路23集成或部分集成。 快閃兄憶體技術的進步促使了各種類型快閃記憶體設 備的出現，以滿足對不同性能、成本和容量的需求。例如， 對於相同的形狀係數，多層單元（MLC”夬閃記憶體設備 比單層單元（SLC )快閃記憶體設備具有更高的容量。and 籲或Super_AND快閃記憶體則被發明用於避開NAND快閃 記憶體的知識産權問題。同時，大頁面（2K位元組）快 閃記憶體比小頁面（512位元組）快閃記憶體具有更好的 寫入性能。此外，快閃記憶體的快速發展使得設備的容量 不斷提高。爲了支援這些不同類型的快閃記憶體，快閃記 憶體控制器必須能夠相應地進行檢測和存取。 在本發明的思想和範圍之内，可同時或獨立實現上述 各新穎特點。例如，圖4爲本發明另一個實施方案的電子 16 200813713 資料快閃記憶體卡loc (或電子資料儲 卡）。根據上述一個或多個實施方案，、體電路 被主機9A存取，由卡身ic、處理單元2C 、 快閃記憶體設備3C構成，其中處理 次夕個 ^ ,f 处里早70 2C由快閃記憶體element. For example, the mixed-signal hybrid circuit can be integrated with the processing unit set re-sizing circuit and the power regulator into the MCP (multi-chip package). The 1C technology essentially allows for the simultaneous integration of analog and digital circuit ports. It is incorporated into the processing unit mold, and includes an input/output interface circuit 5A, a flash memory controller Η, a reset ❿ circuit 23, and a power conditioner 22. In a preferred implementation, the processing unit 2, the input/output interface circuit 5, the power modulator 22, and the re-sizing circuit 23 are integrated or partially integrated by utilizing multi-die packaging techniques or mixed-signal IC techniques. Advances in flash memory technology have led to the emergence of various types of flash memory devices to meet different performance, cost and capacity requirements. For example, for the same form factor, multi-level cell (MLC) flash memory devices have higher capacity than single-layer cell (SLC) flash memory devices. And calls or Super_AND flash memory are invented for avoidance. Open NAND flash memory intellectual property issues. At the same time, large page (2K bytes) flash memory has better write performance than small page (512 bytes) flash memory. In addition, flash The rapid development of memory has led to an increase in the capacity of devices. To support these different types of flash memory, the flash memory controller must be able to detect and access accordingly. Within the scope and scope of the present invention, The novel features described above are implemented simultaneously or independently. For example, FIG. 4 is an electronic 16 200813713 data flash memory card loc (or electronic data storage card) according to another embodiment of the present invention. According to one or more embodiments described above, The circuit is accessed by the host 9A, and is composed of a card body ic, a processing unit 2C, and a flash memory device 3C, wherein the processing is performed on the second night, and the f is 70 2C by the flash memory.

控制益2lc和輸入/輸出介面電路5C構成。電子資料快閃 記憶體卡貴可以是上述電子資料快閃記憶體卡心的功 能子系統，也可以是其他應用系統的功能子系統。 快閃記憶體設備3C t快閃記憶體控帝J|f 2ic產生的 〒7控制，並在快閃記憶體設備中儲存資料檔案。 處理單凡2C通過上述輸入/輸出介面電路與快閃記憶 體又備連接處理單元2C中的快閃記憶體控制器2 1C通 過個或夕個上述方法控制快閃記憶體設備3C。在本發明 的一俩實施方案中，快閃記憶體控制器21C通過執行快閃 °己隐體類型、廣算法（利用存儲於唯讀記憶體（ROM )(圖 中未不）的快閃記憶體控制器邏輯靜態部分）確定快閃記 It體认備3 C疋否被支援；如果是“新”的快閃記憶體類 型’則讀取存儲於快閃記憶體設備3C中的快閃記憶體控 制器邏輯動態部分。 另一方面，啟動輸入/輸出介面電路5C後，通過介面 連接裝置和主機9A建立BOT通訊。主機和快閃記憶體設 備（以下也稱爲“ USB設備” ）USB介面電路之間有四種 類型的USB軟體通訊資料流程：控制、中斷、批量和同步。 控制傳輸是主機通過控制管道向USB設備發送的資料流 17 200813713 私用於向USB設備提供配置和控制資訊。中斷傳輪爲小 貝料ΐ、非周期性、固定等待時間、設備發起的通訊，通 ΐ用於通知主機USB設備所請求的服務。如果沒有即時性 要求，通過USB介面電路移動的大塊資料可採用抵量傳 輸。同步傳輸在同步資料工作時使用。同步傳輸在主機和 USB叹備之間提供周期性和連續性的通訊。介面電路 通㊉支援兩種資料傳輸協定：CBI協定和BOT協定。海量 儲存類CBI傳輸規範適用於全速軟碟驅動，而不適用於= 速没備或軟碟驅動以外的其他設備（由USB規範確定）。 在本發明實施方案中中，峨㈣記憶體設備和主機二 =傳輸高速資料只採用B0T協定。由於BOT傳輸的命令、 貝料、狀恶同時傳輸到批量終端點和默認控制終端點，所 、 疋種比CBI協定更加高效和快速的傳輸協定。 根據前述實現方案，當處理單元2C可通過選擇工作於 α扁程模式下％’處理單元2€啟動輸入/輸出介面 以接收爽白幸德ΟΑ从二欠山、丨^ ^Control Benefit 2lc and input/output interface circuit 5C are constructed. Electronic data flash memory card memory can be the functional subsystem of the above-mentioned electronic data flash memory card core, or it can be the function subsystem of other application systems. The flash memory device 3C t flash memory control device J|f 2ic generates the 〒7 control and stores the data file in the flash memory device. The processing unit 2C controls the flash memory device 3C through the above-described input/output interface circuit and the flash memory controller 2 1C in the flash memory and connection processing unit 2C by one or more of the above methods. In one embodiment of the present invention, the flash memory controller 21C performs flash memory by using a flash type, a wide algorithm (using flash memory stored in a read-only memory (ROM) (not shown). The body controller logic static part) determines whether the flash memory It is 3 C is not supported; if it is a "new" flash memory type, then reads the flash memory stored in the flash memory device 3C Controller logic dynamic part. On the other hand, after the input/output interface circuit 5C is activated, BOT communication is established with the host 9A through the interface connecting means. There are four types of USB software communication data flow between the host and flash memory devices (hereafter referred to as "USB devices") USB interface circuits: control, interrupt, batch, and sync. The control transfer is the flow of data sent by the host to the USB device through the control pipeline. 17 200813713 Privately used to provide configuration and control information to the USB device. The interrupted transfer is a small, aperiodic, fixed wait time, device-initiated communication that is used to notify the host of the requested service by the USB device. If there is no immediacy requirement, the bulk data moved through the USB interface circuit can be transmitted by offset. Synchronous transfer is used when working with synchronized data. Synchronous transmission provides periodic and continuous communication between the host and the USB scream. Interface Circuits Ten supports two data transfer protocols: the CBI Agreement and the BOT Agreement. Massive storage class CBI transmission specifications apply to full-speed floppy drives, not to devices other than flash or floppy drives (as determined by the USB specification). In the embodiment of the present invention, the 峨(4) memory device and the host 2=transmit high-speed data only use the B0T protocol. Due to the BOT transmission of commands, shells, and spoofs simultaneously transmitted to the batch terminal point and the default control terminal point, it is a more efficient and faster transmission protocol than the CBI protocol. According to the foregoing implementation, when the processing unit 2C can select to operate in the alpha flat mode, the %' processing unit 2 starts the input/output interface to receive the cool white singer from the two owing mountains, 丨 ^ ^

7L 2C工作於資料重定模式下時， 體設備3C中被擦除。 3C中的資料，並啟動輸 I輸至主機9Α;當處理單 資料擋案將從快閃記憶 18 200813713 f 本發明中智慧處理單元2C的優點包括： (1) 高集成度，大大減少了所需空間、複雜度和製造 成本； (2) 通過把軟體程式和資料保存在快閃記憶體中，降 低了控制器成本； (3)採用先進的快閃記憶體控制邏輯 憶體的存取速度 以下爲本發明中所使用的術語定義。塊··基本記憶體 擦除單元。各塊包含一定數量的磁區，例如16、32、64 等。如果某個磁區發生寫入錯誤，則整個塊即被確認爲壞 塊，並且該塊内其他全部有效磁區將被重新放置到另一個 塊中。磁區：塊的子單元。典型的磁區由兩個段構成―資 料段和備用段。過期磁區：在編程過程中存儲了資料，而 該資料又隨後被更新的磁區。資料被更新後，過期資料被 保留在過期磁區中，而更新後的資料則被寫入新磁區，新 磁區即成爲有效磁區。無效塊：包含過期磁區的塊。有效 磁區：在編程過程中存儲了資料並且該資料爲當前（未過 期）資料的磁區。損耗平衡：爲了延長快閃記憶體的使用 壽命而均勻分配各快閃記憶體塊擦除次數的方法。快閃記 憶體塊只能承受有限次的擦除操作。例如，典型的να· 快閃記憶體的最大擦除次數爲一百曾a 蚁舄百萬次。備用塊：快閃記 憶體中的保留空間。備用嬙你灿L „ — ^ 爾用塊使快閃記憶體系統可以提前準 備處理壞塊。簇··爲了改盖农性f "存儲性成，作業系統用作文件 存取指標的多個資料磁區。右丨* b 4 在小谷篁記憶體操作中，一個 19 200813713 簇通常由兩個資料磁區構成，簇爲最小的文件大小單元。 典型的記憶體小塊的叙大小爲1 k位元組（即各磁區大小 爲5 12位元組），記憶體大塊的簇大小爲4k位元組（即各 磁區大小爲2 ’ 112位元組）° FAT :保存指向文件地址指 標的文件分配表。簇是FAT指向的最小單元。例如，FAT16 是指簇的地址爲16位。目錄和子目錄：作業系統所定義 的文件指標。主引導記錄（MBR):用於儲存根目錄指標 和相關引導文件（如果可引導）的固定位置。該固定位置 爲第一個塊的最後一個磁區’如果第一個是壞塊，則爲第 二個塊的最後一個磁區。包：USB基本事務單元的可變長 度格式。-個常規的符合USB規範的事務通常由三個包·· 權標（Token)包、資料包和信號交換/交握（Handshake)包。 權標包有m’ 0UT和SETUP三種格式。資料包的大小可 變，例如，USB1.1版爲64位元組，USB2 〇版爲512位元 組。信號交換/交握包有ACK戋NAK炊斗、 及N AK格式，用於通知主機 事務是否完成。晝面（Frame):抵詈When the 7L 2C operates in the data re-setting mode, the body device 3C is erased. The data in 3C, and start the input I to the host 9Α; when processing the single data file will be flash memory 18 200813713 f The advantages of the smart processing unit 2C in the present invention include: (1) high integration, greatly reducing the Space, complexity and manufacturing cost; (2) Reduce the cost of the controller by storing the software program and data in the flash memory; (3) Using the advanced flash memory to control the access speed of the logic memory The following is a definition of the terms used in the present invention. Block··Basic Memory Erase unit. Each block contains a certain number of magnetic regions, such as 16, 32, 64, and the like. If a sector has a write error, the entire block is identified as a bad block and all other valid sectors in the block are relocated to the other block. Magnetic area: A subunit of a block. A typical magnetic zone consists of two segments—a data segment and a spare segment. Expired magnetic zone: A magnetic area that is stored during programming and that is subsequently updated. After the data is updated, the expired data is retained in the expired magnetic area, and the updated data is written into the new magnetic area, and the new magnetic area becomes the effective magnetic area. Invalid block: A block containing an expired magnetic zone. Active Magnetic Zone: The data is stored during programming and is the magnetic area of the current (unexpired) data. Loss Balance: A method of evenly distributing the number of erases of each flash memory block in order to extend the life of the flash memory. Flash memory blocks can only withstand a limited number of erase operations. For example, a typical να· flash memory has a maximum number of erasures of one hundred and one a million. Spare block: Flashes the reserved space in the volume. You can use the block to make the flash memory system ready to deal with bad blocks in advance. Clusters · In order to change the agricultural f " storage, the operating system is used as a file access indicator Data area. Right 丨* b 4 In the operation of the small valley memory, a 19 200813713 cluster usually consists of two data areas, the cluster is the smallest file size unit. The typical memory size is 1 k. The byte group (that is, the size of each magnetic area is 5 12 bytes), and the cluster size of the memory block is 4k bytes (that is, the size of each magnetic area is 2 '112 bytes). FAT: Save to point to file address The file allocation table of the indicator. The cluster is the smallest unit pointed to by FAT. For example, FAT16 means that the cluster address is 16 bits. Directory and subdirectory: file indicators defined by the operating system. Master Boot Record (MBR): used to store the root directory The fixed position of the indicator and the associated boot file (if bootable). The fixed position is the last extent of the first block. 'If the first one is a bad block, it is the last extent of the second block. Package: Variable length of USB basic transaction unit Degree format. A regular USB-compliant transaction is usually composed of three packets, a token package, a data packet, and a handshake/handshake package. The token package has three formats: m' 0UT and SETUP. The size of the data package is variable, for example, the USB1.1 version is 64-bit tuple, and the USB2 〇 version is 512-bit tuple. The handshake/handshake package has ACK, NAK, and N AK format for notification. Whether the host transaction is completed. Frame: Arrival

^ }肌里爭務處理，如果USB 流量爲低，則對佔有書面且有莴 ^ 一 、兩π優先順序。如果USB流量 爲高’批量事務也能等待後續書 ,^ K |面、冬螭點··三個終端點 包括控制、批量輪入和批量輪 缺生丨& 抓从粗α θ ^ 翰出。控制終端點用於系統初 始枚舉。批置輸入終端點用七 鳊點用作主機糸統讀取資料管道。批 里輸出終端點用作主Μ备 (CBWV相人 寫入資料管道。命令塊包 ILBW)· —個命令換由七 如資w“ 個命令塊和相關資訊，例 如貝枓傳輸長度（例如512 丨儿几組，攸第8位元组5篦1 1 位元組）〇CBW開始干3诅兀、、且至弟11 Ί始于包邊界，結束於第31位元組（位元 20 200813713 王部CBW傳輸都應按照從 組0to30 )，以小包形式傳送 最低有效位元（位元組0)向最高有效位元的順序排列。 命令狀態包（CSW): CSW開始于包邊界。精簡塊命令 (RB C ) S C SI協定：10位元組命令描述符。^ } Intramuscular contingency processing, if the USB traffic is low, then the possession is written and has a π, π priority order. If the USB traffic is high, the batch transaction can also wait for the follow-up book. ^K|面,冬螭点··Three terminal points including control, batch round-in and batch round shortage 丨& grab from coarse α θ ^ . Control terminal points are used for initial enumeration of the system. The input input terminal point is used as a host to read the data pipe. The output terminal point in the batch is used as the main backup device (CBWV phase human input data pipeline. Command block packet ILBW) · One command is exchanged by seven such as "command block" and related information, such as Bellow transmission length (for example, 512)丨 几 攸 攸 攸 攸 攸 攸 攸 攸 攸 攸 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 The king CBW transmission shall be transmitted in the order of the least significant bit (byte 0) in the form of a packet to the most significant bit in the form of a packet. Command State Packet (CSW): CSW starts at the packet boundary. Command (RB C ) SC SI Protocol: 10-bit command descriptor.

圖5爲本發明另一個實施方案的電子資料快閃記憶體 卡（記憶體系統）100方框圖。快閃記憶體系統1〇〇通過 介面轉換邏輯102和主機系統52相連，介面轉換邏輯1〇2 負責爲微處理器1〇4處理資料和時序校準。根據不同的應 用環境，介面轉換邏輯102相容多種袼式 PCI-Express、CF、SD、MMC、MS、IDE 等 ’例如 USB、 。主機系統52 可以是個人電腦（PC)、數碼照相機、MP3播放器等。 微處理器104在快閃記憶體系統1〇〇内部執行讀取、 寫入、擦除操作、塊管理操作和其他内務操作。塊管理操 作包括複製和擦除操作，通過後臺運行，即，對主機系統 52隱蔽。唯讀記憶體（R0M) 106用於儲存微處理器ι〇4 操作執行代碼。 微處理器104通過仲裁邏輯106對快閃記憶體系統1〇〇 的各快閃記憶體設備ll〇a、11015和u〇c分別執行塊管理 操作。仲裁邏輯可通過硬體邏輯或可編程邏輯設備實現 (例如’現場可編程閘陣列（FPGAs ))。 暫存器文件112爲快閃記憶體設備丨i 〇a_c分配邏輯塊 地址。映射表114提供了快閃記憶體設備u〇a_e相關的資 訊索引。這些資訊包括邏輯塊地址、設備編號、實體位址 (hy si cal Base Address，PBA)、有效位元和過期位。快閃 21 200813713 記憶體介面控制器116與快閃記憶體u〇a_c連接，執行來 自處理器104的命令。這類命令包括讀取、寫入和擦除操 作。 ^ 圖6爲本發明圖5所示快閃記憶體系統1〇〇的仲裁邏 輯⑽、暫存器文件112和映射表114之間的詳細方框圖。 主機系統52向快閃記憶體系統1〇〇發送邏輯塊位址Μ]。 邏輯塊位址302包含一個磁區偏移位址。 暫存斋文件112負責在各邏輯塊地址3〇2和特定的快 籲μ記憶體設備編號之間建立聯繫。例如，若邏輯塊地址在 第-地址範圍之内’則指向快閃記憶體設備編號u〇a，若 邏輯塊地址在第二地址範圍之内，則指向快閃記㈣設備 編號ll〇b’以此類推❶仲裁邏輯108發送邏輯塊位址和相 _設備編號至映射表114。各快閃記憶體設備位址容量預 先編程保存在相應的暫存器114a]14e中供邏輯塊位址指 派一各特疋的快閃§己憶體設備的實體位址（pBA )被 仲裁邏輯1 0 8確定，全部讀敌/宜 丨項取/寫入刼作都將在設備内部被 • 執行。 映射表114把各邏輯塊位址翻譯成相應的實體位址， 並把設備編號和實體位从絡φ s 貝瓶伹址輸出至快閃記憶體介面控制器 116索引映射表114由一個或多個查詢表（)構成， 可通過易失性隨即存取$ ,隆辨 通|仔取记隐體（RAM)實現，例如靜態 RAM ( SRAM )。在木恭明沾 ^ 桊毛明的一個實現方案中，快閃記憶體 設備11〇a、U〇b和U〇C分別對應映射表114a、114b和 114c。例如，表U4a儲存快閃記憶體設備ll〇a的物理塊 22 200813713 地址貧訊，表114b儲存快閃記憶體設備U〇b的物理塊地 址貝訊，而表114c則儲存快閃記憶體設備〗1〇c的物理塊 T址資訊。映射表114把邏輯塊位址翻譯成由仲裁邏輯1〇8 提供的特定設備編號實體位址。映射表114同時還提供有 效位的值。有效位的值在上電過程中被置零。上電後，快 閃記憶體110首先被掃描以重建映射表114。 在初始化過程中，特定磁區最大量的擦除操作被編程 • 寫入暫存器文件丨12用於地址仲裁。快閃記憶體介面控制 _旨116向特定的㈣記憶體㈣11G發送—系列時序信 號，執行快閃記憶體設備110塊管理相關的寫入和擦除操 由於快閃記憶體設肖110a_c的各暫存器可以獨立編 程’快閃記憶體系、统100的各個快閃記憶體設備ii〇w可 以具有不同的資料儲存容量。甚至可以採用不同品牌的快 閃記憶體設備。這種靈活性降低了總體製造成本。在各快 閃記憶體設備110a_c内部的頁面大小，即各物理磁區的位 元組數應相同（例如，512位元組或2112位元組）。 囷爲傳 '、先塊管理操作方框圖。從圖中可以看出，有 效貝料存儲在快閃記憶體設備A中塊4〇4的磁區術a、 4〇2b和4G2e中。在—個塊管理操作（例如，壞塊替換、 過期塊回收或損耗平衡）過程中，如果磁區術&，侧 和術c變成壞塊、過期或需要進行損耗平衡，存儲在磁區 。a 402b和402c中的有效資料將被重新放置。塊管理 操作通常被稱爲内務操作。這些操作通常以後臺方式完 23 200813713 成，以方便後續寫入操作。本例中的塊管理操作爲壞塊替 換操作。 從圖中可以看出，有效資料首先被重新放置（即複製） 到外部缓衝區406中。然後在其他快閃記憶體設備中執行 可用好塊（即功能塊）搜索程式。傳統的快閃記憶體系統 把多個快閃記憶體設備當作統一的全局單元處理。相應 地，全部快閃記憶體設備的塊都按照全局地址方案分配地Figure 5 is a block diagram of an electronic data flash memory card (memory system) 100 in accordance with another embodiment of the present invention. The flash memory system 1 is coupled to host system 52 via interface conversion logic 102, which is responsible for processing data and timing calibration for microprocessors 1〇4. Depending on the application environment, the interface conversion logic 102 is compatible with a variety of PCI-Express, CF, SD, MMC, MS, IDE, etc., such as USB. The host system 52 can be a personal computer (PC), a digital camera, an MP3 player, or the like. The microprocessor 104 performs read, write, erase operations, block management operations, and other housekeeping operations within the flash memory system. Block management operations include copy and erase operations, running through the background, i.e., concealing host system 52. Read Only Memory (R0M) 106 is used to store the microprocessor ι〇4 operation execution code. The microprocessor 104 performs block management operations on the respective flash memory devices 110a, 11015, and u〇c of the flash memory system 1 by arbitration logic 106, respectively. Arbitration logic can be implemented by hardware logic or programmable logic devices (eg, 'field programmable gate arrays (FPGAs)). The scratchpad file 112 assigns a logical block address to the flash memory device 丨i 〇a_c. The mapping table 114 provides the information index associated with the flash memory device u〇a_e. This information includes logical block addresses, device numbers, hysi cal base addresses (PBAs), valid bits, and expiration bits. Flash 21 21713713 The memory interface controller 116 is coupled to the flash memory u〇a_c to execute commands from the processor 104. Such commands include read, write, and erase operations. Figure 6 is a detailed block diagram of the arbitration logic (10), the scratchpad file 112, and the mapping table 114 of the flash memory system shown in Figure 5 of the present invention. The host system 52 sends a logical block address Μ to the flash memory system. Logical block address 302 contains a sector offset address. The staging file 112 is responsible for establishing a link between each logical block address 3〇2 and a particular fast μ device memory device number. For example, if the logical block address is within the first address range, then it points to the flash memory device number u〇a, and if the logical block address is within the second address range, it points to the flash (four) device number ll〇b' Such push-pull arbitration logic 108 sends the logical block address and phase_device number to mapping table 114. Each flash memory device address capacity is pre-programmed in the corresponding scratchpad 114a] 14e for the logical block address to assign a special flash § hex memory device physical address (pBA) to be arbitrated logic 1 0 8 confirms that all read/received items/writes will be executed inside the device. The mapping table 114 translates each logical block address into a corresponding physical address, and outputs the device number and the physical bit from the network φ s vial address to the flash memory interface controller 116. The index mapping table 114 is composed of one or more A lookup table () consists of a volatile access random $ (RAM) implementation, such as static RAM (SRAM). In an implementation of Kim Kumi-Ming, the flash memory devices 11a, U〇b, and U〇C correspond to mapping tables 114a, 114b, and 114c, respectively. For example, the table U4a stores the physical block 22 of the flash memory device 11a, the address is poor, the table 114b stores the physical block address of the flash memory device U〇b, and the table 114c stores the flash memory device. 〗 1 〇 c physical block T site information. The mapping table 114 translates the logical block address into a specific device number entity address provided by the arbitration logic 〇8. The mapping table 114 also provides values for the valid bits. The value of the valid bit is set to zero during power-up. After power up, the flash memory 110 is first scanned to reconstruct the mapping table 114. During initialization, the maximum amount of erase operation for a particular sector is programmed • Write to scratchpad file 丨12 for address arbitration. Flash memory interface control _ 116 to a specific (four) memory (four) 11G transmission - series timing signals, perform flash memory device 110 block management related write and erase operations due to the flash memory settings 110a_c The memory can be independently programmed. 'Flash memory system, each flash memory device of the system 100 can have different data storage capacity. It is even possible to use different brands of flash memory devices. This flexibility reduces overall manufacturing costs. The page size within each flash memory device 110a-c, i.e., the number of bytes per physical magnetic region, should be the same (e.g., 512 bytes or 2112 bytes).囷为传', block diagram of the first block management operation. As can be seen from the figure, the effective bead material is stored in the magnetic regions a, 4〇2b and 4G2e of the block 4〇4 in the flash memory device A. In the case of a block management operation (for example, bad block replacement, expired block recovery or wear leveling), if the magnetic zone &, the side and the surgery c become bad blocks, expire or need to be wear level balanced, stored in the magnetic zone. The valid data in a 402b and 402c will be relocated. Block management operations are often referred to as housekeeping operations. These operations are usually done in the background mode to facilitate subsequent write operations. The block management operation in this example is a bad block replacement operation. As can be seen from the figure, the valid data is first relocated (i.e., copied) to the external buffer 406. Then, a good block (ie, function block) search program is executed in other flash memory devices. Traditional flash memory systems treat multiple flash memory devices as a unified global unit. Correspondingly, all blocks of the flash memory device are allocated according to the global address scheme.

址，這樣，全部快閃記憶體設備都將進行搜索。如果在另 一個快閃記憶體設備B的塊408中搜索到可用好磁區，則 把有效資料複製到快閃記憶體設備B的好磁區中。在其他 塊管理操作中，外部緩衝區406起相同的作用。 圖8疋爲本發明的塊管理操作方框圖。從圖中可以看 出，有效資料存儲在快閃記憶體設備504中的塊5〇3的磁 區502a、502b* 502c中。在塊管理操作過程中存儲在 磁區502a、502b和502c的有效資料將被重新放置。So, all flash memory devices will search. If a good magnetic zone is found in block 408 of another flash memory device B, the valid data is copied to the good magnetic zone of flash memory device B. External buffer 406 plays the same role in other block management operations. Figure 8 is a block diagram showing the block management operation of the present invention. As can be seen from the figure, the valid data is stored in the magnetic regions 502a, 502b* 502c of the block 5〇3 in the flash memory device 504. The valid data stored in magnetic regions 502a, 502b, and 502c during the block management operation will be relocated.

在本發月中各快閃s己憶體設備執行獨立的塊管理操 作，並在各快閃記憶體設備邊界内部執行。換句話說，在 塊管理操作過程中，存儲在快閃記憶體設# nGa中的有 效資料被重新放置在同一個快閃記憶體設備内部的最佳 位置（即，資料不是轉移到其他快閃記憶體設肖11〇b或 ⑽中）。傳統塊管轉作把有效資料錢放置在不同的 快閃記憶肢備中，與傳統塊管理操作㈣，本發明通過 有效二料重新放置操作限制在同一快閃記憶體設備之 内’提高了總體系統的性能。傳統塊管理操作存在的問題 24 200813713 是可用好塊的搜索範圍太大，需要搜索多 備。此外，傳統塊管理摔作要t 、 D 體没 mi 乍要求使用外部緩衝區（彻^ =所示的頁面緩衝區科把有效資料從-個快閃二 -備傳輸到外部緩衝區，然後再傳輸到另—個 ； 體設備將增加總體操作時間。本發明通過對各快閃二 =執：獨立的塊管理操作來解決該問題，這樣塊管：摔 作可以在各快閃記憶體設備的内部執行。 ’、In the current month, each flash memory device performs independent block management operations and is executed inside the boundaries of each flash memory device. In other words, during the block management operation, the valid data stored in the flash memory device is reset to the optimal position inside the same flash memory device (ie, the data is not transferred to other flashes). The memory is set to 11〇b or (10)). The traditional block tube is transferred to place the effective data in different flash memory limbs, and the traditional block management operation (4), the invention is limited to the same flash memory device by the effective two-material relocation operation 'improving the overall system Performance. Problems with traditional block management operations 24 200813713 The search range for available good blocks is too large and you need to search for multiple devices. In addition, the traditional block management falls to t, D body does not require the use of an external buffer (the page buffer section shown in ^^ = transfers the valid data from the flash to the external buffer, and then Transfer to another; the body device will increase the overall operating time. The present invention solves this problem by performing a separate flash management operation, such as a block management operation, such that the fall can be performed on each flash memory device. Internal execution. ',

本發明的另-個優點是塊管理操作可以在多個快閃纪 憶體設備内部同步發生’從而進-步提高了快閃記情體； 統的性能°例如’第―個資料重新放置操作可以在第一個 快閃記憶體設備内執行，同時第二個資料重新放置摔作在 第二個快閃記憶體設備内執行。同時也使不同快閃記憶體 設備可时擦除和編程。系統並行㈣提高㈣提高了快 閃S己憶體系統的性能。 本例中的塊管理操作爲壞塊替換操作。如果磁區 502a、502b和502c變成壞磁區，則存儲在磁區5〇^，“η 和502 c的有效資料將被重新放置。在本實施方案中，有 效 > 料將被複製到内部緩衝區5〇6中。内部緩衝區是 在快閃記憶體設備504内部功能正常的易失性記憶體磁 區。在本發明的一個實現方案中，易失性記憶體磁區的塊 被預留用於向各快閃記憶體設備提供内部緩衝區5〇6，這 樣可以減少對外部搜索的需求（即在快閃記憶體設備的邊 界之外的搜索）。可用好塊搜索在快閃記憶體設備504内部 其他部分中執行。各快閃記憶體設備的全部塊地址都根據 25 200813713 为散式地址方案分配’如圖8所示，同時全部搜索都被限 制在快閃έ己憶體設備的邊界之内。 搜索到好塊之後’有效資料將被複製到一個或多個好 塊中。無論哪種情況，相比於圖7所示的傳統多晶片搜索 方法，單晶片搜索大大降低了搜索時間。同時，由於壞塊 操作發生在快閃記憶體設備5〇4内部，有效資料重新放置 時間大大減少。本發明消除了對外部緩衝區的需求。相應 地’由於無需把有效資料轉移到外部快閃記憶體設備 504，重新放置時間也大大減少。 本發明的其他塊管理操作過程中，内部緩衝區5〇6也 起相同的作用。另一個方案時，在塊管理操作過程中，有 效貢料無需先被存儲到内部緩衝區5〇6中而被直接重新放 置到好磁區中。 本發明中，各快閃記憶體設備作爲獨立定址單元工 作，並且塊管理操作在各快閃記憶體設備邊界之内發生。 相應地本务明的另一個優點是在同一個快閃記憶體系統 之内可以使用不同容量的快閃記憶體設備。 圖9是本發明的快閃記憶體塊管理方法高級流程圖。 百先，在具有數個快閃記憶體設備的快閃記憶體系統中啓 動至 >一項操作，參考步驟6〇2。在本實施方案中爲塊管 理操作。下一步，在快閃記憶體設備之内搜索目標塊，參 考步驟604。下-步，有效資料在快閃記憶體設備内部從 源塊向目的塊被重新放置，參考步驟6〇6。相應地，多個 快閃記憶體設備可同時執行塊管理操作。在多個快閃記憶 26 200813713 體設備執行塊管理操作 自内部執行獨立的二 快閃記憶體設備都在各 行獨立、同步作。各快閃記憶體設備都能進 圖1❹爲本發明的振Ρ目^ 、己憶體設備700的詳細方框圖， 該方框圖可用於實現 情體嗖備70"八 快閃記憶體設備，快閃記 彳刀配了 一個邏輯塊地址範圍，邏輯塊位址 的摩έ*圍由圖5所示66 /占此 、十裁邏輯Ι0δ決定。快閃記憶體設備 700的物理塊地址從跫 7開始一直增加到快閃記憶體設備 700的最大容量。圖中蚩 一 τ忠出了不列塊706a、706b、706c和 7〇6d。706a 和 706b 分別 a 7 ^ 刀別爲弟一和弟二個實體位址塊而 7〇6d爲最後一個實體位址塊。 在本實施方案中，磁區（通常稱爲頁面）7(Π包含528 個位元組，其中包括512個位隸的賴段和Μ個位元 組的備用段。快閃記恃， G體5又備70〇的資料結構由實體位址 706a、706b、706c 和 7a人-々·ι 、 @ 7〇6d的資料段702和備用段704構 成。各段都有一定的位分έθ紅 疋幻位70組數，該位元組數由具體應用決 疋。例如’資料段可以包含512位元組、UP位元組或更 多位元組，制段可以包含16、64或更多位元組。 貝料段702儲存原始資料，而備用段7〇4儲存記憶體 管理相關資訊。備用段704包括有效磁區段710、過期磁 區段712、壞塊指示段714、擦除計數段716、錯誤校正代 碼（ECC)段718和邏輯塊位址磁區㈣段72q。 區段710用於指示是否磁區中的資料可被有效讀取。過期 磁區段712爲標諸段’用於指示磁區中的資料是否過期標 27 200813713 諸。若發生了後續的寫入或擦除操作，則過期標誌可以被 修改。壞塊指示段7 14用於指示壞塊。在本發明的一個實 施方案中’把〇值存儲於壞塊指示段714用於指示該塊已 被損壞。若嘗試寫入特定磁區或擦除特定塊失敗，則認爲 該塊爲壞塊。在具體的實現方案中，壞塊指示由工廠設置 確疋。快閃s己憶體糸統的固件通過掃描各塊的第一磁區來 確定資料是否能被存取。完整的掃描資訊隨後被保存到各 快閃5己f思體設備最後的塊中。 # 在本實施方案中，用兩個位元組（16位元）來記錄各 塊（16磁區）的壞塊資訊。用兩個磁區（1〇24位元組） 記錄快閃記憶體設備（最多5 12個塊）的壞塊資訊。爲了 達到更高的可靠性，儲存了八份完全相同的壞塊資訊備 伤，以避免在標遠、記錄過程中發生磁區變壞事故。爲了實 現快速存取，這些八份備份都存儲在各快閃記憶體設備的 最後一個塊位置706d中。壞磁區指示段714被保存在最 後塊706d中，以便更方便地被快閃記憶體系統的固件讀 ⑩ 取。 擦除計數段716用於記錄一個塊將在該快閃記憶體設 備整個使用壽命内被擦除的次數。擦除計數段716包含三 個位元組，最多可記錄1600萬次塊擦除操作。ECC段718 包含六個ECC位元組，以確保資料一致性。衆所周知， EEC是一種非常先進的方法，用於錯誤檢測和校正。邏輯 塊位址磁區段720用於電源備份和系統重入。由於快閃記 憶體系統的映射表存儲在易失性記憶體中，因此在掉電過 28 200813713 耘中，無法保存有效磁區的資訊。在系統初始化和停電 時’邏輯塊位址磁區位址段72〇用於重構映射表。邏輯塊 位址磁區位址段720記錄了先前的寫入操作、有效磁區和 過期磁區資訊以便重構映射表。設定了新的諸結構後， 快閃記憶體系統的固件可以修復懸空簇。這可以通過校核 存儲在快閃記憶體設備中快閃記憶體陣列的fat表實現。 圖11爲本發明資料存取方法流程圖。快閃記憶體系統 初始化後，通過查詢快閃記憶體陣列識別號（ID)確定快 閃記憶體設備中快閃記憶體陣列的容量，參考步驟802。 同時，掃描各快閃記憶體設備的實體位址以確定現有壞磁 區（步驟802)。該判斷可以通過讀取壞塊指示段實現。. 邏輯塊位址的範圍通過編程寫入快閃記憶體控制器的 暫存器文件’參考步驟8〇4。給定一個快閃記憶體設備， 由於該快閃記憶體設備中部分空間被預留用於壞塊替 換，所以物理塊地址的範圍比邏輯塊地址的範圍大。例 如，把快閃記憶體陣列的10%用作保留空間是比較合理的。 下一步，從主機系統接收邏輯塊位址磁區位址、資料 和命令’參考步驟8G6 ^採用蔟資料緩衝和寫人後高速緩 衝策略以提高快閃記憶體系統的性能。下一步，由映射表 確定快閃記憶體設備編號和實體位址，參考步驟8〇8。下 一步，分析來自主機系統的命令，參考步驟8ι〇。如果該 命令是讀取命令，則執行讀取操作，參考步驟812。缺後， 校核讀取操作獲得的資料，參考步驟814。利用ecc段位 元組中保存的資訊校核資料。如果資料校核正確，則把資 29 200813713 料返m主機系統，參考步驟8丨^ 料不正確，則勃—FPf^品你忠么果5貝取刼作得到的資 、執订E E C細作來校正資料， 如果該命令爲寫入命令(參考步驟81。二驟二 =入操作。寫入操作所需要的時間明顯：二讀)取: 而要的時間長。例如，寫入操作所需的時間可能比姑 取操作所需時間的長20倍。首先， 明 查自由磁區（即， = =)’參考步驟，如果自由磁區的數量低於自由 -的閥值，則通過垃圾回收操作回收塊，參考步驟— 如果自由磁區的數量不低於自由磁區的閥值，則把* 料寫入該快閃記憶體設備’參考步驟m。寫入操作完成 後’即可確定寫入操作是成功還是失敗，參考步驟826。 如果寫入操作成功，則結束寫人操作，參考步冑828。如 果寫入操作失敗’意味著該塊是壞塊，則執行壞塊操作， 參考步驟8 3 〇 〇 通蔡，若某個塊是壞塊，則該磁區中的資料不可靠。 Ρ使们塊中，、有一個磁區爲壞磁區，這個塊就將被確定 爲壞塊。爲了確保資料的可靠性，資料將不再賦值到壞塊 中，而是重新分配至好塊中。相應地，儲存在壞塊中有效 磁區的資料將被轉移到好塊中供進一步參考。該操作稱爲 壞塊替換。快閃記憶體設備將在内部發出回拷命令用於減 少事務處理時間。 圖12爲本發明的壞塊替換方法流程圖。壞塊中壞磁區 的位置被記錄在快閃記憶體設備的最後兩個塊的保留區 中，參考步驟902。在本發明的一個實現方案中，各塊都 200813713 由1 6個磁區組成。y m ^ ^ - 有十六個位分別與著十六個磁區相 關聯。廷些位兀用於^ 曰不晨磁區。相應地，如果某個位爲 〇，則表明相關的磁區& 、 ^ 匕舄壞磁區，而整個塊即被確認爲壞 塊。廷些位元的編程 最 万式疋通過讀取整個磁區的值，然徭 把原值和位值相加，iAnother advantage of the present invention is that block management operations can occur synchronously within multiple flash memory devices. Thus, the flash memory is improved step by step; the performance of the system is such as 'the first data relocation operation can be Executed in the first flash memory device while the second data is relocated and executed in the second flash memory device. It also allows different flash memory devices to be erased and programmed at the same time. The system is parallel (4) improved (4) to improve the performance of the flash S memory system. The block management operation in this example is a bad block replacement operation. If the magnetic regions 502a, 502b, and 502c become bad magnetic regions, the valid data stored in the magnetic regions 5?, "n and 502c will be repositioned. In this embodiment, the effective > material will be copied to the inside. The buffer area is 〇 6. The internal buffer is a volatile memory magnetic area that functions normally inside the flash memory device 504. In one implementation of the invention, the block of the volatile memory magnetic area is pre- It is reserved for providing internal buffers 5〇6 to each flash memory device, which reduces the need for external search (ie, search outside the boundaries of the flash memory device). Good block search is available in flash memory. The other parts of the internal device 504 are executed. The entire block address of each flash memory device is allocated according to 25 200813713 for the distributed address scheme as shown in FIG. 8 , and all searches are limited to the flash memory device. Within the boundaries of the search. After searching for a good block, 'valid data will be copied to one or more good blocks. In either case, single-chip search is greatly reduced compared to the traditional multi-wafer search method shown in Figure 7. search for At the same time, since the bad block operation occurs inside the flash memory device 5〇4, the effective data relocation time is greatly reduced. The present invention eliminates the need for an external buffer. Accordingly, since there is no need to transfer valid data to the outside. The flash memory device 504, the relocation time is also greatly reduced. During the other block management operations of the present invention, the internal buffer 5 〇 6 also plays the same role. In another solution, during the block management operation, the effective tribute The material does not need to be first stored in the internal buffer 5〇6 and is directly relocated into the good magnetic area. In the present invention, each flash memory device operates as a separate addressing unit, and the block management operation is performed in each flash memory. Another advantage of the present invention is that different sizes of flash memory devices can be used within the same flash memory system. Figure 9 is a flash memory block management method of the present invention. Advanced Flowchart. First, start up to > an operation in a flash memory system with several flash memory devices, refer to step 6〇2. In this embodiment, the block management operation is performed. Next, searching for the target block within the flash memory device, refer to step 604. In the next step, the valid data is relocated from the source block to the destination block within the flash memory device. Referring to step 6〇6, correspondingly, multiple flash memory devices can perform block management operations simultaneously. In multiple flash memory 26 200813713 body device performs block management operations from internal execution of independent two flash memory devices Each row is independent and synchronous. Each flash memory device can be shown in Figure 1 as a detailed block diagram of the vibrating device and the memory device 700 of the present invention. The block diagram can be used to implement the situational device 70" The memory device, the flash memory file is equipped with a logical block address range, and the noise block address of the logical block address is determined by the 66/occupation shown in Fig. 5 and the ten-cut logic Ι0δ. The physical block address of the flash memory device 700 is increased from 跫 7 to the maximum capacity of the flash memory device 700. In the figure, τ τ loyalizes the non-blocks 706a, 706b, 706c and 7〇6d. 706a and 706b are respectively a 7 ^ knife for the brother and brother two physical address blocks and 7 〇 6d for the last entity address block. In this embodiment, the magnetic region (commonly referred to as page) 7 (Π contains 528 bytes, including 512-bit laps and 备用 one-byte spare segments. Flash 恃, G body 5 The 70-inch data structure is composed of the physical segments 706a, 706b, 706c, and 7a, the data segment 702 of the human-々·ι, @7〇6d, and the spare segment 704. Each segment has a certain bit έθ红疋幻The number of 70 groups, the number of bytes is determined by the specific application. For example, the data segment can contain 512 bytes, UP bytes or more, and the segment can contain 16, 64 or more bits. The bedding segment 702 stores the original data, while the spare segment 7〇4 stores the memory management related information. The spare segment 704 includes a valid magnetic segment 710, an expired magnetic segment 712, a bad block indicating segment 714, and an erased counting segment 716. Error correction code (ECC) segment 718 and logical block address magnetic region (four) segment 72q. Section 710 is used to indicate whether the data in the magnetic region can be effectively read. The expired magnetic segment 712 is labeled as segment 'for Indicates whether the data in the magnetic zone has expired. 2008 27,137. If the subsequent write or erase operation occurs, it expires. The bad block indication segment 7 14 is used to indicate a bad block. In one embodiment of the invention 'store the threshold value in the bad block indication segment 714 to indicate that the block has been corrupted. If an attempt is made to write to a particular If the magnetic zone or the erase of a specific block fails, the block is considered to be a bad block. In a specific implementation, the bad block indication is confirmed by the factory setting. The firmware of the flash memory is scanned by the block. A magnetic region is used to determine if the data can be accessed. The complete scan information is then saved to the last block of each flash device. # In this embodiment, two bytes (16 bits) are used. To record the bad block information of each block (16 magnetic regions). Record the bad block information of the flash memory device (up to 5 12 blocks) with two magnetic regions (1〇24 bytes). High reliability, storing eight identical pieces of bad information to prevent damage in the magnetic zone during the remote and recording process. In order to achieve fast access, these eight backups are stored in each flash. The last block position 706d of the memory device. Bad magnetic zone indication Segment 714 is stored in the last block 706d for more convenient reading by the firmware of the flash memory system. The erase count segment 716 is used to record that a block will be erased throughout the life of the flash memory device. The number of erasures. The erase count segment 716 contains three bytes and can record up to 16 million block erase operations. The ECC segment 718 contains six ECC bytes to ensure data consistency. It is well known that EEC is A very advanced method for error detection and correction. Logical block address magnetic section 720 is used for power backup and system re-entry. Since the mapping table of the flash memory system is stored in volatile memory, After power-off 28 200813713 ,, the information of the valid magnetic zone cannot be saved. The logical block address sector address segment 72 is used to reconstruct the mapping table during system initialization and power down. Logic Block The address sector address segment 720 records previous write operations, valid sector and expired sector information to reconstruct the mapping table. After setting the new structures, the firmware of the flash memory system can repair the floating clusters. This can be done by checking the fat table stored in the flash memory array in the flash memory device. 11 is a flow chart of a data access method of the present invention. After the flash memory system is initialized, the capacity of the flash memory array in the flash memory device is determined by querying the flash memory array identification number (ID), refer to step 802. At the same time, the physical address of each flash memory device is scanned to determine the existing bad magnetic region (step 802). This determination can be achieved by reading the bad block indication segment. The range of logic block addresses is programmed into the scratchpad file of the flash memory controller' by referring to step 8〇4. Given a flash memory device, the physical block address range is larger than the logical block address range since some of the space in the flash memory device is reserved for bad block replacement. For example, it is reasonable to use 10% of the flash memory array as a reserved space. Next, receive the logical block address, address, and command from the host system. [Reference step 8G6 ^ Use the data buffer and write the post-shock strategy to improve the performance of the flash memory system. Next, the flash memory device number and physical address are determined by the mapping table, refer to step 8〇8. In the next step, analyze the commands from the host system, refer to step 8ι〇. If the command is a read command, a read operation is performed, referring to step 812. After the missing, check the data obtained by the read operation, refer to step 814. Use the information stored in the ecc segment to check the data. If the data check is correct, then the funds will be returned to the m host system. If the reference is not correct, then the FP-Fif products will be corrected. Data, if the command is a write command (refer to step 81. 2nd step 2 = input operation. The time required for the write operation is obvious: second read) takes: and takes a long time. For example, the time required for a write operation may be 20 times longer than the time required for a get operation. First, check the free magnetic region (ie, ==)' reference step. If the number of free magnetic regions is lower than the free-threshold, the block is recovered by the garbage collection operation. Reference step - if the number of free magnetic regions is not low In the free magnetic zone threshold, the * material is written into the flash memory device' reference step m. After the write operation is completed, it can be determined whether the write operation succeeds or fails. Refer to step 826. If the write operation is successful, the write operation is ended, see step 828. If the write operation fails, meaning that the block is a bad block, perform a bad block operation. Refer to step 8 3 〇 〇 蔡, if a block is a bad block, the data in the magnetic area is not reliable. In the block, there is a magnetic zone as a bad magnetic zone, and this block will be determined as a bad block. In order to ensure the reliability of the data, the data will no longer be assigned to the bad block, but will be redistributed into the good block. Accordingly, the data stored in the valid magnetic zone in the bad block will be transferred to the good block for further reference. This operation is called bad block replacement. The flash memory device will issue a copyback command internally to reduce transaction time. 12 is a flow chart of a bad block replacement method of the present invention. The location of the bad magnetic region in the bad block is recorded in the reserved area of the last two blocks of the flash memory device, with reference to step 902. In one implementation of the invention, each block 200813713 consists of 16 magnetic regions. y m ^ ^ - There are sixteen bits associated with sixteen magnetic regions. The court is used for ^ 曰 not the morning magnetic zone. Correspondingly, if a bit is 〇, it indicates that the associated magnetic zone & , ^ 匕舄 bad magnetic zone, and the entire block is confirmed as a bad block. The programming of some bits is to read the value of the entire magnetic domain, and then add the original value and the bit value, i

後寫入來實現。爲了確保正確性， 固件將生成四個備价。人A 王邛八個塊（4x2塊）都位於各快 閃記憶體設備的最後处 、 二間中。在磁區的使用壽命期限内， 每個位將被設置一次’用於指示壞磁區的位置。 步確疋疋否有寫入命令，參考步驟904。如果 明取操作失敗且沒有寫人命令，壞塊磁區中的有效資料即 被確=，，參考步驟906。如果有寫入命令（參考步驟-爲是”）’則在同一個設備之内執行可用磁區搜索操 作’參考步驟908。如果沒有足夠數量的可用磁區則執 行垃圾回收操作，參考步驟91〇，直到有足夠數量的可用 磁區。如果有足夠數量的可用磁區，映射表的邏輯塊位址 將被更新，參考步㈣2。下一步，寫入操作完成參考 步驟914。寫入操作完成後，壞塊中磁區的有效資料被確 定，參考步驟906 〇若寫入或擦除操作失敗，則執行該操 作0 下—步，確定好塊的目的磁區，用於重新分配壞塊的 有效貝料，參考步驟916。下一步，有效資料被重新放置 (即，複製）到目標磁區中，參考步驟918。在重新放置 過私中在快閃$己憶體$又備内部執行回拷操作，以避免外 部通彳&並提高快閃記憶體系統的性能。下一步，快閃記憶 31 200813713 體控制器中的映射表被更新以反映變化供以後資料存取 用 > 考步驟920。下-步，確定是否全部來自壞塊的有 效資料都已經被轉移到好塊中，參考步驟922。如果沒有， 操作迴圈回到& 906。如果全部有效資料都已經被轉移， 則壞塊替換操作結束。 圖13爲本發明的垃圾回收操作方法流程圖。垃圾回收 操作是在各快閃記憶體設備邊界之内執行的單晶片操 作。相應地’多個垃圾回收操作可以同步在各快閃記憶體 λ備内發生。首先’在快閃記憶體設備内部進行搜索， 以定位含有最多過期磁區的過期塊，參考步驟1〇〇2。特別 地，固件通過掃描整個㈣磁區段以確定各塊過期磁區的 數量。搜索結果存儲在暫存器中。暫存器用於指示含有最 多過期磁區的過期塊。例如，用四個暫存胃指示含有最多 過期磁區的四個過期塊。掃描結果和邏輯塊位址的值被同 時保存用於更新位址映射表。同時，+同的暫存器組被同 時用於記錄該設備中含有最多過期磁區的四個有效塊。目 的是在把有效磁區重新放置到目標（有效）塊中之後擦除 一個過期（源）塊。這四個暫存器組用於提供最匹配的源 塊和目標選擇。 下一步，確疋源塊中有效磁區的數量，參考步驟1⑽4。 下一步，確定有效磁區的位址，參考步驟1〇〇6。這些位址 指向的有效磁區被稱爲目的磁區。下一步，執行回拷操作 把有效資料從過期（源）塊向目標磁區進行複製，參考步 驟1008。在回拷操作中，有效資料可以臨時存儲在内部緩 32 200813713 衝區中。 下一步’確定在垃圾回收操作中是否出現了壞磁區， 參考步驟1010。如果出現了壞磁區，則執行壞塊重新放置 操作，參考步驟1012。如果沒有出現壞磁區，源塊（含有 最多過期磁區的塊）將被擦除並且這個塊各個位的值將被 汉爲1 ’參考步驟1014。下一步，確定擦除操作是否失敗， 多考v驟10 1 6。如果擦除操作失敗，則執行壞塊重新放置 操作，參考步驟1018。如果擦除操作沒有失敗，則過期塊 的垃圾回收操作完成，映射表被更新以反映修改供後續寫 入操作用，參考步驟1〇2〇。下一步，擦除計數段中被擦除 塊的擦除計數增加，參考步驟1 〇22。 圖14爲本發明的損耗平衡操作方法流程圖。在沒有來 自主機系統的資料傳輸請求時，損耗平衡操作將後臺運 ^損耗平衡操作過程中有可能會收到來自主機系統的資 料傳輸明求㈠員耗平衡操作通常把有效資料從低擦除計數 的塊移向面擦除計數的塊。低擦除計數的塊將被擦除，其 擦除計數將增加。這―操作過程可以通過降低塊的最高擦 *十數使其接***均設備擦除計數的方法來平衡塊的擦 除計數。該過程同時推遲了給定塊達到其最大擦除計數的 時間。 首先固件讀取各塊擦除計數段中的擦除計數，並確 疋各丨夬閃§己憶體設備的平均設備擦除計數，參考步驟 2扃後確定全部快閃記憶體設備的平均全局擦除計 數’同樣參考步冑1102。平均設備擦除計數值存儲在各快 33 200813713 情體-備如果 步驟1104。對於各快閃記 備，如果平均設備擦除計數大於設備閥值計數暫存 器的值’収備閥值計數將被更新爲該值。同理，平 均全局擦除計數大於全局㈣計數暫存器的值，全 計數將被更新爲該值。這些值今後都將被用到，參考+ 謂。在本發明的一個實現方案中，指定了三個暫存二 於保存各快閃記憶體設備的擦除計數值U暫存^ 存特定，快閃記憶體設備的平均擦除計數，稱爲設備:除 計數。第二個暫存器儲存特定的快閃記憶體設備的平均擦 除計數，稱爲設㈣值計數。f三個暫存㈣存全部快閃 記憶體設備的平均擦除計數值，稱爲全局閥值計數。、例 如，設備閥值計數可設爲5,000,全局閥值計數可設爲 20 000這兩個值同時被預編程成爲快閃記憶體系統初 始化的一部分。 下一步，確定快閃記憶體設備的設備閥值計數是否大 於或等於全局閥值計數，參考步驟1106。如果不是，確定 _ 該设備的设備擦除計數是否大於或等於設備閥值計數，參 考步驟1108。如果不是，損耗平衡操作結束。如果是，確 定設備中具有最高擦除計數的塊，參考步驟m〇。下一 步，確定設備中具有最低擦除計數塊，參考步驟i丨12。下 一步’具有最低擦除計數的塊中的有效資料被重新放置到 另一個塊中，參考步驟1114。下一步，具有最低擦除計數 的塊被擦除’同時其擦除計數增加，參考步驟Ul6。了一 步’具有最高擦除計數的塊中的有效資料被重新放置到具 34 200813713 有最低擦除計數的塊中，參考步驟1118»下—步，更新映 射表’參考步驟1120。下一步，設備閥值計數增加，參考 步驟1122。損耗平衡操作結束。After writing to achieve. To ensure correctness, the firmware will generate four reserve prices. The eight blocks (4x2 blocks) of the person A Wang are located in the last and the second of each flash memory device. Each bit will be set once during the lifetime of the magnetic zone to indicate the location of the bad magnetic zone. If there is a write command, refer to step 904. If the explicit operation fails and there is no write command, the valid data in the bad block is confirmed =, refer to step 906. If there is a write command (refer to step - YES), then the available magnetic zone search operation is performed within the same device 'Refer to step 908. If there is not a sufficient number of available magnetic regions, perform a garbage collection operation, refer to step 91〇 Until there is a sufficient number of available magnetic regions. If there is a sufficient number of available magnetic regions, the logical block address of the mapping table will be updated, refer to step (4) 2. Next, the write operation is completed with reference to step 914. After the write operation is completed The valid data of the magnetic region in the bad block is determined. Referring to step 906, if the write or erase operation fails, the operation 0 is performed, and the target magnetic region of the good block is determined, and the effective use of the bad block is redistributed. For the material, refer to step 916. Next, the valid data is relocated (ie, copied) to the target magnetic area, refer to step 918. In the re-placement, the flash is saved in the internal memory. Operation to avoid external communication & and improve the performance of the flash memory system. Next, flash memory 31 200813713 The mapping table in the body controller is updated to reflect the changes for future data storage Access > test step 920. Next step, to determine whether all valid data from the bad block has been transferred to the good block, refer to step 922. If not, the operation loops back to & 906. If all valid data All have been transferred, then the bad block replacement operation ends. Figure 13 is a flow chart of the garbage collection operation method of the present invention. The garbage collection operation is a single wafer operation performed within the boundaries of each flash memory device. The garbage collection operation can be synchronized in each flash memory device. First, 'search inside the flash memory device to locate the expired block with the most expired magnetic area, refer to step 1〇〇2. In particular, the firmware The entire (four) magnetic segment is scanned to determine the number of expired magnetic regions for each block. The search results are stored in the scratchpad. The scratchpad is used to indicate the expired block containing the most expired magnetic regions. For example, four temporary gastric indications are included. The four expired blocks of the most expired magnetic zone. The values of the scan result and the logical block address are simultaneously saved for updating the address mapping table. At the same time, the same register group is the same. Used to record the four valid blocks in the device that contain the most expired magnetic regions. The purpose is to erase an expired (source) block after relocating the valid magnetic region into the target (active) block. Used to provide the best matching source block and target selection. Next, to determine the number of valid magnetic regions in the source block, refer to step 1(10) 4. Next, determine the address of the valid magnetic region, refer to steps 1〇〇6. The valid magnetic area pointed to by the address is called the destination magnetic area. Next, the copy-back operation is performed to copy the valid data from the expired (source) block to the target magnetic area, refer to step 1008. In the copy-back operation, the valid data can be temporarily Stored in the internal buffer 32 200813713. Next step 'To determine if a bad magnetic area has occurred in the garbage collection operation, refer to step 1010. If a bad magnetic zone is present, a bad block relocation operation is performed, see step 1012. If no bad magnetic regions are present, the source block (the block containing the most expired magnetic regions) will be erased and the value of each bit of this block will be taken as 1 ' with reference to step 1014. Next, determine if the erase operation has failed. If the erase operation fails, a bad block relocation operation is performed, see step 1018. If the erase operation has not failed, the garbage collection operation of the expired block is completed, and the mapping table is updated to reflect the modification for subsequent write operations, refer to step 1〇2〇. Next, the erase count of the erased block in the erase count segment is increased, refer to steps 1 〇 22. Figure 14 is a flow chart of the wear leveling operation method of the present invention. When there is no data transmission request from the host system, the wear leveling operation will be able to receive the data transmission from the host system during the loss-balance operation. (1) The user balance operation usually takes the valid data from the low erase count. The block moves to the face to erase the counted block. The block with the low erase count will be erased and its erase count will increase. This - the operation process can balance the erase count of the block by lowering the block's highest wipe * tens to bring it closer to the average device erase count. This process also delays the time that a given block reaches its maximum erase count. First, the firmware reads the erase count in each block of the erased count segment, and confirms the average device erase count of each flash memory device. After step 2, the average global value of all flash memory devices is determined. The erase count ' is also referred to step 1102. The average device erase count value is stored in each fast 33 200813713 modal - standby if step 1104. For each flashbook, if the average device erase count is greater than the value of the device threshold count register, the receipt threshold count will be updated to that value. Similarly, the average global erase count is greater than the value of the global (four) count register, and the full count will be updated to that value. These values will be used in the future, refer to +. In an implementation of the present invention, three temporary storage values are specified for storing the erase count value of each flash memory device, and the average erase count of the flash memory device is called a device. : In addition to counting. The second scratchpad stores the average erase count for a particular flash device, called the set (four) value count. f Three temporary storage (four) save all flash memory device average erase count value, called global threshold count. For example, the device threshold count can be set to 5,000 and the global threshold count can be set to 20 000. These two values are also preprogrammed as part of the initialization of the flash memory system. Next, determine if the device threshold count for the flash memory device is greater than or equal to the global threshold count, see step 1106. If not, determine if the device wipe count for the device is greater than or equal to the device threshold count, refer to step 1108. If not, the wear leveling operation ends. If yes, determine the block with the highest erase count in the device, refer to step m〇. In the next step, it is determined that the device has the lowest erase count block, refer to step i丨12. The next step 'the valid data in the block with the lowest erase count is relocated to another block, see step 1114. Next, the block with the lowest erase count is erased' while its erase count is incremented, see step Ul6. The valid data in the block with the highest erase count is relocated to the block with the lowest erase count of 34 200813713, referring to step 1118»down-step, updating the map' with reference to step 1120. Next, the device threshold count is incremented, see step 1122. The wear leveling operation ends.

-個快閃記憶體設備的塊管理操作可能同時牽涉到多 :快閃記憶體設備，此時有效資料通過外部從—個快閃記 憶體設備向另—個設備被重新放置。這從本質上提高快閃 記憶體設備系統的總體性能人在另一個特定的實施方案 中，如果某個特定的快閃記憶體設備進行塊管理操作其 擦除計數高於其他快閃記憶體設備，有效資料可通過外部 從個快閃s己憶體設備向另一個執行重新放置操作，以達 到不同快閃記憶體設備之間的平衡。在本發明中、，既包括 内部重新放置又包括外部重新放置。 返回步驟1106,如果快閃記憶體設備的設備閥值計數 大於或等於全局閥值計數，則確定設備中具有最高擦除計 數的塊，參考步驟1128。下一步，確定具有最低平均擦除 計數的快閃記憶體設備，參考步驟U3〇。下一步，確定設 備中具有最低擦除計數的塊，參考步驟1132。下一步，具 有最低擦除計數的塊中的有效資料被重新放置到另一個 塊中，參考步驟1134。下一步，具有最低擦除計數的塊被 擦除’其擦除什數增加’參考步驟1136。下一步，且有最 高擦除計數的塊中的有效資料被爲重新放置到具有最低 擦除計數的塊中’參考步驟1138。在本發明的一個實施方 案中，有效資料被移動到另一個快閃記憶體設備中。下一 步，更新映射表’參考步驟1140。下一步，全局閥值計數 35 200813713 增加，參考步驟Π42。損耗平衡操作結束❶ 本發明中的快閃記憶體控制 说# 1釗裔可以執行多塊資料存 取。傳統快閃記憶體設備内置一钿〇， 口口办 個512位元組的頁面暫存 态。寫入快閃記憶體設備的資料 抑 元要冩入該頁面暫存 器’然後才能寫入快閃記憶體障利 皁列。傳統的快閃記憶體控 制器及其固件控制著快閃記憶體 〜骽糸統存取周期。傳統快閃 纪憶體控制器每次只能傳輸一個 q现I 5 12位兀組）的資料 到快閃兒憶體設備的頁面暫存、 ^ 仔為中。如果512個位元組的 頁面暫存器已被寫入，則不飴斟#⑶ 則不此對該快閃記憶體設備進行装 他存取。相應地，傳统換閃却，卜立遍t 八 得死於閃°己馑體控制器使用單塊資料存 取技術，這限制了快閃記憶體系統的性能。 在本發明中’㈣記憶體控制器採用大小爲2048位元 組或更大的頁面暫存器。本發明中的快閃記憶體控 多塊存取控制器’通過同時向快閃記憶體設備發送多塊資 料來寫入頁面暫存器。與傳統的單塊資料傳輸控制器相 比，該控制器顯著提高了資料傳輸的性能。 本發明中的快閃記憶體控制器可同時進行雙通道處 理收而進一步改善了快閃記憶體系統的性能。雙通道計 數可提供第二通道，或“自由通道，，，用於執行快閃記憶 體控制器和快閃記憶體錢之間的事務。傳統快閃記憶: 控制器採用單記憶體匯流排結構，多個快閃記憶體設備同 時與匯流排連接。然、而’傳統的單通道架構限制了傳統快 閃記憶體控制器的性能。 、 在本發明中，至少採用了兩條記憶體匯流排。各條記 36 200813713 體匯流排都和獨立的快閃記憶體設備相連。記憶體控制 二可以同日可或單獨存取各快閃記憶體設備。結果，操作執 :可達到採用雙通道處理的兩倍速度。此外，各記‘憶體匯 排還可以進一步擴展爲多條記憶體匯流排結構。 本發明的快閃記憶體控制器還可進行交錯式操作。傳 •先陕閃圯隐體控制器採用單記憶體匯流排結構，多個快閃 記憶體設備同時與匯流排連接。然而，傳統快閃記憶體控 制器母次只能存取一個快閃記憶體設備，而這限制了系統 馨的性能。 本發明中，至Μ β 夕私用了 一個或兩個記憶體控制信號（例 如=k和忙）。此外，共用的記憶體匯流排至少有兩個快 '記：體設備與之相連。當一個快閃記憶體設備爲讀忙或 寫忙盼，本發明中的快閃記憶體控制器可存取另一個快閃 -己隐體δ又備。相應地，本發明中的快閃記憶體控制器充分 利用了共用記憶體匯流排，從而顯著提高了性能。此外， 2過共用記憶體ΙΟ和控制信號，減少了快閃記憶體控制 态的e腳數里。這使快閃記憶體系統的成本實現了最小 化0 在本發明中，在單個快閃記憶體設備的記憶體存取周 ^中1¾時*成夕塊存取技術，多記憶體交錯技術和多通道 操作技術，使其達到了最佳性能。 本發明提出的系統和方法具有諸多優點。例如，大大 提高了快閃記憶體控制器在塊管理操作過程中的搜索可 帛好塊的速度。同時，消除了快閃記憶體控制器對外部緩 37 200813713 衝區的需求。沾 而^ 此外，快閃記憶體控制器支援多塊資料存 #、雙通道處理和多存儲單元交錯式存取。相應地，大大 提高了塊管理操作執行速度。 ^ 本發明主要介紹了快閃記憶體塊管理系統和方法。該 ^、、充和方法提出了 一種配有處理器的快閃記憶體控制 /用；執行快閃記憶體系統操。這裏的操作是指塊管理 操作，具體包括壞塊處理、過期塊回收和損耗平衡操作。 處理器利用炎自# 1 * _ ^ 』用求自仲裁邏輯的資料，對快閃記憶體系統中特 定的陕閃兄憶體設備執行這些操作。由於這些操作都發生 在特定的快閃記憶體設備内部，處理器可以利用來自仲裁 邏輯的資料把可用好塊搜索限定在特定的快閃記憶體設 備内。卩。同時’在有效資料被重新放置前的搜索過程中， 處理斋可以利用快閃記憶體設備的内部緩衝區來儲存有 效貝料。結果，可用好塊搜索時間大大減少，同時消除了 對外部緩衝區的需求。相應地，塊管理操作的執行速度將 顯著提高。 雖然本说明書介紹的是帶有或不帶有指紋識別功能的 電子負料〖夬閃5己憶體卡’在本發明思想和範圍之内，本發 明同樣適用於其他類型的記憶體系統。此外，雖然本文所 介紹的是USB標準，在本發明思想和範圍之内，本發明同 樣適用於其他標準。此外，本發明的方案可通過硬體、軟 體、包含程式指令的電腦可讀介質或其組合實現。相應 地’通過相關技術對本發明進行的修改仍在以下權利要求 的思想和範圍之内。 38 200813713 【圖式簡單說明】 子資:二本發明一個實施方案的帶有指紋識別能力的電 子貝料决閃§己憶體卡方框圖。 圖2爲本發明另一個實施方 卡電路原理方框圖。 …枓快閃記憶體 圖^本發明另一個實施方案的電子資料快閃記憶體 卡祙用的處理單元方框圖。 士二爲本發明另一個實施方案的電子資料快閃記憶體 卡電路原理方框圖。 圖 圖5爲本發明另一個實施方案 的快閃記憶體系統方框 圖6爲本發明圖5所示的快閃記憶體系統仲裁邏輯、 暫存器文件、映射表之間介面的詳細方框圖。 圖7爲傳統塊管理操作方框圖。 圖8爲本發明的塊管理操作方框圖。 圖9爲本發明快閃記憶體壞塊方法管理冑、級流程圖。 圖1 〇爲本發明快閃記憶體設備的詳細方框圖，該詳細 方框圖可用於實現圖6和圖8所示的快閃記憶體設備。 圖11爲本發明的資料存取方法流程圖。 圖12爲本發明的壞塊替換方法流程圖。 圖13爲本發明的垃圾回收操作方法流程圖。 圖14爲本發明的損耗平衡操作方法流程圖。 39 200813713 【主要元件符號說明】- Block management operations of a flash memory device may involve multiple simultaneous flash memory devices, where valid data is relocated from the external flash memory device to another device. This essentially improves the overall performance of the flash memory device system. In another particular embodiment, if a particular flash memory device performs block management operations, its erase count is higher than other flash memory devices. The valid data can be externally reconfigured from one flash memory device to another to achieve a balance between different flash memory devices. In the present invention, both internal relocation and external repositioning are included. Returning to step 1106, if the device threshold count of the flash memory device is greater than or equal to the global threshold count, the block having the highest erase count in the device is determined, see step 1128. Next, determine the flash memory device with the lowest average erase count, refer to step U3〇. Next, determine the block with the lowest erase count in the device, refer to step 1132. Next, the valid data in the block with the lowest erase count is relocated to the other block, see step 1134. Next, the block with the lowest erase count is erased & its erased count is increased by reference to step 1136. Next, the valid data in the block with the highest erase count is relocated to the block with the lowest erase count' reference step 1138. In one embodiment of the invention, the valid material is moved to another flash memory device. Next, update the mapping table' by referring to step 1140. Next, the global threshold count 35 200813713 is added, refer to step Π42. The end of the wear leveling operation 快 The flash memory control in the present invention says that #1 descendants can perform multiple pieces of data access. The traditional flash memory device has a built-in port, and the port has a 512-bit page temporary storage state. The data written to the flash memory device must be inserted into the page scratchpad' before it can be written to the flash memory bar. Traditional flash memory controllers and their firmware control the flash memory ~ 存取 access cycle. The traditional flashing video memory controller can only transmit one q at a time, and the data of the flash memory device is temporarily stored in the page. If the page register of 512 bytes has been written, then #(3) does not access the flash memory device. Correspondingly, the traditional flashover, Bu Lidu t eight died of flashing the 馑 馑 控制器 controller using a single data access technology, which limits the performance of the flash memory system. In the present invention, the '(iv) memory controller employs a page register of size 2048 bits or larger. The flash memory control multi-block access controller of the present invention writes to the page register by simultaneously transmitting a plurality of pieces of data to the flash memory device. Compared to traditional single-block data transmission controllers, this controller significantly improves the performance of data transmission. The flash memory controller of the present invention can simultaneously perform dual channel processing to further improve the performance of the flash memory system. The dual channel count provides a second channel, or "free channel," for performing transactions between the flash memory controller and the flash memory. Traditional flash memory: The controller uses a single memory bus structure Multiple flash memory devices are simultaneously connected to the bus. However, the 'traditional single channel architecture limits the performance of the conventional flash memory controller. In the present invention, at least two memory busses are used. Each of the notes 36 200813713 is connected to a separate flash memory device. Memory Control 2 can access each flash memory device on the same day or separately. As a result, the operation can achieve double channel processing. In addition, the memory of the memory can be further expanded into a plurality of memory bus structures. The flash memory controller of the present invention can also perform interleaved operations. The controller adopts a single memory bus structure, and multiple flash memory devices are simultaneously connected to the bus bar. However, the conventional flash memory controller can only access one flash memory. Equipment, and this limits the performance of the system. In the present invention, one or two memory control signals (for example, =k and busy) are used privately. In addition, there are at least two shared memory buss. Quickly remember: the physical device is connected to it. When a flash memory device is busy for reading or writing, the flash memory controller of the present invention can access another flash-self-hidden δ. Accordingly, the flash memory controller of the present invention makes full use of the shared memory bus, thereby significantly improving performance. In addition, 2 over-memory memory and control signals reduce the control state of the flash memory. In the number of feet, this minimizes the cost of the flash memory system. In the present invention, in the memory access week of a single flash memory device, the digital memory access technology, multi-memory The system and the multi-channel operation technology achieve the best performance. The system and method proposed by the invention have many advantages. For example, the search of the flash memory controller during the block management operation can be greatly improved. Block speed At the same time, it eliminates the need of the flash memory controller for the external buffer 37 200813713. In addition, the flash memory controller supports multiple data storage #, dual channel processing and multi-storage memory interleaved Correspondingly, the execution speed of the block management operation is greatly improved. The present invention mainly introduces a flash memory block management system and method. The method of summation and charging proposes a flash memory control with a processor. Execute the flash memory system operation. The operation here refers to the block management operation, including the bad block processing, the expired block recovery and the wear leveling operation. The processor uses the inflammation from # 1 * _ ^ 』 to use the self-arbitration logic The data is used to perform these operations on specific flash memory devices in the flash memory system. Since these operations occur within a particular flash memory device, the processor can use the data from the arbitration logic to make the available blocks available. The search is limited to a particular flash memory device. Hey. At the same time, during the search process before the valid data is relocated, the processing can use the internal buffer of the flash memory device to store the effective beaker. As a result, the search time available for good blocks is greatly reduced while eliminating the need for external buffers. Accordingly, the execution speed of the block management operation will be significantly improved. Although the present specification describes an electronic negative material with or without a fingerprint recognition function, the present invention is equally applicable to other types of memory systems. Moreover, although the USB standard is described herein, the present invention is equally applicable to other standards within the spirit and scope of the present invention. Furthermore, aspects of the present invention can be implemented by hardware, software, computer readable media containing program instructions, or a combination thereof. Modifications of the present invention by the related art are still within the spirit and scope of the following claims. 38 200813713 [Simplified description of the drawings] Sub-investment: The block diagram of the electronic documentary with the fingerprint recognition capability of one embodiment of the invention. Fig. 2 is a block diagram showing the principle of a card circuit according to another embodiment of the present invention.枓 枓 flash memory FIG. 2 is a block diagram of a processing unit for an electronic data flash memory card according to another embodiment of the present invention. The second principle block diagram of the electronic data flash memory card circuit of another embodiment of the present invention. Figure 5 is a block diagram of a flash memory system according to another embodiment of the present invention. Figure 6 is a detailed block diagram of the interface between the arbitration logic, the scratchpad file, and the mapping table of the flash memory system shown in Figure 5 of the present invention. Figure 7 is a block diagram of a conventional block management operation. Figure 8 is a block diagram showing the block management operation of the present invention. FIG. 9 is a flowchart of a management method and a level of a flash memory block method according to the present invention. 1 is a detailed block diagram of a flash memory device of the present invention, which can be used to implement the flash memory device shown in FIGS. 6 and 8. 11 is a flow chart of a data access method of the present invention. 12 is a flow chart of a bad block replacement method of the present invention. Figure 13 is a flow chart of the garbage collection operation method of the present invention. Figure 14 is a flow chart of the wear leveling operation method of the present invention. 39 200813713 [Description of main component symbols]

卡身 UC 處理單元 2,2A，2CCard body UC processing unit 2, 2A, 2C

快閃 §己憶體设備 3,3C，llOajlOt^llOejiHJOOFlash § Recalling the device 3,3C, llOajlOt^llOejiHJOO

指紋感測器4 輸入/輸出介面電路5，5 A，5 C 顯示單元 6,6A 電源 7Fingerprint sensor 4 Input/output interface circuit 5,5 A,5 C Display unit 6,6A Power supply 7

功能鍵 8,8A 主機 9,9A 電子資料快閃記憶體卡10，10A，1〇C，1〇〇Function key 8,8A host 9,9A electronic data flash memory card 10,10A,1〇C,1〇〇

讀卡器 12 快閃記憶體控制器 功率調節器 22 主機系統 52 微處理器 104Card Reader 12 Flash Memory Controller Power Conditioner 22 Host System 52 Microprocessor 104

介面匯流排 13 21，21C 重置電路 23 介面轉換邏輯 102 ROM 106 仲裁邏輯108 暫存器文件112 映射表114 暫存器114a，114b，114c 快閃記憶體介面控制器 Π6 LAB磁區地址 302Interface Bus 13 21, 21C Reset Circuit 23 Interface Conversion Logic 102 ROM 106 Arbitration Logic 108 Register File 112 Mapping Table 114 Register 114a, 114b, 114c Flash Memory Interface Controller Π6 LAB Magnetic Area Address 302

磁區 402a，402b，402c，502a，502b，502c 快閃記憶體設備A中塊 404 外部頁面緩衝區 406 快閃記憶體設備B的塊 408 快閃記憶體設備504中的塊 503 内部頁面緩衝區 506 磁區（通常稱爲頁面）701 資料段702 備用段704 40 200813713 示列塊 706a,706b,706c,706d 有效磁區段710 過期磁區段712 壞塊指示段7 14 擦除計數段7 16 錯誤校正代碼（ECC)段718 邏輯塊位址磁區位址段720 步驟 602,604,606,802,804,806,808,810,812,814,816,818, 820,822,824,826,828,83 0,902,904,906,908,910,912, 9 14,9 16,9 18,920,922,1 002,1004,1 006,1008,10 10, 1012，1014，1016，1018，1020，1022，1102，1104，1106， 1108，1110，1112，1114，1116，1118，1120，1122，1128， 1 130,1132,1 134,1136,1138,1 140,1142Magnetic regions 402a, 402b, 402c, 502a, 502b, 502c Flash memory device A block 404 External page buffer 406 Flash memory device B block 408 Flash memory device 504 Block 503 Internal page buffer 506 magnetic zone (commonly referred to as page) 701 data segment 702 spare segment 704 40 200813713 display block 706a, 706b, 706c, 706d active magnetic segment 710 expired magnetic segment 712 bad block indication segment 7 14 erase segment 7 16 Error Correction Code (ECC) Segment 718 Logical Block Address Magnetic Region Address Segment 720 Steps 602, 604, 606, 802, 804, 806, 808, 810, 812, 814, 816, 818, 820, 822, 824, 826, 828, 83 0, 902, 904, 906, 908, 910, 912, 9 14, 9 16, 9 18, 920, 922, 1 002, 1004, 1 006, 1008, 10 10, 1012, 1014 , 1016, 1018, 1020, 1022, 1102, 1104, 1106, 1108, 1110, 1112, 1114, 1116, 1118, 1120, 1122, 1128, 1 130, 1132, 1 134, 1136, 1138, 1 140, 1142

Claims (1)

200813713 十、申請專利範圍： 1 · 一種電子資料快閃記 被主機存取，該電子記過建立通訊連接 一卡身； j尤體卡包括·· 憶體設備包含數個非易:::::閃記憶體設備，快閃記 記憶體控制11，與所述的快閃記 輪出介面電路之間的電氣連接，其 〒决閃s己憶體控制器包括： (a)快閃記憶體控制器的處理 測演算法代碼確定一快閃 快閃把憶體檢 ..· 〜骽叹備疋否被支援的手段， ⑴識別快閃記憶體設備無效存儲單元的仲裁手段， 以及把實體位址指派給相關邏輯塊位址的仲裁方法，並 中，各所述實體位址對應多個快閃記憶體設備存儲單元’: (C )手段以選擇性地操作其下之一： 可編程模式··在該模式τ，上述快閃記憶體控 制器啟動輸入/輸出介面電路以接收來自主機的資料 播案，並且把資料檔案儲存到上述快閃記憶體設備的 第-物理文件位址’其係通過上述仲裁手段被指派給 第一邏輯塊位址，上述可編程模式由從主機發送至快 閃記憶體控制器的相關寫入命令啓動； 、 -資料讀取模式：在該模式下，上述快閃記憶體 42 200813713 控制器接e主機發出的讀取命令和卜邏輯塊位 址，並啟動上述輸入/輸出介面電路讀取第—物理位 址的資料檔案傳送給主機；以及 一資料重定模式：該模式下，資料標案將從快閃 記憶體設備被擦除。 2.如權利要求i所述的電子資料快閃記憶體卡，其 中快閃記憶體設備包含第一快閃記憶體設備和第二快閃 記憶體設備。 ' Al 3·如權利要求2所述的電子資料快閃記憶體卡，其 中第一快閃記憶體設備包含第一組存儲單元，第二快閃纪 憶體設備包含第二組存儲單元，且其中第一組存儲 2 於或等於第二組存儲單元。 4 .如權利要求2所述的電子資料快閃記憶體卡，其 中所述仲裁手段包括在第一快閃記憶體設備中至少執行 編程操作，資料讀取操作或資料重定操作中的一項，並2 同步在第二快閃記憶體設備中至少執行編程操作，資料讀 取操作或資料重定操作中的一項的手段。 巧 5 ·如權利要求1所述的電子資料快閃記憶體卡，其 中所述仲裁手段包括該快閃記憶體設備中功能存儲單元 搜索的手段，和把—個或多個無效存儲單元相關的第一邏 43 200813713 體位址 輯塊位址重新分配給功能存儲單元相關的第 的手段。 6·如權利要求i所述的電子資料快閃記憶體卡，宜 : = 體，包括一個内部緩衝區，且其中快閃記憶 體盗为包含在把上述資料存儲到所述第一 址所指向的存儲單元之前，在所述内部緩衝區臨^儲上 述資料檔案的手段。 7·如權利要求Μ述的電子資料快閃記憶體卡，其 中仲裁手段還包括制先前被指派給所述第—邏輯塊位 ㈣無效存儲單元的手段，識別第二實體位址所指向的功 能正常且未被指派的㈣單元的手段，以及把所述第一邏 輯塊位址重新分配給第二實體位址的手段。 8·如權利要求i所述的電子資料快閃記憶體卡，其 中仲裁手段還包括識別第—邏輯塊位址中被更新資料槽 案的手段，把第一邏輯塊位址重新分配給第二實體位址的 手段’以及把被更新的資料㈣存儲到第二實體位址所指 向的存儲單元的手段。 9如權利m所述的電子資料快閃言己憶體卡， 中仲裁手段遷包括在被更新f料檔案被存儲到第二實』 位址所指向的存儲單元後，從第一實體位址指向的存儲· 44 200813713 元中擦除過期資料的手段， _ 給第二邏輯塊位址的手段。及把弟—貫體位址重新分配 “中：年t權》利要？所述的電子資料快閃記憶體卡，其 一棒^ :遷包括弟一實體位址所指向的存儲單元的第 二 =第二實體位址所指向的存儲單元的第二捧 除，比較手段，以及當第一擦除計數大於第: 數時，把資料檔案從第—實體位址的存 ;;者冲 位址的存儲單元傳輸的手段。 。 —只體 I中=如權利要纟1G所述的電子資料快閃記憶體卡， /、中快閃§己憶體設備包括一個内部緩衝區，且其中快閃纪 憶體控制n部分包含在把上述f料相 位址所指向的存儲單亓夕乂 . ^ χ 乐貝體 上述資料樓案刖’在所述内部緩衝區臨時存儲 Φ…二權利要求2所述的電子資料快閃記憶體卡，其 、二;fe體控制器至少支援對第一快閃記憶體設備和 :::二體設備進行雙通道並行存取和交錯式存取 兩種手4又的其中之一。 13 ·如權利要求！所述的電子資料快閃記憶體卡，其 中輸入/輪出介面電路爲通用串列匯流排（USB)介面電 路，該咖介面電路包含採用Β〇τ協定傳輸㈣的手段。 45 200813713 14 ·如權利要求1所述的電子資料快閃記憶體卡，其 中輸入/輸出介面電路可採用SD介面電路、MMC介面電 路、CF介面電路、記憶棒（MS )介面電路、PCI-Express 介面電路、IDE介面電路或SATA介面電路。200813713 X. The scope of application for patents: 1 · An electronic data flash is accessed by the host, the electronic record is established to establish a communication connection, and the card body includes a number of non-easy:::::flash The memory device, the flash memory control 11, and the flash connection interface circuit are electrically connected to each other, and the flash memory controller includes: (a) processing of the flash memory controller The algorithm of the measurement algorithm determines a flash flash flash memory to check the physical examination.. · ~ 骽 疋 疋 被 被 被 被 被 被 被 被 ( 识别 识别 识别 识别 识别 识别 识别 识别 识别 识别 识别 识别 识别 识别 识别 识别 识别 识别 识别 识别 识别 识别 识别 识别 识别 识别 识别 识别 识别 识别 识别 识别Block address arbitration method, wherein each of the physical addresses corresponds to a plurality of flash memory device storage units': (C) means to selectively operate one of the following: Programmable mode · In this mode τ, the flash memory controller starts the input/output interface circuit to receive the data broadcast from the host, and stores the data file to the first physical file address of the flash memory device. The arbitration means is assigned to the first logical block address, and the programmable mode is initiated by an associated write command sent from the host to the flash memory controller; - data reading mode: in the mode, the flashing Memory 42 200813713 The controller is connected to the read command and the logical block address issued by the e host, and starts the above input/output interface circuit to read the data file of the first physical address and transmits it to the host; and a data reset mode: In mode, the data standard will be erased from the flash memory device. 2. The electronic data flash memory card of claim 1 wherein the flash memory device comprises a first flash memory device and a second flash memory device. The electronic data flash memory card of claim 2, wherein the first flash memory device comprises a first group of memory cells, and the second flash memory device comprises a second group of memory cells, and The first group stores 2 or equals the second group of storage units. 4. The electronic data flash memory card of claim 2, wherein said arbitration means comprises at least one of a program operation, a data read operation, or a data reset operation in the first flash memory device, And 2 means for synchronizing at least one of a program operation, a data read operation, or a data reset operation in the second flash memory device. The electronic data flash memory card of claim 1 wherein said arbitration means comprises means for searching for a functional storage unit in said flash memory device and relating to one or more invalid memory locations The first logical 43 200813713 body address tile address is reassigned to the functional storage unit related means. 6. The electronic data flash memory card of claim 1, preferably: = body, including an internal buffer, and wherein the flash memory is included in storing the data to the first address Before the storage unit, the means for storing the above data file is stored in the internal buffer. 7. An electronic data flash memory card as recited in claim 1, wherein the means for arbitrating further comprises means for previously assigning to said first logical block (4) invalid memory location, identifying a function to which the second physical address is directed Means of a normal and unassigned (four) unit, and means for reallocating the first logical block address to a second physical address. 8. The electronic data flash memory card of claim 1, wherein the means for arbitrating further comprises means for identifying the updated data slot in the first logical block address, and reallocating the first logical block address to the second The means of the physical address 'and the means for storing the updated material (4) to the storage unit pointed to by the second entity address. 9 The electronic data flashing self-recalling card according to the right m, wherein the arbitration means is included in the storage unit pointed to by the updated material file, and the first physical address is Pointing to Storage · 44 200813713 The means of erasing expired data, _ the means of giving the second logical block address. And the redistribution of the younger-student address "medium: the right of the year", the electronic data flash memory card, which has a second stick: the second of the storage unit pointed to by the physical address of the younger brother = the second holding of the storage unit pointed to by the second entity address, the comparison means, and when the first erase count is greater than the first: the data file is stored from the first physical address; The means of transporting the memory unit. - - only the body I = the electronic data flash memory card as described in claim 1G, /, the flash flash § the memory device includes an internal buffer, and in which flash The memory part n part of the memory is contained in the storage unit pointed to by the above-mentioned f-phase address. ^ χ Le Be body The above-mentioned data building 刖 'temporary storage in the internal buffer Φ... 2 according to claim 2 The electronic data flash memory card, the second; the fe body controller supports at least two channels of parallel access and interleaved access to the first flash memory device and the ::: two-body device. One of them. 13 · According to the claims! The flash memory card, wherein the input/round interface circuit is a universal serial bus (USB) interface circuit, and the coffee interface circuit comprises means for transmitting (4) using the Β〇τ protocol. 45 200813713 14 The electronic data flash memory card, wherein the input/output interface circuit can adopt an SD interface circuit, an MMC interface circuit, a CF interface circuit, a memory stick (MS) interface circuit, a PCI-Express interface circuit, an IDE interface circuit or a SATA interface circuit. 4646