200811970 九、發明說明： -【發明所屬之技術領域】 胃 本發明係有關一種銲線連接方法，更詳而言之，係有 關一種用以電性導接複數電子元件之銲線連接方法。 【先前技術】 一般半導體封裝件中，為提供半導體晶片與基板間形 成電性連接，主要係將形成於半導體晶片主動面上之輝塾 贏打線至基板上’藉以構成該半導體晶片與基板之電性搞合 響關係。 、再者，於半導體晶片之電路設計時，為增加電流量或 為提升半導體晶片之電性品質，常需在半導體晶片之主動 面上設置接地銲墊或電源銲墊，且在同一接地銲墊或 銲墊上以二條以上之銲線電性連接至基板之接地墊接地 環）或電源墊（電源環）；而為滿足在半導體晶片之單一銲墊 上打設二條以上銲線之需求，業界遂發展出長銲墊之設 _計，該長銲墊之尺寸係較一般之銲墊尺寸大約一倍以上， 如此方可提供足夠之銲墊面積以在同一銲墊上打設多條銲 線。 請參閱第1A及1B圖，係顯示接置於基板u上之半 導體晶片ίο之主動面上設有一般銲墊1〇1與長銲墊1〇2, «亥鋅墊101係用以供該半導體晶片丨〇與基板1丨間訊號傳 遞，而該長銲墊102係用以供半導體晶片1〇與基板n形 成接地或電源之電性連接，因此該基板11上係設有接地墊 (或為接地環）12,以供半導體晶片1〇之長銲墊1〇2透過多 19260 5 200811970 條銲線13而電性連接至該接地墊（接地環）12，該些鲜線u ，係利用銲線機（黯ebGnder)反覆進行打線作#，以使該 ，長銲墊102電性導接至該接地環（接地環）12。 由圖中可看出長銲墊之功效係為了連接出多條銲 線’然而’由於長料U之面積係數倍於-般銲墊，因此 於晶片面積固定下，長銲墊將佔用晶片之可用面積，使得 晶片上的鲜塾數量減少。 /、有長麵墊之晶片其總面積必須加大以容納更 夕數里之知墊，然而這卻與晶片朝小尺寸化之趨勢相違。 復請參閱第2圖，如美國專利第5,777,345號所揭露 .ί顯不另一習知之半導體封裝件示意圖，其係為多晶 片堆豐之半導體封裝件，該半導體封裝件係包括基板& 植設於該基板21上之第一晶片20a、以及植設於該第一晶 =施上之第二晶片鳥，為供該第一及第二晶片20a,2.0b 電性連，至該基板21，該第一晶片施係設有長鲜塾2〇2, •:供5亥弟二晶片20b藉由銲線23a而電性連接至該第一晶 # 20a之長知墊2〇2，再由該第—晶片2如之長銲墊2〇2 错由銲線23b電性連接至基板21。 υΓ，以長#墊進行多層晶4之電性連接，亦具有如前 述的習知缺點。 因此’如何提供—種銲線連接方法，改善前述習知技 柯所存在之缺失，實為當今崎思考之課題。 【發明内容】 ’本發明之一目的在於 鑒於以上所述習知技術之缺點 19260 6 200811970 提供一種可於單一接點上連接出複數條銲線之銲線連接方 、法。 ' 本發明之又一目的為提供一種銲線連接方法，俾增加 晶片之可用面積與節省製程成本。 本發明之另一目的為提供一種銲線連接方法，俾符合 晶片小尺寸化之趨勢。 為達上揭目的，本發明揭示一種銲線連接方法，以供 電性連接複數電子元件，係包括：先於第一電子元件之電 性接點上形成導電凸塊；自第二電子元件之電性接點上打 線至該導電凸塊；接著自該導電凸塊上打線至該第二電子 兀件，以於該導電凸塊上連接複數條銲線，且構成該第一 及苐二電子元件之電性連接。 於實施本發明之製程時，係利用打線機（Wire b〇nder) 之鲜嘴將金線熔成一球狀而形成導電凸塊（金質凸塊（Au Stud))於第一電子元件之電性接點上，並於第二電子元件之 修電=接點上形成一球型接點（ballbond)，再移動該銲嘴 至導電凸塊，接著截斷該銲線以於該導電凸塊上形成一第 一縫接銲點（stitch bond)，接著利甩打線機於該導電凸 塊之第一縫接銲點上形成球型接點，再移動該銲嘴至該第 =電子元件，接著截斷該銲線以形成一第二縫接銲點f而 完成該第一及第二電子元件間之打線作業。 該第一電子元件可為半導體晶片，其電性接點係為設 於該半導體晶片主動面上之銲墊，該第二電子元件可為基 板，其電性接點係為設於該基板上之接地墊（環）或電源^ 19260 7 200811970 (絃）等。另該第二電子元件亦可為導 -點係為=導線架中之接地導腳或晶片座等。-電性接 法亦之銲線連接方法之要點’本發明之銲線連接方 應用於多數電子元件間之電性連接，尤為半導體Γ 片堆豐結構中相互之電性連接， 、日曰 中$ 由^ 係包括·於稷數電子元件 -中，显㈣導I之電性接點接置導電凸塊；自該電子元件 •=於該¥電凸塊所對應之電子元件之電性接點打線至 着"¥電凸塊；接著自該導電凸塊打線至另-電子元件上， ^政該^電凸塊上連接出複數條銲線而電性連接各該電子 兀件。 於一貫施態樣中，該些電子元件係為基板、接置於該 基板上之第一晶片以及接置於該第一晶片上之第二晶片。 於第-晶片銲墊形成導電凸塊，接著自該基板打線 至該弟-晶片之導電凸塊，以形成該第一晶片與基板之電 性連接’然後再自該第二晶片打線至該第一晶片之導電凸 塊:以構成第-及第二晶片之電性連接。亦或先於該第一 及第二晶片銲塾形成導電凸塊，接著利用反向輝線技術自 該基板打線至該第-晶片之導電凸塊，以及自該第一晶片 之導電凸塊打線至該第二晶片之導電凸塊，以構成該基 板、第一及第二晶片之電性連接。 於另-^施態樣中，該複數之電子^件係分別為基 板、以及堆疊於該基板上而成複數階梯狀之半導體晶片， 係先於該底層晶片銲墊上設置導電凸塊，以自該基板之電 性接點打線至该底層晶片之導電凸塊，以及由其餘各層晶 19260 8 200811970 片打線至該底層晶片之導電凸棟，以供接置於基板上 -層晶片藉本發明之銲線連接方法達成各層晶片、以 性連接。另外，亦可於該基板以外之各層晶 -又置¥电凸塊’以利用反向銲線製程之技術電性連接 ::反：=晶片之導電凸塊’再依序由下層晶片之導電凸 二”反向銲線技術打線至上層晶片之導電凸塊，以構成 基板與堆疊其上之晶片間的電性連接。 相較於習知技術中必須以4 而造成_ y ^ 加長之銲墊連接複數銲線 方；:用：片可用面積之現象，藉由本發明之銲線連接 輝if:業集中於單-導電凸塊上，以不加長晶片 使一晶片— 塾之習知技術為了於一具加長鲜塾之晶片上保持鲜 線連接^晶片以較Α之尺寸設計，而本發明之銲 、、又運接方法，因不須設置加長之鍟 =連接多條銲線’因此晶片可朝小尺寸化之 有的’本發明之鲜線連接方法所需之製程技術，以既 之電：:ΓΓ達成:無論應用於晶片與導㈣ 效益 用於夕層晶片的電性連接皆具有良好之 具節tr’本發明之鲜線連接方法可改善習知缺點並 【實二功效’實具備高度產業利用價值。 19260 9 200811970 以下係藉由特定之具體實施例說明本發明之實施方 .式，熟習此技藝之人士可由本說明書所揭示之内容輕易地 -瞭解本發明之優點與功效。 第一實施例 請簽閱第3A圖至第3D圖，係本發明之銲線連接方法 第一實施例之示意圖。 -如第3A圖所示，係將第一電子元件接置於第二電子 ；元件上，該第一電子元件為半導體晶片30，該第二電子元 參件為基板3卜該第一及第二電子元件上係設有電性接點， 如形成於该半導體晶片30主動面上之銲墊3〇1，以及形成 於該基板31上之接地墊（或接地環）32(亦可為電源墊或 電源環），且於該半導體晶片3〇之至少一銲墊3〇1上形成 導電凸塊34，該導電凸塊34可為金質凸塊（Au Stud )， 其係利用鮮線機燒結金線而成型於焊塾上。 如第3B圖所示，利用反向銲線技術（reverseb〇nd) _自基板31之接地墊（環）32上銲接銲線33a至該導電凸 塊34，使該銲線33a以接近水平之角度銲結於該導電凸塊 34。該銲線33a係為金線，其係利用一打線機（Wire b〇nder) 之銲嘴35於該基板31之接地墊(環）32上利用銲嘴35先形 成一球型接點331a ( ball bond)，再移動該銲嘴至該 導電凸塊34,接著截斷該銲線33a以形成一縫接銲點332a (stitch bond)，而完成自該基板31上之接地墊（環）32 至汶半$體晶片30上之導電凸塊34之打線作業。復請配 &參閱第3C圖，係為對應第3B圖之上視圖，用以顯示接 19260 10 200811970 =於第曰二電子元件（基板)上之第—電子元件（半導體晶片） 利用鲜線而相互形成電性導接。 、如弟3D圖所不，再利用—般打線作業，&自先前形 成；該‘ ι凸塊34上之縫接銲點332a上銲接銲線现至 «亥基板31之接地塾（環）32。該打線作業係於導電凸塊μ 之縫接銲點332a上絲成—球型接點 35至該基板31之接地塾(環”2,接著截斷該鮮線2 以形成另一縫接銲點33孔，而完成該第一及第二電子元件 (晶片及基板)間之重覆打線作業，如第 示該第3D圖之上相m。H 丄# 馬”、、頁 ϋ之上視圖另，由於該半導體晶片30與該基 之弟-次銲線連接係由該基板31 #丁線至該導電凸 34,藉著銲線33a以接近水平角度銲結於該導電凸塊a 而不影響後續於該導電凸塊34之銲線…之縫接鮮點 a上形成鲜線33b之製程。 ^二貫施例 _ 請參閱第4圖， 之示意圖。 係本發明之銲線連接方法第二實施例 本毛月之第一貫施例與第一實施例大致相同，盆主要 差異係在於第二實施例中，該第二電子元件係為導線架 Λ $線木41具有—晶片座411以及複數設於該晶片座 41周圍之導腳412，以 χ日日片庄 丰¥體晶片40之第一電子元件 上#^日日片座Μ1上，且於該半導體晶片4G之銲塾401 又有導電凸塊44，以利用銲線43a及銲線视先後自 4腳架之電性接點，亦即該導腳412(例如為接地導腳） 19260 11 200811970 電性連接至該半導體晶片4G之導電凸塊44 -凸塊44電性連接至導腳412。 自該¥ % ，另該導㈣之t性接點除可料料，_ 座，以利用該晶片座提供半導體晶片接地作用。 _第三實施例 外請參閱第5A圖至第5C圖’係本發明之鋒線連接方^ 弟二實施狀示意圖m性連接複數電子元件。 如第5A圖所示，該些電子元件係具有晶片承载件， 例如基板5〗、接置於該基板51上之第—晶片咖、以及為 置於該第-晶片5Ga上之第二晶片_，於該基板51、第 —晶片50 a及第二晶片50b上係分別設有接地墊51〇、箱 ，50U及銲墊501b等電性接點，且於該第—晶片5^之 鮮墊501a上設置有導電凸塊54。 、如第5B圖所示，接著，利用反向銲線作業以自未設 有導電凸塊之電子元件，打線至該導電凸塊，亦即自該基 春板51之接地墊510銲接銲線53a至該第一晶片5〇&之導^ 凸塊54。該反向銲線作業係於基板51之接地墊51〇上利 用銲嘴55先形成有一球型接點531a(ballb〇nd)，再移 動该銲嘴55至該導電凸塊54，接著截斷該銲線53a以形 成缝接!干點532a ( stitch bond)，而完成自該基板51之 電丨生接點（接地塾510)至該第一晶片5〇a之導電凸塊54之 打線作業。另外，該基板51之電性接點除可為接地墊外亦 可為電源墊等。 如第5C圖所示，於該第二晶片5〇b之銲墊501b上以 12 19260 200811970 銲鳴55形成一球型接點53lb’再移動該銲嘴55至該導電 凸塊54上之縫接銲點532a’以形成銲線53b，接著截斷該 銲，53b而形成另一縫接銲點532b，以形成該第二晶片5仳 至第一晶片50a之電性連接。 另外，该第一、二晶片50a，5〇b間之銲線連接亦可以 反向銲線製程之技術來達成，如第5D圖所示，可先於該 第二晶片50b之銲墊5〇ib上形成有一導電凸塊54，，當完 ，該基板51與該第一晶片術間之銲線連接後，可於縫接 銲點532a上形成球型接點531b，並由該球型接點，以 反向銲線之技術銲接銲線53b，至該第二晶片5〇b之導電凸 塊54 ，而兀成该第一、二晶片5〇a，5〇b間之打線作業。 弟四貫施例 〆、 請參閱第6圖，係應用本發明之銲線連接方法第四實 施例所形成之半導體結構之示意圖。 、 本發明之第四實施例係與第三實施例大致相同，其主 籲要差異在於該半導體結構具一基板61以及接置於該美 61上之複數層半導體晶片，包括位於底層之第一晶/ 6〇a、設於該第一晶片60a上之第二晶片6叽、以^接續設 於該第二晶片60b上之第三晶片6〇c，而形成一階梯狀之 半導體結構。該多晶片堆疊之半導體結構中，至少該第一 晶片60a之銲墊上接置有導電凸塊64。 本實施例係自該基板61之電性接點以反向銲線之技 術銲接銲線63a至該第一晶片60a之導電凸塊64，接著於 該第二晶片60b上形成球型接點65a並由該球型接點65a 19260 13 200811970 銲接銲線63b至該第一晶片60a之導電凸塊64，同樣地， 於該第三晶片60c上形成一球型接點65b，並由該球型接 •點65b銲接銲線63c至該第一晶片6〇a之導電凸塊64，而 使該第片60a所具之導電凸塊64上連接有多條婷線。 應注意的是，本實施例亦可以參照前述第三實施例之 反向銲線製程之技術電性連接各層之晶片，在此一情況下 •除了該基板61外各層之晶片均具有導電凸塊。 目此，料晶片堆疊之半導體結構可藉此銲線連接方 法電性連接各元件，其中所有的半導體晶片皆藉一正常尺 寸之電性連接塾即可同時具有複數條銲線以連接至上層及200811970 IX. INSTRUCTIONS: - [Technical field to which the invention pertains] The present invention relates to a bonding wire bonding method, and more particularly to a bonding wire bonding method for electrically conducting a plurality of electronic components. [Prior Art] In the general semiconductor package, in order to provide an electrical connection between the semiconductor wafer and the substrate, the main line is formed on the active surface of the semiconductor wafer to win the wire onto the substrate to form the semiconductor wafer and the substrate. Sexual engagement. Furthermore, in the circuit design of a semiconductor wafer, in order to increase the amount of current or to improve the electrical quality of the semiconductor wafer, it is often necessary to provide a ground pad or a power pad on the active surface of the semiconductor wafer, and in the same ground pad. Or two or more bonding wires on the pad are electrically connected to the grounding pad grounding ring of the substrate or the power pad (power ring); and in order to meet the demand for two or more bonding wires on a single pad of the semiconductor wafer, the industry develops According to the design of the long soldering pad, the size of the long soldering pad is more than double the size of the conventional soldering pad, so that a sufficient pad area can be provided to lay a plurality of bonding wires on the same bonding pad. Please refer to FIGS. 1A and 1B, which show that the semiconductor wafer 接 on the substrate u is provided with a general pad 1 〇 1 and a long pad 1 〇 2, and the «Zinc pad 101 is used for the The semiconductor wafer is connected to the substrate 1 for signal transmission, and the long pad 102 is used for electrically connecting the semiconductor wafer 1 to the substrate n or the power source. Therefore, the substrate 11 is provided with a ground pad (or The grounding ring 12 is electrically connected to the grounding pad (grounding ring) 12 by the long bonding pad 1〇2 of the semiconductor wafer 1 through the plurality of 19260 5 200811970 bonding wires 13 , and the fresh wires u are utilized The wire bonding machine (黯ebGnder) repeatedly performs wire bonding so that the long bonding pad 102 is electrically connected to the grounding ring (grounding ring) 12. It can be seen from the figure that the effect of the long pad is to connect a plurality of bonding wires. However, since the area factor of the long material U is doubled to the general pad, the long pad will occupy the wafer when the wafer area is fixed. The available area reduces the amount of fresh enamel on the wafer. /, the wafer with the long-faced pad must have a larger area to accommodate the mat in the eve, but this is in contradiction with the tendency of the wafer to be smaller. Please refer to FIG. 2, as disclosed in US Pat. No. 5,777,345. Another schematic diagram of a conventional semiconductor package is a multi-chip semiconductor package including a substrate & The first wafer 20a disposed on the substrate 21 and the second wafer bird implanted on the first substrate are electrically connected to the first and second wafers 20a, 2.0b to the substrate 21. The first wafer is provided with a long fresh sputum 2 〇 2, and the galvanic two dies 20b are electrically connected to the first crystal pedestal 2 〇 2 of the first crystal # 20a by a bonding wire 23a, and then The first wafer 2, such as the long solder pad 2〇2, is electrically connected to the substrate 21 by the bonding wires 23b. υΓ, the electrical connection of the multilayer crystal 4 with the long pad also has the conventional disadvantages as described above. Therefore, how to provide a wire bonding method and improve the lack of the aforementioned conventional technology is a subject of today's thinking. SUMMARY OF THE INVENTION One object of the present invention is to provide a wire bonding method and method for connecting a plurality of bonding wires to a single contact in view of the above-mentioned disadvantages of the prior art. It is still another object of the present invention to provide a wire bonding method which increases the usable area of the wafer and saves process cost. Another object of the present invention is to provide a bonding wire bonding method which is in line with the trend of miniaturization of wafers. In order to achieve the above, the present invention discloses a wire bonding method for electrically connecting a plurality of electronic components, comprising: forming a conductive bump before an electrical contact of the first electronic component; and electrically generating electricity from the second electronic component Wire the wire to the conductive bump; then wire the conductive bump to the second electronic component to connect the plurality of bonding wires to the conductive bump, and form the first and second electronic components Electrical connection. In the process of carrying out the invention, the gold wire is melted into a spherical shape by using a fresh wire of a wire boring machine to form a conductive bump (a gold stud) to the first electronic component. a ball bond is formed on the contact point of the second electronic component, and the ball bond is formed on the contact point of the second electronic component, and then the tip is moved to the conductive bump, and then the wire is cut off to the conductive bump. Forming a first stitch bond, and then forming a ball joint on the first seam of the conductive bump, and then moving the tip to the electronic component, and then moving the tip to the electronic component The bonding wire is cut to form a second seam solder joint f to complete the wire bonding operation between the first and second electronic components. The first electronic component can be a semiconductor wafer, and the electrical contact is a solder pad disposed on the active surface of the semiconductor chip, and the second electronic component can be a substrate, and the electrical contact is disposed on the substrate. Grounding pad (ring) or power supply ^ 19260 7 200811970 (string), etc. In addition, the second electronic component may also be a ground lead or a wafer holder in the lead frame. - The main point of the wire bonding method of the electrical connection method is that the wire bonding connection of the present invention is applied to the electrical connection between most electronic components, in particular, the electrical connection between the semiconductor chip stacking structures, and in the future. The electrical contact is connected to the electrical component of the electronic component of the electronic component, and the electrical component of the electronic component is electrically connected to the electronic component corresponding to the electronic component. Clicking on the wire to the "¥ electric bump"; then, the conductive bump is wired to the other electronic component, and the plurality of bonding wires are connected to the electrical bump to electrically connect the electronic components. In a consistent manner, the electronic components are a substrate, a first wafer attached to the substrate, and a second wafer attached to the first wafer. Forming a conductive bump on the first wafer pad, and then wireting the conductive bump from the substrate to the conductive bump of the transistor to form an electrical connection between the first wafer and the substrate and then bonding from the second wafer to the first A conductive bump of a wafer: to electrically connect the first and second wafers. Forming a conductive bump before the first and second wafer pads, and then bonding the substrate from the substrate to the conductive bump of the first wafer by reverse glow technology, and routing the conductive bump from the first wafer to The conductive bumps of the second wafer are electrically connected to the substrate, the first and second wafers. In another embodiment, the plurality of electronic components are respectively a substrate, and a plurality of semiconductor wafers stacked on the substrate, and the conductive bumps are disposed on the underlying wafer pads. The electrical contacts of the substrate are wired to the conductive bumps of the underlying wafer, and the remaining layers of the layer 19260 8 200811970 are wired to the conductive bumps of the underlying wafer for connection to the substrate-layer wafer. The wire bonding method achieves each layer of wafers and is electrically connected. In addition, it is also possible to use the technology of the reverse bonding wire process to electrically connect the layers of the substrate other than the substrate: the reverse: = the conductive bumps of the wafer are sequentially electrically conductive from the underlying wafer. The convex two" reverse bonding wire technology is wired to the conductive bumps of the upper wafer to form an electrical connection between the substrate and the wafer stacked thereon. Compared with the prior art, it is necessary to cause _ y ^ lengthening welding The pad is connected to a plurality of bonding wires; the use of: the available area of the film, by the bonding wire of the present invention, the connection of the if: industry is concentrated on the single-conducting bump, so as not to lengthen the wafer to make a wafer - the conventional technique of The fresh wire connection is maintained on a wafer with a long fresh slab. The wafer is designed in a relatively small size, and the soldering and transporting method of the present invention does not need to be lengthened 鍟 = connecting a plurality of bonding wires. The process technology required for the fresh wire connection method of the present invention can be reduced to a small size: the same as: the application of the wafer and the guide (four) benefits for the electrical connection of the wafer A good line connection method of the present invention Improvements to the disadvantages of the prior art and the fact that the actual two functions have a high degree of industrial use. 19260 9 200811970 The following is a specific embodiment to illustrate the embodiments of the present invention. Those skilled in the art can disclose the contents disclosed in the present specification. Easily-understand the advantages and effects of the present invention. First Embodiment Please refer to Figures 3A to 3D, which are schematic views of the first embodiment of the wire bonding method of the present invention. - As shown in Figure 3A, The first electronic component is placed on the second electronic component; the first electronic component is a semiconductor wafer 30, and the second electronic component is a substrate 3. The first and second electronic components are electrically connected. a contact pad, such as a pad 3〇1 formed on the active surface of the semiconductor wafer 30, and a ground pad (or ground ring) 32 (which may also be a power pad or a power ring) formed on the substrate 31, and A conductive bump 34 is formed on at least one pad 3〇1 of the semiconductor wafer 3. The conductive bump 34 may be a gold bump (Au Stud), which is formed on the solder bump by using a fresh wire machine to sinter the gold wire. As shown in Figure 3B, using reverse wire bonding The bonding wire 33a is soldered to the conductive bump 34 from the ground pad (ring) 32 of the substrate 31, so that the bonding wire 33a is soldered to the conductive bump 34 at a nearly horizontal angle. The wire 33a is a gold wire, which is formed on the grounding pad (ring) 32 of the substrate 31 by a tip 35 of a wire splicer to form a ball joint 331a (ball bond). And moving the soldering tip to the conductive bump 34, and then cutting the bonding wire 33a to form a stitch bond 332a (stitch bond), and completing the ground pad (ring) 32 from the substrate 31 to the half The wire bonding operation of the conductive bumps 34 on the body wafer 30. Please refer to Figure 3C for the corresponding view of Figure 3B to show the connection of 19260 10 200811970 = the first electronic component (semiconductor wafer) on the second electronic component (substrate) And each other forms an electrical connection. If the 3D drawing is not used, the general-purpose wire bonding operation is performed, and the welding is performed on the seam 343a of the y-bump 34 to the grounding 塾 (ring) of the substrate 31 32. The wire bonding operation is performed on the seam solder joint 332a of the conductive bump μ to form a ball joint 35 to the grounding ring (ring) 2 of the substrate 31, and then the fresh wire 2 is cut to form another seam solder joint. 33 holes, and complete the repeated wire bonding operation between the first and second electronic components (wafer and substrate), as shown in the figure 3D, the upper phase m. H 丄 #马", the top view of the page Since the semiconductor wafer 30 and the base-sub-bonding wire are connected from the substrate 31 to the conductive bump 34, the conductive bumps are soldered to the conductive bumps a by a horizontal angle of the bonding wires 33a without affecting Subsequent to the process of forming the fresh line 33b on the seam of the bonding wire of the conductive bump 34. ^Two embodiment _ Please refer to Fig. 4, which is a schematic diagram of the second method of bonding the wire of the present invention. The first embodiment of the present month is substantially the same as the first embodiment. The main difference of the basin is in the second embodiment. The second electronic component is a lead frame Λ $ 线 41 has a wafer holder 411 and A plurality of guide pins 412 disposed around the wafer holder 41 are placed on the first electronic component of the Japanese film Zhuangfeng ¥ body wafer 40. The solder bumps 401 of the semiconductor wafer 4G further have conductive bumps 44 for utilizing the bonding wires 43a and the bonding wires to electrically connect the electrical contacts from the 4-stand, that is, the guiding pins 412 (for example, Grounding lead) 19260 11 200811970 Conductive bump 44 electrically connected to the semiconductor wafer 4G - The bump 44 is electrically connected to the lead 412. From the %, the other four (t) t-contacts can be materialized , the socket is used to provide the grounding action of the semiconductor wafer by using the wafer holder. _ Third embodiment exception, please refer to FIG. 5A to FIG. 5C, which is a schematic diagram of the front side of the present invention. As shown in FIG. 5A, the electronic components have a wafer carrier, such as a substrate 5, a first wafer placed on the substrate 51, and a second wafer placed on the first wafer 5Ga. The substrate 51, the first wafer 50a and the second wafer 50b are respectively provided with electrical contacts such as a ground pad 51, a box, a 50U and a pad 501b, and a fresh pad on the first wafer 5 501a is provided with a conductive bump 54. As shown in FIG. 5B, then, the reverse bonding wire is used for the operation. The electronic component of the conductive bump is wired to the conductive bump, that is, the soldering wire 53a is soldered from the ground pad 510 of the base spring 51 to the conductive bump 54 of the first wafer 5 〇 & The wire operation is formed on the ground pad 51 of the substrate 51 by using a soldering nozzle 55 to form a ball contact 531a (ballb〇nd), and then moving the soldering nozzle 55 to the conductive bump 54, and then cutting the bonding wire 53a. A stitching 532a (stitch bond) is formed to complete the wire bonding operation from the electrical contact (ground 塾 510) of the substrate 51 to the conductive bump 54 of the first wafer 5A. In addition, the electrical contact of the substrate 51 may be a power pad or the like in addition to the ground pad. As shown in FIG. 5C, a ball joint 53lb' is formed on the pad 501b of the second wafer 5b by 12 19260 200811970, and then the tip 55 is moved to the seam on the conductive bump 54. Solder joint 532a' is formed to form bond wire 53b, and then the weld is cut 53b to form another seam weld 532b to form an electrical connection of the second wafer 5 to the first wafer 50a. In addition, the bonding of the first and second wafers 50a, 5〇b can also be achieved by the technique of the reverse bonding wire process. As shown in FIG. 5D, the bonding pad 5 of the second wafer 50b can be used. A conductive bump 54 is formed on the ib. After the substrate 51 is connected to the bonding wire of the first wafer, a ball joint 531b can be formed on the seam solder joint 532a, and the ball type is connected by the ball type. At the point, the bonding wire 53b is soldered by the technique of the reverse bonding wire to the conductive bump 54 of the second wafer 5b, and the wire bonding operation between the first and second wafers 5a, 5b is formed. A four-part embodiment 请, please refer to Fig. 6, which is a schematic view of a semiconductor structure formed by the fourth embodiment of the wire bonding method of the present invention. The fourth embodiment of the present invention is substantially the same as the third embodiment, and the main difference is that the semiconductor structure has a substrate 61 and a plurality of semiconductor wafers attached to the US 61, including the first layer on the bottom layer. The crystal/6〇a, the second wafer 6叽 disposed on the first wafer 60a, and the third wafer 6〇c disposed on the second wafer 60b form a stepped semiconductor structure. In the semiconductor structure of the multi-wafer stack, at least the conductive bumps 64 are connected to the pads of the first wafer 60a. In this embodiment, the bonding pads 63a are soldered from the electrical contacts of the substrate 61 to the conductive bumps 64 of the first wafer 60a by the technique of reverse bonding wires, and then the ball contacts 65a are formed on the second wafer 60b. And the ball joint 65a 19260 13 200811970 welds the wire 63b to the conductive bump 64 of the first wafer 60a, and similarly, a ball joint 65b is formed on the third wafer 60c, and the ball type is formed by the ball type Point 65b is soldered to the conductive bump 64 of the first wafer 6A, and a plurality of Ting wires are connected to the conductive bump 64 of the first piece 60a. It should be noted that the present embodiment can also electrically connect the wafers of the respective layers with reference to the technique of the reverse bonding wire process of the third embodiment. In this case, the wafers of the layers except the substrate 61 have conductive bumps. . Therefore, the semiconductor structure of the wafer stack can be electrically connected to each component by means of a wire bonding method, wherein all of the semiconductor wafers can have a plurality of bonding wires to connect to the upper layer by a normal size electrical connection.
I層之半導體晶片。此外，該多晶片之堆疊數目不以:圖 式之3層晶片為限。 M 再者说述之多晶片堆疊之丰導士雄__ 、、 2架作為晶片承載件’並得利用銲線以供堆疊於該 •腳切數層+導體晶片電㈣接至該導線架之晶片座及導 二以加長之電性連接塾連接複數銲線 成^用曰曰片可用面積之現象 方法，將打線作業集中於單 /月之#線連接 連接塾之前提下使—電性賴 加晶片之可用面積。夕以線’進而增 另外’習知技術為了於— 保持電性連接塾之數旦_/、加“性連接塾之晶片上 而本發明之銲、=二只能將晶片以較大之尺寸設計^ 連接方法，因為不須具有加長之電性連接 19260 14 200811970 墊即可便利地於單一電性連接墊上連接多條銲線，因此晶 •片可朝小尺寸化之趨勢持續發展。 • 再者，本發明之銲線連接方法所需之製程技術以既有 的機台設備即可達成，無論應用於由晶片電性連接至具導 腳之導電裝置或應用於多層晶片的電性連接皆具有良好之 效益。 ‘ 惟以上所述之具體實施例，僅係用以例釋本發明之特 • 點及功效，而非用以限定本發明之可實施範疇，在未脫離 _本發明上揭之精神與技術範疇下，任何運用本發明所揭示 内容而完成之等效改變及修飾，均仍應為下述之申請專利 範圍所涵蓋。 【圖式簡單說明】 第1A及1B圖係顯示習知技術之銲線連接方法應用於 電性連接晶片與基板， 第2圖係顯示習知技術之銲線連接方法應用於電性連 _接具多層晶片之半導體封裝件； • 第3A至第3E圖係說明本發明之銲線連接方法之第一 具體實施例； 第4圖係說明本發明之銲線連接方法之第二具體實施 例； 第5A至第5D圖係說明本發明之銲線連接方法之第三 具體實施例；以及 第6圖係說明本發明之銲線連接方法之第四具體實施 例0 15 19260 200811970 【主要元件符號說明】 Ί0 半導體晶片 -101 一般銲墊 102 長銲墊 11 基板 12 接地環 13 鲜線 21 基板 20a 第一晶片 20b 弟二晶片 202 長銲墊 23a 銲線 23b 鲜線 30 半導體晶片 31 基板 1 301 鲜塾 32 接地墊（環） 33a 銲線 331a 球型接點 332a 縫接銲點 33b 銲線 331b 球型接點 332b 縫接銲點 34 導電凸塊 200811970 35 銲嘴 ，40 半導體晶片 -401 銲墊 41 導線架 411 晶片座 412 導腳 43a 鋅線 43 b 銲線 44 導電凸塊 50a 第一晶片 501a 銲墊 50b 第二晶片 501b 鲜塾 51 基板 510 鲜線藝 1 53a 焊線 531a 球型接點 531b 球型接點 532a 缝接銲點 532b 缝接銲點 53b，53b， 銲線 54,54， 導電凸塊 55 銲嘴 60a 第一晶片 200811970 60b 弟二晶片 ^ 60c 第三晶片 -61 基板 63a 銲線 63b 銲線 63c 銲線 - 64 導電凸塊 * 65a 球型接點 • 65b 球型接點A semiconductor wafer of the I layer. In addition, the number of stacked stacks of the multi-wafer is not limited to the 3-layer wafer of the drawing. M is further described as a multi-wafer stack of Feng Shixiong __, 2 as a wafer carrier' and has to use a bonding wire for stacking on the pin-cut layer + conductor wafer (4) to the lead frame The wafer holder and the second lead are connected by a lengthy electrical connection to connect the plurality of bonding wires into a method for using the available area of the cymbal, and the wire bonding operation is concentrated on the single/month connection of the wire. The usable area of the Laiga wafer. In the evening, the line 'further adds another' to the conventional technology in order to maintain the electrical connection 塾 _ /, plus the "sexual connection" on the wafer and the welding of the invention, = two can only make the wafer to a larger size Design ^ connection method, because it is not necessary to have an extended electrical connection 19260 14 200811970 pad can easily connect multiple bonding wires on a single electrical connection pad, so the crystal chip can continue to develop toward a smaller size. The process technology required for the wire bonding method of the present invention can be achieved by using an existing machine tool, whether it is applied to a conductive connection from a wafer to a conductive device with a lead or to a multilayer wafer. It is to be understood that the specific embodiments described above are merely used to exemplify the features and functions of the present invention, and are not intended to limit the scope of the present invention. In the spirit and technology, any equivalent changes and modifications made by the disclosure of the present invention should be covered by the following patent application. [Simplified illustration] Figures 1A and 1B show the habits The wire bonding method of the technology is applied to electrically connect the wafer and the substrate, and the second figure shows the wire bonding method of the prior art applied to the electrical connection of the semiconductor package of the multilayer wafer; • 3A to 3E The first embodiment of the bonding wire bonding method of the present invention is explained; the fourth embodiment is a second embodiment of the bonding wire bonding method of the present invention; and the fifth embodiment to the fifth embodiment illustrate the bonding wire bonding method of the present invention. The third embodiment of the present invention and the sixth embodiment illustrate the fourth embodiment of the bonding wire bonding method of the present invention. 0 15 19260 200811970 [Description of main components] Ί0 Semiconductor wafer - 101 General bonding pad 102 Long bonding pad 11 substrate 12 Grounding ring 13 Fresh wire 21 Substrate 20a First wafer 20b Second chip 202 Long pad 23a Bond wire 23b Fresh wire 30 Semiconductor wafer 31 Substrate 1 301 Fresh 塾 32 Ground pad (ring) 33a Wire 331a Ball joint 332a Seam joint 33b bond wire 331b ball joint 332b seam weld 34 conductive bump 200811970 35 tip, 40 semiconductor wafer - 401 pad 41 lead frame 411 wafer Seat 412 Leading 43a Zinc wire 43 b Wire bonding wire 44 Conducting bump 50a First wafer 501a Pad 50b Second wafer 501b Fresh 塾 51 Substrate 510 Fresh wire 1 53a Bonding wire 531a Ball joint 531b Ball joint 532a Seam solder joint 532b seam solder joint 53b, 53b, bond wire 54, 54, conductive bump 55 solder tip 60a first wafer 200811970 60b second wafer ^ 60c third wafer - 61 substrate 63a bonding wire 63b bonding wire 63c welding Wire - 64 Conductive Bumps * 65a Ball Joints • 65b Ball Joints