200811867 九、發明說明： 【發明所屬之技術領域】 本發明一般而g係關於快閃EEPROM(電可抹除及可程式 化唯讀記憶體）型之非揮發性半導體記憶體，尤其係操作 反及型記憶體單元陣列的結構及方法。本申請案中引用之 • 所有專利、專利申請案及其他材料在此藉由參考全數併 « 入0 【先前技術】 •今日使用許多商業上已成功之非揮發性記憶體產品，尤 其係依小形狀因數卡之形式，其使用一快閃EEpR〇M單元 陣列。 一範例記憶體系統係由圖丨之方塊圖所示。包括配置在 一矩陣中之複數個記憶體單元的記憶體單元陣列丨係由— 行控制電路2、一列控制電路3、一 c源極控制電路4及_ P井控制電路5所控制。在此範例中，該記憶體單元陣列】 φ ，反及型快閃記憶體陣列。一控制電路2係連接至記憶體 單兀•陣列1之位70線（BL)，用於讀取儲存在記憶體單元内 2資料，用於在程式操作期間決定該記憶體單元的一狀 以及用於控制位元線（BL)的電位位準以促成程式化或 、 禁j程式化。列控制電路3係連接至字元線（WL)以選擇該 等字元線（WL)中之-，施加讀取電壓，施加組合受行控制 電路2控制的位元線電位位準之程式電壓，並施加一與其 上形成記憶體單it的-P型區（單以井）之—電壓搞合的抹 除電壓。C源極控制電路4控制—連接至該等記憶體單元之 120783.doc 200811867 共用源極線。e-p井控制電路5控制單元p井電壓。 儲存在§己憶體單元中之資料係由行控制電路2讀出，且 係經由一 I/O線及一資料輸入/輸出緩衝器6輸出至外部1/〇 線。欲儲存在記憶體單元中之程式資料係經由外部ι/〇線 輸入至資料輸入輸出緩衝器6，且轉移至行控制電路2。外 部I/O線係連接至控制器9。控制器9包括各種類型之暫存 ，及包括一揮發性隨機存取記憶體（RAM) 1〇的其他記憔 體。 " 用於控制快閃記憶體裝置之命令資料係輸入至連接外部 控制線的命令電路7，外部控制線係連接控制器9。命令資 料通知快閃記憶體係要求哪一種操作。輸入命令被轉移至 一狀態機8，其控制行控制電路2、列控制電路3、e源極控 制4、c-p井控制電路5及資料輸入/輸出緩衝器6。狀態機^ 可輸出快閃記憶體的狀態資料，諸如REadY/busy或 PASS/FAIL。 控制器9係連接或可連接一主機系統（例如個人電腦、數 位相機或個人數位助理）。主機開始命令，例如將資料儲 存至記憶體陣列1内或從記憶體陣列丨讀取資料，並分別提 供或接收此資料。控制器將此等命令轉換成為命令信號， 其可由命令電路7解譯及執行。控制器通常亦含有緩衝記 憶體，用於被寫至記憶體陣列或自其讀出之使用者資料。 典型記憶體系統包括一積體電路晶片丨1A，其包括控制器 9，·以及一或多個積體電路晶片nB，其各包含一記憶體陣 列與相關控制、輸入/輸出及狀態機電路。可將一系統之 120783.doc 200811867 記憶體陣列與控制器電路一起整合在一或多個積體電路晶 片上。 可嵌入圖1之記憶體系統成為主機系統的一部分，或可 將其包括在一記憶卡内，該記憶卡係可移除地可***一主 機系統之一配合插座中。此—^可包括整個記憶體系統，200811867 IX. Description of the Invention: [Technical Field] The present invention generally relates to a non-volatile semiconductor memory of a flash EEPROM (Electrically Erasable and Programmable Read Only Memory) type, in particular, an operational inverse Structure and method of a memory cell array. All patents, patent applications, and other materials cited in this application are hereby incorporated by reference in its entirety in the entire disclosures in the the the the the the the the the the the the the the In the form of a form factor card, it uses a flash EEpR〇M cell array. An example memory system is shown in the block diagram of the figure. The memory cell array including a plurality of memory cells arranged in a matrix is controlled by a row control circuit 2, a column control circuit 3, a c source control circuit 4, and a _P well control circuit 5. In this example, the memory cell array is a φ, inverted-type flash memory array. A control circuit 2 is connected to the memory unit 兀 Array 1 bit 70 line (BL) for reading data stored in the memory unit 2 for determining the shape of the memory unit during program operation and Used to control the potential level of the bit line (BL) to facilitate stylization or stylization. The column control circuit 3 is connected to the word line (WL) to select - in the word line (WL), applies a read voltage, and applies a program voltage that combines the potential level of the bit line controlled by the line control circuit 2. And applying an erase voltage that is coupled to the voltage of the -P-type region (single well) on which the memory single is formed. C source control circuit 4 controls - connected to the memory cells 120783.doc 200811867 shared source line. The e-p well control circuit 5 controls the cell p-well voltage. The data stored in the § memory unit is read by the row control circuit 2 and output to the external 1/〇 line via an I/O line and a data input/output buffer 6. The program data to be stored in the memory unit is input to the data input/output buffer 6 via the external ι/〇 line, and is transferred to the line control circuit 2. The external I/O line is connected to the controller 9. The controller 9 includes various types of temporary storage and other recordings including a volatile random access memory (RAM). " The command data for controlling the flash memory device is input to the command circuit 7 connected to the external control line, and the external control line is connected to the controller 9. The command information informs the flash memory system which operation is required. The input command is transferred to a state machine 8, which controls the row control circuit 2, the column control circuit 3, the e source control 4, the c-p well control circuit 5, and the data input/output buffer 6. The state machine ^ can output status data of the flash memory, such as REadY/busy or PASS/FAIL. The controller 9 is connected or connectable to a host system (e.g., a personal computer, a digital camera, or a personal digital assistant). The host initiates a command, such as storing data in or reading from the memory array 1 and providing or receiving the data separately. The controller converts these commands into command signals that can be interpreted and executed by the command circuit 7. The controller typically also contains a buffer memory for writing to the memory array or user data read from it. A typical memory system includes an integrated circuit chip 1A that includes a controller 9, and one or more integrated circuit chips nB, each of which includes a memory array and associated control, input/output, and state machine circuits. A system of 120783.doc 200811867 memory arrays can be integrated with one or more integrated circuit wafers along with the controller circuitry. The memory system that can be embedded in Figure 1 becomes part of the host system or can be included in a memory card that is removably insertable into one of the host systems to fit into the socket. This - ^ can include the entire memory system,
或具相關周邊電路之控制器與記憶體陣列及可提供在分離 卡内。若干卡實施方案係（例如）在美國專利第5,887，145號 中說明，該專利係全部以此引用清楚地併入本文。 一流行快閃EEPROM架構利用反及陣列，其中大量記惊 體單元串係在個別位元線與一參考電位間透過一或多個選 擇電晶體來連接。此一陣列之一部分係顯示於圖2A的平面 圖中。BL0至BL4(其中BL1至BL3亦標記為12至16)表示至 總體垂直金屬位元線（未顯示）之擴散位元線連接。儘管在 各串中係顯示四個浮動閘極記憶體單元，但該等個別串一 般在一行内包括16、32或更多記憶體單元電荷儲存元件， 例如浮動閘極。標記為WL0至WL3之控制閘極（字元）線（在 圖2B中標記為P2，沿圖2A之線A_A的斷面），且串選擇線 SGD及SGS在浮動閘極（通常在多晶 串延伸（在圖2B中標示為P1)。然而 石夕中）之列上橫跨多個 ’對於電晶體40及50而 言，可電連接控制閘極及浮動閘極(未顯示)。該等控制閘 極線-般係於該等浮㈣極上形成為—自對準堆疊，並透 過一中間介電層19來相互電容性輕合，如圖2B所示。該串 =部及底部—般透過一使用浮動閘極材料（ρι)作為其由 周邊電驅動之主_極的電晶體，而分別連接至位元線及 120783.doc 200811867 一共用源極線。在浮動閘極與控制閘極之間的此電容性耦 合允許藉由增加在該處所耦合之控制閘極上的電壓來提升 、子動閘極之電壓❶在一行内的一個別單元係藉由置放一相 對較高電壓在其個別字元線上，並藉由置放一相對較低電 壓在一選定字元線上來使該串内的剩餘單元開啟，使得流 過各串之電流主要僅取決於儲存在選定字元線下的已定址 單元内的電荷位準，來在程式化期間讀取並驗證。該電流 一般針對大量的串來平行感測，從而沿一列浮動閘極平行 地讀取電荷位準狀態。 反及i陕閃δ己彳思體及其操作的相關範例係於以下美國專 利案/專利申請案中提供，其全部以引用方式併入本文： 5,570,315 ； 5,774,397 ； 6,046,935 ； 6,456,528 及 6,522,580號。 目前快閃EEPROM陣列之電荷儲存元件大多數係導電浮 動閘極，通常由摻雜多晶矽材料形成。然而，具有電荷儲 存能力而無須導電之其他材料亦可使用。此一替代材料之範 幻係氮化碎。此一單元係於Takaaki Nozaki等人之文獻，'半導 體碟片應用之具MONOS記憶體單元的丨Mb EEpR〇M” (IEEE固態電路期刊，第26卷，第4號，丨的丨年#月，第497 至501頁）中說明。 典型非揮發性快閃陣列之記憶體單元係分為-起抹除的 單之離散區塊1 ’該區塊含有係可單獨抹除而一起成 為抹除單兀之單元的最小數目，冑然在單一抹除操作中 可抹除多於-區塊。各區塊通常儲存一或多數頁的資料， 120783.doc 200811867 >頁疋義為料進行f料料減讀取操作成為程式化及 言買取之基本單元的置- 早兀之最小數目，雖然在單一操作中 程式化或讀取多於_ ;頁。各頁一般儲存一或多個資料區 段’區段大小得由士她/ 、 —v、機系統來定義。一範例為使用者資料 之512位το组之區段，其依循採用磁碟機建立的桿 上關於使用者資料及/或其中儲存之區塊的額外負擔資訊 之某數目的位元組。 、 如在大多數積體電路應用巾’快閃EEpR〇M陣列中亦存 在用以縮小實施一些積體電路功能所需的矽基板面積之壓 力持々而要增加可儲存在一矽基板給定區域中之數位資 ^的量’以增加一給定大小記憶卡及其他封裝型之儲存容 量’或同時增加容量並減小大小。增加資料儲存密度之另 -方法係每一記憶體單元電荷儲存元件儲存多於一資料位 元。此係藉由將電荷儲存元件之可允許電壓或電荷儲存窗 分成多於二狀態而達成。使用四個此類狀態使得各單元可 儲存二資料位元’八狀態可每_單元儲存三資料位元，依 此類推。-多狀態快閃EEPR0M結構及操作係描述於美國 專利第 5,〇43,94〇，· 5，172,338; 5,57〇,315及6〇46 935 號 中。 用於-使用反及結構之快閃記憶體系統的典型架構將包 括反及陣列’其中各陣列包括數個反及串。例如，圖从僅 顯示圖2 A之記憶體陣列的三個反另虫 ,0 ^ 1 丨口久及串II、13及15，該陣列 含有多於三個反及串。圖3A之反；5& 久及串中的各者包括二個選 擇電晶體與四個記憶體單元。例 a ^ ^ 1夕J如，反及串II包括選擇電 120783.doc 200811867 晶體20及30 ’及記憶體單元22、24、26及28。反及串13包 括選擇電晶體40及50，及記憶體單元42、44、46及48。各 串係藉由其選擇電晶體（如選擇電晶體3〇及選擇電晶體5〇) 連接至源極線。使用一選擇線SGS來控制源極侧還擇閘 極。各種反及串藉著由選擇線SGD所控制的選擇電晶體 20、40等與個別位元線連接。在其他具體實施例中，該等 選擇線不一定必須為共用。字元線WL3係連接至記憶體單 元22及記憶體單元42的控制閘極。字元線WL2係連接至記 憶體單元24及記憶體單元44的控制閘極。字元線WL1係連 接至記憶體單元26及記憶體單元46的控制閘極。字元線 WL0係連接至記憶體單元28及記憶體單元48的控制閘極。 如圖所示，各位元線及連接至其的反及串形成記憶體單元 陣列的該等行。字元線（WL3、WL2、WL1及WL0)包含該 陣列的該等列。各字元線連接該列中各記憶體單元的控制 閘極。例如，字元線WL2係連接至記憶體單元24、44及64 的控制閑極。 圖3B係描述一些反及串的電路圖，其中一區塊中之各串 由一組共用字元線控制。一區塊係一反及記憶體陣列的抹 除單元。共享一共用組字元線和源極及汲極選擇線之串形 成圖2A至3B的反及設計中之一區塊。圖2A及3A至3B的串 11、13連同其他串出現在圖3B中之一區塊中。如圖3B中顯 示，相同陣列中之各反及串（如U、13)係連接至複數個位 元線12 ' 14、…中之一且至一共用源極線，及係由一共用 組字元線（WL0至WL3)控制。 120783.doc -10- 200811867 ㈣體單元可儲存資料(類比或 數位資料時(二進制記憶體單元) ：儲存-位- 界電屢範圍係分成二範圍，其係指派;:：的可能臨 。在一及另刑k a 為邏輯資料”1"及 在反及型快閃記憶體之範例中 後的臨界電壓為負且係定義為邏輯— 體単兀 臨界電壓為正且係定義為邏輯心t臨界=操作後之 由向控制極施加〇伏特來嘗試 ，純負亚猎Or a controller and memory array with associated peripheral circuitry and can be provided in a separate card. A number of card embodiments are described, for example, in U.S. Patent No. 5,887,145, the entire disclosure of which is hereby incorporated by reference. A popular flash EEPROM architecture utilizes an inverse array in which a large number of stunned cell strings are connected between individual bit lines and a reference potential through one or more selective transistors. A portion of this array is shown in the plan view of Figure 2A. BL0 to BL4 (where BL1 to BL3 are also labeled 12 to 16) represent diffusion bit line connections to the overall vertical metal bit line (not shown). Although four floating gate memory cells are shown in each string, the individual strings typically include 16, 32 or more memory cell charge storage elements, such as floating gates, in a row. The control gate (character) lines labeled WL0 through WL3 (labeled P2 in Figure 2B, along the line A_A of Figure 2A), and the string select lines SGD and SGS are at the floating gate (usually in polycrystalline The string extension (labeled P1 in Figure 2B), however, spans a plurality of 'in the case of transistors 40 and 50, electrically connected to control gates and floating gates (not shown). The control gates are typically formed as self-aligned stacks on the floating (four) poles and capacitively coupled to one another via an intermediate dielectric layer 19, as shown in Figure 2B. The string = portion and the bottom are connected to the bit line and a common source line by using a floating gate material (ρι) as a main-electrode transistor driven by the periphery. This capacitive coupling between the floating gate and the control gate allows the voltage of the sub-gate to be boosted by a voltage on the control gate coupled to the location. Placing a relatively high voltage on its individual word lines and opening a remaining cell within the string by placing a relatively low voltage on a selected word line such that the current flowing through the strings is primarily dependent only on The level of charge stored in the addressed location below the selected word line is read and verified during stylization. This current is typically sensed in parallel for a large number of strings to read the charge level state in parallel along a column of floating gates. A related example of the smear and its operation is provided in the following U.S. Patent/Patent Application, which is hereby incorporated by reference in its entirety herein in its entirety in the the the the the the the the the the the the the the Most of the current charge storage elements of flash EEPROM arrays are electrically conductive floating gates, typically formed of doped polysilicon material. However, other materials having charge storage capability without conduction are also available. The paradigm of this alternative material is nitrided. This unit is based on the literature of Takaaki Nozaki et al., 'Mb EEpR〇M with MONOS memory unit for semiconductor disc applications' (IEEE Solid State Circuits, Vol. 26, No. 4, 丨 丨 # #月, pages 497 to 501. The memory unit of a typical non-volatile flash array is divided into a single discrete block of erased 1 'the block containing the system can be erased separately and become erased together The minimum number of units in a single unit can be erased more than a block in a single erase operation. Each block usually stores one or more pages of data, 120783.doc 200811867 > The material minus read operation becomes the minimum number of pre-programmed and buy-after basic units, although it is programmed or read more than _ in a single operation; each page generally stores one or more data areas. The segment 'segment size is defined by Shi She /, -v, machine system. An example is the 512-bit τ group of the user data, which follows the information about the user created by the disk drive and/or Or a certain number of bits of additional burden information for the block stored therein For example, in most integrated circuit application wiper 'flash EEpR 〇 M arrays, there is also a pressure holding for reducing the area of the ruthenium substrate required to implement some integrated circuit functions, and it is necessary to increase the storage on a substrate. The amount of digital information in a given area 'to increase the storage capacity of a given size memory card and other package type' or increase the capacity and reduce the size at the same time. Another method to increase the data storage density is the charge of each memory unit. The storage element stores more than one data bit. This is achieved by dividing the allowable voltage or charge storage window of the charge storage element into more than two states. Four such states are used such that each unit can store two data bits. Eight states can store three data bits per _ unit, and so on. - Multi-state flash EEPR0M structure and operation are described in U.S. Patent No. 5, 〇 43, 94 〇, 5, 172, 338; 5, 57 〇, 315 And 6 〇 46 935. A typical architecture for a flash memory system using an inverse structure will include an inverse array where each array includes several inverse strings. For example, the figure shows only Figure 2A. Memory array The three anti-existing insects, 0 ^ 1 丨口久 and strings II, 13 and 15, the array contains more than three inverse and string. Figure 3A is the opposite; 5 & long and the string includes two options The transistor and the four memory cells. Example a ^ ^ 1 夕 J, and the string II includes the selection of electricity 120783.doc 200811867 Crystals 20 and 30 ' and memory cells 22, 24, 26 and 28. Reverse and string 13 The selection includes transistors 40 and 50, and memory cells 42, 44, 46, and 48. Each string is connected to the source line by its selection transistor (e.g., select transistor 3 〇 and select transistor 5 〇). A select line SGS is used to control the source side to also select the gate. The various reverse strings are connected to the individual bit lines by the selection transistors 20, 40 and the like controlled by the selection line SGD. In other embodiments, the select lines do not have to be shared. The word line WL3 is connected to the control unit of the memory unit 22 and the memory unit 42. The word line WL2 is connected to the control gate of the memory unit 24 and the memory unit 44. The word line WL1 is connected to the control gates of the memory unit 26 and the memory unit 46. The word line WL0 is connected to the control unit of the memory unit 28 and the memory unit 48. As shown, the individual lines and the inverted strings connected thereto form the rows of the memory cell array. The word lines (WL3, WL2, WL1, and WL0) contain the columns of the array. Each word line is connected to the control gate of each memory cell in the column. For example, word line WL2 is coupled to the control idles of memory cells 24, 44, and 64. Figure 3B is a circuit diagram depicting some inverse strings in which the strings in a block are controlled by a common set of word lines. One block is an erase unit that is opposite to the memory array. The shared common group word line and the source and drain select lines are formed into one of the blocks of Figures 2A to 3B and the design. The strings 11, 13 of Figures 2A and 3A through 3B appear in one of the blocks of Figure 3B along with other strings. As shown in FIG. 3B, each of the inverse strings (eg, U, 13) in the same array is connected to one of the plurality of bit lines 12' 14, ... and to a common source line, and is shared by a common group. Word line (WL0 to WL3) control. 120783.doc -10- 200811867 (4) Body unit can store data (in the case of analog or digital data (binary memory unit): storage - bit - the boundary of the boundary is divided into two ranges, the system is assigned; the possibility of:: One and the other penalty ka is the logical data "1" and the threshold voltage in the anti-flash memory example is negative and is defined as logic - the body threshold voltage is positive and the system is defined as the logical heart t-critical = After the operation, try to apply 〇Vot to the control pole, pure negative sub-hunting
會傳導電流以指示正在儲存邏輯一:：二=體單元 _ ^ _ 田臨界電壓為正並嘗 I㈣操作時’記憶體單元關閉’其指示储存邏輯零。 一記憶體單元亦可儲存多位準之資訊，例如，多位元之數 位資料。在儲存多位準資料的情形下，可能的臨界電虔範 圍係分為資料位準之數目。例如，若儲存四位準的資訊， 則將會有四臨界電壓範圍’各範圍指派予一資料值。藉由 在臨界電壓之多個（即多於二）範圍間微分來储存資料^記 憶體係稱為多狀態記憶體。在反及型記憶體之—範例中， 抹除操作後之臨界電壓係負並定義為"η"β正臨界電壓係 用於"10”、”01，，及，，00，’之狀態。 當程式化一反及快閃記憶體單元時，一程式電壓係施加 至控制閘極，且被選定用於程式化之反及串的通道區域係 接地（0V)。來自反及串下通道區域之電子係注入浮動閘 極。當電子累積在浮動閘極中時，該浮動閘極變為帶負電 而該單元的臨界電壓提升。為了使選定反及串之通道區域 接地’對應位元線係接地（〇伏特），而8〇〇係連接至一足夠 高之電壓（通常Vdd在例如3·3伏特），其係高於選擇電晶體 120783.doc -11 · 200811867A current is conducted to indicate that the logic one is being stored:: ==body unit _ ^ _ The field threshold voltage is positive and the I (four) operation 'memory unit off' indicates that it stores logic zero. A memory unit can also store multiple levels of information, such as multi-bit digital data. In the case of storing multiple levels of data, the range of possible thresholds is divided into the number of data levels. For example, if four levels of information are stored, then there will be four threshold voltage ranges' each range assigned to a data value. The data is stored by differentiating between multiple (i.e., more than two) ranges of the threshold voltage. The memory system is called multi-state memory. In the example of the inverse memory type, the threshold voltage after the erase operation is negative and defined as "η"β positive threshold voltage is used for "10", "01,,,,, 00,' status. When stylized with a flash memory cell, a program voltage is applied to the control gate and the channel region selected for stylized inverse is tied to ground (0V). The electrons from the reverse channel region are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the critical voltage of the cell rises. In order to ground the channel region of the selected inverse string and the corresponding bit line is grounded (〇V), and the 8〇〇 system is connected to a voltage high enough (usually Vdd is, for example, 3·3 volts), it is higher than the selection. Transistor 120783.doc -11 · 200811867
之臨界Μ。4了將程式電壓施加至被程式化單元之控制 閘極’該程式電壓被施加至適當字元線上。如上述，該字 元線亦與利用相同字元線的其他反及串之各串内的一單元 連接。例如’當程式化圖3Α之單元24時，程式亦將會 被施加至單元44之控制閘極，因為二單元共享相同字元 線。^需要在—字元線上程式化-單元而不程式化連接至 相同子7L線之其他單元，例如當需要程式化單元24而非單 70 44時’會產生—問題。因為程式電壓係施加至連接至一 字元線的所有單元，在該字元線上之一未選定單元（一不 欲程式化之單元）可能被不慎地程式化。例如，單元44係 =近早70 24。當程式化單元24時，可能有不預期地程式化 單元44之虞。選定字元線上之未選定單元的不預期程式化 稱為"程式干擾"。更一般而言，"程式干擾"係用於描述任 何不希望的臨界電壓偏移，不論在正或負方向中，其可能 發生在程式化操作期間且無須限於選定字元線。 可使用若干技術來防止程式干擾。一種稱為"自增壓 用SB方案程式化期間，未選定反及串之通道區域係與其對 應位元線電絕緣。其後，一中間之通電壓（如1〇伏特）係施 Γ^’’）的方法係由K.D. Suh等人在"一種具増量步進脈衝程 式化方案之3.3伏特32 Mb反及快閃記憶體”，固態電路期 刊’第30卷，第U號，1995年叫，第1149 ii55i在使 加至未選定字元線’而一高程式化電壓(如18伏特)係施加 至選定字元線。在此申請案中，名詞"絕緣"及"電絕緣"係 可交換使用，且名詞"寫入電壓"、”程式電壓"及"程式化電 120783.doc -12· 200811867 壓”係可交換使用。未選定反及串的通道區域係電容性耦 合至未選定字元線，造成一電壓（如六伏特，假設〇.6之耦 合比）存在於未選定反及串的通道區域中。此所謂"自增壓” 減少未選定反及串通道區域及施加至選定字元線的程式電 壓間之電位差。結果，對於在未選定反及串中之記憶體單 元，且尤其是對於選定字元線上此等串中的記憶體單元， 橫跨穿隨氧化物之電壓且因此程式干擾係明顯地減少。 參考圖3 A，當將一自增壓程式技術應用至圖3 A中之記 憶體陣列’以程式化位元線12上之該等單元中之一時，例 如將零伏特施加至位元線12，且電壓Vdd (如3·3伏特）係施 加至位元線14。電壓Vdd係施加至汲極選擇線SGD以連通 電晶體20及40，及將零伏特施加至源極選擇線SGS以使電 曰曰體3 0及5 0未連通。假設陣列4 2至4 8中之所有記憶體單元 在正常開啟狀態（如抹除或負臨界電壓狀態），電晶體4〇及 50間在之反及串中的所有單元之通道電位，係藉由施加至 SGD之Vdd及選擇電晶體40的臨界電壓間之差提供。例 如，若Vdd係3.3伏特且電晶體40之臨界電壓係丨.3伏特，則 所有單元42至48之通道電位係充電至2伏特。可將上述操 作稱為"預充電’’，因為在此情況下通道電位係預充電至一 約2V的預定義電位。因為電晶體5〇不連通，且電晶體⑽在 反及串的通道電位已達到足夠高值（在此情況下2 v)後將自 動地不連通，故記憶體單元42至48的通道電位變得浮動。 因此，當高程式電壓Vpgm(如18伏特）係施加至字元線 WL2，及一中間電壓Vpass(如1〇伏特）係施加至剩餘字元線 120783.doc •13- 200811867 時，由於電容性耦合，記憶體單元42至48之通道電位從2 伏特（初始預充電位準）啟動或增壓至例如8伏特的值，此假 设一約0.6之耦合比。因此，即使將例如18伏特之高電壓 施加至纪憶體單元44的控制閘極，在此高電壓及通道電位 間之電位差不足以造成電子透過氧化物穿隧至記憶體單元 44的浮動閘極，從而防止程式干擾。在自增壓期間可能發 ^ 生之一問題係，，增壓電壓干擾"（或"Vpass干擾”），其中施加 _ 乂肸“至字元線造成在該等字元線下之浮動閘極的一些充 電。雖然Vpass—般係選擇為低（約1〇伏特），但可能發生一 些充電，尤其在在其他字元線程式化期間將Vpass重複施 加至一字元線之後。Vpass的一較高值可提供一較高通道 電壓用於程式化被禁止之串，且從而允許使用Vpgm的較 低值，導致較少Vpgm干擾。然而，較高Vpass導致更多增 壓電壓干擾。因此，在選擇用於Vpass之值時通常會有折 衷。 • 一反及串通常係（但不恆）從源極側至汲極侧程式化，例 如，從圮憶體單元28至記憶體單元22 ^當程式化程序係預 備程式化該反及串之最後（或靠近最後）記憶體單元時，若 該串上之所有或大多數被禁止之先前已程式化單元（如串 13)被程式化’則在先前已程式化單元的浮動閑極中會有 負電荷。因為在浮動閘極上的此負電荷，預充電不能完全 發生，導致反及串下通道區域之低初始電位，且此通道區 域之後續自增壓亦變得較不有效。因此，未選定反及串之 通道中的增壓電位可能無法變得足夠高，且在最後少數字 120783.doc 200811867 元線上仍可能有H干擾。例如’當程式化電壓係施加至 WL3時，若在一被禁止串上的單元48、46及44被程式化 % ’則該等s己憶體單兀44、46、48之各者在其浮動閘極上 具一負電荷’此將限制自增壓程序之增壓位準及可能造成 在單元42上之程式干擾。 鑒於上述問題，丁. S. Jimg等人在，，一種用於大量儲存應 用之3.3伏特128 Mb多位準反及快閃記憶體”，ISSCC96， 會期2，快閃記憶體，Paper Tp 21，mEE，第32頁，中提 出一種局部自增壓（"LSB”）技術作為一改良。 在LSB方案中，當將一高程式化電壓施加至字元線 WL2 ’以減少或防止有關被禁止之一串上的記憶體單元44 之程式干擾時，一絕緣電壓（通常〇伏特）係施加至字元線 WL1及WL3，使得記憶體單元42及46關閉。然後記憶體單 元44中之通道電位則不受記憶體單元42、46及48之通道區 中之自增壓影響，或至少較少受其影響。因此，記憶體單 元44中之通道區的通道電位可藉由高程式化電壓vpgm自 增壓’至一高於當記憶體單元44中之通道區受到剩餘記憶 體單元42、46及48中自增壓影響時達到的電壓位準。此防 止菖A 體早元24正程式化時之程式干擾。至於自增壓及 局部自增壓之更詳細解釋，請參見美國專利第6，1〇7,658 號，尤其第6至10行中的描述。The critical point. 4. The program voltage is applied to the control gate of the programmed unit. The program voltage is applied to the appropriate word line. As described above, the word line is also connected to a unit in each of the other strings of the same word line. For example, when the unit 24 of Figure 3 is programmed, the program will also be applied to the control gate of unit 44 because the two units share the same word line. ^ Need to be stylized on the word line - the unit is not programmed to connect to other units of the same sub 7L line, for example when the stylized unit 24 is needed instead of the single 70 44. Since the program voltage is applied to all cells connected to a word line, one of the unselected cells (a unit that is not to be programmed) on the word line may be inadvertently programmed. For example, unit 44 is = 70 24 early. When the unit 24 is programmed, there may be an undesired stylization of the unit 44. Unexpected stylization of unselected cells on selected character lines is called "program interference". More generally, "program interference" is used to describe any unwanted threshold voltage offset, whether in the positive or negative direction, which may occur during stylized operation and is not limited to the selected word line. Several techniques can be used to prevent program interference. One type of channel is called "" self-boosting. During the stylization of the SB scheme, the channel region of the unselected inverse string is electrically insulated from its corresponding bit line. Thereafter, a middle pass voltage (eg, 1 volt volt) is applied by KD Suh et al., a 3.3 volt 32 Mb anti-flash with a stepping pulse stylization scheme. Memory", Solid State Circuits Journal, Vol. 30, No. U, 1995, called 1149 ii55i, applied to unselected word lines' and a highly stylized voltage (eg, 18 volts) applied to selected characters In this application, the noun "insulation" and "electrical insulation" are used interchangeably, and the noun "write voltage", "program voltage" and "programmed electricity 120783.doc -12· 200811867 Pressure" is interchangeable. The channel region of the unselected inverse string is capacitively coupled to the unselected word line, causing a voltage (eg, six volts, assuming a coupling ratio of 〇.6) to be present. In contrast to the channel region of the string, this so-called "self-boosting" reduces the potential difference between the unselected reverse string channel region and the program voltage applied to the selected word line. As a result, for memory cells in the unselected inverse string, and especially for memory cells in such strings on the selected word line, the voltage across the oxide and thus the program disturb is significantly reduced. Referring to FIG. 3A, when a self-boosting technique is applied to the memory array of FIG. 3A to program one of the cells on the bit line 12, for example, zero volts is applied to the bit line 12 And a voltage Vdd (e.g., 3.3 volts) is applied to the bit line 14. The voltage Vdd is applied to the drain select line SGD to connect the transistors 20 and 40, and zero volts is applied to the source select line SGS so that the electrodes 30 and 50 are not connected. Assuming that all of the memory cells in arrays 4 2 to 48 are in a normally-on state (such as an erase or negative threshold voltage state), the channel potentials of all the cells in the transistor between the transistors 4 and 50 are borrowed. Provided by the difference between the Vdd applied to the SGD and the threshold voltage of the selected transistor 40. For example, if Vdd is 3.3 volts and the threshold voltage of transistor 40 is 33 volts, the channel potential of all cells 42 to 48 is charged to 2 volts. The above operation can be referred to as "precharge'' because the channel potential is precharged to a predefined potential of about 2V in this case. Since the transistor 5 is not connected, and the transistor (10) is automatically disconnected after the channel potential of the reverse string has reached a sufficiently high value (in this case 2 v), the channel potential of the memory cells 42 to 48 is changed. Have to float. Therefore, when the high program voltage Vpgm (such as 18 volts) is applied to the word line WL2, and an intermediate voltage Vpass (such as 1 volt) is applied to the remaining word line 120783.doc • 13-200811867, due to capacitive Coupling, the channel potential of memory cells 42 through 48 is initiated or boosted from 2 volts (initial precharge level) to a value of, for example, 8 volts, assuming a coupling ratio of about 0.6. Therefore, even if a high voltage of, for example, 18 volts is applied to the control gate of the memory cell unit 44, the potential difference between the high voltage and the channel potential is insufficient to cause electrons to pass through the oxide to the floating gate of the memory cell 44. To prevent program interference. One problem that may occur during self-boosting is that boost voltage interference " (or "Vpass interference"), where _ 乂肸 "to the word line causes floating under the word line Some charging of the gate. Although Vpass is generally chosen to be low (about 1 volt volt), some charging may occur, especially after Vpass is repeatedly applied to a word line during other character threading. A higher value of Vpass provides a higher channel voltage for staging the disabled string and thus allows the use of lower values of Vpgm, resulting in less Vpgm interference. However, a higher Vpass causes more boost voltage interference. Therefore, there is usually a tradeoff in choosing the value for Vpass. • A reverse string is usually (but not constant) stylized from the source side to the drain side, for example, from the memory unit 28 to the memory unit 22 ^ when the stylized program is ready to program the back and string In the last (or near the last) memory cell, if all or most of the previously programmed stylized elements (such as string 13) on the string are stylized, then in the floating idle of the previously programmed unit There is a negative charge. Because of this negative charge on the floating gate, pre-charging does not occur completely, resulting in a low initial potential in the reverse channel region, and subsequent self-boosting of this channel region becomes less effective. Therefore, the boost potential in the channel where the inverse and the string are not selected may not become sufficiently high, and there may still be H interference on the last few digits. For example, 'When a stylized voltage is applied to WL3, if the units 48, 46, and 44 on a prohibited string are programmed to %', then each of the suffixes 44, 46, 48 is in it. There is a negative charge on the floating gate 'This will limit the boost level from the boost process and may cause program disturb on unit 42. In view of the above problems, Ding. S. Jimg et al., a 3.3 volt 128 Mb multi-bit quasi-reverse flash memory for mass storage applications, ISSCC96, session 2, flash memory, Paper Tp 21 , mEE, page 32, proposes a partial self-boosting ("LSB") technique as an improvement. In the LSB scheme, an insulating voltage (usually volts) is applied when a high stylized voltage is applied to the word line WL2' to reduce or prevent program disturb with respect to the memory unit 44 on one of the prohibited strings. Up to the word lines WL1 and WL3, the memory cells 42 and 46 are turned off. The channel potential in memory unit 44 is then unaffected by, or at least less affected by, self-boosting in the channel regions of memory cells 42, 46 and 48. Therefore, the channel potential of the channel region in the memory cell 44 can be self-pressurized by the high stylized voltage vpgm to a higher level than when the channel region in the memory cell 44 is subjected to the remaining memory cells 42, 46 and 48. The voltage level reached when the boost is affected. This prevents the program from interfering when the 菖A body is in the early 24th. For a more detailed explanation of self-pressurization and partial self-pressurization, see U.S. Patent No. 6,1,7,658, especially in lines 6-10.
另一提出作為局部自增壓之替代例的技術，係描述於頒 予Tanaka等人之美國專利第6,525,964號中，且係稱為一抹 除區域自增壓（”EASB，，）。EASB與LSB之不同在於，與LSB 120783.doc -15- 200811867 中使未選定單元任一側上之二記憶體單元關閉來防止單元 的程式干擾不同的是，EASB僅使在未選定單元之源極側 上的記憶體單元關閉。例如，當正程式化記憶體單元24 時，僅使記憶體單元46關閉，而不關閉記憶體單元單元 42，以防止在單元44處之程式干擾。因此，將一絕緣電壓 供應給在選定字元線之源極側上的相鄰字元線。 當一低絕緣電壓係大體上施加至二側上之相鄰字元線 (LSB)或一側上之相鄰字元線（EASB)時，LSB及EASB二技 術會發生一問題。此一低電壓（如〇伏特）可能影響欲程式化 之浮動閘極的電壓。圖4A顯示在LSB程式化在字元線WLn 下之一列記憶體單元期間，一反及串的斷面。浮動閘極 FGn及相鄰字元線WLn-Ι及WLn+Ι間之電容性耦合亦顯示 在圖4A中。圖4B顯示在沿字元線WLn(即當WLn係選定字 元線時）程式化單元期間供應給字元線WLn-3至WLn+3之電 壓。如圖4B顯示，緊鄰字元線WLn之字元線（字元線WLn-1及WLn+1)，接收一絕緣電壓（Viso)以造成在WLn-Ι及 WLn+Ι下之記憶體單元關閉，從而絕緣在WLn下之基板的 部分。然而，在字元線WLn-1及WLn+Ι上之電壓係電容性 耦合相鄰字元線下之浮動閘極。尤其係，在字元線WLn-1 及WLn+Ι上的電壓係電容性耦合至浮動閘極FGn，——在選 定字元線WLn下的浮動閘極。在此範例中，浮動閘極FGn 被程式化，所以在浮動閘極FGn下的通道係保持在一低電 壓（典型為0伏特）。為了造成電子透過閘極氧化層穿隧至浮 動閘極FGn内，浮動閘極FGn之電壓係藉由在字元線WLn 120783.doc -16- 200811867 上施加一程式化電壓（約18至20伏特）而提升至一高電壓。 然而’在麵合至浮動閘極FGn之WLn-l及WLn+l上的低絕 緣電壓使此更困難。此等低電壓傾向於抵消來自字元線 WLn之高電壓Vpgm的耦合。結果係用於Vpgm的電壓可能 比需求更高，其增加在其他浮動閘極中之干擾問題。同樣 地，若不藉由字元線WLn-1及WLn+Ι耦合低電壓，程式化 可能I費更久。儘管圖4A及4B顯示針對LSB情況之問題， 該問題亦發生在EASB方案中，雖然僅在選定字元線之一 侧上。 儘管LSB及EA SB用於許多應用可能較有利，當此等方案 係依其目前形式使用時仍會遭遇到某些問題，尤其當未來 世代之裝置的兄憶體單元尺寸係持續減少或比例縮小時。 尤其係’當兄憶體陣列在尺寸中減少時，並非所有尺寸皆 成比例減少。通常在例如圖4A顯示的一反及快閃記情體 中，從位於下方浮動閘極分離字元線的多晶矽間介電 (IPD)層’係未與相鄰字元線或浮動閘極間之間距減少成 比例的減少。因此，當一陣列縮小時，WLn_1&FGn間之 耦合相對於WLn及FGn間的耦合係增加。因此，來自鄰近 選定字元線之字元線的絕緣電壓之耦合（以上已關於圖4a 及4B描述），當記憶體陣列尺寸縮小時，一般而言會變得 更明顯。 【發明内容】 一增壓電壓方案施加至與選定字元線相鄰之一未選定字 元線的增壓電壓，係比施加至係遠離選定字元線之未選定 120783.doc -17- 200811867 字70線的電壓更高。施加至選定字元線及相鄰未選定字元 線之增壓電壓顯示一階梯狀模式，其中電壓自一選定字元 線上之程式電壓，下降至與選定字元線相鄰之一字元線上 的較高增壓電壓，及至一在遠離該選定字元線之一字元線 上的較低增壓電壓。一區塊之未選定字元線中所有或僅一 些可依據一階梯狀增壓電壓方案來接收增壓電壓0在某此 情況下，僅靠近選定字元線之未選定字元線依據一階梯狀 增壓電壓方案接收電壓。其他未選定字元線接收一預設增 壓電壓。 一施加至與該選定字元線相鄰之字元線的較高增壓電 壓，傾向於麵合至一選定浮動閘極（選定字元線下之一浮 動閘極）。因此，該較高增壓電壓與程式化電壓一起運作 以造成浮動閘極之充電。然而，藉由僅將較高增壓電壓施 加至有限數目之字元線，由此較高增壓電壓（增壓電壓干 擾）產生的問題係維持在一低位準。藉由施加一系列下降 電壓至靠近一選定字元線之字元線，一適當平衡係維持在 較高增壓電壓之優點（耦合較高電壓至選定浮動閘極及至 通道，該優點促進更接近選定字元線），及較高增壓電壓 的缺點（增壓電壓干擾，該缺點一般不取決於與選定字元 線之距離）間。將一南增壓電壓用於與選定字元線相鄰之 字元線，有助於造成電荷流至浮動閘極及可允許使用一減 少的程式化電壓，因而減少Vpgm干擾。 一階梯狀增壓電壓方案可與將一絕緣電壓施加至一或多 個字元線結合，以提供一修改之LSB或EASB方案。在一範 120783.doc • 18 - 200811867 例中，將-絕緣電Μ施加至該選定字元線__侧上之相鄰未 選定字元線，且隨著離敎字元線之距離下降的二或多個 增麼電Μ，係施加至敎字元線另—側上之未選定字元 線。在另-範财，-階梯狀模式之電壓係施加至該選定 字元線任-侧上的三或多財元線，且絕緣電㈣施加至 此二或多個字元線任—侧上之字元線。依此方法，增壓係 限制在靠近選定字元線之一區。Another technique proposed as an alternative to the local self-pressurization is described in U.S. Patent No. 6,525,964 issued to Tanaka et al. The difference is that, unlike LSB 120783.doc -15- 200811867, the two memory cells on either side of the unselected cell are turned off to prevent program disturb of the cell, the EASB is only on the source side of the unselected cell. The memory unit is turned off. For example, when the memory unit 24 is being programmed, only the memory unit 46 is turned off without turning off the memory unit unit 42 to prevent program disturb at the unit 44. Therefore, an insulation is provided. The voltage is supplied to adjacent word lines on the source side of the selected word line. When a low isolation voltage is applied substantially to adjacent word lines (LSBs) on one side or adjacent words on one side In the case of the EASB, a problem occurs in the LSB and EASB technologies. This low voltage (such as volts) may affect the voltage of the floating gate to be programmed. Figure 4A shows the LSB stylized at the word line WLn. During the next column of memory cells, one And the cross section of the string. The capacitive coupling between the floating gate FGn and the adjacent word lines WLn-Ι and WLn+Ι is also shown in Figure 4A. Figure 4B shows the along the word line WLn (ie when the WLn system is selected) The word line is supplied to the voltages of the word lines WLn-3 to WLn+3 during the stylizing unit period. As shown in FIG. 4B, the word lines (word lines WLn-1 and WLn+1) adjacent to the word line WLn are displayed. Receiving an insulation voltage (Viso) to cause the memory cells under WLn-Ι and WLn+Ι to be turned off, thereby insulating the portion of the substrate under WLn. However, on the word lines WLn-1 and WLn+Ι The voltage is capacitively coupled to the floating gates under adjacent word lines. In particular, the voltages on word lines WLn-1 and WLn+Ι are capacitively coupled to floating gate FGn, at selected word lines. The floating gate under WLn. In this example, the floating gate FGn is programmed, so the channel under the floating gate FGn is kept at a low voltage (typically 0 volts). To cause electrons to pass through the gate oxide layer. Tunneling into the floating gate FGn, the voltage of the floating gate FGn is applied by applying a stylized voltage on the word line WLn 120783.doc -16- 200811867 ( It is raised to a high voltage by about 18 to 20 volts. However, the low insulation voltage on WLn-1 and WLn+1 that is brought into the floating gate FGn makes this more difficult. These low voltages tend to offset from words. The coupling of the high voltage Vpgm of the line WLn. The result is that the voltage for Vpgm may be higher than the demand, which increases the interference problem in other floating gates. Similarly, without the word lines WLn-1 and WLn +Ι coupled with low voltage, stylized may take longer. Although Figures 4A and 4B show problems for the LSB case, this problem also occurs in the EASB scheme, albeit only on one side of the selected word line. Although LSB and EA SB may be advantageous for many applications, some problems will still be encountered when these programs are used in their current form, especially when the size of the brothers' cell unit in future generations continues to decrease or scale down. Time. In particular, when the size of the brother's memory array is reduced in size, not all sizes are proportionally reduced. Typically, in a reverse flash memory such as that shown in Figure 4A, the polysilicon dielectric (IPD) layer from the lower floating gate separation word line is not between adjacent word lines or floating gates. The pitch is reduced proportionally. Therefore, when an array is scaled down, the coupling between WLn_1 & FGn increases with respect to the coupling between WLn and FGn. Thus, the coupling of the insulation voltage from the word lines adjacent to the selected word line (described above with respect to Figures 4a and 4B) generally becomes more apparent as the memory array size shrinks. SUMMARY OF THE INVENTION A boost voltage scheme is applied to a boost voltage of an unselected word line adjacent to a selected word line, which is applied to an unselected 120783.doc -17- 200811867 The word line 70 has a higher voltage. The boost voltage applied to the selected word line and the adjacent unselected word line displays a staircase pattern in which the voltage drops from a programmed voltage on a selected word line to a word line adjacent to the selected word line The higher boost voltage, and a lower boost voltage on a word line away from the selected word line. All or only some of the unselected word lines of a block may receive boost voltage 0 according to a stepped boost voltage scheme. In some cases, only unselected word lines near the selected word line are based on a ladder The boost voltage scheme receives the voltage. Other unselected word lines receive a predetermined boost voltage. A higher boost voltage applied to the word line adjacent the selected word line tends to face to a selected floating gate (one of the floating gates below the selected word line). Therefore, the higher boost voltage operates in conjunction with the programmed voltage to cause charging of the floating gate. However, by applying only a higher boost voltage to a limited number of word lines, the problem caused by the higher boost voltage (boost voltage interference) is maintained at a low level. By applying a series of falling voltages to the word line near a selected word line, an appropriate balance maintains the advantage of a higher boost voltage (coupling a higher voltage to the selected floating gate and to the channel, which advantage facilitates closer The selected character line), and the disadvantage of a higher boost voltage (boost voltage interference, which generally does not depend on the distance from the selected word line). Using a south boost voltage for the word line adjacent to the selected word line helps to cause charge flow to the floating gate and allows a reduced stylized voltage to be used, thereby reducing Vpgm interference. A stepped boost voltage scheme can be combined with applying an isolation voltage to one or more word lines to provide a modified LSB or EASB scheme. In a case of 120783.doc • 18 - 200811867, an insulated power is applied to adjacent unselected word lines on the selected word line __ side, and decreases with distance from the 敎 character line Two or more additional powers are applied to the unselected word lines on the other side of the character line. In another example, the voltage of the stepped mode is applied to the three or more financial lines on either side of the selected word line, and the insulating power (four) is applied to any one or more of the two or more word lines. Word line. In this way, the boost is limited to a region near the selected word line.
施加至選定及未選定字元線二者之電壓可步進地增加， 以減少由電職變造成的干擾。在—範例中，選定字元線 及一相鄰未選定字元線被提升至一第一增壓電壓。接著， ^較近之未選定字元線與該選定字元線被提升至一較高之 第一增壓電壓，同時維持較遠之未選定字元線在該第一增 壓電壓。而後，該選定字元線係提升至一程式化電壓，而 忒第一及第二增壓電壓係分別維持至較遠及較近字元線。 依此方法，一系列電壓係隨著時間依階梯狀模式施加至一 個別字元線直至達到一最後電壓。用於相鄰字元線之最後 電壓形成一階梯狀模式，其具有被施加至一選定字元線之 程式化電壓，及一系列被施加之增壓電壓（少於該程式化 電壓），使得增壓電壓隨著離該選定字元線之距離下降。 在曰代方案中’未選定字元線在一第一時間直接傾斜至 其所需增壓電壓。該選定字元線在此時係傾斜至一等於最 高增壓電壓的電壓（與選定字元線相鄰之字元線的增壓電 疋）其後’選定字元線係傾斜至一程式化電壓，且未選 定字70線仍維持在其所需增壓電壓處。 120783.doc -19- 200811867 【實施方式】 圖5顯示在一依據本發明之具體實施例經歷程式化的快 閃記憶體陣列中之反及串的一部分的斷面。圖5顯示表示 在反及串之一些元件間的電容性耦合的電容器。未顯示在 兀件間之所有耦合。例如，字元線係堅固地耦合至浮動閘 極的正下方，允許浮動閘極被程式化。同樣地，浮動閘極 及字元線二者係耦合至下方基板之一部分。所顯示之特定 麵5係被選來顯示此具體實施例優於先前技術程式化方案 的一些優點。同樣地，當反及陣列之橫向尺寸在大小方面 係比例縮小地比垂直尺寸比例縮小更快時，所顯示的耦合 變得更明顯。 圖6顯不依據本發明之一具體實施例施加至圖$的字元線 WLn-3至WLn+3之電壓。WLn係選定字元線且一程式化電 壓Vpgm係施加至WLn。與WLn之任一侧上的字元線WLn相 鄰之子元線WLn_l及WLn+Ι接收一第一增壓電壓Vpassl。 與子元線WLn-Ι及WLn+1相鄰之字元線WLn-2及WLn+2接 收一第二增壓電壓Vpass2，其係小於第一增壓電壓 Vpassl。與字元線WLn_2&WLn+2相鄰之字元線WLn_3及 WLn+3接收一第三增壓電壓Vpass3，其係小於Vpass2。因 此，在字元線WLn-3至WLn+3上之電壓形成一階梯狀電壓 方案’其中增壓電壓隨著離選定字元線之距離增加而下 降。額外之字元線可跟隨此模式。在一些情況下，一串之 所有未選定字元線可依據一階梯型電壓方案接收增壓電 壓。在其他情況下，僅靠近選定字元線之未選定字元線具 120783.doc •20· 200811867 有階梯型電壓，且其他未選定字元線接收一預設增壓電 壓。因此，在圖6的具體實施例中，額外字元線（未顯示）可 接收額外之增壓電壓，諸如Vpass4、Vpass5、…等等，或 額外字元線可皆接收Vpass3，或一些其他預設增壓電壓。 不同於上述LSB及EASB方案，在圖6之方案中不提供絕緣 電壓，因此在字元線WLn-3至WLn+3下方之記憶體單元被 開啟。在從一位元線接收一程式化電壓的複數串，及從一 位元線接收一程式禁止電壓的該等串中之記憶體單元係皆 開啟。因此，一串之源極/没極及通道區形成一電連續 條。依此方法，圖6之程式化方案類似SB方案。然而，在 階梯型方案中使用一不同增壓電壓之範圍，具有優於使用 一單一增壓電壓用於所有未選定字元線的習知SB方案之優 點。 增壓電壓Vpass 1係所使用的最高增壓電壓且係僅施加至 字元線WLn-Ι及WLn+1，其係與選定字元線相鄰。字元線 WLn-Ι及WLn+Ι係耦合至浮動閘極FGn，且因此傾向於增 加浮動閘極FGn上之電壓。此有助於程式化浮動閘極 FGn。與圖4A及4B之LSB範例相反，高增壓電壓Vpassl與 Vpgm—起動作以提升浮動閘極FGn的電壓，使得可將他者 外之一較低電壓用作Vpgm。將一較低電壓用作Vpgm可減 少Vpgm干擾。 字元線 WLn-3、WLn-2、WLn+2 及 WLn+3 係比 WLn-Ι 及 WLn+1更遠離WLn，且係因此比WLn_l及WLn+1較少耦合 至WLn。字元線WLn-2及WLn+2係透過浮動閘極FGn-Ι及 120783.doc -21- 200811867 FGn+1主要耦合至浮動閘極FGn。字元線WLn_3及WLn+3 亦係透過相鄰浮動閘極主要耦合至浮動閘極FGn。字元線 WLn-Ι 及 WLn+1接收比 Vpassl 低的電壓 vpass2及 Vpass3。 因為此等字元線係較少耦合至WLn，故有較少原因須施加 咼電壓，且藉由使Vpass2及Vpass3保持相對較低，增壓電 壓干擾的危險會減少。尤其係，相對較高電壓Vpassi係僅 在一特定字元線之單元的程式化期間施加至二字元線。因 此’當選定任一側上的相鄰字元線時，在一串之程式化期 間’一字元線一般經歷Vpassl二次。因此，不同於先前SB 方案’可使用Vpassl之相對較高值，而不使單元曝露於增 壓電壓干擾之危險，若此一電壓係要施加至所有未選定字 元線時其將會發生。其他增壓電壓（如Vpass3)可能較低， 使得增壓電壓干擾的危險係據以較低。 誠然，其他階梯狀電壓方案亦可行且本具體實施例不受 限於任何特定電壓值。例如，二或多個字元線能施加 Vpassl。同樣地，二或多個字元線能施加vpass2，二或多 個字元線能施加Vpass3，且依此類推。此一方案係藉由靠 近選定字元線時使用一較高Vpass值，且更遠離選定字元 線時使用一較低Vpass值，而仍能達到施加不同Vpass電壓 的益處。 在另一具體實施例（在圖7中顯示）中，係應用一修改的 EASB方案。與圖6之具體實施例相反，在此一階梯型電壓 方案係僅施加至選定字元線一側上的字元線。階梯型電壓 方案一般係應用在抹除侧（汲極或位元線側）。在程式化侧 120783.doc -22- 200811867 (源極側）上係提供一絕緣電壓（Vis〇)，因此一串之通道區 係非電連，_且在字元線WLn至WLn+3ir之通道係與字元線 WLn-3下的通道絕緣。絕緣電avis〇可為〇伏特，或使一浮 動閘極電晶體不連通之一些其他電壓(在圖7或其他圖式 中’ X軸無須在零伏特處與γ軸相交）。在此情況下，一絕 緣電壓係施加至二字元線’以減少閉極引發波極茂漏 (GIDL)的危險。此係—可造成透過未連通之電晶體使 茂漏的現象，|中該電晶體的閘極長度較小且源極及汲極 間的電壓差大。藉由在-串中將二電晶體用於絕緣，各電 晶體之源極及汲極間的電壓減少且GIDL的危險減少。因 為提供絕緣，使得增壓僅發生在抹除區域中，此可視為 EASB的-範例。然'而’如圖6之範例中，—階梯型電壓方 案係用於供應至抹除區域之增壓電壓。如前文，最靠近選 定字元線WLn的字元線WLn+1接收最高增壓電壓vpassi^ 以致此較高增壓電壓傾向於耦合至FGn，且有助於提升 FGn的電壓，而因此造成電荷流入FGn。後續之較低增壓 電壓Vpass2及Vpass3係分別施加至字元線WLn+2及 WLn+3。因此，增壓電壓干擾的危險減少，目為在此情況 下’當ϋ定該源極側上之相鄰字元線時，—字元線僅經歷 V—-次。當選定其他字元線時，一字元線經歷較低 Vpass電壓。因為增壓區域係與源極側上之程式化單元絕 緣，程式化係較少受已程式化單元之浮動閘極上的電荷影 響，因此可使用較低Vpgm。 在另一具體實施例（顯示在圖8中）中，係應用一修改之 120783.doc •23- 200811867 LSB方案。如圖6中，一階梯型增壓電壓方案係應用至一 選定字元線任一侧上之字元線。然而，不同於圖6之範 例’一絕緣電壓（Viso)係提供給增壓字元線任一侧上之字 元線’從而絕緣增壓區域與該串之其餘者。此提供與_些 已程式化記憶體單元的絕緣，且所以減少電荷在此等單元 之浮動閘極中的影響。增壓電壓係僅施加至少數字元線 (在此範例中為四），因此減少增壓電壓干擾的危險。絕緣 電壓（Viso)係顯示施加至選定字元線wLn任一侧上之一字 元線’雖然在某些情況下可將二或多個字元線用於絕緣。 圖9A將一反及串之末端部分顯不於斷面中。包括於圖 9A中係一源極侧選擇閘極（SGs)及字元線WL1至WL6，連 同下方之浮動閘極FG1至FG6。在FG1程式化期間，Vpgm 係施加至WL1且一階梯型增壓電壓方案係應用至圖9B中顯 示的字元線WL2至WL6。選擇閘極SGS經歷一絕緣電壓 Viso ’其將反及串與一共用源極線絕緣。然而，viso傾向 於耦合至浮動閘極FG1，使浮動閘極FG1之程式化更形困 難。為了抵消此效應，可將一電壓Vpassl，施加至WL2，其 中Vpassr係高於Vpassl，較後施加至與一選定字元線相鄰 之未選定字元線的電壓，如圖6至8之範例中所示。因此， Vpassl1係一用來補償Viso施加至SGS之效應的增壓電壓。 在此情況下亦可修改其他Vpass電壓。在各字元線之程式 化期間’增壓電壓之值無須相同。因此，Vpassl、 Vpass2、VpaSS3、…等等可具有用於程式化一特定字元線 WLn之特定值’但在另一字元線WLn+x之程式化期間的不 120783.doc -24- 200811867 同值。儘管在各情況下可使用一階梯型電壓方案，但在不 同字元線之程式化期間可使用不同電壓值。 圖9C顯示WL2之程式化，其係在圖9B中所示WL1之程式 化後。一階梯狀電壓方案係如先前圖6及7顯示施加至字元 線WL3至WL6。字元線WL3(其係緊鄰汲極側上之選定字元 線WL2)接收電壓Vpassl。然而，緊鄰源極侧上選定字元 線WL2之字元線WL1在此情況下不接收Vpassl。而係WL1 接收Vpassx。在此範例中，Vpassx係一少於Vpassl的 Vpass電壓。因為施加至WL1的一高Vpass電壓（例如 Vpassl)可造成熱電子在選擇閘極SGS下產生及注入FG1或 FG2，故使用一較低Vpass電壓（Vpassx)。由SGS處之熱電 子注入造成的干擾之現象及將減少Vpass電壓使用於WL1 來壓制此問題，係在美國專利公開案第2005/0174852號中 更詳細討論。該申請案中描述之技術可結合本發明的具體 實施例以達到二方法的益處。儘管Vpassx係顯示在Vpassl 及Vpass2間，在其他範例中，Vpassx可等於或小於 Vpass2。圖9C顯示依據本發明之一具體實施例的非對稱階 梯狀電壓方案的範例。各種其他階梯狀電壓方案，如對稱 及不對稱二者皆在本發明的範圍内。 圖10A顯示一在WLn程式化期間應用至未選定字元線 WLn+1至WLn+4之階梯狀電壓方案。在此情況下，四增壓 電壓（Vpassl至Vpass4)係施加至字元線WLn+l至WLn+4。 電壓Vpassl至Vpass4具有一階梯狀曲線，其中電壓依據離 選定字元線WLn之距離縮減。在選定字元線WLn (WLn-1 120783.doc -25- 200811867 等等，未顯示在圖10A中）另一側上，Vpass電壓係鏡射該 等字元線WLn+Ι至WLn+4來施加。在一替代具體實施例 中，可將一絕緣電壓施加至選定字元線WLn其他侧上之一 或多個字元線。在其他替代例中，可將Vpass電壓及絕緣 電壓的一些其他結合可施加至WLn另一侧上之字元線。此 具體實施例不要求電壓相對於選定字元線對稱地施加，以 獲得該電壓方案的益處。即使當階梯狀電壓方案僅應用至 選定字元線之一側上時，亦可導致一些益處。圖10A顯示 於沿字元線WLn程式化單元期間在一特定時間處施加之電 壓的靜態圖。在此範例中，增壓電壓未在其最後位準處立 即施加，而是漸增地增加至一最後位準。 圖10B顯示經過一時間施加至圖10A之字元線WLn-4至 WLn+4的電壓之時序圖，其包括由圖10A表示之時間（圖 10B中之時間週期丨9至t1(>)。在t9之前，電壓係步進地增加 直至其達到其最後值。圖10B之範例顯示選定字元線WLn 具有依階梯狀方式增加至Vpgm的電壓。同樣地，字元線 WLn+Ι至WLn+4及字元線WLn-Ι至WLn-4經歷階梯狀電壓 增加。在此範例中，施加至字元線的電壓係關於選定字元 線WLn對稱，其中字元線WLn+Ι及WLn-Ι接收相同電壓， 字元線WLn+2及WLn-2接收相同電壓，且依此類推。在其 他情況中，電壓可能不對稱地施加。在時間t〇之前，字元 線WLn-4至WLn+4可在一例如零伏特之基極電壓處。在時 間tG處，施加至字元線WLn-4至WLn+4之電壓係傾斜向 上，且在時間心處，傾斜停止，且至字元線WLn-4至 •26- 120783.doc 200811867 WLn+4之電壓係保持在Vpass4的電壓處。其後，在時間t2 處，施加至字元線WLn-3至WLn+3之電壓傾斜直至時間 t3，當傾斜停止且施加至字元線WLn-3至WLn+3之電壓係 保持在Vpass3。當施加至字元線WLn-3至WLn+3之電壓傾 斜及保持在Vpass3時，施加至字元線WLn-4及WLn+4之電 壓係維持在電壓Vpass4且不使其電壓傾斜。其後，在時間 t4處，施加至字元線WLn-2至WLn+2的電壓傾斜直至時間 t5，當傾斜停止且施加至字元線WLn-2至WLn+2的電壓保 持在Vpass2。當施加至字元線WLn-2至WLn+2之電壓傾斜 及保持在Vpass2時，至字元線WLn-4及WLn+4之電壓係維 持在Vpass4，且至字元線WLn-3及WLn+3之電壓係如前維 持在Vpass3。其後，在時間t6處，施加至字元線WLn-1至 WLn+Ι的電壓係傾斜直至B夺間t7，當傾斜停止且施加至字 元線WLn-Ι至WLn+Ι的電壓係維持在Vpassl。當施加至字 元線WLn-Ι至WLn+Ι之電壓傾斜及維持在Vpassl時，至字 元線WLn-4至WLn-2及WLn+2至WLn+4之電壓係維持在其 先前值。其後，在時間18處，施加至選定字元線WLn之電 壓傾斜直至時間t9，當傾斜停止且施加至字元線WLn的電 壓係維持在一程式電壓Vpgm。當施加至選定字元線WLn 之電壓傾斜及在Vpgm維持時，字元線WLn_4至WLn-Ι及 WLn+Ι至WLn+4係維持在其先前值。此時（在時間19後）施 加至字元線WLn-4至WLn+4的電壓可在圖10A中見到。其 後，在時間11()處，施加至字元線WLn-4至WLn+4的電壓傾 斜向下且在時間tn達到一基極電壓。 120783.doc •27- 200811867 與若電壓直接自一基極電壓直接傾斜至其最後電壓相 比，圖10B之時序圖中顯示之電壓方案對記憶體單元造成 車乂 J干擾。電壓中的漸增改變一般比大改變造成較少干 擾。由圖10B之具體實施例中的電壓改變造成之任何雜 訊，傾向於比例如使字元線WLn上之電壓從一基極電壓傾 斜至Vpgm所造成的雜訊較少。在一些具體實施例中，程 式化係藉由將程式化電壓之脈衝重覆施加至一選定字元線 及驗證脈衝間下方浮動閘極電晶體之臨界電壓而達到。因 此，在tn之後，可讀取WLn下之單元的臨界電壓且其後可 將程式電壓的另一脈衝以相同方式施加，其係藉由依階梯 狀電壓傾斜序列施加增壓電壓。脈衝及讀取可依次重複直 至字元線WLn之所有單元的臨界電壓係在其所需狀態中。 圖10C顯示一依據一替代具體實施例之電壓方案的時序 圖。圖10C之電壓方案提供一在從“至u之時間週期中與圖 10A所示相同的電壓曲線。因此，在此時間期間，相同階 梯狀模式之電壓係施加至字元線WLn-4至WLn+4。然而， 在前的週期期間，電壓係以與圖loc所示不同之方式傾 斜。於時間tG之前，字元線WLn-4至WLn+4係維持在一基 極電壓，例如零伏特。在時間tG處，施加至字元線WLn_4 至WLn+4的電壓係傾斜向上，且在時間^處，傾斜停止且 至字元線WLn-4至WLn+4之電壓係維持在Vpass4之電壓（對 於 WLn-4 及 WLn+4)、Vpass3(對於 WLn-3 及 WLn+3)、 Vpass2(對於 WLn-2及 WLn+2)及 Vpassl(對於 WLn-1、WLn 及WLn+1)。因此，在此範例中，供應至未選定字元線之 120783.doc -28- 200811867 電壓係從一基極電壓直接傾斜至其所需增壓電壓。儘管該 傾斜係顯不為針對所有字元線採取相同量之時間，但在某 些情況下’其對於提升至較高電壓之字元線可花更久時 間。其後’在時間h處，在選定字元線WLn上之電壓係傾 斜及在時間t3處，傾斜停止且WLn上之電壓維持在Vpgm直 至時間“。當供應至選定字元線之電壓傾斜及維持在 Vpgm(從時間h至，所有未選定字元線仍保留在其所需 增壓電壓（Vpassl至Vpass4)。其後，在時間％，供應至字 元線WLn-4至WLn+4之電壓係向下傾斜至基極電壓。此方 案可在時間至u達到一階梯狀電壓模式的許多優點，但 因為其無須多次增加電壓至未選定字元線，程式化可能更 快速。 上述增壓電壓方案可使用適當電路達到，其係位於與記 憶體陣列相同之晶片上作為周邊電路，或在另一晶片上。 例如，列控制電路可調適以依上述方式將一階梯狀電壓方 案提供給未選定字元線，或傾斜至未選定字元線之電壓。 在某些情況下，使用替代增壓電壓方案亦可符合需求，所 以可選擇一階梯狀增壓電壓方案作為一模式，其中亦可用 一或多個其他模式。另一增壓電壓方案可為一預設方案， 使得一階梯狀增壓電壓方案僅在其致能時才被選擇。在一 範例中，在相同記憶體陣列中，記憶體陣列之不同部分可 使用不同增壓電壓方案。例如，該記憶體陣列之不同2塊 可使用不同增壓電壓方案。同樣地，可在一時間處選二」 增壓電壓方案，且可在-較晚時間處選擇—不同增壓電壓 120783.doc -29- 200811867 方案用於一記憶體陣列之一部分（咬 (次針對整個記憶體陣 -或多個干擾的頻率，欲儲存資料之本質(資料之重要性 及使用ECC或其他方法修復該資料之可能性），程式化該資 列）。在由末知使用者接收該記憶體前，可在_記憶體系 統之初始測試及組態期間選擇一增壓電壓方案。或者日 當使用記憶體時’可基於某些標準選擇一適合增：電：方 案。此等標準可包括磨損(由所有或部分記憶二車列經歷 之使用量），發生在記憶體陣列（或_部分記憶體陣列）中之The voltage applied to both the selected and unselected word lines can be stepped up to reduce the interference caused by the electrical job. In the example, the selected word line and an adjacent unselected word line are boosted to a first boost voltage. Next, the closer unselected word line and the selected word line are boosted to a higher first boost voltage while maintaining the farther unselected word line at the first boost voltage. The selected character line is then boosted to a stylized voltage, and the first and second boost voltages are maintained to a farther and closer word line, respectively. In this way, a series of voltages are applied to an individual word line in a stepped pattern over time until a final voltage is reached. The final voltage for adjacent word lines forms a stepped pattern having a programmed voltage applied to a selected word line and a series of applied boost voltages (less than the programmed voltage) such that The boost voltage decreases with distance from the selected word line. In the deuterated scheme, the unselected word line is directly tilted to its desired boost voltage at a first time. The selected word line is then tilted to a voltage equal to the highest boost voltage (the boost voltage of the word line adjacent to the selected word line) and then the selected character line is tilted to a stylized The voltage, and the unselected word 70 line, remains at its desired boost voltage. 120783.doc -19- 200811867 [Embodiment] FIG. 5 shows a cross section of a portion of a reverse flash string in a flash memory array that has been programmed in accordance with an embodiment of the present invention. Figure 5 shows a capacitor showing capacitive coupling between some of the elements of the string. All couplings between the components are not shown. For example, the word line is firmly coupled directly below the floating gate, allowing the floating gate to be programmed. Similarly, both the floating gate and the word line are coupled to a portion of the underlying substrate. The particular face 5 shown is selected to show some of the advantages of this embodiment over prior art stylized solutions. Similarly, the displayed coupling becomes more pronounced when the lateral dimension of the array is scaled down more rapidly than the vertical dimension. Figure 6 shows the voltage applied to word lines WLn-3 through WLn+3 of Figure $ in accordance with an embodiment of the present invention. WLn is the selected word line and a stylized voltage Vpgm is applied to WLn. The sub-element lines WLn_1 and WLn+1 adjacent to the word line WLn on either side of the WLn receive a first boost voltage Vpass1. The word lines WLn-2 and WLn+2 adjacent to the sub-element lines WLn-Ι and WLn+1 receive a second boost voltage Vpass2 which is smaller than the first boost voltage Vpass1. The word lines WLn_3 and WLn+3 adjacent to the word line WLn_2 & WLn+2 receive a third boost voltage Vpass3 which is smaller than Vpass2. Therefore, the voltages on word lines WLn-3 to WLn+3 form a stepped voltage scheme 'where the boost voltage drops as the distance from the selected word line increases. Additional word lines can follow this pattern. In some cases, all of the unselected word lines of a string can receive boost voltage in accordance with a stepped voltage scheme. In other cases, only unselected word lines near the selected word line have a stepped voltage and other unselected word lines receive a preset boost voltage. Thus, in the particular embodiment of FIG. 6, additional word lines (not shown) may receive additional boost voltages, such as Vpass4, Vpass5, ..., etc., or additional word lines may all receive Vpass3, or some other pre- Set the boost voltage. Unlike the LSB and EASB schemes described above, the isolation voltage is not provided in the scheme of Fig. 6, so that the memory cells below the word lines WLn-3 to WLn+3 are turned on. A plurality of memory cells in a string that receives a stylized voltage from a bit line and a program inhibit voltage from a bit line are turned on. Therefore, a series of source/defective and channel regions form an electrical continuous strip. In this way, the stylized scheme of Figure 6 is similar to the SB scheme. However, the use of a range of different boost voltages in a stepped scheme has advantages over conventional SB schemes that use a single boost voltage for all unselected word lines. The boost voltage Vpass 1 is the highest boost voltage used and is applied only to the word lines WLn-Ι and WLn+1, which are adjacent to the selected word line. The word lines WLn-Ι and WLn+ are coupled to the floating gate FGn and thus tend to increase the voltage on the floating gate FGn. This helps to program the floating gate FGn. In contrast to the LSB example of Figures 4A and 4B, the high boost voltages Vpassl and Vpgm act in concert to boost the voltage of the floating gate FGn such that one of the other lower voltages can be used as Vpgm. Using a lower voltage as Vpgm reduces Vpgm interference. The word lines WLn-3, WLn-2, WLn+2, and WLn+3 are further away from WLn than WLn-Ι and WLn+1, and thus are less coupled to WLn than WLn_1 and WLn+1. The word lines WLn-2 and WLn+2 are mainly coupled to the floating gate FGn through the floating gates FGn-Ι and 120783.doc -21- 200811867 FGn+1. The word lines WLn_3 and WLn+3 are also primarily coupled to the floating gate FGn through adjacent floating gates. The word lines WLn-Ι and WLn+1 receive voltages lower than Vpass1, vpass2 and Vpass3. Since these word lines are less coupled to WLn, there are fewer reasons to apply the 咼 voltage, and by keeping Vpass2 and Vpass3 relatively low, the risk of boosted voltage interference is reduced. In particular, the relatively high voltage Vpassi is applied to the two-character line only during the stylization of the cells of a particular word line. Therefore, when a neighboring word line on either side is selected, a word line in a stylized period of a string generally experiences Vpassl twice. Therefore, unlike the previous SB scheme, a relatively high value of Vpassl can be used without exposing the unit to the risk of surge voltage interference, which would occur if this voltage is to be applied to all unselected word lines. Other boost voltages (such as Vpass3) may be lower, so that the risk of boost voltage interference is lower. It is true that other stepped voltage schemes are possible and the specific embodiment is not limited to any particular voltage value. For example, two or more word lines can apply Vpassl. Similarly, two or more word lines can apply vpass2, two or more word lines can apply Vpass3, and so on. This approach uses a higher Vpass value when the word line is selected closer, and a lower Vpass value when it is further away from the selected word line, while still achieving the benefit of applying different Vpass voltages. In another embodiment (shown in Figure 7), a modified EASB scheme is applied. In contrast to the embodiment of Figure 6, a stepped voltage scheme is applied to only the word lines on one side of the selected word line. The stepped voltage scheme is generally applied to the erase side (drain or bit line side). An insulating voltage (Vis〇) is provided on the stylized side 120783.doc -22- 200811867 (source side), so that a series of channel regions are non-electrically connected, _ and in word lines WLn to WLn+3ir The channel is insulated from the channel under word line WLn-3. The insulated electrical avis 〇 can be 〇 volts, or some other voltage that prevents a floating gate transistor from being connected (in Figure 7 or other figures, the 'X-axis does not have to intersect the γ-axis at zero volts). In this case, an insulative voltage is applied to the two-character line ' to reduce the risk of the gate-induced wave leakage (GIDL). This system can cause leakage through an unconnected transistor, where the gate length of the transistor is small and the voltage difference between the source and the drain is large. By using the two transistors for insulation in the -string, the voltage between the source and the drain of each transistor is reduced and the risk of GIDL is reduced. Because of the insulation provided, pressurization only occurs in the erased area, which can be considered as an example of EASB. However, as in the example of Fig. 6, the stepped voltage scheme is used for the boost voltage supplied to the erase region. As before, the word line WLn+1 closest to the selected word line WLn receives the highest boost voltage vpassi^ such that this higher boost voltage tends to couple to FGn and helps boost the voltage of FGn, thus causing charge Flow into FGn. Subsequent lower boost voltages Vpass2 and Vpass3 are applied to word lines WLn+2 and WLn+3, respectively. Therefore, the risk of boosted voltage interference is reduced, and in this case, when the adjacent word line on the source side is determined, the word line only experiences V--times. When other word lines are selected, one word line experiences a lower Vpass voltage. Because the boost region is inseparable from the stylized cells on the source side, the stylization is less affected by the charge on the floating gate of the programmed cell, so a lower Vpgm can be used. In another embodiment (shown in Figure 8), a modified 120783.doc • 23-200811867 LSB scheme is applied. As shown in Figure 6, a stepped boost voltage scheme is applied to the word lines on either side of a selected word line. However, unlike the example of Figure 6, an insulation voltage (Viso) is provided to the word line ' on either side of the boost word line to insulate the boost region from the remainder of the string. This provides isolation from some of the programmed memory cells and therefore reduces the effects of charge in the floating gates of such cells. The boosted voltage is applied with at least a digital line (four in this example), thus reducing the risk of boost voltage interference. The insulation voltage (Viso) is shown to be applied to one of the word lines on either side of the selected word line wLn, although in some cases two or more word lines may be used for insulation. Fig. 9A shows that the end portion of the inverted string is not in the cross section. Included in Fig. 9A is a source side select gate (SGs) and word lines WL1 through WL6, which are connected to the lower floating gates FG1 to FG6. During FG1 stylization, Vpgm is applied to WL1 and a stepped boost voltage scheme is applied to word lines WL2 through WL6 shown in Figure 9B. The gate SGS is selected to experience an insulation voltage Viso' which insulates the string from a common source line. However, the vos tends to be coupled to the floating gate FG1, making the stylization of the floating gate FG1 more difficult. To counteract this effect, a voltage Vpassl can be applied to WL2, where Vpassr is higher than Vpassl and later applied to the voltage of the unselected word line adjacent to a selected word line, as in the example of Figures 6-8. Shown in . Therefore, Vpassl1 is a boost voltage used to compensate for the effect of Viso applied to SGS. In this case, other Vpass voltages can also be modified. The value of the boost voltage does not have to be the same during the stylization of each word line. Thus, Vpassl, Vpass2, VpaSS3, ..., etc. may have a specific value for programming a particular word line WLn 'but not during the stylization of another word line WLn+x 120783.doc -24- 200811867 The same value. Although a stepped voltage scheme can be used in each case, different voltage values can be used during stylization of different word lines. Figure 9C shows the stylization of WL2, which is after the stylization of WL1 shown in Figure 9B. A stepped voltage scheme is applied to word lines WL3 through WL6 as previously shown in Figures 6 and 7. The word line WL3 (which is adjacent to the selected word line WL2 on the drain side) receives the voltage Vpass1. However, the word line WL1 adjacent to the selected word line WL2 on the source side does not receive Vpass1 in this case. The WL1 receives Vpassx. In this example, Vpassx is less than the Vpass voltage of Vpassl. Since a high Vpass voltage applied to WL1 (e.g., Vpassl) can cause hot electrons to be generated and injected into FG1 or FG2 at select gate SGS, a lower Vpass voltage (Vpassx) is used. The phenomenon of interference caused by the thermoelectric injection at SGS and the use of a reduced Vpass voltage for WL1 to suppress this problem are discussed in more detail in U.S. Patent Publication No. 2005/0174852. The techniques described in this application can be combined with specific embodiments of the invention to achieve the benefits of the two methods. Although Vpassx is shown between Vpassl and Vpass2, in other examples, Vpassx can be equal to or less than Vpass2. Figure 9C shows an example of an asymmetric step ladder voltage scheme in accordance with an embodiment of the present invention. Various other stepped voltage schemes, such as symmetrical and asymmetrical, are within the scope of the present invention. Figure 10A shows a stepped voltage scheme applied to unselected word lines WLn+1 through WLn+4 during WLn stylization. In this case, four boost voltages (Vpass1 to Vpass4) are applied to the word lines WLn+1 to WLn+4. The voltages Vpass1 to Vpass4 have a stepped curve in which the voltage is reduced in accordance with the distance from the selected word line WLn. On the other side of the selected word line WLn (WLn-1 120783.doc -25-200811867, etc., not shown in Figure 10A), the Vpass voltage mirrors the word lines WLn+Ι to WLn+4. Apply. In an alternate embodiment, an isolation voltage can be applied to one or more of the word lines on the other side of the selected word line WLn. In other alternatives, some other combination of Vpass voltage and isolation voltage can be applied to the word line on the other side of WLn. This particular embodiment does not require that the voltage be applied symmetrically with respect to the selected word line to achieve the benefits of this voltage scheme. Even when the stepped voltage scheme is applied only to one side of the selected word line, some benefits may result. Figure 10A shows a static map of the voltage applied at a particular time during the stylization of the cells along word line WLn. In this example, the boost voltage is not applied immediately at its last level, but is incrementally increased to a final level. Fig. 10B shows a timing chart of voltages applied to the word lines WLn-4 to WLn+4 of Fig. 10A over a period of time, including the time indicated by Fig. 10A (time period 丨9 to t1 (> in Fig. 10B) Before t9, the voltage is stepwise increased until it reaches its final value. The example of Fig. 10B shows that the selected word line WLn has a voltage that is increased to Vpgm in a stepwise manner. Similarly, the word line WLn+Ι to WLn The +4 and word lines WLn-Ι to WLn-4 experience a stepped voltage increase. In this example, the voltage applied to the word line is symmetric about the selected word line WLn, where the word lines WLn+Ι and WLn- Ι receiving the same voltage, word lines WLn+2 and WLn-2 receive the same voltage, and so on. In other cases, the voltage may be applied asymmetrically. Before time t〇, word lines WLn-4 to WLn +4 may be at a base voltage of, for example, zero volts. At time tG, the voltage applied to word lines WLn-4 to WLn+4 is tilted upward, and at the time center, the tilt stops, and to the character Line WLn-4 to •26- 120783.doc 200811867 The voltage of WLn+4 is maintained at the voltage of Vpass4. Thereafter, at time t2 The voltages applied to the word lines WLn-3 to WLn+3 are tilted until time t3, when the tilt is stopped and the voltages applied to the word lines WLn-3 to WLn+3 are held at Vpass3. When applied to the word line WLn- When the voltage of 3 to WLn+3 is tilted and held at Vpass3, the voltages applied to the word lines WLn-4 and WLn+4 are maintained at the voltage Vpass4 without tilting the voltage. Thereafter, at time t4, applied to The voltages of the word lines WLn-2 to WLn+2 are tilted until time t5, when the tilt is stopped and the voltages applied to the word lines WLn-2 to WLn+2 are held at Vpass2. When applied to the word lines WLn-2 to WLn When the voltage of +2 is tilted and held at Vpass2, the voltages to word lines WLn-4 and WLn+4 are maintained at Vpass4, and the voltages to word lines WLn-3 and WLn+3 are maintained at Vpass3 as before. Thereafter, at time t6, the voltages applied to the word lines WLn-1 to WLn+Ι are tilted until B is struck, and the voltage applied to the word lines WLn-Ι to WLn+Ι is maintained when the tilt is stopped. At Vpassl, when the voltage applied to the word line WLn-Ι to WLn+Ι is tilted and maintained at Vpass1, the voltages to the word lines WLn-4 to WLn-2 and WLn+2 to WLn+4 are maintained at previously Thereafter, at time 18, the voltage applied to the selected word line WLn is tilted until time t9, when the tilt is stopped and the voltage applied to the word line WLn is maintained at a program voltage Vpgm. When applied to the selected character The voltage of the line WLn is tilted and the word lines WLn_4 to WLn-Ι and WLn+Ι to WLn+4 are maintained at their previous values while Vpgm is maintained. The voltage applied to the word lines WLn-4 to WLn+4 at this time (after time 19) can be seen in Fig. 10A. Thereafter, at time 11 (), the voltage applied to the word lines WLn-4 to WLn+4 is inclined downward and reaches a base voltage at time tn. 120783.doc •27- 200811867 The voltage scheme shown in the timing diagram of Figure 10B causes turbulence interference with the memory cell when the voltage is directly ramped from a base voltage to its final voltage. The incremental change in voltage generally causes less interference than a large change. Any noise caused by the voltage change in the embodiment of Fig. 10B tends to be less than the noise caused by, for example, causing the voltage on word line WLn to tilt from a base voltage to Vpgm. In some embodiments, the programming is achieved by applying a pulse of the programmed voltage to a selected word line and verifying the threshold voltage of the floating gate transistor below the pulse. Thus, after tn, the threshold voltage of the cell under WLn can be read and thereafter another pulse of the program voltage can be applied in the same manner by applying a boost voltage in a stepped voltage ramp sequence. The pulse and read can be repeated in sequence until the threshold voltage of all cells of word line WLn is in its desired state. Figure 10C shows a timing diagram of a voltage scheme in accordance with an alternate embodiment. The voltage scheme of Fig. 10C provides a voltage curve which is the same as that shown in Fig. 10A in the period from "to u. Therefore, during this time, the voltage of the same stepped mode is applied to the word lines WLn-4 to WLn. + 4. However, during the previous period, the voltage is tilted in a different manner than shown in Figure loc. Prior to time tG, word lines WLn-4 through WLn+4 are maintained at a base voltage, such as zero volts. At time tG, the voltages applied to the word lines WLn_4 to WLn+4 are tilted upward, and at time ^, the tilt stops and the voltages to the word lines WLn-4 to WLn+4 are maintained at the voltage of Vpass4. (for WLn-4 and WLn+4), Vpass3 (for WLn-3 and WLn+3), Vpass2 (for WLn-2 and WLn+2), and Vpassl (for WLn-1, WLn, and WLn+1). In this example, the voltage supplied to the unselected word line is 120783.doc -28- 200811867. The voltage is directly ramped from a base voltage to its desired boost voltage. Although the tilt is not for all word lines. Take the same amount of time, but in some cases 'it can take longer for word lines that are raised to higher voltages. After 'at the time h, based on the voltage of the selected word line WLn and inclined at time t3, and the voltage on the stop inclination WLn maintained until Vpgm time. " When the voltage supplied to the selected word line is tilted and maintained at Vpgm (from time h to, all unselected word lines remain at their desired boost voltage (Vpassl to Vpass4). Thereafter, at time %, supply to The voltages of word lines WLn-4 to WLn+4 are tilted down to the base voltage. This scheme can achieve many advantages of a stepped voltage mode over time, but because it does not need to increase the voltage multiple times to unselected words. The line can be programmed more quickly. The boost voltage scheme described above can be achieved using a suitable circuit that is located on the same wafer as the memory array as a peripheral circuit or on another wafer. For example, the column control circuit can be adapted. In the above manner, a stepped voltage scheme is provided to the unselected word line, or to the voltage of the unselected word line. In some cases, an alternative boost voltage scheme can also be used to meet the demand, so a ladder can be selected. The boost voltage scheme is used as a mode in which one or more other modes can be used. Another boost voltage scheme can be a preset scheme, so that a stepped boost voltage scheme is only enabled in its In an example, different boost voltage schemes can be used for different portions of the memory array in the same memory array. For example, different boost blocks can use different boost voltage schemes. The second boost voltage scheme can be selected at one time and can be selected at a later time - different boost voltages 120783.doc -29- 200811867 scheme for one part of a memory array (biting (secondary for the whole) Memory array - or the frequency of multiple disturbances, the nature of the data to be stored (the importance of the data and the possibility of using ECC or other methods to repair the data), stylized the list). Received by the end user Before the memory, you can select a boost voltage scheme during the initial test and configuration of the _memory system. Or when using the memory, you can choose a suitable one based on some standards: electricity: scheme. Including wear (used by all or part of the memory of the two trains), occurring in the memory array (or _ partial memory array)
料之時間限制，程式化該資料之功率限制，儲存在一單一 記憶體單元巾之邏輯狀態的數目，將臨界t壓特別指定給 記憶體狀態及記憶體陣列的其他特徵。選擇一適合增壓電 壓方案可藉由控制器或由在與記憶體陣列相同晶片上之專 用電路執行。 雖然本發明已在上面參考各種不同具體實施例描述，但 應了解可進行變更及修改而不脫離本發明的範圍，其僅由 隨附申請專利範圍及其等效者所定義。本文所參考的所有 參考資料均以引用方式併入本文中。 【圖式簡單說明】 圖1係其中可實施本發明之記憶體單元陣列及操作改良 的先前技術記憶體系統類型之方塊圖。 圖2 A係先前技術之一先前技術反及陣列之平面圖。 圖2B係圖2A之先前技術反及陣列沿線A-A的斷面圖。 圖3A係描述圖2A之三個先前技術反.及串的電路圖。 圖3B係描述一些先前技術反及串的電路圖。 120783.doc -30- 200811867 圖4 A顯示在程式化一浮動閘極期間之先前技術反及串的 斷面’其包括在一選定浮動閘極及相鄰字元線間之電容性 耦合。 圖4B顯不在依據LSB方案程式化期間施加至圖‘a之先前 技術反及串的字元線之電壓。 圖5顯示在一反及串的組件間之一些電容性耦合，尤其 疋在相鄰浮動閘極下之字元線及浮動閘極間的耦合。 圖6顯示依據本發明之一具體實施例施加至圖$的反及串 之字元線的階梯狀增壓電壓。 圖7顯示依據本發明另一具體實施例施加至選定字元線 之一侧上的圖5之反及串的字元線之階梯狀增壓電壓，及 轭加至選定字元線之另一側上的字元線的絕緣電壓。 圖8顯示依據本發明另一具體實施例施加至圖$的反及串 之字元線的階梯狀電壓，其具施加至接收階梯狀電壓之字 元線的任一侧上的字元線之絕緣電壓。 圖9A顯示包括一源極選擇閘極（SGS)線及多個字元線及 浮動閘極之一反及串的一端之斷面。 圖9B顯示在沿字元線WL丨程式化期間施加至圖9 a之字 元線的修改的階梯狀電壓方案之範例，其中已增加之增壓 電壓係施加至WL2以抵消在選擇閘極線上之低電壓。 圖9C顯示在沿字元線WL2程式化期間施加至圖9 a之字 元線的修改的階梯狀電壓方案之另一範例，其中已減少之 增壓電壓係施加至字元線㈣以減少由在祕選擇閘極下 產生之熱電子造成的干擾。 120783.doc • 31 - 200811867 圖10A顯示當WLn在Vpgm時在程式化字元線WLn下之記 憶體單元期間，施加至字元線WLn至WLn+4的階梯狀增壓 電壓。 圖10B顯示在程式化圖10A之WLn下的記憶體單元期間 經過一時間週期（其包括當WLn係在Vpgm之時間）後，施加 至子兀線AVLn -4至W^n+4之電壓’包括從一基極電壓在增 壓電壓中之階梯狀增加。The time limit of the material, the power limit of the program is stored, the number of logic states stored in a single memory unit, and the critical t-pressure is specifically assigned to the memory state and other features of the memory array. Selecting a suitable boost voltage scheme can be performed by the controller or by a dedicated circuit on the same wafer as the memory array. While the invention has been described above with reference to the various embodiments of the present invention, it is understood that the invention may be modified and modified without departing from the scope of the invention. All references cited herein are hereby incorporated by reference. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing the type of prior art memory system in which the memory cell array of the present invention can be implemented and improved in operation. Figure 2A is a plan view of one of the prior art prior art and arrays. Figure 2B is a cross-sectional view of the prior art of Figure 2A taken along line A-A. Figure 3A is a circuit diagram depicting the three prior art inverses and strings of Figure 2A. Figure 3B is a circuit diagram depicting some prior art inverse strings. 120783.doc -30- 200811867 Figure 4A shows a prior art cross section of a string during a staging of a floating gate, which includes a capacitive coupling between a selected floating gate and adjacent word lines. Figure 4B shows the voltage applied to the word line of the previous technique of Figure 'a against the string during the LSB scheme stylization. Figure 5 shows some capacitive coupling between components in a reversed string, especially between the word lines and floating gates under adjacent floating gates. Figure 6 shows a stepped boost voltage applied to the inverse and string of word lines of Figure $ in accordance with an embodiment of the present invention. Figure 7 shows a stepped boost voltage applied to the word line of the inverse of the string of Figure 5 on one side of the selected word line, and the yoke applied to the selected word line, in accordance with another embodiment of the present invention. The insulation voltage of the word line on the side. 8 shows a stepped voltage applied to the inverse and string word lines of FIG. $ with a word line applied to either side of the word line receiving the stepped voltage, in accordance with another embodiment of the present invention. Insulation voltage. Figure 9A shows a section including one source select gate (SGS) line and one of a plurality of word lines and floating gates opposite the end of the string. Figure 9B shows an example of a modified stepped voltage scheme applied to the word line of Figure 9a during stylization along word line WL, where the increased boost voltage is applied to WL2 to cancel on the select gate line. Low voltage. 9C shows another example of a modified stepped voltage scheme applied to the word line of FIG. 9a during stylization along word line WL2, wherein the reduced boost voltage is applied to the word line (4) to reduce Interference caused by hot electrons generated under the secret selection gate. 120783.doc • 31 - 200811867 FIG. 10A shows the stepped boost voltage applied to the word lines WLn to WLn+4 during the memory cell under the stylized word line WLn when WLn is at Vpgm. FIG. 10B shows the voltage applied to the sub-wires AVLn-4 to W^n+4 after a period of time (which includes the time when the WLn is at Vpgm) during the staging of the memory cells in WLn of FIG. 10A. This includes a stepwise increase in voltage from a base voltage in the boost voltage.
圖10C顯示一用於達到圖10A之電壓曲線的替代方案， 其係藉由在未選定字元線上傾斜電壓至其目標電壓而無須 步進通過中間電壓。 【主要元件符號說明】 1 記憶體單元陣列 2 行控制電路 3 列控制電路 4 c源極控制電路 5 C-p井控制電路 6 資料輸入/輸出緩衝器 7 命令電路 8 狀態機 9 控制器 10 隨機存取記憶體（RAM) 11 反及串 11A 積體電路晶片 11B 積體電路晶片 120783.doc -32 - 200811867Figure 10C shows an alternative for achieving the voltage profile of Figure 10A by ramping the voltage to its target voltage on unselected word lines without stepping through the intermediate voltage. [Main component symbol description] 1 Memory cell array 2 Row control circuit 3 Column control circuit 4 c Source control circuit 5 Cp well control circuit 6 Data input/output buffer 7 Command circuit 8 State machine 9 Controller 10 Random access Memory (RAM) 11 and string 11A Integrated circuit chip 11B Integrated circuit chip 120783.doc -32 - 200811867
12 13 14 15 16 19 20 22 26 28 3 0 40 42 44 46 48 50 64 位元線 反及串 位元線 反及串 位元線 中間介電層 選擇電晶體 記憶體單元 記憶體单元 記憶體單元 記憶體單元 選擇電晶體 選擇電晶體 記憶體單元 記憶體單元 記憶體單元 記憶體單元 選擇電晶體 記憶體單元 120783.doc -33-12 13 14 15 16 19 20 22 26 28 3 0 40 42 44 46 48 50 64 bit line reverse and serial bit line reverse and bit line line intermediate dielectric layer selection transistor memory unit memory unit memory unit Memory cell selection transistor selection transistor memory cell memory cell memory cell memory cell selection transistor memory cell unit 120783.doc -33-