TW200811565A - TFT array substrate and method of manufacturing the same, and display device using the same - Google Patents

Abstract

To provide a display device having excellent display quality and high productivity. A TFT array substrate has on a substrate 110, a gate electrode 1, a gate insulating film 3, a semiconductor layer 23, source and drain electrodes 11b and 11c composed of a transparent conductive film 11 and a pixel electrode 11a extended from the drain electrode 11c. An interlayer dielectric 8 having a source electrode contact hole 27 reaching the source electrode 11b and a source line 22 connected to the source electrode 11b through the source electrode contact hole 27 are formed on the transparent conductive film 11.

Description

200811565 九、發明說明： 【發明所屬之技術領域】 本發明係有關於薄膜電晶體陣列基板及其製造方法， 以及使用該基板之顯示裝置。 【先前技術】 以使用液晶之顯示器（d i sp 1 ay )用電性光學元件而 5 ’有使用單純矩陣（matrix)型液晶顯示裝置與開關 (switching)元件的主動矩陣（active matrix)型液晶顯示 裝置。尤其是，在主動矩陣型液晶顯示裝置中，使用薄膜 電晶體（Thin Film Transistor ; TFT)-LCD，由於攜帶性、 顯不品質良好的緣故，因此廣泛地實用於筆記型電腦 (notebook computer)。在 TFT — LCD 中，一般而言，係在薄 膜電晶體陣列基板與對向基板之間夾置液晶層。τ{?τ在薄 膜電晶體陣列基板上形成陣列狀。在此薄膜電晶體陣列基 板及對向基板之外側分別設置偏光板。而且，在一方之側 設置背光（back 1 ight)源。 為了降低顯示裝置之製造成本（cost)，薄膜電晶體陣 列基板之製造成本的降低也是一大課題。藉由減少薄膜電 晶體陣列基板之製造步驟中微影製程（ph〇t〇i i让叩Mpb process)之回數，因此有人提出簡化製程的技術（特許文獻 1、2) 〇 在特許文獻1中，係揭露一插斜键n替+ n 丨τ构路種對溥膜電晶體陣列基板 進行5回微影製程而形成主動矩束200811565 IX. Description of the Invention: [Technical Field] The present invention relates to a thin film transistor array substrate, a method of manufacturing the same, and a display device using the same. [Prior Art] An active matrix type liquid crystal display using a simple type of liquid crystal display device and a switching element is used for an optical optical device using a liquid crystal display (di sp 1 ay ) Device. In particular, in an active matrix type liquid crystal display device, a thin film transistor (TFT)-LCD is widely used for a notebook computer because of its portability and poor quality. In a TFT-LCD, generally, a liquid crystal layer is interposed between a thin film transistor array substrate and a counter substrate. τ{?τ forms an array on the thin film transistor array substrate. A polarizing plate is disposed on each of the thin film transistor array substrate and the opposite side of the opposite substrate. Also, a backlight (back 1 ight) source is provided on one side. In order to reduce the manufacturing cost of the display device, the reduction in the manufacturing cost of the thin film transistor array substrate is also a major issue. By reducing the number of times of the lithography process in the manufacturing process of the thin film transistor array substrate, a technique for simplifying the process has been proposed (licensed documents 1, 2). , revealing a slanting key n for the + n 丨τ structure to perform a five-time lithography process on the enamel transistor array substrate to form an active moment beam

初跑1早型液晶顯不裝置的製造 2185-8937-PF 5 200811565 種對薄膜電晶體陣列基 動矩陣型液晶顯示裝置 方法，在特許文獻2中，係揭露一 板進行4或5回微影製程而形成主 的製造方法。 特許文獻1所揭示之習知例之薄膜電晶體陣列基板的 平面圖係繪示於圖11中；並在圖12〜14中綠示其主要部 份的剖面圖。圖12係繪示圖η…，切斷部的剖面圖。 圖13及圖丨4係分別繪示設於顯示區域之外側之Tcp(Tape Carrier Package)之端子部之剖面構造的典型圖。Tcp係 從問極（gate)配線、源極（SGU⑽配線、補助容量配線及 對向基板之共通電極之信號電位源分別向問極配線、源極 配線、補助容量配線及共通電極供給信號電位。 如圖12所示，習知例之TFT | & μ ^ 基板係以覆蓋設於基板 110上之閘極電極1、閘極電極ljL之閘極絕緣膜3、間極 絕緣膜3上之半導體層23、半導體層23上之源極電極7 及汲極（draiiO電極6、源極電極7及汲極電極6的方式而Manufacture of a first-running early-type liquid crystal display device 2185-8937-PF 5 200811565 A method for a thin film transistor array base matrix type liquid crystal display device, in Patent Document 2, a board is disclosed for 4 or 5 lithography The process forms the main manufacturing method. A plan view of a thin film transistor array substrate of a conventional example disclosed in Patent Document 1 is shown in Fig. 11; and a cross-sectional view of a main portion thereof is shown green in Figs. Figure 12 is a cross-sectional view showing the cut portion of Figure η. FIG. 13 and FIG. 4 are typical views showing a cross-sectional structure of a terminal portion of a Tcp (Tape Carrier Package) provided on the outer side of the display region. The Tcp is supplied with a signal potential from the signal potential source of the gate wiring, the source (SGU (10) wiring, the auxiliary capacity wiring, and the common electrode of the opposite substrate to the gate wiring, the source wiring, the auxiliary capacity wiring, and the common electrode. As shown in FIG. 12, the TFT | & μ ^ substrate of the conventional example is a semiconductor covering the gate electrode 1 on the substrate 110, the gate insulating film 3 of the gate electrode 1jL, and the interlayer insulating film 3. The layer 23, the source electrode 7 on the semiconductor layer 23, and the drain (the draiiO electrode 6, the source electrode 7, and the drain electrode 6)

形成’且包括具有到達汲極電極6之晝素接觸洞(COMM hall )9的層間絕緣膜8與層間絕緣膜8上之透明導電膜 11。半導體層23係包括半導體主動膜4及歐姆接觸 contact)膜 5 〇 閘極電極1係閘極配線21之-部份、或是成為從閘極 配線21分岐而與各TFT連接之端子的電極。另外，補助容 量配線20之一部份係以與透明導電膜u重疊 的方式而配置，並形成補助容量。 在特許文獻1所記載之薄膜電晶體陣列基板中，源極It is formed 'and includes an interlayer insulating film 8 having a COMM hall 9 reaching the gate electrode 6 and a transparent conductive film 11 on the interlayer insulating film 8. The semiconductor layer 23 includes a semiconductor active film 4 and an ohmic contact contact film 5 〇 a gate electrode 1 is a portion of the gate wiring 21 or an electrode which is a terminal which is branched from the gate wiring 21 and connected to each TFT. Further, one portion of the auxiliary capacity wiring 20 is disposed so as to overlap the transparent conductive film u, and a supplementary capacity is formed. In the thin film transistor array substrate described in Patent Document 1, the source

2185-8937-PF 6 200811565 配線22及源極電極7在顯示部内未超越半導體層23之段 差。因此，可以避免產生因半導體層23之段差所^引起的: 極配線22及源極電極7之斷線。另夕卜於透明導電膜u 之周邊附近有半導體層23。但是’透明導電膜u與半導 體層23、及透明導電膜u與源極配線22係藉由層間絕緣 膜8而分離。藉此’可㈣免半導體層23及源極配線a 之圖案（pattern)不良。因此，可以防止源極配線22與透 明導電膜11之間的單純短路、或在光照射下半導體主動膜 4為低電阻化時發生短路。 但是，在特許文獻1所記載之薄膜電晶體陣列基板 中’在使用A1膜於源極配線22之情況下，有因為加熱而 在A1膜表面發生微小突起（HlU〇ck)並產生層間絕緣不'良 的問題。另外，有所謂在源極配線2 2與透明導電膜11之 間產生氧化層，且在源極配線2 2與透明導電膜丨丨之連接 部的接觸電阻變高而產生顯示不良的問題。 而且，在使用單層A1膜於源極配線22之金屬薄膜材 料的情況下，在與源極配線22電性連接之半導體層23的 連接部中，引起A1肖Si之相互擴散，而有接觸電阻變高 並導致顯示不良的問題。 如特許文獻2所揭示，為了謀求晝素電極與汲極電極 之接觸電阻的極小化，因此將閘極配線或閘極電極作成由 第1層與第2層構成之積層構造，其中第j層由 合金構成，而第2層乃藉由在A1或A1合金中添加N、c、 〇中至少1種的不純物而構成；且將形成源極電極、源極2185-8937-PF 6 200811565 The wiring 22 and the source electrode 7 do not exceed the step of the semiconductor layer 23 in the display portion. Therefore, it is possible to avoid the occurrence of disconnection of the pole wiring 22 and the source electrode 7 due to the step difference of the semiconductor layer 23. Further, a semiconductor layer 23 is provided in the vicinity of the periphery of the transparent conductive film u. However, the transparent conductive film u and the semiconductor layer 23, and the transparent conductive film u and the source wiring 22 are separated by the interlayer insulating film 8. Thereby, the pattern of the semiconductor layer 23 and the source wiring a can be prevented from being defective. Therefore, it is possible to prevent a short circuit between the source wiring 22 and the transparent conductive film 11 or a short circuit when the semiconductor active film 4 is reduced in resistance under light irradiation. However, in the thin film transistor array substrate described in Patent Document 1, when the A1 film is used for the source wiring 22, micro-protrusions (H1U〇ck) are generated on the surface of the A1 film due to heating, and interlayer insulation is not generated. 'Good question. In addition, an oxide layer is formed between the source wiring 2 2 and the transparent conductive film 11, and the contact resistance between the source wiring 2 2 and the transparent conductive film 变 is increased, resulting in display failure. Further, in the case where a single-layer A1 film is used for the metal thin film material of the source wiring 22, in the connection portion of the semiconductor layer 23 electrically connected to the source wiring 22, mutual diffusion of A1 xiao Si is caused, and there is contact. The resistance becomes high and causes a problem of poor display. As disclosed in Patent Document 2, in order to minimize the contact resistance between the halogen electrode and the drain electrode, the gate wiring or the gate electrode is formed as a laminated structure composed of the first layer and the second layer, wherein the jth layer It is composed of an alloy, and the second layer is formed by adding at least one of N, c, and yttrium to the A1 or Al alloy; and the source electrode and the source are formed.

2185-8937-PF 200811565 配線及汲極電極之第？ 至屬薄膜作成Mo合金之單層或A1 合金與Mo合金之積声播 槓曰構w的構造。在特許文獻3中，揭示 一種在A1膜之上厣拟Λ、p 、 曰/成Cr或Mo等高融點金屬的方法，以 作為防止由微小突扭3丨4 ^ 引起之層間絕緣不良以及與透明導電 膜11之接觸不良，卫尤 、， 在A1膜之下層也形成高融點金屬， 並防止與半導+ 卞守舣層23之接觸不良的方法。 另外在特許文獻4中，揭示-種將源極信號線、源 極電極、汲極電極、透過晝素電極形成在同-層（layer) 的技術。藉此，可以防止接觸不良。 [特+文獻1]特開平1〇 —268353號公報 [特許文獻2]特開2005-62802號公報段落番號 0027 [特許文獻3]特開2000-284326號公報 [特許文獻4]特開2000-258802號公報 【發明内容】 在特許文獻2所記載之薄膜電晶體陣列基板中，閘極 配線等第1金屬薄膜之材料需要2種類以上。另外，在特 许文獻3所記載之薄膜電晶體陣列基板中，源極配線材料 需要2種類（A1與Cr或M〇等高融點金屬）以上。結果， 由於成膜、钱刻（etching)之製造工數增加而無法避免成本 上升。另外’在特許文獻3中係由於源極配線為三層構造 的緣故，因此難以控制加工後之剖面形狀，而有招致良率 降低的問題點。2185-8937-PF 200811565 Wiring and drain electrodes? It is a structure in which a film is formed as a single layer of a Mo alloy or an acoustic layer of an A1 alloy and a Mo alloy. In Patent Document 3, a method of simulating a high melting point metal such as yttrium, p, lanthanum/cr or Mo on the A1 film is disclosed as a barrier to interlayer insulation caused by a microbend 3?4^ and The contact with the transparent conductive film 11 is poor, and Wei, a high-melting point metal is formed under the layer of the A1 film, and a method of preventing contact with the semiconductor layer 23 is prevented. Further, Patent Document 4 discloses a technique in which a source signal line, a source electrode, a drain electrode, and a passivation electrode are formed in a same layer. Thereby, contact failure can be prevented. [Patent Document 2] JP-A-2005-62802, paragraph number 0027 [Patent Document 3] JP-A-2000-284326 [Private Document 4] Special Edition 2000 In the thin film transistor array substrate of the patent document 2, the material of the first metal thin film such as the gate wiring is required to be two or more types. Further, in the thin film transistor array substrate described in the third aspect of the invention, the source wiring material requires two types (A1 and Cr or M〇 high melting point metal) or more. As a result, the cost increase due to an increase in the number of manufacturing processes of film formation and etching is unavoidable. Further, in Patent Document 3, since the source wiring has a three-layer structure, it is difficult to control the cross-sectional shape after processing, and there is a problem that the yield is lowered.

2185-8937-PF 8 200811565 另外’在特許文獻4所記載之薄膜電晶體陣列基板 中源極彳5就線、源極電極、汲極電極、透過晝素電極係 由透明導電膜與金屬膜構成。結I，需要2種類以上之材 料，因為成膜、蝕刻等製造工數之增加而導致成本上升。 而且由於源極信號線與透過晝素電極之間沒有層間絕緣 膜的緣故，所以源極信號線與透過晝素電極易短路 (Short)而有導致因點燈不良所引起之良率降低等問題 點。 另方面，特許文獻1所記載之薄膜電晶體陣列基板 係使用低電阻之Ag膜作為源極配線22之金屬薄膜的配線 材料。但是，一般而言，Ag的耐電漿（plasma)性低，且於 接觸洞形成時’有接觸洞内之Ag消失的問題點。 有鑑於上述背景，本發明係提供顯示品質優、且生產 性南之顯不裝置。 [課題解決之手段] 本發明之薄膜電晶體陣列基板，包括：閘極電極，設 置於基板上；閘極絕緣膜，形成於該閘極電極之上；半導 體層，形成於該閘極絕緣膜上，且配置於該閘極電極之對 面；源極電極及汲極電極，由形成於該半導體層之上的透 明導電膜組成；畫素電才圣，自該汲極電極延伸，由該透明 導電膜組成；f間絕緣膜，形成於該晝素電極、該源極電 極 '及該㈣電極之上’具有到達該源極電極之接觸洞； 以及源極配線’形成於該層間絕緣膜之上，且隔著該接觸 洞而與該源極電極連接。 2185-8937-PF 9 200811565 [發明效果] 裝置 藉由本發明可以提供 顯示品質優 且生產性高之顯示 【實施方式】 乂下。兄月可以適用於本發明之實施形態。以下之說 明係有關本發明之實施形態，但本發明並非限定於以下之 實施形態。 實施形態1. -開始，使用圖1說明本發明之薄膜電晶體陣列基板 適用之主動矩陣型之顯示裝置。目1係緣示用於顯示裝置 之薄膜電晶體陣列基板之構成的平面圖。雖然本發明之顯 不裝置係以液晶顯示裝置為例作為說明，但是僅是其中一 個例不而已，也可以使用有機EL顯示裝置等平面型顯示裝 置（Flat Panel display)等。 本發明之顯示裝置具有基板110。基板11〇例如是薄 膜電晶體陣列基板。在基板11 〇設置額緣區域丨丨2，以包 圍顯示區域111。在此顯示區域丨i丨中，形成複數個閘極 配線（知目田“號線）21與複數個源極配線（顯示信號線）2 2。 複數個閘極配線21係平行設置。同樣地，複數個源極配線 22係平行設置。閘極配線21與源極配線22係相互交叉而 形成。閘極配線21與源極配線22係直交。而且，由相鄰 閘極配線21與源極配線22所圍之區域係成為晝素丨丨7。 因此，在基板11 0，晝素11 7係呈矩陣狀配列。 2185-8937-PF 10 200811565 而且，在基板110之額緣區域112設置掃瞄信號驅動 電路115與顯示信號驅動電路116。閘極配線21係從顯示 區域111延伸至額緣區域112。閘極配線21係在基板 之端部與掃瞄信號驅動電路115連接。源極配線22也同樣 地從顯示區域111延伸至額緣區域112。源極配線22係在 基板110之端部與顯示信號驅動電路i丨6連接。外部配線 118連接在掃瞄信號驅動電路丨15附近。另外，外部配線 11 9連接在顯示信號驅動電路丨丨6附近。外部配線丨丨8、 119 例如疋 FPC (Flexible printed Circuit)等配線基板。 來自外部之各種信號藉由外部配線丨丨8、丨丨9而供給至 掃瞄信號驅動電路11 5、及顯示信號驅動電路丨丨6。掃瞄信 號驅動電路115根據來自外部之控制信號，將閘極信號（掃 瞄信號）供給至閘極配線21。藉由此閘極信號，依序選擇 閘極配線21。顯示信號驅動電路116係根據來自外部之控 制#唬、或顯不數據而將顯示信號供給至源極配線22。藉 此，將因應顯示數據之顯示電壓供給至各晝素117。 曰 在晝素117内至少形成i個TFT12(^TFT12〇係配置於 源極配線22與閘極配線21之交叉點附近。例如，此τρτΐ2〇 在畫素電極供給顯示電壓。也就是說，藉由來自閘極配線 21之閘極信號而作為開關元件之TFn2〇開啟。藉此，顯 不電壓從源極配線22而施加在與TFT之汲極電極連接的晝 素電極上。而1，在晝素電極與對向電極之間產生因應顯 示電壓之電場。而且，在基板11〇之表面形成配向膜（圖未2185-8937-PF 8 200811565 Further, in the thin film transistor array substrate described in Patent Document 4, the source 彳5 line, the source electrode, the drain electrode, and the transmissive element electrode are composed of a transparent conductive film and a metal film. . In the case of I, two or more types of materials are required, and the cost increases due to an increase in the number of manufacturing processes such as film formation and etching. Moreover, since there is no interlayer insulating film between the source signal line and the transmissive element electrode, the source signal line and the transmissive element electrode are short-circuited (Short), which causes problems such as a decrease in yield due to lighting failure. point. On the other hand, in the thin film transistor array substrate described in Patent Document 1, a low-resistance Ag film is used as a wiring material of a metal thin film of the source wiring 22. However, in general, Ag has low plasma resistance and has a problem that Ag in the contact hole disappears when the contact hole is formed. In view of the above background, the present invention provides an apparatus which is excellent in display quality and productive in the south. [Means for Solving the Problem] The thin film transistor array substrate of the present invention includes: a gate electrode provided on the substrate; a gate insulating film formed on the gate electrode; and a semiconductor layer formed on the gate insulating film And disposed on the opposite side of the gate electrode; the source electrode and the drain electrode are composed of a transparent conductive film formed on the semiconductor layer; the pixel is electrically extended from the gate electrode, and the transparent a conductive film composition; an inter-f insulating film formed on the halogen electrode, the source electrode 'and the (four) electrode 'having a contact hole reaching the source electrode; and a source wiring ' formed on the interlayer insulating film And connected to the source electrode via the contact hole. 2185-8937-PF 9 200811565 [Effect of the Invention] Apparatus According to the present invention, it is possible to provide a display having excellent display quality and high productivity. [Embodiment] The brother and the moon can be applied to the embodiment of the present invention. The following description relates to the embodiments of the present invention, but the present invention is not limited to the following embodiments. Embodiment 1. First, an active matrix type display device to which a thin film transistor array substrate of the present invention is applied will be described with reference to Fig. 1 . Fig. 1 is a plan view showing the configuration of a thin film transistor array substrate for a display device. Although the display device of the present invention has been described by taking a liquid crystal display device as an example, only one of them may be used, and a flat display device such as an organic EL display device may be used. The display device of the present invention has a substrate 110. The substrate 11 is, for example, a thin film transistor array substrate. A margin area 丨丨2 is provided on the substrate 11 to surround the display area 111. In the display area 丨i丨, a plurality of gate wirings (the imaginary line "number line" 21 and a plurality of source wirings (display signal lines) 2 2 are formed. The plurality of gate wirings 21 are arranged in parallel. A plurality of source wirings 22 are provided in parallel. The gate wiring 21 and the source wiring 22 are formed to intersect each other. The gate wiring 21 and the source wiring 22 are orthogonal to each other. Further, the adjacent gate wiring 21 and the source are provided. The area surrounded by the wiring 22 is a halogen sheet 7. Therefore, in the substrate 110, the halogen 11 7 is arranged in a matrix. 2185-8937-PF 10 200811565 Moreover, a sweep is provided in the fore edge region 112 of the substrate 110. The tracking signal driving circuit 115 and the display signal driving circuit 116. The gate wiring 21 extends from the display region 111 to the front edge region 112. The gate wiring 21 is connected to the scanning signal driving circuit 115 at the end of the substrate. Similarly, 22 extends from the display region 111 to the fore edge region 112. The source wiring 22 is connected to the display signal drive circuit i6 at the end of the substrate 110. The external wiring 118 is connected in the vicinity of the scan signal drive circuit 丨15. In addition, external wiring 11 9 In the vicinity of the display signal drive circuit 丨丨6, the external wiring 丨丨8, 119 is a wiring board such as a printedFPC (Flexible Print Circuit). Various external signals are supplied to the scan by the external wiring 丨丨8 and 丨丨9. The signal driving circuit 117 and the display signal driving circuit 丨丨6. The scanning signal driving circuit 115 supplies a gate signal (scanning signal) to the gate wiring 21 based on a control signal from the outside. The gate wiring 21 is sequentially selected. The display signal driving circuit 116 supplies a display signal to the source wiring 22 in accordance with control from external control or data display. Thereby, the display voltage corresponding to the display data is supplied to Each of the halogens 117. At least one of the TFTs 12 is formed in the pixel 117 (the TFT 12 is disposed in the vicinity of the intersection of the source wiring 22 and the gate wiring 21. For example, this τρτΐ2〇 supplies the display voltage to the pixel electrode. That is, TFn2 is turned on as a switching element by the gate signal from the gate wiring 21. Thereby, a voltage is not applied from the source wiring 22 to be connected to the drain electrode of the TFT. On day pixel electrode. 1 and, in response to the pixel electrode day display field voltage. Further, formed on the surface of the substrate with 11〇 (not between the electrodes to produce the film

顯示）。 2185-8937-PF 11 200811565 而且’對向基板係在基板11 〇對向配置。對向基板例 如是彩色濾光片（color fi Iter)基板，配置於視認侧。於 對向基板形成彩色濾光片、黑色矩陣（black matrix ; BM)、 對向電極、及配向膜等。而且，對向電極也有配置於基板 110側的情況。而且，在基板11 〇與對向基板之間夾置液 晶層。也就是說，於基板11 〇與對向基板之間注入液晶。 而且，於基板11 〇與對向基板之外側之面配設偏光板、及 位相差板等。另外，於液晶顯示面板之反視認側配設背光 單元等。 藉由晝素電極與對向電極之間的電場而驅動液晶。也 就是說，基板間之液晶之配向方向產生變化。藉此，通過 液晶層之光的偏光狀態產生變化。也就是說，通過偏光板 並成為直線偏光之光係藉由液晶層而使偏光狀態產生變 化。具體而a，來自背光單元之光係藉由陣列基板側之偏 光板而成為直線偏光。而且，藉由此直線偏光通過液晶層 而使偏光狀態產生變化。 因此，因應偏光狀態，則通過對向基板側之偏光板的 光i產生k化。也就疋說，在來自背光單元而透過液晶顯 示面板之透過光中，通過視認側之偏光板之光的光量產生 變化。液晶之配向方向係因為施加之顯示電壓而變化。因 此，藉由控制顯示電壓，可以變化通過視認側之偏光板的 光量。也就是說，藉由在每個晝素改變顯示電壓，可以顯 示所欲之影像。 接著，關於基板110上之TFT120之構成，使用圖2及display). 2185-8937-PF 11 200811565 Further, the 'opposing substrate is disposed opposite to the substrate 11'. The counter substrate, for example, a color fiiter substrate, is disposed on the viewing side. A color filter, a black matrix (BM), a counter electrode, an alignment film, and the like are formed on the opposite substrate. Further, the counter electrode may be disposed on the substrate 110 side. Further, a liquid crystal layer is interposed between the substrate 11 and the opposite substrate. That is, liquid crystal is injected between the substrate 11 and the opposite substrate. Further, a polarizing plate, a phase difference plate, and the like are disposed on the surface of the substrate 11 and the outer surface of the counter substrate. In addition, a backlight unit or the like is disposed on the opposite side of the liquid crystal display panel. The liquid crystal is driven by an electric field between the halogen electrode and the counter electrode. That is to say, the alignment direction of the liquid crystal between the substrates changes. Thereby, the polarization state of the light passing through the liquid crystal layer changes. In other words, the light that passes through the polarizing plate and becomes linearly polarized changes the polarization state by the liquid crystal layer. Specifically, a light from the backlight unit is linearly polarized by a polarizing plate on the array substrate side. Further, the polarization state is changed by the linear polarized light passing through the liquid crystal layer. Therefore, in response to the polarization state, the light i of the polarizing plate on the opposite substrate side is k-ized. In other words, in the transmitted light transmitted from the backlight unit through the liquid crystal display panel, the amount of light passing through the polarizing plate on the viewing side changes. The alignment direction of the liquid crystal changes due to the applied display voltage. Therefore, by controlling the display voltage, the amount of light passing through the polarizing plate on the viewing side can be changed. That is to say, by changing the display voltage at each element, the desired image can be displayed. Next, regarding the configuration of the TFT 120 on the substrate 110, FIG. 2 and

2185-893 7-PF 12 200811565 圖3進行說明。圖2係繪示本發明之實施形態丨之薄膜電 晶體陣列基板之主要部之構成的平面圖。圖3係繪示圖2 中薄膜電晶體陣列基板之χ- — χ’部之剖面圖。 複數個閘極配線21係平行地設於基板丨丨〇。另外，源 極配線22也平行地設置。閘極配線21與源極配線22係相 互交又而形成。閘極配線21與源極配線22直交。而且， 在相鄰閘極配線.21與源極配線22所圍之區域上形成晝素 電極11a。 一 、 閘極配線21係連接於閘極電極丨。在與相鄰閘極配線 21之間配置補助容量配線2〇。補助容量配線2()係與閑極 配線21平行而形成。而且，補助容量配線2〇係與晝素電 極11a對向。藉此而形成補助容量。在閑極配線^與源 極配線22之交叉點附近形成作為開關元件之別。 TFT120係具有由半導體主動膜4、及歐姆接觸膜$所構成 之半導體層23。半導體層23係形成於閘極電極i之上。 汲極電極11c與畫素電極Ua係一體形成 而且’在半導體層23之上形成汲極電極、及源極電極 Ub。在源極電極llb、及汲極電極以之上形成層間絕緣 膜8。在層間絕緣膜8之上形成源極配線22。而且，在層 :曰:絕緣膜8形成到達源極電極m之源極電極接觸洞π: 精由源極電極接觸洞27而源極電極Ub與源極配線^電 性連接。畫素電極lla從汲極電極Uc延伸。也就是說， 之I造方法。圖4係纷示 ’在本實施形態中，藉由 接著，使用圖4說明TFT120 本實施形態之製造步驟圖。而且2185-893 7-PF 12 200811565 Figure 3 illustrates. Fig. 2 is a plan view showing the configuration of a main portion of a thin film transistor array substrate according to an embodiment of the present invention. Figure 3 is a cross-sectional view showing the χ- —' portion of the thin film transistor array substrate of Figure 2. A plurality of gate wirings 21 are provided in parallel to the substrate 。. Further, the source wirings 22 are also disposed in parallel. The gate wiring 21 and the source wiring 22 are formed to be mutually intersected. The gate wiring 21 is orthogonal to the source wiring 22. Further, a halogen electrode 11a is formed on a region surrounded by the adjacent gate wiring .21 and the source wiring 22. 1. The gate wiring 21 is connected to the gate electrode 丨. The auxiliary capacity wiring 2 is disposed between the adjacent gate wirings 21. The auxiliary capacity wiring 2 () is formed in parallel with the idle wiring 21 . Further, the auxiliary capacity wiring 2 is opposed to the halogen electrode 11a. Thereby, the subsidized capacity is formed. The difference between the idler wiring and the source wiring 22 is formed as a switching element. The TFT 120 has a semiconductor layer 23 composed of a semiconductor active film 4 and an ohmic contact film $. The semiconductor layer 23 is formed over the gate electrode i. The drain electrode 11c is formed integrally with the pixel electrode Ua, and a drain electrode and a source electrode Ub are formed on the semiconductor layer 23. An interlayer insulating film 8 is formed over the source electrode 11b and the drain electrode. A source wiring 22 is formed on the interlayer insulating film 8. Further, in the layer: 曰: the insulating film 8 forms a source electrode contact hole π which reaches the source electrode m: the source electrode contact hole 27 is finely connected, and the source electrode Ub is electrically connected to the source wiring. The pixel electrode 11a extends from the drain electrode Uc. That is to say, the method of making it. Fig. 4 is a view showing a manufacturing step of the TFT 120 in the present embodiment. and

2185-8937-PF 13 200811565 5回之微影製程而製造薄膜電晶體陣列基板。 (A)第1微影製程 (a)首先，以純水洗淨玻璃基板等基板u 〇。在此種情 況下’也可以使用熱硫酸取代純水而進行洗淨。（b )接著， 在基板11 0上形成用於形成閘極電極1、閘極配線21及補 助容量配線20之第1金屬薄膜。（c)為了將第1金屬薄膜 圖案化，而進行第1回之微影製程。具體而言，塗布光阻 (resist)、曝光、顯影而形成光阻圖案。以第1金屬薄膜 而言，較佳者係可以使用電性比電阻低之A1、M〇、Cr、或 以上述材料為主成分之合金。在本實施形態中，可以使用 在A1中添加〇.2mol%之Nd的A1Nd合金。例如，藉由使 用 之 Ar( gas)的 DC 磁控錢錢（Magnetron sputtering) 法了 乂幵^成膜厚200nm之AINd膜。（d)之後，使用習知 之包含磷酸與碗酸的溶液而對A1Nd膜進行溼蝕刻（wet etchmg)。（e)然後，將光阻圖案剝離，並以純水洗淨。藉 形成閘極電極1、閘極配線21及補助容量配線2 〇。 (B)第2微影製程 + (〇接著，依序形成由氮化矽（SiN)所組成之第丨絕緣 膜、與非晶石夕UmOrphQUS si ! i _)所組成之半導體主動膜 、/、小力不、、、屯物之n +非晶矽所組成的歐姆接觸膜5。（g) 為I圖案化半導體主動膜4、與歐姆接觸膜5，進行第2 口 U轾。在此之際，除了包含形成薄膜電晶體之部分， 也形成較後述之装 所形成之源極配線22及汲極電極 11 c之圖案大且連鯖 、的形狀。以本實施形態而言，使用化2185-8937-PF 13 200811565 5 lithography process to manufacture a thin film transistor array substrate. (A) First lithography process (a) First, the substrate u 等 such as a glass substrate is washed with pure water. In this case, it is also possible to use hot sulfuric acid instead of pure water for washing. (b) Next, a first metal thin film for forming the gate electrode 1, the gate wiring 21, and the auxiliary capacity wiring 20 is formed on the substrate 110. (c) In order to pattern the first metal thin film, the first lithography process is performed. Specifically, a photoresist pattern is formed by applying a resist, exposure, and development. In the first metal thin film, it is preferable to use an alloy having a low specific electrical resistance, A1, M?, Cr, or an alloy containing the above materials as a main component. In the present embodiment, an A1Nd alloy in which 2 mol% of Nd is added to A1 can be used. For example, an AINd film having a film thickness of 200 nm is formed by using an Ar (gas) DC magnetron sputtering method. (d) Thereafter, the A1Nd film was wet-etched (wet etchmg) using a conventional solution containing phosphoric acid and bowl acid. (e) Then, the photoresist pattern was peeled off and washed with pure water. The gate electrode 1, the gate wiring 21, and the auxiliary capacity wiring 2 are formed. (B) The second lithography process + (〇, sequentially, a semiconductor active film composed of tantalum nitride (SiN), and an amorphous active film, UmOrphQUS si ! i _), An ohmic contact film 5 composed of n + amorphous, 屯 之 n + amorphous 矽. (g) The first patterned semiconductor active film 4 and the ohmic contact film 5 are subjected to a second port U?. In this case, in addition to the portion including the thin film transistor, the pattern of the source wiring 22 and the gate electrode 11 c formed by the later-described mounting is formed to be large and continuous. In this embodiment, use

2185-8937-PF 14 200811565 學氣相沈積咖）法，依序形成4QGnm厚之siN膜作為第】 :緣膜150nm厚之非晶矽膜作為半導體主動膜*、 厚且添加磷（P)作為不純物之^非晶石夕膜作為歐姆接觸膜 、…曾）之後藉由白知之使用氟系氣體的乾蝕刻法而蝕刻 半導體主動膜4與歐姆接_ 5。⑴之後，剝離光阻圖案， 並以純水洗>r。藉此，形成由半導體主動m 4及歐姆接觸 *、5所構成之半導體層23以作為半導體圖案。另外，第1 絕緣膜成為閘極絕緣膜3。在此種情況下，不純物也可以 在成膜後添加。 (C)第3微影製程 ⑴接著’形成透明導電膜u。⑴進行第3回之微影 製程而圖案化透明導電膜η。形成汲極電極llc、晝素電 極lla、與源極電極llb。而且，在此㈣中，也同時形 成用於在閘極配線21 #給信號之閘極端子襯墊、及用於 在祕㈣22供給㈣之源極端子㈣（㈣）。以本實施 。而。使用此合氧化銦（In2〇3)與氧化錫（Sn 膜作為透明導電膜U。藉由習知 尸 白知之使用Ar氣體的濺鍍法 而形成ιο〇ηω厚之透明導電膜u。⑴然後，使用習知之 包含鹽酸舆魏的溶液而進行濕㈣1此，形成㈣電 ，Uc、畫素電極11a、源極電極llb、閘極端子襯塾及源 極端子襯塾。而且，關於閑極端子襯塾、及源極端子襯墊 之構成’將於後敘述士)而且，使用習知之氟系氣體，對 源極電極m及沒極電们lc之間之歐姆接觸膜5進行乾 蝕刻。00接著，剝離光阻圖案，並以純水洗淨。藉此，形2185-8937-PF 14 200811565 vapor deposition method), sequentially forming a 4QGnm thick siN film as the first]: a 150 nm thick amorphous germanium film as a semiconductor active film*, thick and phosphorus (P) The amorphous magnetic film of the impurity is used as an ohmic contact film, and the semiconductor active film 4 and the ohmic junction are etched by dry etching using a fluorine-based gas. (1) Thereafter, the photoresist pattern was peeled off and washed with pure water > r. Thereby, the semiconductor layer 23 composed of the semiconductor active m 4 and the ohmic contacts *, 5 is formed as a semiconductor pattern. Further, the first insulating film serves as the gate insulating film 3. In this case, impurities may also be added after film formation. (C) Third lithography process (1) Next, a transparent conductive film u is formed. (1) The third lithography process is performed to pattern the transparent conductive film η. A drain electrode llc, a halogen electrode 11a, and a source electrode 11b are formed. Further, in the above (4), the gate terminal pad for the signal to be gated in the gate wiring 21 # and the source terminal (four) for the supply of (4) to the secret (four) 22 are simultaneously formed ((4)). Take this implementation. and. Indium oxide (In2〇3) and tin oxide (Sn film is used as the transparent conductive film U. The transparent conductive film u of ιο〇ηω thick is formed by a conventional sputtering method using Ar gas. (1) Then Wet (four) 1 is formed using a conventional solution containing guanidine hydrochloride, forming (four) electricity, Uc, pixel electrode 11a, source electrode 11b, gate terminal lining and source terminal lining. The composition of the lining and the source terminal pad is described later. Further, the ohmic contact film 5 between the source electrode m and the galvanic electrode lc is dry etched using a conventional fluorine-based gas. 00 Next, the photoresist pattern was peeled off and washed with pure water. By this shape

2185-8937-PF 200811565 成源極電極11 b、汲極電極11 c、畫素電極π a、tf T通道 部2 6、閘極端子襯墊、及源極端子襯墊。 在前述之内容中，以ΙΤ0膜作成透明導電膜u。在此 種情況下，也可以使用非晶質IT〇膜。另外，也可以使用 氧化錫膜、氧化銦膜、氧化鋅膜作為透明導電膜1 1。而且， 也可以使用由氧化銦與氧化鋅混合之ΙΖ〇膜、或氧化銦與 氧化錫與氧化鋅混合之I τζο膜。上述透明導電膜11係可 利用弱酸之草酸蝕刻。因此，於透明導電膜u之蝕刻時， 由於不會腐蝕其它配線及電極的緣故，故可以提升良率。 (D) 第4微影製程 ()接者為了形成層間絕緣膜8，而形成由s i N所組 成之第2絕緣膜成膜。以本實施形態而言，使用化學氣相 沈積（CVD)法而形成300nm厚之氮化矽（SiN)膜以作為第2 絕緣膜。（P)接著，進行第4回微影製程。（q)之後，使用 白知之氟系氣體進行乾蝕刻。（r)此時，在第2絕緣膜中， 形成貝通至源極電極！ lb表面之源極電極接觸洞2了。之 後’剝離光阻圖案，並以純水洗淨。藉此，形成具有源極 電極接觸洞27之層間絕緣膜8。 (E) 第5微影製程 (s)接著，形成第2金屬薄膜。以第2金屬薄膜而言， 係以M或A1合金者較佳。也可以使用Cr或Cr合金、Mo 或M 1以本實施形態而言，藉由習知之使用Ar氣體 的藏魏法而形4、〇 η Λ r- ^成20 0ηπι厚之AINi合金膜（在A1中添加2mol2185-8937-PF 200811565 Source electrode 11 b, drain electrode 11 c, pixel electrode π a, tf T channel portion 26, gate terminal pad, and source terminal pad. In the foregoing, the transparent conductive film u is formed of a ΙΤ0 film. In this case, an amorphous IT tantalum film can also be used. Further, a tin oxide film, an indium oxide film, or a zinc oxide film may be used as the transparent conductive film 11 . Further, a ruthenium film mixed with indium oxide and zinc oxide or an I τ ζ film in which indium oxide is mixed with tin oxide and zinc oxide may also be used. The above transparent conductive film 11 can be etched using a weak acid oxalic acid. Therefore, when etching the transparent conductive film u, since the other wirings and electrodes are not corroded, the yield can be improved. (D) The fourth lithography process () is formed by forming a second insulating film composed of s i N in order to form the interlayer insulating film 8. In the present embodiment, a 300 nm-thick tantalum nitride (SiN) film is formed by a chemical vapor deposition (CVD) method to serve as a second insulating film. (P) Next, the fourth lithography process is performed. After (q), dry etching was performed using a fluorine-based gas of Shichi. (r) At this time, a beton-to-source electrode is formed in the second insulating film! The source electrode of the lb surface contacts the hole 2. Thereafter, the photoresist pattern was peeled off and washed with pure water. Thereby, the interlayer insulating film 8 having the source electrode contact holes 27 is formed. (E) Fifth lithography process (s) Next, a second metal thin film is formed. In the case of the second metal thin film, it is preferred to use an alloy of M or Al. It is also possible to use Cr or a Cr alloy, Mo or M 1 in the present embodiment, by using a conventional Wei method of Ar gas, and forming an AINi alloy film of 20η Λ r-^ into a thickness of 20 ηππ (in Add 2mol to A1

之 Ni ) 0 2185-8937-PF 16 200811565 (t)接者，為了圖案化第2金屬薄臈，進行第5回微影 而且，使用習知之包含璘酸與硝酸的溶液而進行 “蝕刻。⑺之後，剝離光阻圖案，而圖案化第2金屬薄膜。 藉此’形成與源極配線22同層之導電膜19,盆中、 極配線22係藉由源極電極接觸洞27而與源 電、 性連接（參照圖5、 6)。也就^ ^ 也就疋魂，導電膜19係利用第 金屬溥膜而形成。而且，在此第5微影製程⑻中， :職端子襯塾圖案28與間極端子觀墊圖案29 (參照圖5、 具體而言’如圖5所示，藉由閘極端子部接觸洞31而 =間極配線21連接之閉極端子概塾圖案29係利用導電膜 J9而形成。而且，圖5你儉；田 ’、、、’日不用於在閘極配線21輸入作 號之閉極端子部之構成的剖面圖。而且，如圖6所示，； t源極端子部接觸洞32而與源極端子概塾18連接之源極 立而子襯塾圖荦2 8 #南丨田it命j 以拥 導電膜19而形成。而且，源極端 子襯墊圖案28係從源極配綠” 一、、泉22而延伸。圖6係繪示用於 在源極配線2 2輸入作缺夕、、店#山 、 ° 源極糕子部之構成的剖面圖。閘 °而°卜及源極端子部係配置於額緣區域112。 :圖5所不’閘極端子襯墊圖案29係藉由設於層間絕 緣膜8之接觸洞33而盥 ^ I m /、由透明V電膜11構成之閘極端子 概墊14連接。而且，閘 „ ^ ^ 閉極‘子襯墊圖案29係藉由設於層 間絶緣膜8與閘極絕緣膜 極配線連接（參照圖5 Γ 31而與間 )因此’閘極配線21與閘極端 子襯墊14係藉由閘極沪 而子襯墊圖案29而電性連接。而且， 源極^子襯塾圖案28與源極端子襯塾_由設於層間絕Ni) 0 2185-8937-PF 16 200811565 (t) In order to pattern the second metal thin layer, the fifth lithography is performed and "etching is performed using a conventional solution containing tannic acid and nitric acid. (7) Thereafter, the photoresist pattern is peeled off to pattern the second metal thin film. Thus, the conductive film 19 in the same layer as the source wiring 22 is formed, and the pot-and-pole wiring 22 is connected to the source by the source electrode contact hole 27. , sexual connection (refer to Figure 5, 6). In other words, ^ ^ is also the soul, the conductive film 19 is formed by the metal ruthenium film. Moreover, in the fifth lithography process (8), : the terminal lining pattern 28 and the intermediate terminal pad pattern 29 (see FIG. 5, specifically, as shown in FIG. 5, the closed terminal outline pattern 29 connected by the gate terminal contact hole 31 and the interpole wiring 21 is utilized. The conductive film J9 is formed. Moreover, FIG. 5 is a cross-sectional view of the structure in which the ', ', and ' days are not used to input the closed terminal portion of the gate wiring 21. Moreover, as shown in FIG. The source terminal contacts the hole 32 and is connected to the source terminal. The source is connected to the source and the sub-line is 塾2 8 #南丨田it life j The conductive film 19 is formed. Further, the source terminal pad pattern 28 extends from the source with green, and the spring 22. Figure 6 shows the input for the source wiring 2 2 for the eve, shop #山, ° A cross-sectional view of the composition of the source cake portion. The gate and the source terminal are arranged in the fore edge region 112. The non-gate terminal pad pattern 29 of Figure 5 is designed. The contact hole 33 of the interlayer insulating film 8 is connected to the gate terminal 14 formed of the transparent V film 11. Moreover, the gate „ ^ ^ closed-pole sub-pad pattern 29 is provided by The interlayer insulating film 8 is connected to the gate insulating film (refer to FIG. 5 and FIG. 31). Therefore, the gate wiring 21 and the gate terminal pad 14 are electrically connected by the gate pad pattern 29. Sexual connection. Moreover, the source lining pattern 28 and the source terminal lining _ are set between the layers

2185-8937-PF 17 200811565 種产二源子部接觸洞32而連帛（參照圖6)。在此 二：，間極信號、源極信號分別藉著由透明導電膜u ^子«而供給至閘極配線2卜源極配線&而 且’设於間極端+都 12、 rn^ 口 、汲極端子部之各接觸洞係在第4 被〜製私（D )中形成。 在習知技術中，在使用A彳 綠、π β + 使用A1膜或Α1合金膜作為源極配 、、！-源極電極及汲極電極 之障况下，則必須在A1膜或A1 合金膜之下層與上層分 . ⑴便用Cr或Mo等咼融點金屬。藉 匕’防止A1膜之a 1、盥歐妞妓奋 人姆接觸膑之Si之間的相互擴散， 而可以仔到良好接觸特性。 仁 如丽所述，必須堆疊A1 、或A1 ,金膜’而有製造工數增加的問題。 根據本發明的話，藉由 g由在旦素電極lla使用之透明導 尾膜11 (例如，Τ τπ赠、r rr/、、 、 形成源極電極11 b與汲極電極 c。因此，在歐姆接觸膜5、與源極配線⑷Ni)22之 夾置透明導雷膜n 餘lL 曰 電膜11猎此，不需堆疊A1膜。結果，不需 曰加因上述之積層而多出 伽c . 之I垃工數，即可以防止因為A1 ” 1之相互擴散所引起之電性接觸特性的劣化。 另外’在習知技術中，由 ^ ΤΤΛ ^ Τ由於疋以Α1或A1合金膜（下 曰、IT0膜（上層）之順序而直接積#之禮、& 且设積增之構造的緣故，所以 有所明在接觸部產生Α1〇χ的問 J 1J ^ 在本發明中，1T0膜為 曰，A1或A1合金為上層。杜果 之電性接觸特性。 -果了以大幅改善Μ與IT。 σ電性接觸的情況下’會有驗性顯影液中之IT0發2185-8937-PF 17 200811565 The two-source sub-portion contact hole 32 is produced and connected (see Fig. 6). Here, the inter-polar signal and the source signal are respectively supplied to the gate wiring 2 and the source wiring & by the transparent conductive film u ^ sub«, and are set at the extremes + 12, rn^, Each contact hole of the 汲 extreme part is formed in the fourth 制 制 私 (D). In the prior art, an A1 film or a Α1 alloy film is used as a source with A 彳 green, π β + , and! - Under the condition of the source electrode and the drain electrode, it must be separated from the upper layer of the A1 film or the A1 alloy film. (1) The metal is melted with Cr or Mo. By 匕 'preventing the A1 film a 1 , 盥 妓 妓 妓 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人As stated by Ren Ruli, it is necessary to stack A1, or A1, gold film, and there is a problem that the number of manufacturing increases. According to the present invention, the transparent tail film 11 is used by the d-electrode electrode 11a (for example, Ττπ, r rr / , , , and the source electrode 11 b and the drain electrode c are formed. Therefore, in ohm The contact film 5 and the source wiring (4) Ni) 22 are sandwiched by a transparent lightning-guide film, and the remaining layer of the film is not required to be stacked. As a result, it is possible to prevent the deterioration of the electrical contact characteristics caused by the mutual diffusion of A1 "1" without adding the I-work number of the galvanic layer due to the above-mentioned laminate. Further, in the prior art, Since ^ ΤΤΛ ^ Τ is directly formed by the Α1 or A1 alloy film (the lower 曰, the IT0 film (upper layer)), and the structure is increased, it is known that it is produced at the contact portion. In the present invention, the 1T0 film is ruthenium, and the A1 or A1 alloy is the upper layer. The electrical contact characteristics of Duguo. - The result is a substantial improvement in Μ and IT. σ electrical contact. 'There will be IT0 hair in the developer solution

2185-8937-PF 18 200811565 生還原腐钱之虞。結果，較佳者係 族元素(Ni、Co、Fe等)之j 3 σ』表第8 八m A 禋以上之金屬的A1合全、七 含乳⑻^膜或A1合金膜盃包 1種以上之金屬的Μ合金中、.㈠周期表第8族元素之 、中蚪、加鼠的A1合金膜。 可以提供能解決此問題且良率古 精此， ^良羊呵之溥膜電晶體陣列基板。 另夕卜’在本實施形態中，在源極配線22、晝素 專透明導電膜11之間設置層間絕緣膜8。藉此，例如，特 §午文獻3所揭示之源極電極、沒極電極、源極配Μ” 善因為與畫素電極形成在同一層時而產生之源極配線Μ 與透明導電膜Π之電性短路或點燈不良的問題。 如上所述，記載著利用透明導電膜11而形成閘極端子 襯塾圖案29。但是，在不需要透明導電膜η的情況下， 如圖7所示，可以將閘極端子襯墊14與第丨金屬薄膜同時 形成。而且，如圖8所示，利用源極配線22與同層之導電 膜1 9也可以形成源極端子襯墊1 8。 實施形態2. 接著’使用圖9及圖1 0說明本發明之實施形態2之顯 示裝置用薄膜電晶體陣列基板之構成。圖9係綠示實施形 悲2之液晶顯示裝置用薄膜電晶體陣列基板。圖1 〇係纷示 圖9之Y-Y’部之剖面圖。 在本實施形態中，除了實施形態1所示之構成，還設 置晝素反射電極25。而且’關於晝素反射電極25以外之 構成’由於與實施形態1相同的緣故，因此省略說明。以 下敘述構成之相異點。 2185-8937-PF 19 200811565 首先以覆蓋透明導電膜11的方式，疊積具有源極電 極接觸洞27及晝素接觸洞24之層間絕緣膜8。在層間絕 緣膜8上設置源極配線22及晝素反射電極25。晝素電極 lla係藉由晝素接觸洞24而與晝素反射電極25連接。 如此一來，實施形態2也使用實施形態1之（E)中形成 之第2金屬薄膜作為畫素反射電極25。換句話說，晝素反 射電極25係藉由源極配線22與同層 貫施形態2提供具有晝素反射電極25 裝置。 之導電膜19而形成。 之半透過型液晶顯示 也就疋"兒未形成畫素電極11a之晝素反射電極2 5的 部分成為透過部’而設有晝素反射電極25之部分成為反射 部。如此-來，藉由形成畫素反射電極25，可以形成在1 旦素内具有透過部與反射部的半透過型液晶顯示裝置。 在本實施形態2之製造步驟中，使用圖4進㈣明。 在本貫施形態2中，於實施形態1所示之製造步驟之外， v成i素反射電極25及晝素接觸洞24。而且 之形成步驟料，省略舆實施形態丨同樣之說明。 (D) 弟4微影製程 在圖4之⑻所示之步驟中，除了以下之點 施形態1相同。也就是說，在本實施形態2中， ^ 中於汲極電極He形成貫通至伸 晝素電極Ua表面的晝素接觸洞24。 (E) 弟5微影製程 在圖4之⑴所示之步驟中’除了以下之點，其餘與實2185-8937-PF 18 200811565 The birth of the rot. As a result, it is preferable that the group of the group elements (Ni, Co, Fe, etc.) has a total of A1, a seven-milk (8) film or an A1 alloy film cup of the metal above the 8th 8 m A 表 table. Among the above-mentioned bismuth alloys of metals, (a) elements of Group 8 of the periodic table, middle bismuth, and A1 alloy film of rat. Can provide this can solve this problem and the rate of ancient fine this, ^ Liang Yang 溥 溥 film transistor array substrate. In the present embodiment, the interlayer insulating film 8 is provided between the source wiring 22 and the halogen transparent conductive film 11. Therefore, for example, the source electrode, the electrodeless electrode, and the source electrode disclosed in the Japanese Patent Publication No. 3 are good because the source wiring Μ and the transparent conductive film are formed when the pixel electrode is formed in the same layer. The problem of electrical short circuit or defective lighting is as described above. It is described that the gate electrode lining pattern 29 is formed by the transparent conductive film 11. However, in the case where the transparent conductive film η is not required, as shown in FIG. The gate terminal pad 14 can be formed simultaneously with the second metal film. Further, as shown in FIG. 8, the source terminal pad 18 can be formed by the source wiring 22 and the same layer of the conductive film 19. 2. Next, the configuration of the thin film transistor array substrate for a display device according to the second embodiment of the present invention will be described with reference to Fig. 9 and Fig. 10. Fig. 9 is a thin film transistor array substrate for a liquid crystal display device of the second embodiment. Fig. 1 is a cross-sectional view showing a portion Y-Y' of Fig. 9. In the present embodiment, in addition to the configuration shown in the first embodiment, a halogen reflective electrode 25 is provided. The configuration 'is the same as in the first embodiment For the sake of explanation, the description will be omitted. The difference between the constituents will be described below. 2185-8937-PF 19 200811565 First, an interlayer insulating film having a source electrode contact hole 27 and a halogen contact hole 24 is laminated so as to cover the transparent conductive film 11. 8. The source wiring 22 and the halogen reflection electrode 25 are provided on the interlayer insulating film 8. The halogen electrode 11a is connected to the halogen reflection electrode 25 by the halogen contact hole 24. Thus, the second embodiment is also used. The second metal thin film formed in the first embodiment (E) is used as the pixel reflective electrode 25. In other words, the halogen reflective electrode 25 is provided with the halogen reflective electrode by the source wiring 22 and the same layer forming form 2. The device is formed by the conductive film 19. The semi-transmissive liquid crystal display is also provided with a pixel reflective electrode 25 in which a portion of the elementary reflection electrode 25 of the pixel electrode 11a is not formed as a transmissive portion. In the manufacturing process of the second embodiment, a semi-transmissive liquid crystal display device having a transmissive portion and a reflecting portion in a single denier can be formed by forming the pixel reflective electrode 25. Figure 4 In the present embodiment 2, in addition to the manufacturing steps shown in the first embodiment, v is the i-ray reflective electrode 25 and the halogen contact hole 24. Further, the steps are formed, and the same embodiment is omitted. (D) The fourth lithography process is the same as that of the first embodiment in the step shown in (8) of Fig. 4, that is, in the second embodiment, the gate electrode He is formed to penetrate to The alizarin contact hole 24 on the surface of the extensor electrode Ua. (E) The lithography process of the 5th lithography process is shown in the step shown in (1) of Fig. 4 except for the following points.

2185-8937-PF 20 200811565 施形態i相同。也就是說，於第2金屬薄膜之圖案形成時， 形成晝素反射電極25。另外，以藉由晝素接觸洞24而與 汲極電極llc及晝素電㉟lla電性連接的方式而形成畫素 反射電極2 5。藉此，完成音始取0 凡成貝施形悲2之液晶顯示用薄膜電 晶體陣列基板。 乂本只施开v恶之第2金屬薄膜而言，較佳者係使用電 性比電阻低、且與透明導電m U之電性接觸特性及反射 特性良好的AINi。A1Nl以在A1令添力口 2m〇1%之Ni的材 料為佳。 f施形熊 在本實施形態中，與實施形態2相異之點係在第2金 屬薄膜中使用Ag或Ag合金。因此，關於與實施形態2共 通之内容則省略說明。藉由在帛2金屬薄膜中使用竑或2185-8937-PF 20 200811565 The form i is the same. That is, when the pattern of the second metal thin film is formed, the halogen reflective electrode 25 is formed. Further, the pixel reflective electrode 25 is formed so as to be electrically connected to the drain electrode 11c and the halogen electrode 3511a by the halogen contact hole 24. Thereby, the completion of the sound is taken from 0 to the film-forming transistor array substrate for liquid crystal display. In the case of the second metal thin film in which only V is used, it is preferable to use an AINi having a low electrical specific resistance and good electrical contact characteristics and reflection characteristics with the transparent conductive m U . A1Nl is preferably a material having a Ni of 2m 〇 1% in A1. f Stereo Bear In the present embodiment, the point different from the second embodiment is that Ag or an Ag alloy is used for the second metal thin film. Therefore, the description of the contents common to the second embodiment will be omitted. By using 竑 or in the 帛2 metal film

Ag合金，可以提供低電阻且反射特性優異、光學特性與電 性特性優異之半透過型液晶顯示用的薄膜電晶體陣列基 板。 特許文獻1記載著在源極配線22等使用Ag膜。但是， 接觸洞形成之際，由於乾蝕刻時利用電漿而導致Ag會受損 而有消失的問題點。因此，在習知之TFT構造中難以使用The Ag alloy can provide a thin film transistor array substrate for a transflective liquid crystal display which has low resistance and excellent reflection characteristics and is excellent in optical characteristics and electrical characteristics. Patent Document 1 describes that an Ag film is used for the source wiring 22 and the like. However, when the contact hole is formed, the use of the plasma during dry etching causes the Ag to be damaged and the problem of disappearance. Therefore, it is difficult to use in conventional TFT construction.

Ag及Ag合金。但是，在本發明中，源極配線22係在接觸 洞形成後成膜。因此，位於上層之源極配線係不會遭受由 乾餘刻引起之電漿損害（damage)，而可以防止電性特性之 劣化。 另外’在於第2金屬薄膜使用Ag合金的情況下，較佳Ag and Ag alloys. However, in the present invention, the source wiring 22 is formed after the contact hole is formed. Therefore, the source wiring line located in the upper layer does not suffer from the plasma damage caused by the dry residue, and the deterioration of the electrical characteristics can be prevented. Further, in the case where the second metal thin film is made of an Ag alloy, it is preferably

2185-8937-PF 21 200811565 者係使其具有 Pd、Cu、Mo、Nd、Ru、Ge、Au 及 SnOx 之 1 種以上。藉此，可以得到密著性優、且低電阻之源極配線。 另外，可以形成密著性及反射特性優之晝素反射電極。 實施形態允 在本實施形態中，與實施形態1相異之點係在第2金 屬薄膜中使用Cu或Cu合金。因此，關於與實施形態1共 通之内容則省略說明。藉由在第2金屬薄膜中使用電阻較 A1低之Cu或Cu合金，可以提供高精細且大晝面之薄膜電 晶體陣列基板。另外，一旦使用在Cu添加Mo之CuMo合金 膜的話’則可以形成密著性優、且低電阻之源極配線。 在習知技術中，由於難以控制將Cu或Cu合金形成厚 膜之際之蝕刻的緣故，因此配線之兩側之剖面形狀變差， 而難以在Cu膜之上層形成晝素電極等電性元件。在本發明 中’將第2金屬薄膜形成於薄膜電晶體陣列基板之最上 層。藉此，剖面形狀不會對良率造成影響。 實施形態1〜4之透明導電膜11係作為源極電極7、 汲極電極6、閘極端子槻墊圖案及源極端子襯墊圖案使用。 而且，在實施形態1〜4之構成中，源極配線22即使作成 單層’也可以&供顯示品質高、生產性高之顯示裝置。 而且’也可以在源極配線22之下層形成與源極配線 22電性連接之透明導電膜丨丨。例如，也可以在源極配線 22下隔著層間絕緣膜8而形成與源極配線22幾乎同樣形 狀之透日月v電膜11。在此種情況下，必須於源極配線2 2 下之層間絕緣膜8形成無數之接觸洞，並與源極配線22.及2185-8937-PF 21 200811565 It is one or more types of Pd, Cu, Mo, Nd, Ru, Ge, Au, and SnOx. Thereby, a source wiring having excellent adhesion and low resistance can be obtained. Further, a halogen reflective electrode excellent in adhesion and reflection characteristics can be formed. (Embodiment) In the present embodiment, a point different from that of the first embodiment is the use of Cu or a Cu alloy in the second metal thin film. Therefore, the description of the contents common to the first embodiment will be omitted. By using a Cu or Cu alloy having a lower electric resistance than A1 in the second metal thin film, it is possible to provide a high-definition and large-faced thin film transistor array substrate. Further, when a CuMo alloy film in which Mo is added to Cu is used, a source wiring having excellent adhesion and low resistance can be formed. In the prior art, since it is difficult to control etching when Cu or a Cu alloy is formed into a thick film, the cross-sectional shape of both sides of the wiring is deteriorated, and it is difficult to form an electric element such as a halogen electrode in the upper layer of the Cu film. . In the present invention, the second metal thin film is formed on the uppermost layer of the thin film transistor array substrate. Thereby, the cross-sectional shape does not affect the yield. The transparent conductive film 11 of the first to fourth embodiments is used as the source electrode 7, the drain electrode 6, the gate terminal pad pattern, and the source terminal pad pattern. Further, in the configuration of the first to fourth embodiments, the source wiring 22 can be made of a single layer, and a display device having high display quality and high productivity can be provided. Further, a transparent conductive film 电 electrically connected to the source wiring 22 may be formed under the source wiring 22. For example, the permeable solar cell film 11 having almost the same shape as the source wiring 22 may be formed under the source wiring 22 via the interlayer insulating film 8. In this case, the interlayer insulating film 8 under the source wiring 2 2 must form an infinite number of contact holes, and the source wiring 22 and

2185-8937-PF 22 2008115652185-8937-PF 22 200811565

透明導電膜11連接。扁，士，湄扰：A 搔在此源極配線22與源極配線22之 下層之透明導電臈1 1係以相同 N見度而平仃形成。也就是 說，源極配線22與源極配線22之下層之透明導電膜⑴系 作成相同圖案形狀。因此，在第3微影製程⑹中於形成透 明導電膜11之際，沪菩π詈、、馬扠ώ 化者3又置源極配線22之方向形成透 導電膜11。 ”另夕卜，以與源極配、線22同樣之形狀的方式而除去層間 、、’巴緣膜8 ’並將源極配線22之一部份或全部作成源極配線 22(上層）與透明導電膜u(下層）之積層構造也可以。在此 種情況下’即使源極配線22斷線’也因為在該斷線部之下 層形成透明導電膜的緣故，因此得到冗長配線之效果，而 且可以提供高良率之薄膜電晶體陣列基板。 【圖式簡單說明】 [圖1 ]本發明之實施形態之薄膜電晶體陣列基板之構 成的平面圖。 [圖2]本發明之實施形態丨之薄膜電晶體陣列基板之 畫素構成的平面圖。 [圖3]本發明之實施形態丨之薄膜電晶體陣列基板之 晝素構成的剖面圖。 [圖4 ](A )〜（E)本發明之貫施形態1之薄膜電晶體陣列 基板之製造步驟的流程圖。 [圖5 ]本發明之實施形態丨之閘極端子部之構成的剖The transparent conductive film 11 is connected. The flat conductive traces of the lower layer of the source wiring 22 and the source wiring 22 are formed flat by the same N-degree. That is, the source wiring 22 and the transparent conductive film (1) under the source wiring 22 are formed in the same pattern shape. Therefore, in the third lithography process (6), when the transparent conductive film 11 is formed, the transparent conductive film 11 is formed in the direction in which the source wiring 22 is placed in the puddle. Further, in the same manner as the source and line 22, the interlayer, the 'bar film 8', and a part or all of the source wiring 22 are formed as the source wiring 22 (upper layer) and The laminated structure of the transparent conductive film u (lower layer) may be used. In this case, even if the source wiring 22 is broken, a transparent conductive film is formed under the broken portion, so that the effect of redundant wiring is obtained. Further, a high-yield thin film transistor array substrate can be provided. [Schematic Description] [Fig. 1] A plan view showing a configuration of a thin film transistor array substrate according to an embodiment of the present invention. [Fig. 2] Fig. 3 is a cross-sectional view showing the structure of a thin film transistor array substrate according to an embodiment of the present invention. [Fig. 4] (A) to (E) Flowchart of the manufacturing process of the thin film transistor array substrate of the first embodiment. [Fig. 5] Fig. 5 is a cross-sectional view showing the configuration of the gate terminal of the embodiment of the present invention

2185-8937-PF 23 200811565 [圖6 ]本發明之實施形態1之閘極端子部之構成的剖 面圖。 [圖7 ]本發明之實施形態1之其它閘極端子部之構成 的剖面圖。 [圖8 ]本發明之實施形態1之其它源極端子部之構成 的剖面圖。 [圖9]本發明之實施形態2之薄膜電晶體陣列基板之 構成的平面圖。 [圖10]本發明之實施形態2之薄膜電晶體陣列基板之 構成的剖面圖。 [圖11]習知之液晶顯示裝置用薄膜電晶體陣列基板之 構成的平面圖。 [=12]習知之薄膜電晶體陣列基板之構成的剖面圖。 S 3 ]白知之液晶顯示裝置用薄膜電晶體陣列基板之 閘極端子部的剖面圖。 * 4 ]白知之液晶顯示裝置用薄膜電晶體陣列基板之 源極端子部的剖面圖。 【主要元件符號說明】 1 閘極電極、 2 、、 補助谷量電極、 g 閘極絕緣膜、 4 半導體主動膜、 5 歐姆接觸膜、 2185-8937-Pp 24 200811565 6 >及極電極、 7 源極電極、 8 層間絕緣膜、 9 晝素接觸洞、 10 具有補助容量之部分 11 透明導電膜、 11a 晝素電極、 lib 源極電極、 11c 沒極電極、 14 閘極端子襯墊、 18 源極端子襯墊、 19 導電膜、 20 補助容量配線、 21 閘極配線、 22 源極配線、 23 半導體層、 24 晝素接觸洞、 25 晝素反射電極、 26 TFT通道部、 27 源極電極接觸洞、 28 源極端子概墊圖案、 29 閘極端子襯墊圖案、 31 閘極端子部接觸洞、 32 源極端子部接觸洞、 252185-8937-PF 23 200811565 Fig. 6 is a cross-sectional view showing the configuration of a gate terminal portion according to the first embodiment of the present invention. Fig. 7 is a cross-sectional view showing the configuration of another gate terminal portion according to the first embodiment of the present invention. Fig. 8 is a cross-sectional view showing the configuration of another source terminal portion according to the first embodiment of the present invention. Fig. 9 is a plan view showing the configuration of a thin film transistor array substrate according to a second embodiment of the present invention. Fig. 10 is a cross-sectional view showing the configuration of a thin film transistor array substrate according to a second embodiment of the present invention. Fig. 11 is a plan view showing the configuration of a conventional thin film transistor array substrate for a liquid crystal display device. [=12] A cross-sectional view showing the structure of a conventional thin film transistor array substrate. S 3 ] A cross-sectional view of a gate terminal portion of a thin film transistor array substrate for a liquid crystal display device. * 4 ] A cross-sectional view of the source terminal portion of the thin film transistor array substrate for a liquid crystal display device. [Description of main component symbols] 1 gate electrode, 2, auxiliary grid electrode, g gate insulating film, 4 semiconductor active film, 5 ohm contact film, 2185-8937-Pp 24 200811565 6 > and pole electrode, 7 Source electrode, 8 interlayer insulating film, 9 halogen contact hole, 10 part with auxiliary capacity 11 transparent conductive film, 11a halogen electrode, lib source electrode, 11c electrodeless electrode, 14 gate terminal pad, 18 source Extreme Substrate, 19 Conductive Film, 20 Supplemental Capacity Wiring, 21 Gate Wiring, 22 Source Wiring, 23 Semiconductor Layer, 24 Alizarin Contact Hole, 25 Alizarin Reflective Electrode, 26 TFT Channel Section, 27 Source Electrode Contact Hole, 28 source terminal pad pattern, 29 gate terminal pad pattern, 31 gate terminal contact hole, 32 source terminal contact hole, 25

2185-8937-PF 200811565 110 基板、 111 顯示區域、 112 額緣區域、 115 掃目苗信號驅動電路、 116 顯示信號驅動電路、 117 晝素、 118 外部配線、 119 外部配線、2185-8937-PF 200811565 110 Substrate, 111 display area, 112 front edge area, 115 Wiggle signal drive circuit, 116 display signal drive circuit, 117 、, 118 external wiring, 119 external wiring,

120 TFT 26120 TFT 26

2185-8937-PF2185-8937-PF

Claims (1)

200811565 十、申請專利範圍·· 1 · 一種薄膜電晶體陣列基板，包括： 閘極電極，設置於基板上； 閘極絕緣膜，形成於該閘極電極之上； 半導體層，形成於該閘極絕緣膜上，且配置於該閘極 電極之對面； 源極電極及汲極電極，由形成於該半導體層之上的透 明導電膜組成； 晝素電極，自該汲極電極延伸，由該透明導電膜組成； 層間絕緣膜，形成於該晝素電極、該源極電極、及該 汲極電極之上，具有到達該源極電極之接觸洞；以及 源極配線，形成於該層間絕緣膜之上，且隔著該接觸 洞而與該源極電極連接。 2·如申μ專利範圍第丨項所述之薄膜電晶體陣列基 板’其中該源極配線包含Α丨、Ag或Cu。 3 ·如申明專利範圍第丨或2項所述之薄膜電晶體陣列 基板其中5玄透明導電膜係在該源極配線之下層沿著設有 该源極配線之方向而形成，且形成於該源極配線之下層的 忒透明導電膜係與該源極配線電性連接。 4·如申請專利範圍第丨或2項所述之薄膜電晶體陣列 基板其中與該閘極電極連接之閘極配線係隔著閘極端子 口P接觸洞而連接由與該源極配線同層之導電膜所構 子襯墊圖案·， 而 "亥透明導電膜隔著該接觸洞而與該端子襯墊圖案連 2185-8937-PF 27 200811565 接； 接 該閘極配線與該透明導電膜隔著該端子襯塾圖案而連 杯申請專利範圍第3項所述之薄膜電晶體陣列基 中與該閉極電極連接之閉極配線 : 襯塾圖案；^原極配線同層之導電膜所構成的端子 接；/透月¥ f膜隔著該接觸洞而與該端子襯墊圖案連 該間極配線每·读gg憎雨 _ 接。 ¥電膑隔著該端子襯墊圖案而連 6. —種顯示裝置，具有如申請專利範圍第！或2項所 述之薄膜電晶體陣列基板。 β 、斤 7. -種顯示裝置，具有如申請專利範圍 薄膜電晶體陣列基板。 、斤义之 8· —種薄膜電晶體陣列基板之製造方法，包括·· 在基板上形成閘極電極的步驟； 在該閘極電極上形成閘極絕緣膜的步驟，· 在該閘極絕緣膜上以配置於該閘極電極之對面的 而形成半導體層的步驟； 在該半導體層上形成由透明導電膜所構成之源極電 極、汲極電極、及自該汲極電極延伸之畫素電極的步驟； 2層間絕緣膜的步驟，其中該層間絕緣膜係形成於 忒旦素電極、該源極電極、及該汲極電極上，I具有到達 2185-893 7-PF 28 200811565 該源極電極之接觸洞；以及 洞而形成與該源極電 在該層間絕緣膜之上隔著該接觸 極連接之源極配線的步驟。 9 ·如申明專利範圍第8項所述之薄膜電晶體陣列基 板之製造方法’其中該源極配線包含Al、Ag或Cu。 申明專利範圍第8或9項所述之薄膜電晶體陣 列土板之製迨方法，其中在形成該源極電極、汲極電極、 及畫素電極的步驟中，、沿著設置該源極配線之方向而在該 源極配線之下；形；、 曰I成该透明導電膜，且形成於該源極配線 之下層的4透明導電膜與該源極配線電性連接。 2185-893 7-PF 29200811565 X. Patent Application Scope 1 · A thin film transistor array substrate comprising: a gate electrode disposed on the substrate; a gate insulating film formed on the gate electrode; a semiconductor layer formed on the gate The insulating film is disposed opposite to the gate electrode; the source electrode and the drain electrode are composed of a transparent conductive film formed on the semiconductor layer; the halogen electrode extends from the drain electrode, and the transparent a conductive film composition; an interlayer insulating film formed on the halogen electrode, the source electrode, and the drain electrode, having a contact hole reaching the source electrode; and a source wiring formed on the interlayer insulating film And connected to the source electrode via the contact hole. 2. The thin film transistor array substrate as described in claim 5, wherein the source wiring comprises germanium, Ag or Cu. 3. The thin film transistor array substrate according to claim 2 or 2, wherein a 5" transparent conductive film is formed under the source wiring layer along a direction in which the source wiring is provided, and is formed in the The tantalum transparent conductive film under the source wiring is electrically connected to the source wiring. 4. The thin film transistor array substrate according to claim 2 or 2, wherein the gate wiring connected to the gate electrode is connected to the gate wiring via the gate terminal P and is connected to the source wiring. The conductive film is patterned by a conductive film, and the transparent conductive film is connected to the terminal pad pattern 2185-8937-PF 27 200811565 via the contact hole; the gate wiring and the transparent conductive film are connected The closed-electrode wiring connected to the closed-electrode electrode in the thin-film transistor array base according to the third aspect of the invention is connected to the terminal lining pattern: a lining pattern; a conductive film of the same layer of the original wiring The formed terminal is connected; the through-hole ¥f film is connected to the terminal pad pattern via the contact hole, and the inter-pole wiring is connected to the gg. The electric cymbal is connected to the terminal pad pattern and has a display device as described in the patent application scope! Or 2 of the thin film transistor array substrates described. , 斤 7. A display device having a thin film transistor array substrate as claimed in the patent application. , a method for manufacturing a thin film transistor array substrate, comprising: a step of forming a gate electrode on a substrate; a step of forming a gate insulating film on the gate electrode, · insulating the gate a step of forming a semiconductor layer on the opposite side of the gate electrode; forming a source electrode composed of a transparent conductive film, a drain electrode, and a pixel extending from the gate electrode a step of an electrode; a step of insulating the interlayer film, wherein the interlayer insulating film is formed on the ruthenium electrode, the source electrode, and the drain electrode, and I has reached the source of 2185-893 7-PF 28 200811565 a contact hole of the electrode; and a hole forming a source wiring electrically connected to the source via the contact electrode via the contact electrode. 9. The method of manufacturing a thin film transistor array substrate according to claim 8, wherein the source wiring comprises Al, Ag or Cu. The method for manufacturing a thin film transistor array earth plate according to the above aspect of the invention, wherein in the step of forming the source electrode, the drain electrode, and the pixel electrode, the source wiring is disposed along the source wiring The direction is below the source wiring; the shape; 曰I is the transparent conductive film, and the 4 transparent conductive film formed under the source wiring is electrically connected to the source wiring. 2185-893 7-PF 29