200810365 九、發明說明： 【發明所屬之技術領域】 本發明係有關於鎖相迴路之技術’尤指調整鎖相迴路 之振盪器的方法與相關之頻率合成器。 【先前技術】 對許多通訊裝置（例如行動電話）而言，多通訊模式 (Multi-Mode) /多頻段（Multi-Band)的應用愈來愈受到 重視。在這類的應用中，行動通訊裝置通常係使用頻率調 整範圍較廣的頻率合成器（frequency synthesizer )來提供 所需的時脈訊號。 頻率合成器一般係以鎖相迴路（phase-locked loop, PLL)的架構來實現。為滿足行動通訊標準中對於相位雜 訊的嚴格要求，頻率合成器之鎖相迴路中的振盪器增益應 、准持在較低的水平。為達到這樣的目的，頻率合成器中的 振鹽^器夕半係利用切換電容式壓控振盪器（switched ca_ pacitor VCO)來實現，以提升頻率合成器的頻率調整範圍。 眾所週知’鎖相迴路的鎖定速度對頻率合成器的整體 月匕有彳艮大影響。因此，如何有效提升使用切換電容式振 盟為架構之鎖相迴路的鎖定速度，實係有待解決的問題。 200810365 【發明内容] =鑑於此，切日把目的之—在於提 叫相關之頻率合成器，以解決上述問題。 本說明書提佴τ 、亡人 " /、了種頻率合成器之實施例，其包含 鎖相迴路，具有—振n —切換單元，用以將該 置，路狀態或_路狀態’·以及一設定带 ’用來於_相迴路處於開迴路 _ 脈與該振盪哭所鈐 伋猓參考蚪 其中當該鎖相迴路處於開迴路狀態時，該 員^ 號係實質上固定。 派盈抑之&制訊 有.2r、f另提供了—種頻率合成器之實施例，其包含 σ。/目迴路’其包含有用來產生一振盪訊號之-振盪 :二第=對：振盪訊號進行除頻以產生-第-除頻訊號 曼Η、/于置；一切換單元，用以將該鎖相迴路切換 路^日士狀態或閉迴路狀態’其中當該鎖相迴路處於開迴 Μ ’该振盤器之控制訊號係實質上固定；一第二除 ’早几’用來對-參考時脈進行除頻，以產生一第一除頻 #。數用於該鎖相迴路處於開迴路狀態時，依 ^弟、弟二除頻訊號進行計數，以產生一計數值；一 來，該計數值與一預定值，以產生一比較結 决定皁元，用來依據該比較結果，調整該振盪 200810365 器之頻率。 '本說明書另提供了-種調整鎖相迴路中之振蓋器的方 法’其包含有：將該鎖相迴路切換 ㈣器之嫩號維持固定;當該鎖相迴路處於開迴= 心日守依據-參考日禮與該振盡器所輸出之—振盡訊號調 整邊振盪ϋ之頻率；當該㈣器之頻率達到—預設目標 後’將該鎖相迴路切換至閉迴路狀態；以及當該鎖相迴路 處於閉迴路狀態時，依據該參考時脈與該振盪訊號來調整 該振盪器之控制訊號。 【實施方式】 請參考第1圖，其所繪示為本發明第一實施例之頻率 合成為100簡化後之方塊圖。頻率合成器1〇〇包含有鎖相 迴路（PLL) 102、設定裝置1〇4以及切換單元1〇6。本實 施例之鎖相迴路102包含檢測器110，用來檢測參考時脈 Sref與除頻訊號Sf之頻率差及/或相位差；電荷泵（比打狀 pump) 120’用來依據檢測器no的檢測結果產生控制電 流’迴路濾、波為（loop filter) 130，用來依據該控制電流產 生控制訊號Vc ;振盪器（osciiiator) 14〇，用來依據控制 訊號Vc產生振盪訊號Sosc ;以及除頻裝置15〇，用來對振 盪訊號Sosc進行除頻，以產生除頻訊號Sf。實作上，檢測 器 110 可用相頻檢測器（phase frequency detector，PFD)來 7 200810365 實現，迴路濾波器130可以是各種主動式濾波器或被動式 濾波器，而振盪器140則可用切換電容式壓控振盘器 (switched capacitor VCO )來實現0 在頻率合成器100中，設定裝 你用來調整振盪 器140的振盪頻率，而切換單元106則係用以將鎖相迴路 102切換至開迴路狀態（〇peni〇〇pstatus)或閉迴路狀熊 (loop Status )。鎖相迴路丨〇2中之振盪器14〇的調^、校 過程可分成兩個模式’分別是粗略調整模式（c〇_ Z)與微調模式（fine tuning m〇de )。在袓略調整模式中， 會將鎖相迴路⑽切換至開趣路狀態，而在 以Γ單元1%則會將鎖相迴—切換至閉 的調整;式。將搭配第2圖來進-步說明振!器140 ^ ^ ΙΓ-Γί ^ 102 ^ 140 兹分述如下 糊2。°。流程圖2。〇所包含之步驟 v -驟210中，切換單元⑽會將 態，並致使振蓋器14。的輪入IS102切換 在進人粗略調整模式。如第1圖所〒:制訊號維持 在本貫施例中係一相迴路：:：單元⑽ 濾波器130與 8 200810365 振盤态140之間。當切換一 號切換至實質上㈣之1G6將振盪器14G之控制訊 形成開迴路狀態。請注：·考電壓Vref時，鎖相迴路102會 切換單元⑽之實際設;方^僅係為—實施例，而非限制 例如，弟3圖所纟會示1 眘#加.^ , 丁马切換單元106之設置方式的另 一貫施例。如第3圖所示 .θ ^ ^ _ /、’本實施例中之迴路滤波器130 係為具有運算放大器-電 氣容（OP-RC)架構之濾波器 (OP-RC fUter)，而切換 ^ 、早凡106則係耦接於迴路濾波器 130之運算放大器的輪 省 / 而與輪出端之間。當切換單元106 導通（turn on)且電荷泵〗 σσ 20被禁能（disable)時，迴路濾波 器130所輸出之控制訊號v 化Vc即會等於實質上固定之參考電 壓Vref，這等效於使鎖相询 子目设路102變成開迴路狀悲。 當鎖相迴路102處於開迴路狀態時，設定裝置1〇4會 依據參考時脈Sref與振盪器M〇依據參考電壓Vref所產生 之振盪訊號Sosc，來調整振盪器140之頻率/頻段（步驟 220)。 如第1圖所示，本實施例之設定裝置1〇4包含比較裝 置170以及決定單元180。比較裝置170係用來對振盪訊 號Sosc與參考時脈進行比較，而決定單元18〇則會依 據比較裝置170的比較結果，決定如何調整振盡器140之 9 200810365 頻率。例如’比較裝f 170可比較振盡訊號W與參考日士 脈Sref兩者的頻率高低’並輸出—比較結果，而決定單： ⑽則可㈣該比較結絲難振14㈣解，凡 到對振盪器140進行粗略調整的目的。 比較裝置170之第-實施例的方塊圖係如第4圖所检 ;示。本實施例之比較裝置17。包含兩除頻裝^ 41。及伽曰、 計數器430以及比較器44〇。除頻裝置41〇係用來對振堡 訊號S〇SCit行除頻，以產生—第—除頻訊號刚，而 裝置貝'1會對參考時脈Sref進行除頻，卩產生一第二除 頻訊號FD2。計數器43〇會依據第一除頻訊號阳！與= 除頻訊號助進行計數’而比較器440則會對計數器43〇 之計數結果與財值進概較，並輸A比較結果。 正苇N况下，振盪訊號s〇sc的目標頻率應為參考時脈 Sref之頻率乘以鎖相迴路1()2之除頻裝置⑼的除數值。 例如’假設參考時脈Sref的頻率為1〇〇MHz，而除頻裝置 150的除數值為4，職蓋訊號s〇sc的目標頻率應為伽 邊。倘若比較裝置17〇中之除頻裝置之除數值為$， :除V員衣置420之除數值為10，則第二除頻訊號的頻 率係為10 MHz’而第一除頻訊號刚的理想頻率應為肋 MHz。因a匕’計數器43〇可計數在第二除頻訊號咖的一 個週期中，第-除頻訊號FD1的上升緣（或下降緣）個數， 200810365 而比較器440則可將計數器43〇所得到之計數值與預定值 8 (=80/10)進行比較，以判斷振盪器14〇的振盪頻率是否 為所需要的值。 倘若該計數值大於預定值8,代表振盪器14〇的振盪 頻率過快；若該計數值小於預定值8，代表振盪器14〇的 振盪頻率過慢；而若該計數值等於預定值8，則代表振盪 為140當時的設定符合所需的頻率調整範圍，亦即振盪器 140當時所選擇的頻段是適當的。實作上，除頻裝置 與420兩者的除數值宜為整數，而預定值為2n較佳（其中， N為正整數），以降低後續電路的複雜度。 由前述說明可知，設定裝置104之比較裝置170可藉 由比較振盪訊號S〇sc與參考時脈Sref的方式，來判斷振盪 器140之設定是否適當，但此僅係為一實施例，而非限定 本發明之實際實施方式。例如，第5圖為比較裝置之 第二實施例的方塊圖。在此實施例中，計數器43〇係依據 第一除頻吼號FD2與鎖相迴路1〇2之除頻裝置15〇所輸出 之除頻λ號sf進行計數，而比較器44〇會對計數器之 計數結果與預定值進行比較，並輸出比較結果。相仿地， 计數為430可計數在第二除頻訊號FD2的一個週期中，除 頻訊號sf的上升緣（或下降緣）個數，而比較器44〇只需 將计數為430所得到之計數值與除頻裝置42〇之除數值進 200810365 行比較’即可判斷振盪器140的設定是否適當。換_之 設定裝置104之比較裝置no亦可藉由比較除力 " 平乂1承頰訊號Sf與 苓考日寸脈Sref，來判斷振盪器140之設定是否適卷。备作 上’除頻裝置150與420兩者的除數值宜為整衾 貝 ^ ，而予頁定 值為2N較佳（其中，N為正整數），以降低後續電路的複雜 度。在一較佳實施例中，比較裝置170與鎖相迴路1〇2可 共用相同的除頻裝置15〇，以降低整體電路的面積。接著， 比較裝置170會將比較結果傳送給決定單元18()，使決定 單元180據以調整振盪器14〇的設定值。具體而言，以振 盪器140由切換電容式振盪器實現時為例，當切換電容式 振盪器的振盪頻率過快時，決定單元180會增加切換電容 式振盪器之總電容值，以降低其振盪頻率。當切換電容式 振盪器的振盪頻率過慢時，決定單元180則會減少切換電 容式振盪器之總電容值，以加快其振盪頻率。實作上，決 定單元180在調整切換電容式振盪器之變容器設定值的過 程中’可採用線性搜尋（linear search)、二元搜尋（binary search )或逐次逼近（successive appr〇ximati〇n )等演算法。 由剞述說明可知，設定裝置104可設計成依據參考時 脈Sref與振盪訊號Sosc來調整振盪器140之頻率，亦可設 计成依據參考時脈Sref與除頻訊號Sf來調整振盪器140 之頻率。 12 200810365 在一較佳實施例中，振盪器140由切換電容式振盪器 所實現時，設定裝置104在步驟220中還會參考切換電容 式振盪器之變容器調整特性（varactor tuning characteristics) 來選擇切換 電容式振盪器 之頻段 。進一步而言 ，若設 定裝置104之決定單元180無法藉由調整切換電容式振盪 器之變容器設定值的方式，使比較裝置170之計數器430 的計數值與比較器440所使用之預定值兩者達到相等的狀 態，則本實施例中之決定單元180會依據切換電容式振盪 器之變容器調整特性，為切換電容式振盪器決定適當的頻 段。 請參考第6圖，其所繪示為切換電容式振盪器之變容 器調整特性的一實施例示意圖600。在第6圖中，610、620 與630表示切換電容式振盪器可選擇的三個頻段，而參考 電壓Vref係對應於這些頻段的中點。假設切換電容式振盪 器目前選擇的頻段為頻段630，當頻率合成器100進入微 調模式後，切換電容式振盪器要從目前頻段630的頻率點 602往右上方調整，才會達到目標頻率的位置。若選擇頻 段620，則切換電容式振盪器要從頻段620的頻率點604 往左下方調整，才會達到目標頻率的位置。如第6圖所示， 頻段630之頻率點602右方的調整特性曲線斜率較平緩， 但頻段620之頻率點604左方的調整特性曲線較陡峭。因 此，設定裝置104之決定單元180會將切換電容式振盪器 13 200810365 的頻段改為頻段620，以縮短頻率人 卞σ成為100進入微言周抬 式後的鎖定時間。 巧拉 ▲ t第2圖之流程圖200戶斤示，在振盡器140達到粗略 调整模式之目標頻率前，設定裝 ’、 運作。 义衣置104會重複步驟220之 當振咖0達到粗略調整模式之目標頻 =換單元106會將鎖相迴略102切換至 (步驟240)，以進入微調模式。在第⑶ 心 換單元⑽會將振細。的輪入端切換至二^ 所輸出之控制訊號VC，以使鎖相趣路收形成閉迴路Γ off)，以使鎖相迴路102變成一般的閉迴路狀皞。 當鎖相迴路1〇2處於閉迴路狀態時，鎖相迴路1⑽合 依據參考時脈Sref與振盪訊號Sosc來調敕枳 曰 正艰盪器140之控 制訊號Vc (步驟250)，以使振盪訊號s〇s V步貝率月包達到 所需的目標頻率。由於鎖相迴路102在閉捆 d 你闹疫路狀態中的鎖 定運作為習知技術，為簡潔起見，在此不多 加贅述。 臟整振盪器的方式’亦適用於各種非整數頻率合 成器（fractional-N frequency synthesizer)的架構中 14 200810365 . 請參考第7圖，其所繪示為本發明第二實施例之頻率 合成器700簡化後之方塊圖。頻率合成器7〇〇包含有鎖相 迴路702、設定裝置7〇4以及切換單元7〇6。本實施例之鎖 相迴路702包含檢測器710’用來檢測參考時脈Sref與除 頻訊號Sf之頻率差及/或相位差；電荷泵720，用來依據檢 測器710的檢測結果產生控制電流；避路遽波哭73〇，用"" 來依據該控制電流產生控制訊號Vc;振盪器74〇，用來依 據控制訊號Vc產生振盪訊號S〇sc;除頻壯晉 # 振盪訊號Sosc進行除頻，以產生除頻訊號Sf;以及除數設 定裝置760，用來間歇地調整除頻裝置75〇之除數值， 除頻裝置750對振盪訊號Sosc進行一非整數除頻運作使 與前述實施例相同’設定襄置7〇4的運作血實施方 ^亦與前揭之設定裝置104實質上相同。也就是說，設 ^裝置剔Γ設計成依據參考時脈㈣與振盪訊號Sosc又 鱼凋整振盈11740之頻率’亦可設計成依據參考時脈㈤ =頻訊號Sf來調整振盪器之頻率。惟需 机 二置二Γ調整模式中(亦_ 係依據除頻訊號參考時脈㈣來調整振 時當鎖相迴路702處於開迴路狀態 固定=:T76°應將除頻裝置750之除數值設為-口疋整數值。鎖相迴路702之其他元件的 與前揭實施例係實質上相同，故不再贅述。’…式 15 200810365 可耦接於迴路濾波器730與振200810365 IX. Description of the Invention: [Technical Field] The present invention relates to a technique for a phase-locked loop, particularly a method of adjusting an oscillator of a phase-locked loop and a related frequency synthesizer. [Prior Art] For many communication devices (such as mobile phones), the application of Multi-Mode/Multi-Band has become more and more important. In such applications, the mobile communication device typically uses a frequency synthesizer with a wide frequency adjustment to provide the desired clock signal. Frequency synthesizers are typically implemented in a phase-locked loop (PLL) architecture. In order to meet the stringent requirements for phase noise in the mobile communication standard, the oscillator gain in the phase-locked loop of the frequency synthesizer should be kept at a low level. In order to achieve such a goal, the oscillatory phase of the frequency synthesizer is implemented by a switched capacitor voltage controlled oscillator (switched ca_ pacitor VCO) to increase the frequency adjustment range of the frequency synthesizer. It is well known that the locking speed of the phase-locked loop has a large effect on the overall moon of the frequency synthesizer. Therefore, how to effectively improve the locking speed of the phase-locked loop using the switched capacitor type oscillator is a problem to be solved. 200810365 [Summary] In view of this, the purpose of the day is to call the relevant frequency synthesizer to solve the above problem. This specification proposes an embodiment of a frequency synthesizer, which includes a phase-locked loop having a -n-switching unit for setting the state of the road, or the state of the road. A set band 'is used in the _ phase loop is in the open loop _ pulse and the oscillation is crying reference 蚪 where the phase locked loop is in an open loop state, the member is substantially fixed. There are also examples of frequency synthesizers that include σ. /mesh loop 'which includes an oscillation signal for generating an oscillation signal: two = pair: the oscillation signal is divided to generate a - first-division signal, and a switching unit for the lock Phase loop switching path ^ 日士 state or closed loop state 'When the phase locked loop is in the open loop Μ 'The control signal of the oscillator is substantially fixed; a second divide 'early couple' is used for the reference The pulse is divided to generate a first frequency division #. When the number is used in the open loop state, the frequency is counted according to the frequency division signal to generate a count value; and the count value and a predetermined value are used to generate a comparison knot determining soap element. , used to adjust the frequency of the oscillation 200810365 according to the comparison result. 'This specification also provides a method for adjusting the vibrator in the phase-locked loop', which includes: maintaining the phase of the phase-locked circuit switching (four) device fixed; when the phase-locked circuit is in the open circuit = According to the reference day gift and the output of the vibrating device, the frequency of the oscillation signal is adjusted to oscillate ϋ; when the frequency of the (four) device reaches the preset target, the phase-locked loop is switched to the closed loop state; When the phase locked loop is in a closed loop state, the control signal of the oscillator is adjusted according to the reference clock and the oscillation signal. [Embodiment] Please refer to Fig. 1, which is a block diagram showing a simplified frequency synthesis of 100 according to a first embodiment of the present invention. The frequency synthesizer 1A includes a phase locked loop (PLL) 102, a setting device 1〇4, and a switching unit 1〇6. The phase-locked loop 102 of this embodiment includes a detector 110 for detecting a frequency difference and/or a phase difference between the reference clock Sref and the frequency-divided signal Sf; the charge pump (than the beat pump) 120' is used according to the detector no The detection result generates a control current 'loop filter', a loop filter 130 for generating a control signal Vc according to the control current; an oscillator (osciiiator) 14〇 for generating an oscillation signal Sosc according to the control signal Vc; The frequency device 15 is configured to perform frequency division on the oscillating signal Sosc to generate a frequency-divided signal Sf. In practice, the detector 110 can be implemented by a phase frequency detector (PFD) 7 200810365, the loop filter 130 can be various active filters or passive filters, and the oscillator 140 can be switched by capacitive voltage. The switch capacitor VCO is used to implement 0. In the frequency synthesizer 100, the oscillation frequency used to adjust the oscillator 140 is set, and the switching unit 106 is used to switch the phase locked loop 102 to the open loop state. (〇peni〇〇pstatus) or closed loop (loop status). The tuning and calibration process of the oscillator 14〇 in the phase-locked loop 丨〇2 can be divided into two modes', respectively, a coarse adjustment mode (c〇_Z) and a fine tuning mode (fine tuning m〇de). In the strategy adjustment mode, the phase-locked loop (10) will be switched to the open circuit state, and in the first unit, the lock phase will be switched back to the closed adjustment. Will be accompanied by the second picture to further explain the vibration! 140 ^ ^ ΙΓ-Γί ^ 102 ^ 140 is described as follows. °. Flowchart 2. Steps included in step v - In step 210, the switching unit (10) will state and cause the vibrator 14. The round-in IS102 switch is in the rough adjustment mode. As shown in Figure 1, the signal is maintained in the first embodiment. One-phase loop:::cell (10) Filter 130 and 8 200810365 between the disc states 140. When the switching number 1 is switched to the substantially (4) 1G6, the control signal of the oscillator 14G is turned on. Please note: When the voltage Vref is tested, the phase-locked loop 102 will switch the actual setting of the unit (10); the square is only for the embodiment, not the limitation, for example, the brother 3 shows that 1 caution #加.^, D Another embodiment of the manner in which the horse switching unit 106 is arranged. As shown in Fig. 3, θ ^ ^ _ /, 'the loop filter 130 in this embodiment is a filter with an operational amplifier-electrical capacitance (OP-RC) architecture (OP-RC fUter), and switching ^ The 106 is coupled between the wheel of the operational amplifier of the loop filter 130 and the wheel. When the switching unit 106 turns on and the charge pump σσ 20 is disabled, the control signal vc outputted by the loop filter 130 is equal to the substantially fixed reference voltage Vref, which is equivalent to The lock-inquiring sub-director 102 is turned into a loop-like sorrow. When the phase-locked loop 102 is in the open loop state, the setting device 1〇4 adjusts the frequency/band of the oscillator 140 according to the oscillation signal Sosc generated by the reference clock Sref and the oscillator M〇 according to the reference voltage Vref (step 220). ). As shown in Fig. 1, the setting device 1A of the present embodiment includes a comparing device 170 and a determining unit 180. The comparing means 170 is for comparing the oscillating signal Sosc with the reference clock, and the determining unit 18 决定 determines how to adjust the frequency of the 200810365 of the oscillating device 140 according to the comparison result of the comparing means 170. For example, 'Comparative installation f 170 can compare the frequency of both the vibration signal W and the reference Japanese pulse Sref' and output-comparison result, and the decision list: (10) then (4) the comparison of the knot filament is difficult to 14 (four) solution, where to The oscillator 140 performs the purpose of coarse adjustment. The block diagram of the first embodiment of the comparison device 170 is as shown in Fig. 4. Comparison device 17 of this embodiment. Contains two frequency divisions ^ 41. And gamma, counter 430, and comparator 44A. The frequency dividing device 41 is used to divide the frequency of the vibration signal S〇SCit to generate a -first frequency signal, and the device "1" divides the reference clock Sref to generate a second division. Frequency signal FD2. The counter 43 will be based on the first divisor signal yang! The comparator 440 compares the count result of the counter 43〇 with the financial value, and inputs the A comparison result. In the case of positive N, the target frequency of the oscillation signal s〇sc should be the frequency of the reference clock Sref multiplied by the divisor of the frequency division device (9) of the phase-locked loop 1()2. For example, 'assuming that the frequency of the reference clock Sref is 1 〇〇 MHz, and the division value of the frequency dividing device 150 is 4, the target frequency of the cover signal s 〇 sc should be a gamma. If the dividing value of the frequency dividing device in the comparing device 17 is $, the frequency of the second frequency dividing signal is 10 MHz' and the frequency of the first frequency dividing signal is 10, except that the dividing value of the V member set 420 is 10. The ideal frequency should be rib MHz. Because the counter 〇 counter 〇 can count the number of rising edges (or falling edges) of the first-division signal FD1 in one cycle of the second divisor signal, 200810365, and the comparator 440 can set the counter 43 The obtained count value is compared with a predetermined value of 8 (= 80/10) to determine whether the oscillation frequency of the oscillator 14 is the desired value. If the count value is greater than the predetermined value 8, it means that the oscillation frequency of the oscillator 14〇 is too fast; if the count value is less than the predetermined value 8, the oscillation frequency of the oscillator 14〇 is too slow; and if the count value is equal to the predetermined value 8, It then represents that the oscillation is set to 140 at the time and the desired frequency adjustment range is met, that is, the frequency band selected by the oscillator 140 at the time is appropriate. In practice, the divisor values of both the frequency dividing device and the 420 are preferably integers, and the predetermined value is preferably 2n (where N is a positive integer) to reduce the complexity of subsequent circuits. It can be seen from the foregoing description that the comparison device 170 of the setting device 104 can determine whether the setting of the oscillator 140 is appropriate by comparing the oscillation signal S〇sc with the reference clock Sref, but this is only an embodiment, instead The actual embodiments of the invention are defined. For example, Fig. 5 is a block diagram of a second embodiment of the comparing means. In this embodiment, the counter 43 is counted according to the first frequency division code FD2 and the frequency division λ number sf output by the frequency dividing device 15〇 of the phase locked loop 1〇2, and the comparator 44〇 counter The count result is compared with a predetermined value, and the comparison result is output. Similarly, the count 430 can count the number of rising edges (or falling edges) of the frequency signal sf in one cycle of the second frequency dividing signal FD2, and the comparator 44 only needs to count 430. The count value is compared with the division value of the frequency dividing device 42〇 into the 200810365 line' to determine whether the setting of the oscillator 140 is appropriate. The comparison device no of the setting device 104 can also determine whether the setting of the oscillator 140 is suitable by comparing the de-duplication " Pingyi 1 buccal signal Sf and the reference time Sref. The divisor values of both the frequency dividing devices 150 and 420 are preferably integer ^, and the predetermined value is 2N (where N is a positive integer) to reduce the complexity of subsequent circuits. In a preferred embodiment, the comparing means 170 and the phase locked loop 1 〇 2 can share the same frequency dividing means 15 以 to reduce the area of the overall circuit. Next, the comparing means 170 transmits the comparison result to the decision unit 18(), causing the decision unit 180 to adjust the set value of the oscillator 14A. Specifically, when the oscillator 140 is implemented by a switched capacitor oscillator, when the oscillation frequency of the switched capacitor oscillator is too fast, the determining unit 180 increases the total capacitance of the switched capacitor oscillator to reduce its Oscillation frequency. When the oscillation frequency of the switched capacitor oscillator is too slow, the decision unit 180 reduces the total capacitance of the switched capacitor oscillator to speed up its oscillation frequency. In practice, the determining unit 180 may adopt a linear search, a binary search, or a successive approximation (successive appr〇ximati〇n) in the process of adjusting the varactor setting value of the switched capacitor oscillator. Equal algorithm. As can be seen from the description, the setting device 104 can be designed to adjust the frequency of the oscillator 140 according to the reference clock Sref and the oscillation signal Sosc, and can also be designed to adjust the oscillator 140 according to the reference clock Sref and the frequency-divided signal Sf. frequency. 12 200810365 In a preferred embodiment, when the oscillator 140 is implemented by a switched capacitor oscillator, the setting device 104 also selects the varactor tuning characteristics of the switched capacitor oscillator in step 220. Switch the frequency band of the capacitive oscillator. Further, if the determining unit 180 of the setting device 104 cannot adjust the varactor setting value of the switched capacitor oscillator, the counter value of the counter 430 of the comparing device 170 and the predetermined value used by the comparator 440 are both When the equal state is reached, the determining unit 180 in this embodiment determines the appropriate frequency band for the switched capacitor oscillator according to the varactor adjustment characteristic of the switched capacitor oscillator. Please refer to FIG. 6, which is a schematic diagram 600 showing an embodiment of a varactor adjustment characteristic of a switched capacitor oscillator. In Fig. 6, 610, 620 and 630 represent three frequency bands selectable by the switched capacitor oscillator, and the reference voltage Vref corresponds to the midpoint of these bands. It is assumed that the currently selected frequency band of the switched capacitor oscillator is the frequency band 630. When the frequency synthesizer 100 enters the fine adjustment mode, the switched capacitive oscillator is adjusted from the frequency point 602 of the current frequency band 630 to the upper right to reach the position of the target frequency. . If the frequency band 620 is selected, the switched capacitive oscillator is adjusted from the frequency point 604 of the frequency band 620 to the lower left to reach the position of the target frequency. As shown in FIG. 6, the slope of the adjustment characteristic curve to the right of the frequency point 602 of the frequency band 630 is relatively flat, but the adjustment characteristic curve to the left of the frequency point 604 of the frequency band 620 is steep. Therefore, the decision unit 180 of the setting device 104 changes the frequency band of the switched-capacitor oscillator 13 200810365 to the frequency band 620 to shorten the lock time after the frequency 卞 σ becomes 100 and enters the micro-weekly lift mode.巧拉 ▲ t The flow chart of Figure 2 shows that the device is set to operate before the vibration frequency of the coarse adjustment mode is reached. The garment setting 104 repeats the step 220. When the vibration coffee 0 reaches the target frequency of the coarse adjustment mode = the switching unit 106 switches the lock phase return 102 to (step 240) to enter the fine adjustment mode. The (3) heart-changing unit (10) will be shimmered. The turn-in end switches to the control signal VC outputted by the second control unit to form a closed loop (off), so that the phase-locked loop 102 becomes a general closed loop state. When the phase-locked loop 1〇2 is in the closed loop state, the phase-locked loop 1 (10) adjusts the control signal Vc of the hard-acting device 140 according to the reference clock Sref and the oscillation signal Sosc (step 250) to make the oscillation signal The s〇s V step rate monthly package reaches the desired target frequency. Since the locking operation of the phase-locked loop 102 in the state of the closed loop is a conventional technique, for the sake of brevity, it will not be repeated here. The mode of the dirty oscillator is also applicable to the architecture of various fractional-N frequency synthesizers. 14 200810365 . Please refer to FIG. 7 , which is a frequency synthesizer according to a second embodiment of the present invention. 700 simplified block diagram. The frequency synthesizer 7A includes a phase locked loop 702, a setting device 7〇4, and a switching unit 7〇6. The phase-locked loop 702 of this embodiment includes a detector 710' for detecting a frequency difference and/or a phase difference between the reference clock Sref and the frequency-divided signal Sf. The charge pump 720 is configured to generate a control current according to the detection result of the detector 710. The way to avoid the road cries 73 〇, use "" to generate the control signal Vc according to the control current; the oscillator 74 〇 is used to generate the oscillation signal S〇sc according to the control signal Vc; the frequency deflation # oscillation signal Sosc Performing frequency division to generate the frequency division signal Sf; and divisor setting means 760 for intermittently adjusting the division value of the frequency dividing means 75, the frequency dividing means 750 performing a non-integer frequency division operation on the oscillation signal Sosc to enable The operation blood implementation of the same embodiment as the setting device 7 is also substantially the same as the previously described setting device 104. That is to say, the device is designed to adjust the frequency of the oscillator according to the reference clock (5) = frequency signal Sf according to the reference clock (4) and the oscillation signal Sosc and the frequency of the fish 11148. However, it is necessary to adjust the mode according to the frequency division reference clock (4). When the phase-locked loop 702 is in the open circuit state fixed =: T76°, the value of the frequency dividing device 750 should be set. The value of the other components of the phase-locked loop 702 is substantially the same as that of the previous embodiment, and therefore will not be described again. '... Equation 15 200810365 can be coupled to the loop filter 730 and the oscillator
同樣地，切換單元706 盈器740之間。倘若迴路滤 由於前揭之頻率合成器係以開迴路方式來對振盪器 。(例如切換電容式振盪器）進行粗略設定與調整，再以閉 迴路方式對其控制訊號進行微調，故可有效提升振盪器的 調校速度，進而改善頻率合成器的整體效能。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖為本發明之頻率合成器的第_實施例簡化後的方塊圖。 第2圖為本發明調整鎖相迴路之振盪器之方法的一實施例流程圖。 第3圖為第1圖中之切換單元之設置方式的另一實施例。 第4圖為第1圖中之比較裝置之第一實施例的方塊圖。 第5圖為第1圖中之比較裝置之第二實施例的方塊圖。 第6圖為本發明一實施例中之切換電容式振盪器之變容器 特性示意圖。 第7圖為本發明之頻率合成器的第二實施例簡化後的方塊圖。 16 200810365 【主要元件符號說明】 100 、 700 頻率合成器 102 > 702 鎖相迴路 104 、 704 設定裝置 106 、 706 切換單元 110 、 710 檢測器 120 > 720 電荷泵 130 、 730 迴路濾、波器 140 、 740 振盪器 150 、 750 、 410 、 420 除頻裝置 170 比較裝置 180 決定單元 430 計數器 440 比較器 600 變容器特性 602 > 604 頻率點 610 、 620 、 630 頻段 760 除數設定裝置 17Similarly, the switching unit 706 is between the hoppers 740. In the case of the loop filter, the frequency synthesizer is connected to the oscillator in an open loop manner. (For example, switching the capacitive oscillator) for rough setting and adjustment, and then fine-tuning its control signal in a closed loop mode, which can effectively improve the tuning speed of the oscillator, thereby improving the overall performance of the frequency synthesizer. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should fall within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a simplified block diagram of a first embodiment of a frequency synthesizer of the present invention. 2 is a flow chart of an embodiment of a method for adjusting an oscillator of a phase locked loop according to the present invention. Fig. 3 is another embodiment of the arrangement of the switching unit in Fig. 1. Figure 4 is a block diagram of a first embodiment of the comparing device of Figure 1. Figure 5 is a block diagram of a second embodiment of the comparing device of Figure 1. Fig. 6 is a schematic view showing the characteristics of a varactor of a switched capacitor oscillator according to an embodiment of the present invention. Figure 7 is a simplified block diagram of a second embodiment of the frequency synthesizer of the present invention. 16 200810365 [Description of main component symbols] 100, 700 frequency synthesizer 102 > 702 phase-locked loop 104, 704 setting device 106, 706 switching unit 110, 710 detector 120 > 720 charge pump 130, 730 loop filter, wave device 140, 740 oscillator 150, 750, 410, 420 frequency dividing device 170 comparison device 180 decision unit 430 counter 440 comparator 600 varactor characteristic 602 > 604 frequency point 610, 620, 630 frequency band 760 divisor setting device 17