TW200805211A

TW200805211A - Panel control signal picking-apparatus and method

Info

Publication number: TW200805211A
Application number: TW95124951A
Authority: TW
Inventors: Shih-Tsun Kuo
Original assignee: Emine Technology Company Ltd
Priority date: 2006-07-07
Filing date: 2006-07-07
Publication date: 2008-01-16

Abstract

A panel control signal picking-apparatus and method are disclosed in the present invention. The invention is used for connecting with the panel controller of a display apparatus and picking a control signal transmitted by the panel controller. The control signal contains an image data and a clock data. By using a clock data, the image data states generated at different time are sequentially stored in a first-in first-out memory so as to transmit to the bus interface. Based on time sequence, image data at different periods are outputted and stored after they are sequentially transmitted to the bus interface. Thus, it is capable of storing the variations of image as a function of time as the control data according to time sequence.

Description

200805211 九、發明說明：【發明所屬之技術領域】毛員取有關，特別是關於一種直接由顯像資料之面板控制訊號擷取裝置及方本發明係與影像資料之示裝置之面板控制器擷取影法0 【先前技術】 2參閱「第丨圖」所示’係為習知技術中的面板控制器的系 =塊圖，錢設置於液轉示裝置中，肋· rgb類比訊號 1將其轉換為控制訊號，例如丁几信號（如___ 广啊υ或是低電壓差動訊號（職㈣），輸出至顯示面對顯示面板進行控制，使顯示面板進行顯示。此—面板控制益⑽包含有類比數位轉換器110 (編wDigitai 撕）、記憶體120、縮放引擎130 (Scalar)、處理控制器140及 -輸出介面15〇。其帽比數位轉換器⑽是用訊號產生端，例如-攝影機、電駐機之影像卡所輸出之RGB= 比讯唬，加以轉換成數位訊號後，進行進一步的處理。然而m贿構下將影像贿於—電腦主機時，並非直接紀錄控制面板之控制訊號，而是接收直接職類比訊號之後，透過編碼轉換，轉換成—般影像槽格式。儲存於電腦。而再度輸=至顯示裝置時，必須經過—次解壓縮程序後，形成紅綠藍^ 象貝料（RGBDATA)，再傳輸至面板控制器轉換為面板的控制訊旒。不論是儲存過程中的轉換編碼，或是後續再輸出的解壓縮過 5 200805211 釭都不疋直接輸入或輪出面板的控制訊號，而需要耗費電腦主機的硬辟絲進行影像處。若是制時記錄多個影像資料來源時H駐機絲無法貞荷這制㈣處理量，而導致影像品質必細齡。因此如何改變影像擷取模式，來降低電腦主機所需要織㈣統資源，成為_項重要的技術課題。【發明内容】 #於以上的問題，本發明的主要目的在於提供—種面板控制喊擷«置及籍，财直接由顯示裝践面缝織榻取影像貢料’直接進行_、應用，後續再輸出至顯示科，也可以直接輸出可轉面板的控制峨，不t再透過複雜哺換程序。為了達成上违目的’本發明提供一種面板控制訊號榻取裝置’用以連接於-顯示裝置之面板控_，擷取面板控制器傳輪 -控制峨’依據㈣峨巾_域能喊，將㈣訊號中的影像貝枓由匯流排介面輸出，而形成控制資料，此—裝置包含有一先進先出記紐，職供寫人影像龍，並將寫人影像資料傳輸至匯流齡面。-控魏路，可棚示致能訊號產生時啟動先進先出記憶體以寫人影像#料，並傳輸至匯流排介面，使每一文顯示致能峨產生時之影像:雜料序雜紐賴介面，而妒成一控制資料。 ^ 本發明更提供一種面板控制訊號擁取方法，用以由一顯示裝 200805211 含有一影像資料、一垂直同步訊號及一顯示致能訊號，面板控制器係可依據該顯示致能訊號產生時之該影像資料使顯示裝置產生一場晝面（FieldFrame)，方法包含有下列步驟：接收垂直同步訊號及顯示致能信號，以啟動一先進先出記憶體之寫入週期。依據顯示致能信號產生一寫入致能訊號及一寫入時脈，使先進先出記憶體影像資料寫入。對匯流排介面發出一直接存取請求信號，使匯流排介面傳回一直接存取認可信號。於接收直接存取認可信號之後’發動先進先出記憶體的讀出週期，使先進先出記憶體中的資料於匯流排介面出現，將每一次顯示致能訊號產生時之影像資料依時序傳輸至匯流排介面，而被儲存形成影像資料隨時序變化之控制資料。本發明之功效在於，此-裝置及方法係可透過面板控制器直接擷取影像龍，不需再透過影像辆及轉換，此—編碼亦可直接被還原輸出至面板控制H，因此不需要耗費大量硬體資源於影像貧料的格式賴，藉以提昇影㈣料之儲存及輸出的效率。以下在貫施方式巾詳細敘述本剌之詳細特徵以及優點，其内容足以使任何熟習相驗藝者了解本發明之技術内容2據以實施，且根據本說明書所揭露之内容、憎專利翻及圖式，任ς 熟習相關技藝者可輕易地理解本發_關之目的及優點。以上之關於本發咖容之制及以下之實施 :示範與解釋本發明之原理，並且提供本發狀專_二= 進一步之解釋 7 200805211 【實施方式】為使對本發明的目的、構造、特徵、及其功能有進一步的瞭解，茲配合實施例詳細說明如下。200805211 IX. Description of the invention: [Technical field of invention] The panel controller of the device for controlling the signal extraction device directly from the panel of the image data and the device for displaying the image data of the present invention撷Take the picture method 0 [Prior Art] 2 Refer to the "Figure 」" as shown in the "Technology" panel controller = block diagram, money is set in the liquid transfer device, rib · rgb analog signal 1 will It is converted into a control signal, such as a few signals (such as ___ 广 υ or low voltage differential signal ((4)), output to the display to control the display panel, so that the display panel is displayed. This - panel control benefits (10) includes an analog digital converter 110 (programmed wDigitai tear), a memory 120, a scaling engine 130 (Scalar), a processing controller 140, and an output interface 15A. The cap ratio digital converter (10) is a signal generating end, for example - The RGB= signal output from the video card of the camera and the electric station is converted into a digital signal for further processing. However, when the bribe is used to bribe the image to the computer, it is not straight. After recording the control signal of the control panel, it receives the direct job analogy signal and converts it into a general image slot format through code conversion. It is stored in the computer, and when it is converted to the display device, it must undergo the decompression process. Form red, green and blue ^ RGBDATA, and then transfer to the control panel of the panel controller to convert to the panel. Whether it is the conversion code in the storage process, or the subsequent decompression of the output 5 200805211 Directly input or rotate the control signal of the panel, and it is necessary to use the hard wire of the computer host to carry out the image. If the source of multiple image data is recorded during the system, the H station wire can not be loaded (4) processing volume, resulting in image quality. Therefore, how to change the image capturing mode to reduce the resources required by the computer mainframe becomes an important technical issue. [Invention] In the above problems, the main purpose of the present invention is to provide The panel control shouts «Zhe Ji Ji, Cai directly from the display of the dressing surface to sew the sofa to take the image tribute' directly to _, application, and then output to the display Section, you can also directly output the control panel of the translatable panel, and then pass through the complicated feeding procedure. In order to achieve the above objective, the present invention provides a panel control signal reclining device for connecting to the panel control of the display device. According to (4) 峨 _ domain can shout, the image of the (4) signal is output from the bus interface to form control data, this device contains a first-in-first-out The job is to write the image dragon, and transfer the image data of the person to the sinking age. - Control Wei Road, when the signal is generated, the first-in first-out memory is activated to write the image and transmitted to the convergence. The interface is arranged to enable each image to display the image when the enabler is generated: the miscellaneous material is mixed with the interface, and the control data is formed. ^ The present invention further provides a panel control signal acquisition method for containing a display device 200805211 An image data, a vertical sync signal and a display enable signal, the panel controller can cause the display device to generate a field frame according to the image data when the display enable signal is generated. The method includes the steps of: receiving a vertical sync signal and displaying an enable signal to initiate a write cycle of a first in first out memory. A write enable signal and a write clock are generated according to the display enable signal, so that the first in first out memory image data is written. A direct access request signal is sent to the bus interface to transmit a direct access acknowledgement signal to the bus interface. After receiving the direct access approval signal, the first FIFO memory read cycle is initiated, so that the data in the FIFO memory appears on the bus interface interface, and the image data when each display enable signal is generated is transmitted in time series. To the bus interface, and stored to form control data of the image data as time series changes. The effect of the present invention is that the device and the method can directly capture the image dragon through the panel controller, and no need to pass through the image vehicle and convert, the code can also be directly restored to the panel control H, so no need to consume A large number of hardware resources are used in the format of image poor materials, so as to improve the efficiency of storage and output of shadows. The detailed features and advantages of the present invention are described in detail below, and the contents thereof are sufficient for any familiar practitioner to understand the technical content of the present invention, and according to the contents disclosed in the present specification, Schematic, Ren Yi The familiar art can easily understand the purpose and advantages of this issue. The above description of the present invention and the following implementations: exemplifying and explaining the principles of the present invention, and providing the present invention _2 = further explanation 7 200805211 [Embodiment] For the purpose, structure, and features of the present invention Further understanding of the functions and functions thereof is described in detail below with reference to the embodiments.

請參閱「第2圖」所示，係為本發明實施例所揭露之一種面板控㈣細取裝置，係可連接於—顯示裝置的面板控 …制器、310，直接榻取面板控制器31〇傳輸至面板32〇的控制訊號 C ^ ^ ( Transistor-Transistor Logic Signal ^ TTL • Slgnal)或疋一低電壓差動訊號（Low Voltage Differential SigM ^ LVDS)，加以轉換形成一控制資料D，透過一匯流排介面4〇〇傳輸至-本地端電觀進行儲存及應用。如此—來，本地端電腦即可直接儲存用來控制此面板320用的控制訊號c，用以供後續還原輸出至面板320進行顯示，由於本地端電腦是直接儲存控制訊號，因此就不需要再對RGB訊號或是DVI訊號進行轉換，可有效節省本地端電腦的系統資源。 _ 请再度茶照「第2圖」所示，面板控制訊號擷取裝置200主要包含有一控制電路210、一接收單元220、一先進先出記憶體、—230。控制電路210可為一可程式化邏輯元件（cpLD，c〇mplexPlease refer to FIG. 2 , which is a panel control (four) fine extraction device disclosed in an embodiment of the present invention, which can be connected to a panel control device of the display device, 310, and a direct control panel controller 31. 〇 transmitted to panel 32〇 control signal C ^ ^ (Transistor-Transistor Logic Signal ^ TTL • Slgnal) or a low voltage differential signal (Low Voltage Differential SigM ^ LVDS), converted to form a control data D, through a The bus interface 4 is transmitted to the local terminal for storage and application. In this way, the local computer can directly store the control signal c used for controlling the panel 320 for subsequent restoration output to the panel 320 for display. Since the local computer directly stores the control signal, there is no need to Converting RGB signals or DVI signals can effectively save system resources on the local computer. _ Please repeat the tea photo "Fig. 2", the panel control signal capturing device 200 mainly includes a control circuit 210, a receiving unit 220, a first-in first-out memory, -230. Control circuit 210 can be a programmable logic element (cpLD, c〇mplex

Programmable Logic Device )或是可程式化的邏輯晶片（FPGA，Programmable Logic Device) or a programmable logic chip (FPGA,

Field-Programmable Gate Array)，用以供寫入預設程式，以驅動控制電路210。控制電路21〇係電連於接收單元22〇及先進先出記憶體230 ’以控制接收單元220及先進先出記憶體23Q的運作。 200805211Field-Programmable Gate Array) for writing a preset program to drive the control circuit 210. The control circuit 21 is electrically coupled to the receiving unit 22 and the first in first out memory 230' to control the operation of the receiving unit 220 and the first in first out memory 23Q. 200805211

接收單元220係連接於面板控制器310，用以接收面板控制斋310輸出之控制訊號c。一般而言，面板控制器31〇傳輸至面板320的訊號有電晶體邏輯訊號(TTL)及低電壓差動訊號(LVDS) 兩種型態。若控制訊號C為電晶體邏輯訊號（TTL)，則接收單元 220可直接將電晶體邏輯訊號（TTL)直接分割傳輸至先進先出記憶體230及控制電路210。若控制訊號c為低電壓差動訊號 (LVDS)，則接收單元220會將低電壓差動訊號（LVDS)轉換為電晶體邏輯訊號（TTL)之後再輸出。、先進先出記憶體230係連接於接收單元22〇及控制電路21〇, 其中控制電路210可分析控制訊號c中的時脈資料，例如同步訊號及％脈訊號，產生先進先出記憶體23〇之寫入時脈 F正〇lCLK(Write-C1〇ck)，同時產生寫人致能訊號 WREWABLE (Wnte_Enable) ’以作為先進先出記憶體23〇的時序控制，將每一時刻中的紅綠藍影像資料（RGB DATA) R0 朴 G7 B〇〜B7舄入先進先出記憶體230，接著讓此紅綠監影像貧料R〇〜P7、m 7 GO〜G7、Β0〜Β7於匯流排介面400上出現’以供連接於主控端電腦接收，依據時序將每一個時刻中被” 滚結”於先進先出記憶體的紅綠藍影像資料R〇〜R7、G〇〜 B〇 B7加以輪出’即可形成資料型態的控制資料D。請再細「第3圖」及「第4圖」所示’係為本發明實施例拍電路圖。其中直接存取單元係整合於控路210中。面制°° 310依據其所輪出的資料型態，以對應數目的訊號接 9 200805211 腳，將控制訊號C傳輪至接收單元220。本實施例中之控制訊號 C為低電壓差動訊號（lvds)，其訊號接腳包含rx〇+、狀〜、 RX1+、RX1-、RX2+、RX2-、RX3+、RX3_ 等，接收單元 22〇可先將低電壓差動訊號轉換為電晶體邏輯訊號再進行傳輸。若控制訊號c為電晶體邏輯訊號（TTL)，就不需要接收單元，可直接將此控制訊號c中的紅綠藍影像資料（RGB DATA)及時脈資料傳輸至先進先出記憶體230及傳輸至控制電路210。 φ 紅綠監影像資料（RGB DATA) R0〜R7、G0〜G7、B0〜B7 包含有顯示面板320上，對應的每一像素是否被啟動進行顯示的強度資料。而時脈資料則包含有水平同步信號HSYNC、垂直同步信號VSTOC、顯示致能信❹E (DisplayEnable)及像素點掃瞎頻率DCLK (Dot Clock)等。控制電路210可以將像素點掃_ 率DCLK作為時序基準，再根據顯示致能信號DE決定場晝面 (Field Frame)的寫入週期是否被啟動，而此一寫入週期中進行 φ 水平畫素更新或是垂直畫素的更新則由水平同步信號HSYNC、垂直同步信號VSYNC決定。在母一個時刻的場晝面（Field Frame)寫入週期開始時，控制電路210可產生先進先出記憶體230之寫入時脈 (Wnte-Clock )，同時產生寫入致能訊號FIFawR_ENABLE (Write-Enable)，使先進先出記憶體23〇以寫入時脈 FIFO-TO-CLK (Write-Clock)為時序依據，將每一個時刻中的紅綠藍影像資料R0〜R7、G0〜G7、B〇〜B7寫入先進先出記憶體 200805211 230中，亚使其出現在匯流排介面彻，而供本地端電腦加以接收亚進行儲存，依據時序使每一個時刻中的紅綠藍影像資料r〇〜 R7 G0〜G7、B0〜B7在匯流排介面4〇〇形成匯流排地址/資料信號AD0〜AD31，就可將紅綠藍影像資料r〇〜r7、g〇〜g7、別〜B7隨時間的變化記錄成控制資料d。第4圖」所不為本發明中之控制電路21〇的一種實施態樣，其包含有一直接存取控制器211 (DMAc〇ntr〇ller)，一本地端匯流 φ 212 (Local BUS Interface) > 213(AddressThe receiving unit 220 is connected to the panel controller 310 for receiving the control signal c outputted by the panel control module 310. Generally, the signals transmitted from the panel controller 31 to the panel 320 are in the form of a transistor logic signal (TTL) and a low voltage differential signal (LVDS). If the control signal C is a transistor logic signal (TTL), the receiving unit 220 can directly split the transistor logic signal (TTL) to the first in first out memory body 230 and the control circuit 210. If the control signal c is a low voltage differential signal (LVDS), the receiving unit 220 converts the low voltage differential signal (LVDS) into a transistor logic signal (TTL) before outputting. The first in first out memory 230 is connected to the receiving unit 22 and the control circuit 21, wherein the control circuit 210 can analyze the clock data in the control signal c, such as the synchronization signal and the % pulse signal, to generate the first in first out memory 23写入When the write clock F is 〇 lCLK (Write-C1 〇 ck), at the same time generate the write enable signal WREWABLE (Wnte_Enable) ' as the FIFO memory 23 〇 timing control, will be red at each moment Green and blue image data (RGB DATA) R0 Park G7 B〇~B7 breaks into the FIFO memory 230, and then let the red and green monitor image poor materials R〇~P7, m 7 GO~G7, Β0~Β7 in the bus On the interface 400, there is a red, green and blue image data R 〇 R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R Take the round out to form the data type control data D. Please refer to the "Fig. 3" and "Fig. 4" for the sake of the circuit diagram of the embodiment of the present invention. The direct access unit is integrated in the control path 210. The surface °° 310 transmits the control signal C to the receiving unit 220 according to the data type that it is rotating, with the corresponding number of signals connected to the 200805211 pin. The control signal C in this embodiment is a low voltage differential signal (lvds), and the signal pin includes rx〇+, 〜~, RX1+, RX1-, RX2+, RX2-, RX3+, RX3_, etc., and the receiving unit 22 The low voltage differential signal is first converted to a transistor logic signal for transmission. If the control signal c is a transistor logic signal (TTL), the receiving unit is not needed, and the red, green and blue image data (RGB DATA) in the control signal c can be directly transmitted to the FIFO memory 230 and transmitted. To control circuit 210. φ Red and green monitor image data (RGB DATA) R0 to R7, G0 to G7, and B0 to B7 include intensity data on whether or not each pixel corresponding to the display panel 320 is activated for display. The clock data includes a horizontal synchronizing signal HSYNC, a vertical synchronizing signal VSTOC, a display enable signal E (DisplayEnable), and a pixel sweep frequency DCLK (Dot Clock). The control circuit 210 can use the pixel sweep rate DCLK as a timing reference, and then determine whether the write period of the field frame is activated according to the display enable signal DE, and perform the φ horizontal pixel in the write period. The update or vertical pixel update is determined by the horizontal sync signal HSYNC and the vertical sync signal VSYNC. At the beginning of the field frame write period at one time, the control circuit 210 can generate the write clock (Wnte-Clock) of the FIFO memory 230, and simultaneously generate the write enable signal FIFawR_ENABLE (Write). -Enable), so that the first-in first-out memory 23〇 writes the clock FIFO-TO-CLK (Write-Clock) as the timing basis, and the red, green and blue image data R0~R7, G0~G7 in each moment, B〇~B7 is written into the first-in first-out memory 200805211 230, so that it appears in the bus interface, and is used by the local computer to receive the sub-storage. According to the timing, the red, green and blue image data in each moment is r. 〇~ R7 G0~G7, B0~B7 form the bus address/data signals AD0~AD31 in the bus interface 4〇〇, and the red, green and blue image data r〇~r7, g〇~g7, and other than B7 The change in time is recorded as control data d. Figure 4 is an embodiment of the control circuit 21A of the present invention, which includes a direct access controller 211 (DMAc〇ntr〇ller), a local BUS Interface >; 213 (Address

Latch)、-解碼器 214 (DeeGder)、_組態空間 2i5 ( c触gum—Latch), - decoder 214 (DeeGder), _ configuration space 2i5 (c touch gum -

Space)、一面板暨記憶體介面電路216 (pand & fif〇 Circuit)及一時脈產生器 217 (a〇ckGeneratOT)。其中％脈產生裔217可接收來自匯流排介面4〇〇之時脈訊號 CLKIN，產生控制電路21〇内部運作時所需要之運作時脈，將此一運作時脈CLKIN輸出至本地端匯流排控制器212 '直接存取控 • 制器211及面板暨記憶體介面電路216，以作為運作時所需要的曰守脈訊號。面板控制器320產生之控制訊號c，係先經過分割後，形成 • ·匯流排地址/資料信號AD0〜AD31及時脈資料。匯流排地址/資料信號AD0〜AD31係先由鎖存電路213鎖存之後，傳輪至解碼哭 214，產生致能信號CS及狀態信號R/w，傳輸至組態空間215，接著組態空間215可以針對匯流排介面4〇〇，產生一個符合匯流排介面400的組態，以使直接存取控制器211依據此一組態，使 11 200805211 用對應的通訊協定與匯流排介面400進行通訊。面板暨記憶體介面電路216係用以接收時脈資料，包含水平同步信號H-SYNC、垂直同步信號VSYNC、顯示致能信號de (Display Enable)及像素點掃瞄頻率dCLK (D〇t Q〇ck)，產生寫入能訊號FIFO_WR_ENABLE及冑人_脈FIFawR_CLK，使先進先出圯憶體230接收之紅綠藍影像資料（R〇〜R7、G〇〜G7、 BO B7)，出現在匯流排介面4⑻形成匯流排地址/資料信號 _ 〜AD31。以將特定時刻的紅綠藍影像資料（R()〜r7、⑼〜⑺、 BO B7)舄入先進先出§己憶體230中力口以儲存，接著輸出至匯流排介面400形成匯流排地址/資料信號，將每一時刻所儲存的紅綠藍影像資料R〇〜R7、G〇〜G?、B〇〜B7於匯流排介面400依據時序形成匯流排地址/資料信號Mo〜ADy，形成隨時間變化之控制資料D。在紅綠藍影像資料r〇〜R7、G〇〜G7、B〇〜B7被寫入先進先 • 出記憶體23〇時，面板暨記憶體介面電路210可同時產生一個觸 . 發訊唬（Tn^er)至直接存取控制器211 (DMA controller)，透過直接存取控制器211使本地端匯流排控制器212發出一個直接存取明求仏號D· REQ (DMA Request)至匯流排介面400。匯流排介面400接收直接存取請求信號D. 之後，可發出直接存取認可仏號D.GNT，使直接存取控制器211產生匯流排控制信號 frame#、匯流排命令/位元組致能信號BE〇〜BE3及主設備準備好域IRDY#等信號至匯流排介s 4〇〇，以發動先進先出記憶體 12 200805211 230的項出週期’使產生前述之面板暨記憶體介面電路產生記憶體讀取時脈FIFaRD-CLK、記憶體讀取致能信號 HFO-RD_ENABLE等先進先出記憶體咖的讀取信號，使先缺出記憶體230中的紅綠藍影像資料R〇〜R7、G〇〜G7、b〇〜B7 於匯流齡面上的對應地址形顧流獅址/資料信號侧〜AD3卜以將構成该時刻中之場晝面的紅綠藍影像資料助〜 …R7、G0〜G7、B0〜B7加以儲存或應用。在下一個場晝面產生時， • 此一先進先出記憶體230的寫入週期可再重複-次，因此使得每一時刻下控制訊號c形成的紅綠藍影像資料R〇〜R7、G〇〜G7、 B0〜B7可以依據時序於匯流排介面4〇〇形成匯流排地址/資料信號AD0〜細1，並且依據時序被儲存成資料型態的控制資料〇，以供儲存或是應用。钱第5八圖」及「第5B圖」所示，依據本發明實施例所揭露之裝置，本發明更提㈣—種面健伽號擷取方法，用以 • 由一顯示裝置300之面板控制器310擷取控制訊號c，並將控制 ‘ 訊號°^加以轉換形成控制資料D，透過匯流排介面輪出，方 ' 法包含有下列步驟：啟動（power on)或重置（Reset)系統，接著進行系統初始化（步驟510)。依據先進先出記憶體230中由指標定義的位址數，由匯流排 "面400设定迴圈計數值（1〇〇p c〇unter value)，並清除先進先出記憶體230之中由各指標定義的寫入及讀取位址（步驟a〗）。 13 200805211 叙-開始迴圈’判斷匯流排介面驟512)，若接收到開始命令，_彳^ 、出開始命令（步待貝1執仃下-步驟。若否，則繼續等設定-垂直同步信號VSYNC等待迴圈，判斷步信號VSYNC輸入，以接收垂直同步訊號（步‘驟叫有垂直同Space), a panel and memory interface circuit 216 (pand & fif〇 Circuit) and a clock generator 217 (a〇ckGeneratOT). The % pulse generator 217 can receive the clock signal CLKIN from the bus interface interface 4, and generate the operation clock required for the internal operation of the control circuit 21, and output the operation clock CLKIN to the local terminal bus control. The device 212' directly accesses the controller 211 and the panel and memory interface circuit 216 as the pulse signals required for operation. The control signal c generated by the panel controller 320 is first divided to form a bus bar address/data signal AD0~AD31 time-of-day data. The bus address/data signals AD0 to AD31 are first latched by the latch circuit 213, and then transmitted to the decoding cry 214 to generate the enable signal CS and the status signal R/w, which are transmitted to the configuration space 215, and then the configuration space. 215 can generate a configuration conforming to the bus interface 400 for the bus interface 4, so that the direct access controller 211 can communicate with the bus interface 400 with the corresponding communication protocol according to the configuration. . The panel and memory interface circuit 216 is configured to receive clock data, including a horizontal sync signal H-SYNC, a vertical sync signal VSYNC, a display enable signal de (Display Enable), and a pixel scan frequency dCLK (D〇t Q〇). Ck), the write energy signal FIFO_WR_ENABLE and the ___FIFawR_CLK are generated, so that the red, green and blue image data (R〇~R7, G〇~G7, BO B7) received by the first-in first-out memory 230 appears in the busbar The interface 4 (8) forms a bus bar address / data signal _ ~ AD31. In order to store the red, green and blue image data (R()~r7, (9)~(7), BO B7) at a specific moment into the first-in first-out § 忆忆 230, and then output to the bus interface 400 to form a bus The address/data signal, the red, green and blue image data R〇~R7, G〇~G?, B〇~B7 stored at each moment are formed in the bus interface interface 400 according to the timing to form the bus address/data signal Mo~ADy, A control data D that changes with time is formed. When the red, green and blue image data r〇~R7, G〇~G7, B〇~B7 are written into the advanced memory port 23, the panel and memory interface circuit 210 can simultaneously generate a touch. Tn^er) to the direct access controller 211 (DMA controller), through the direct access controller 211, the local end bus controller 212 sends a direct access nickname D·REQ (DMA Request) to the busbar Interface 400. After receiving the direct access request signal D., the bus interface 400 can issue a direct access authorization number D.GNT, so that the direct access controller 211 generates the bus control signal frame#, the bus line command/byte group enablement. The signals BE〇~BE3 and the master device prepare the domain IRDY# and other signals to the busbar s 4〇〇 to launch the FIFO cycle of the first-in first-out memory 12 200805211 230 to generate the aforementioned panel and memory interface circuit generation. The memory reads the clock FIFaRD-CLK, the memory read enable signal HFO-RD_ENABLE and other FIFO memory reading signals, so that the red, green and blue image data in the memory 230 is missing first R〇~R7 , G〇~G7, b〇~B7 The corresponding address on the sinking age is shaped like the lion's address/data signal side~AD3, which will constitute the red, green and blue image data of the scene in the moment. , G0~G7, B0~B7 are stored or applied. When the next field is generated, • the write cycle of the first-in first-out memory 230 can be repeated again, so that the red, green and blue image data R〇~R7, G〇 formed by the control signal c at each moment is made. ~G7, B0~B7 can form the bus address/data signal AD0~1 according to the timing on the bus interface interface 4, and are stored in the data type control data according to the timing for storage or application. According to the apparatus disclosed in the embodiment of the present invention, the present invention further provides (4) a method for extracting a gamma number for use in a panel of a display device 300. The controller 310 captures the control signal c and converts the control 'signal' to form the control data D, which is rotated through the bus interface. The method includes the following steps: power on or reset system Then, system initialization is performed (step 510). According to the number of addresses defined by the indicator in the FIFO memory 230, the loop count value (1〇〇pc〇unter value) is set by the bus " face 400, and the FIFO memory 230 is cleared. Write and read addresses defined by each indicator (step a). 13 200805211 Start-start loop 'determination bus interface interface 512), if the start command is received, _彳^, the start command (step to wait for 1) - if no, continue to wait for setting - vertical synchronization The signal VSYNC waits for the loop, and the step signal VSYNC is input to receive the vertical sync signal (step 'sudden has vertical same

設定-顯示致能信號DE等待迴圈，判斷是否有顯示致能作號DE輸入’以決定是否開始將紅綠藍影像資料助〜幻〜 G7、B0〜B7舄入先進先出記憶體23〇 (步驟5⑷。依據顯示致能信號DE及像素點掃_率DCLK，以控制帝路2H)產生寫入致能訊號齡魏孤避£及寫二二 FIFO-WR-CLK，使先進先出記憶體細接收之紅綠藍影像資料 R0〜R7、GG〜G7、B0〜B7，將紅綠藍影像資料rq〜r7、⑼〜 G7、B0〜B7寫入先進先出記憶體23〇中（步驟515)。判斷下-個的垂直同步域VSYNC是否處於高準位的啟動狀態（步，驟516)。若否’重新對寫入先進先出記憶體23〇進行寫入（步驟515)。若為是’代表所擷取影像#料為此—時刻中的垂直掃瞄線資料，則執行下一步驟，將資料輸出。以直接存取控制器211將直接存取請求信號D REQ設定為啟動狀態對匯流排介面4GG發出（步驟517)，等待匯流排介面_ 傳回直接存取認可信號D.GNT (步驟518)。以直接存取控制器211產生匯流排控制信號FRAME#、匯流排命令/位元組致能信號ΒΕ0〜BE3及主設備準備好信號IRDY# 14 200805211Set-display enable signal DE waiting for loop, determine whether there is a display enablement DE input ' to decide whether to start red, green and blue image data help ~ illusion ~ G7, B0 ~ B7 into the first-in first-out memory 23〇 (Step 5 (4). According to the display enable signal DE and the pixel sweep _ rate DCLK, to control the circuit 2H) to generate the write enable signal, the age of Wei, and the write of the second FIFO-WR-CLK, so that the first-in first-out memory Red, green and blue image data R0~R7, GG~G7, B0~B7 received by the body, and the red, green and blue image data rq~r7, (9)~G7, B0~B7 are written into the FIFO memory 23〇 (step 515). It is judged whether or not the next vertical sync domain VSYNC is in the high-level start state (step, step 516). If no, the write of the FIFO memory 23 is rewritten (step 515). If it is 'representing the captured image# for this purpose—the vertical scan line data at the time, the next step is executed to output the data. The direct access controller 211 sets the direct access request signal D REQ to the boot state to the bus interface 4GG (step 517), and waits for the bus interface _ to return the direct access acknowledge signal D.GNT (step 518). The bus bar control signal FRAME#, the bus sequence command/bit group enable signal ΒΕ0~BE3, and the master ready signal IRDY# 14 200805211 are generated by the direct access controller 211.

專仏號至匯流排介面400，同時以面板暨記憶體介面電路216產生記憶體讀，取時脈FIFO-RD-CLK、記憶體讀取致能信號 FIFO-RD-ENABLE等先進先出記憶體23〇的讀取信號，以發動先進先出記憶體230的讀出週期。依據像素計數值設定指標，使先進先出記鍾23G巾對賴指標的紅賴影像資料R()〜r7、g〇〜G7、BO〜B7傳輪至匯流排介面彻，而於匯流排介面形成匯流排地址/資料信號AD0〜AD31 (步驟519)。使迴圈計數值遞減（步驟520)，判斷迴圈計數值是否為零（步驟52D。若迴圈計數值不等於零，則重複執行上一步驟，雜連接匯流排介面之主控端電腦接收並記錄。若迴圈計數值為零，則代表先進先出記憶體230中的紅綠藍影像資料r〇〜R7、g〇〜g7、 B〇〜B7已經完全傳輸至匯流排介面彻，則執行下—步驟。停止由直接存取控制器211對匯流排介面請求信號D.REQ，產生一初料竹知出罝接存取定迴圈物Λ 2 (步驟522)。重複再進行設寫入及、位址^ Α記憶體挪之中由各指標定義的操取，以擷取下―垂直掃卿細現之影像n號致能訊細產生時之影像資料依時序傳輪至匯冷排ΓΓ 被儲存形成影像資料隨時序變化之_料D[為| _’而請再參閱「第6A圖」、「第狃圖據本發明__露之打，本發以^」所示，依擷取方法，包含有下列步驟：出弟—種面板控制訊號 15 200805211 啟動（Po體on)或重置（Reset)系統，接著進行系統初始化（步驟610)。清除先進先出記憶體230之中由夂沪妒丫田谷知祆疋義的寫入及讀取位址（步驟611)。設定-開始迴圈’到斷匯流排介面是否發出開始命令，若接收到開始命令’則執行下-步驟’若繼續等待（步驟 612)。 ”The nickname is connected to the bus interface 400, and the memory is read by the panel and memory interface circuit 216, and the first-in first-out memory such as the clock FIFO-RD-CLK and the memory read enable signal FIFO-RD-ENABLE are taken. The 23 读取 read signal is used to initiate the read cycle of the FIFO memory 230. According to the pixel count value setting index, the FIFO image of the FIFO clock 23G towel is used to transfer the red image data R()~r7, g〇~G7, BO~B7 to the bus interface, and the bus interface is in the bus interface. Busbar address/data signals AD0 to AD31 are formed (step 519). Decrease the loop count value (step 520), and determine whether the loop count value is zero (step 52D. If the loop count value is not equal to zero, repeat the previous step, and the host computer of the miscellaneous connection bus interface receives and Record. If the loop count value is zero, it means that the red, green and blue image data in the FIFO memory 230 r〇~R7, g〇~g7, B〇~B7 have been completely transmitted to the bus interface, then execute The next step is to stop the bus interface interface request signal D.REQ from the direct access controller 211, and generate a preliminary data access terminal 2 (step 522). And the address ^ Α memory movement is defined by the operation of each indicator, in order to take the image of the vertical image of the n-throwing ΓΓ Stored to form image data with timing changes _ material D [for | _' and please refer to "6A map", "the map according to the invention __露之打,本发以^", according to The method of capturing includes the following steps: Attendant-type panel control signal 15 200805211 Startup (Po The system is either on or reset, and then the system is initialized (step 610). The write-and-read address of the FIFO memory 230 is deleted from the 先妒丫妒丫 ( 谷 (step 611). Set - Start Loop' to whether the bus interrupt interface issues a start command, and if the start command is received, execute the next step - if it continues to wait (step 612).

设疋-垂直㈤步彳道VSYNC等待迴圈，判斷是^有垂直同步信號VSYNC輸入，以接收垂直同步訊號VSYNC (步驟SB)。設定-顯示致能信號DE等待迴圈，判斷是否有顯示致能信號DE輸入（步驟614)，以決定是否開始將紅綠藍影像資料〜R7、GO〜G7、B0〜B7寫入先進先出記憶體23〇。依據顯示致能信號DE及像素點掃瞄頻率DCLK，以控制電路210產生寫入致能訊號F正0-WR-ENABLE及寫入時脈 FIFO-WR-CLK，使先進先出記憶體230接收之紅綠藍影像資料 R0〜R7、G0〜G7、B0〜B7，將紅綠藍影像資料R〇〜R7、⑼〜 G7、B0〜B7寫入先進先出記憶體230中，對應一指標的位址中，此一指標對應一像素計數值。接著對像素計數值進行累加（步驟 615) 〇判斷此時刻的顯示致能信號DE是否處於低準位的關閉狀態。若否，重新對寫入先進先出記憶體230進行寫入（步驟615)，並進行像素計數值。若為是，則執行下一步驟，將資料輪出（步 16 200805211 驟 616 ) 〇以直接存取控制器211將直接存取請求信號D REQ設定為啟動狀態對匯流排介面400發出（步驟617)。判斷匯流排介面400是否傳回直接存取認可信號D (步驟618)。若是，執行下一步驟。若否，先判斷顯示致能信號de -、是否處於高準位的開啟狀態（步驟619)。如果顯示致能信號De •—仍為開啟狀態，則回歸先進先出記憶體230寫入步驟（步驟615)，驗將紅綠藍影像資料R0〜R7、G0〜G7、B0〜B7寫入先進先出記情體230中，並將累加過後的像素計數值作為位址指標將資料寫入新指標的位址中。如果顯示致能信號DE為關閉狀態，則代表先進先出§己憶體230的位址已被填入所有的影像資料，則繼續等待匯流排介面400傳回直接存取認可信號D.GNT。匯流排介面400傳回直接存取認可信號d.GNT (步驟618) 之後’以直接存取控制器211產生匯流排控制信號、匯馨流排命令/位元組致能信號ΒΕ0〜BE3及主設備準備好信號1虹)γ# 等信號至匯流排介面400，同時以面板暨記憶體介面電路216產生s己丨,¾體§買取日寸脈FJPO-RD-CLK、記憶體讀取致能信號 FIFO-RD-ENABLE等先進先出記憶體230的讀取信號，以發動先進先出§己憶體230的*1買出週期。依據像素計數值設定指標，使先進先出記憶體230中對應指標的資料，於匯流排介面4〇〇中形成匯流排地址/資料信號AD0〜AD31 (步驟620)。Let 疋-vertical (five) step VSYNC wait for the loop, and judge that there is a vertical sync signal VSYNC input to receive the vertical sync signal VSYNC (step SB). The setting-display enable signal DE waits for a loop to determine whether there is a display enable signal DE input (step 614) to determine whether to start writing the red, green and blue image data ~R7, GO~G7, B0~B7 to the first in first out Memory 23〇. According to the display enable signal DE and the pixel scanning frequency DCLK, the control circuit 210 generates the write enable signal F positive 0-WR-ENABLE and the write clock FIFO-WR-CLK to enable the first-in first-out memory 230 to receive The red, green and blue image data R0~R7, G0~G7, B0~B7, the red, green and blue image data R〇~R7, (9)~G7, B0~B7 are written into the FIFO memory 230, corresponding to an indicator In the address, this indicator corresponds to a pixel count value. Then, the pixel count value is accumulated (step 615) 〇 It is judged whether or not the display enable signal DE at this moment is in the off state of the low level. If not, the write to the FIFO memory 230 is rewritten (step 615), and the pixel count value is performed. If yes, the next step is executed, the data is rotated (step 16 200805211 step 616), and the direct access controller 211 sets the direct access request signal D REQ to the startup state to issue to the bus interface 400 (step 617). ). It is determined whether the bus interface 400 returns a direct access approval signal D (step 618). If yes, go to the next step. If not, it is first determined whether the display enable signal de - is in the on state of the high level (step 619). If the display enable signal De is still on, the return FIFO memory 230 write step (step 615), and the red, green and blue image data R0~R7, G0~G7, B0~B7 are written into the advanced First, in the case 230, the accumulated pixel count value is used as the address index to write the data into the address of the new indicator. If the display enable signal DE is off, the address representing the first-in first-out § 体 230 has been filled in all the image data, and then waits for the bus interface 400 to return the direct access approval signal D.GNT. The bus interface 400 returns the direct access approval signal d.GNT (step 618). Then, the bus controller control signal is generated by the direct access controller 211, and the bus flow command/byte enable signal ΒΕ0~BE3 and the main The device is ready to signal 1 rainbow) γ# and other signals to the bus interface 400, and the panel and memory interface circuit 216 generates s 丨丨, 3⁄4 body § buy the day pulse FJPO-RD-CLK, memory read enable The read signal of the first-in first-out memory 230 such as the signal FIFO-RD-ENABLE is used to launch the *1 purchase cycle of the first-in first-out suffix body 230. According to the pixel count value setting index, the data of the corresponding index in the first-in first-out memory 230 is formed into the bus address/data signals AD0 to AD31 in the bus interface interface 4 (step 620).

使像素計數值遞減（步驟621)。判斷垂直同步信號VSYNC 17 200805211 疋否仍處於開啟狀態（步驟622)。若為是，執行下一步驟，繼續進行先進先出記憶體230的讀出。若否，再度判斷顯示致能信號 DE是否處於低雜關驗態，叫定是否錄_先進先出記憶體230寫入步驟，或是繼續等待匯流排介面4〇〇傳回直接存取認可信號D_GNT。判斷像素計數值是否為零（步驟623)。若像素計數值不等於零’則發動先進先出記憶體230的讀出週期（步驟624)，接著遞減像素計數值（步驟625) ’錄比對像素計紐是私零（步驟 623)。若像素計數值為零’停止由直接存取控繼2ιι對匯流排介面400發出直接存取請求信號DR£q，產生一初始化訊號（步The pixel count value is decremented (step 621). It is judged that the vertical synchronizing signal VSYNC 17 200805211 is still in the on state (step 622). If so, the next step is executed to continue the reading of the FIFO memory 230. If not, it is judged again whether the display enable signal DE is in a low miscellaneous check state, whether to record the _first in first out memory 230 writing step, or continue to wait for the bus interface interface 4 to return the direct access approval signal. D_GNT. It is judged whether or not the pixel count value is zero (step 623). If the pixel count value is not equal to zero' then the read cycle of the first in first out memory 230 is initiated (step 624), and then the pixel count value is decremented (step 625). The pixel count is private zero (step 623). If the pixel count value is zero, the direct access request signal DR£q is sent to the bus interface 400 by the direct access control 2, and an initialization signal is generated.

驟625)。回歸至步驟610，清除先進先出記憶體23〇之中由各指標定義的寫人及讀取位址1複執行下—次面板控制訊號娜，以擷取下-衫觸職出狀f彡像麵。使每—次顯示致能訊號DE產生時之影像資料依時序於匯流排介面伽形成匯流排地址/資料信號AD0〜細，而被儲存形成影像資料隨時序變化之控制資料D。雖然本發日⑽前述之實_揭露如上，然其並_以限定本發明。在不脫離本發明之精神和範_，所為之更__，均所附之申請專利範圍【圖式簡單說明】屬本發明之細紐範圍。關於本發贿界定之保魏圍請參考第1圖習知技術中的影像處理祕的流程方塊圖； 18 200805211 弟2圖為本發明實施例之面板控制訊號擷取裝置與-顯示裝置連接之系統方塊圖；第3圖為本發明實施例之電路圖，· 第4圖為本發明實施例中’控制電路内部之電路圖；第5A圖及第5B圖為本發明所揭露之第一種面板控制訊取方法之流程方塊圖；及號擷Step 625). Returning to step 610, the write-on person and the read address defined by each index among the FIFOs 23 are cleared, and the next-sub-panel control signal is executed to take the next-shirt touch. Image side. The image data at the time when each display enable signal DE is generated is formed into a bus address/data signal AD0 to fine according to the bus interface interface gamma, and is stored to form a control data D of the image data as a function of time series. Although the foregoing disclosure of the present invention (10) is as above, it is intended to limit the present invention. Without departing from the spirit and scope of the present invention, the scope of the appended claims is hereby incorporated by reference. Please refer to the flow block diagram of the image processing secret in the prior art of FIG. 1 for the definition of the bribe definition of the present bribe; 18 200805211 2 is a panel control signal extraction device connected to the display device according to the embodiment of the present invention. FIG. 3 is a circuit diagram of an embodiment of the present invention, and FIG. 4 is a circuit diagram of the inside of the control circuit according to the embodiment of the present invention; FIGS. 5A and 5B are the first panel control disclosed in the present invention. Flow chart of the method of communication; and number 撷

第6A圖、第6B圖及第6C圖為本發明所揭露之〜一控制訊號擷取方法之流程方塊圖。罘一種面板【主要元件符號說明】 100 影像處理系統 110 類比數位轉換器 120 記憶體 130 縮放引擎 140 處理控制器 150 輸出介面 200 面板控制訊號擷取裝置 210 控制電路 211 直接存取控制器 212 本地端匯流排控制器 213 鎖存電路 214 解碼器 215 組態空間 19 200805211 216 面板暨記憶體介面電路 217 時脈產生器 220 接收單元 230 先進先出記憶體 300 顯示裝置 310 面板控制器 320 面板 400 匯流排介面 C 控制訊號 D 控制資料 FIFOWR-CLK 寫入時脈 FIFO-WR-ENABLE 寫入致能訊號 FIFO-RD-CLK 記憶體讀取時脈6A, 6B, and 6C are block diagrams showing a method for extracting control signals according to the present invention.罘One panel [Main component symbol description] 100 Image processing system 110 Analog-to-digital converter 120 Memory 130 Scaling engine 140 Processing controller 150 Output interface 200 Panel control signal acquisition device 210 Control circuit 211 Direct access controller 212 Local end Bus controller 213 latch circuit 214 decoder 215 configuration space 19 200805211 216 panel and memory interface circuit 217 clock generator 220 receiving unit 230 first in first out memory 300 display device 310 panel controller 320 panel 400 bus Interface C control signal D control data FIFOWR-CLK write clock FIFO-WR-ENABLE write enable signal FIFO-RD-CLK memory read clock

FIFO-RD-ENABLE 記憶體讀取致能信號 RX0+、RX0_、RX1+、RX1-、RX2+、RX2-、RX3+、RX3- 訊號接腳 HSYNC 水平同步信號 VSYNC 垂直同步信號 DE 顯示致能信號 DCLK 像素點掃瞄頻率 CLKIN 時脈訊號 AD0 〜AD31 匯流排地址/資料信號 20 200805211 R0 〜R7、GO 〜G7 、BO〜B7 紅綠監影像資料 CS 致能信號 R/W 狀態信號 D. REQ 直接存取請求信號 D.GNT 直接存取認可信號 FRAME# 匯流排控制信號 BEO 〜BE3 匯流排命令/位元組致能信號 IRDY# 主設備準備好信號 TRDY# 從設備準備好信號 21FIFO-RD-ENABLE memory read enable signal RX0+, RX0_, RX1+, RX1-, RX2+, RX2-, RX3+, RX3- signal pin HSYNC horizontal sync signal VSYNC vertical sync signal DE display enable signal DCLK pixel sweep Sight frequency CLKIN clock signal AD0 ~ AD31 bus address / data signal 20 200805211 R0 ~ R7, GO ~ G7, BO ~ B7 red green image data CS enable signal R / W status signal D. REQ direct access request signal D.GNT direct access approval signal FRAME# bus control signal BEO ~BE3 bus command / byte enable signal IRDY# master ready signal TRDY# slave ready signal 21

Claims

200805211 十、申請專利範圍： 1.:種面板控制訊號擷取I置.連接於_顯示裝置之面板控 ^，擷取該面板㈣n傳輸_控制峨，射該控制訊號包 3有-影像資料及__時脈· ’該時脈資料包含有—依時序產生之顯示魏喊，該面板控繼射域_示致能訊號產 S時之該影像資料使該顯示裝置產生-場晝面（關 ’ F^e)，該面板控觀號擷取裝置可觀錄像㈣形成一控泰 .]資料’透過―匯流排介面輸出n置包含有：一先進先出記憶體’肋供寫人該影像資料，並將寫入該影像資料傳輸至該匯流排介面；及 -控制電路’電連於魏進先出記憶體及該匯流排介面，該控制電料可於賴示致能職產生時啟_先進先出記憶體以寫人該影像資料’並傳輸至顧流齡面，使每一次該 -頁不致心ii餘生時之該影像資料依時序傳輸至該匯流排介 φ 面，而形成一控制資料。 2·如申明專利範圍第1項所述之面板控制訊!^擷取裝置，其中更 ⑽有—接收單元，用以將該控制訊號分割為該影像資料及該時脈資料。 3·如申凊專利細第2項所述之面板控制訊號操取裝置，其中該接收早兀制以將-低電壓差動訊號格式之該控制訊號轉換為一電晶體邏輯訊號。 4·如申明專利範圍第1項所述之面板控制訊號擷取裝置，其中該 22 200805211 控制電路係為一可程式化邏輯元件（CPLD，c〇mplex Programmable Logic Device)，用以供寫入預設程式以驅動該控制電路。 5.如申請專利範圍第1項所述之面板控制訊號擷取裝置，其中該控制電路係為一可程式化的邏輯晶片（FpGA， \ Field-Pr〇srammable Gate A^y)，用以供寫入預設程式以驅動 ^ - 該控制電路。 • 6·如申請專利範圍第1項所述之面板控制訊號擷取裝置，其中該控制電路係可依據該顯示致能訊號產生一寫入時脈及一寫入致能訊號，該寫入時脈係用以作為該先進先出記憶體的時序控制，該舄入致此訊號係用以啟動該先進先出記憶體之寫入週期。 7·如申請專利範圍第1項所述之面板控制訊號擷取裝置，其中該控制電路包含有： • 一面板暨記憶體介面電路（Panel & FIFO Interface Circuit)，用以接收該時脈資料，產生該寫入致能訊號及該寫入時脈而啟動該先進先出記憶體之寫入週期，並產生一觸發訊、，號；一本地端匯流排控制器（Local BUS Interface)，用以接收該觸發訊號，輯該匯流齡面發出—錢存取請求信號，並接收該匯流排介面發出一直接存取認可信號；直接存取控制器（DMAcontroller)，當該本地端匯流排 23 200805211 控制裔接收該直接存取認可信號之後，該直接存取控制器可產生匯流排控制信號、匯流排命令/位元組致能信號及主設備準備好彳δ號，於該匯流排介面形成匯流排地址/資料信號，以使該匯流排介面接收被寫入該先進先出記憶體之影像資料；及一時脈產生器（Clock Generator )，用以接收該匯流排介面產生之一時脈訊號，以作為該直接存取控制器、本地端匯流排控制裔及該面板暨記憶體介面電路運作時所需要之運作時脈。 8·如申請專利範圍第7項所述之面板控制訊號擷取裝置，其中該控制電路更包含有：一鎖存電路（Address Latch )，該影像資料先由鎖存電路鎖存之後對外傳輸；一解碼器（Decoder)，用以接收該鎖存器鎖存之該影像資料，而產生一致能信號及一狀態信號；及一組態空間（Configuration Space)，用以接收該致能信號及該狀態信號，產生一符合該匯流排介面的組態。 9·如申請專利範圍第7項所述之面板控制訊號擷取裝置，其中於該影像資料傳輸至該匯流排介面之後，該面板暨記憶體介面電路可接收該匯流排介面回傳之一從設備準備好信號，以結束該先進先出土丨思體的舄入週期，並關閉該直接存取控制哭。 10· —種面板控制訊號擷取方法，用以由一顯示裝置之面板控制器娜該面健制猶輸之-控繼號，可轉_鋪訊號形成 -控制資料，透過-匯流排介面輸出，其中該控制訊號包含有 24 200805211 一影像資料、一垂直同步訊號及一顯示致能訊號，該面板控制器係可依據該顯示致能訊號產生時之該影像資料使該顯示裝置產生一場畫面（FieldFrame)，該方法包含有下列步驟：接收該垂直同步訊號及該顯示致能信號，以啟動一先進先出記憶體之寫入週期；依據該顯示致能信號產生一寫入致能訊號及一寫入時脈，使該先進先出記憶體影像資料寫入；對該匯流排介面發出一直接存取請求信號，使該匯流排介面傳回一直接存取認可信號；及於接收該直接存取認可信號之後，發動該先進先出記憶體的項出週期，使該先進先出記憶體中的資料於該匯流排介面形成匯流排地址/資料信號，將每一次該顯示致能訊號產生時之影像資料依時序傳輸至該匯流排介面，而被儲存形成該影像資料隨時序變化之該控制資料。 U·如申請專利範圍第10項所述之面板控制訊號擷取方法，其中更包含有一步驟迴圈，係先由該匯流排介面設定一迴圈計數值’用以作為一位址指標，使該先進先出記憶體對應該指標的衫像資料於該匯流排介面形成匯流排地址/資料信號，接著使 σ亥迴圈计數值遞減’重複該先進先出記憶體對應該指標的影像資料於該匯流排介面形成匯流排地址/資料信號。 2·如申請專利範圍第1〇項所述之面板控制訊號擷取方法，其中更包含有定義一像素計數值，用以作為一位址指標，使該影像 25 200805211 資料寫入該先進先出記憶體對座击#, 艰對應中該指標的位址，接著對該像素計數值進行累加，重複進行号Γ旦“多一， .. 夂^丁 β衫像貧料寫入該先進先出記憶體對應中該位址指標的位址。 " 13·如申请專利範圍第12項所述之面板控制訊號擷取方法，其中發動该先進先出s己憶體的言買出週期之步驟包含有一步驟迴圈： ’ · 依據該像素計數值設定該位址指標指標，使該先進先出記，· 憶體中對應位址指標的資料於該匯流排介面中出現，接著使該 • 像素計數值遞減，重複使該先進先出記憶體中對應位址指標的資料於該匯流排介面。200805211 X. Patent application scope: 1.: Panel control signal capture I. Connect to the panel control of the display device, select the panel (4) n transmission _ control 峨, shoot the control signal packet 3 - image data and __clock· 'The clock data contains—the display generated by the time series Wei, the panel controls the field _ indicates that the image data when the signal is generated S causes the display device to generate a field surface (off) 'F^e), the panel-controlled view number capture device can watch the video (4) form a control.] The data 'through the bus interface output n set contains: a first-in first-out memory' rib for the person to write the image data And transmitting the image data to the bus interface; and - the control circuit is electrically connected to the Weijin first-out memory and the bus interface, and the control material can be activated when the enabling position is generated. The memory is written to write the image data and transmitted to the Gu Runling surface, so that the image data is transmitted to the bus surface φ surface in time series every time the page is not in the heart, thereby forming a control data. 2. The panel control device according to claim 1 of the patent scope, wherein the (10) receiving-receiving unit is configured to divide the control signal into the image data and the clock data. 3. The panel control signal manipulation device of claim 2, wherein the receiving is early to convert the control signal in the low-voltage differential signal format into a transistor logic signal. 4. The panel control signal acquisition device according to claim 1, wherein the 22 200805211 control circuit is a programmable logic component (CPLD) for writing A program is provided to drive the control circuit. 5. The panel control signal acquisition device according to claim 1, wherein the control circuit is a programmable logic chip (FpGA, \ Field-Pr〇srammable Gate A^y) for Write the preset program to drive ^ - the control circuit. 6. The panel control signal capture device of claim 1, wherein the control circuit generates a write clock and a write enable signal according to the display enable signal. The pulse system is used as the timing control of the FIFO memory, and the signal is used to initiate the write cycle of the FIFO memory. 7. The panel control signal capture device of claim 1, wherein the control circuit comprises: • a panel & FIFO interface circuit for receiving the clock data Generating the write enable signal and the write clock to initiate a write cycle of the FIFO memory and generate a trigger signal, a local BUS Interface, Receiving the trigger signal, collecting the money flow request signal, and receiving a direct access approval signal from the bus interface; directly accessing the controller (DMA controller), when the local terminal bus 23 200805211 After receiving the direct access acknowledgement signal, the direct access controller may generate a bus control signal, a bus command/bit enable signal, and the master device prepares a 彳δ number to form a convergence on the bus interface. Address/data signals such that the bus interface receives image data written to the FIFO memory; and a clock generator The receiving of the bus interface generates a clock signal as a working clock required for the direct access controller, the local bus, and the panel and memory interface circuit. 8. The panel control signal capture device of claim 7, wherein the control circuit further comprises: a latch circuit (Address Latch), the image data is first latched by the latch circuit and then transmitted externally; a decoder (Decoder) for receiving the image data latched by the latch to generate a consistent energy signal and a status signal; and a configuration space for receiving the enable signal and the The status signal produces a configuration that conforms to the bus interface. 9. The panel control signal capture device of claim 7, wherein the panel and memory interface circuit can receive one of the bus interface backhauls after the image data is transmitted to the bus interface The device is ready to signal to end the intrusion cycle of the FIFO, and turn off the direct access control cry. 10·--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- The control signal includes a video data of 24 200805211, a vertical sync signal, and a display enable signal. The panel controller can cause the display device to generate a picture according to the image data when the display enable signal is generated ( FieldFrame), the method includes the following steps: receiving the vertical sync signal and the display enable signal to initiate a write cycle of a first-in first-out memory; generating a write enable signal and a signal according to the display enable signal Writing a clock to write the FIFO memory image data; issuing a direct access request signal to the bus interface interface, causing the bus interface interface to return a direct access approval signal; and receiving the direct storage After taking the approval signal, launching the item ejection period of the FIFO memory, so that the data in the FIFO memory forms a bus bar in the bus interface interface Address / data signal, each time when image data of the display enabling signal is generated by the transmission timing to the bus interface, the image is formed resource materials stored sequence changes at any of the control information. U. The panel control signal acquisition method described in claim 10, further comprising a step loop, wherein the loop count value is first set by the bus interface interface as an address indicator. The FIFO memory corresponding to the indicator image data forms a bus address/data signal in the bus interface, and then the Sigma threshold is decremented by repeating the image data of the FIFO memory corresponding to the indicator. The bus interface forms a bus address/data signal. 2. The method for extracting the panel control signal according to the first aspect of the patent application, further comprising defining a pixel count value for use as an address indicator to write the image 25 200805211 data to the first in first out The memory pair hits #, the address corresponding to the indicator in the hard, and then accumulates the pixel count value, repeating the number "Done, .. 夂^丁β衫 is like the poor material written in the first in first out The memory corresponds to the address of the address indicator. " 13· The method for extracting the panel control signal according to item 12 of the patent application scope, wherein the step of initiating the purchase cycle of the first-in-first-out suffix The method includes a step loop: ' · setting the address index indicator according to the pixel count value, so that the data of the corresponding address index in the first in first occurrence, the memory element appears in the bus interface, and then the pixel is made The count value is decremented, and the data of the corresponding address indicator in the FIFO memory is repeated in the bus interface.

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