TW200742965A - System and method for power on-reset - Google Patents

System and method for power on-reset

Info

Publication number
TW200742965A
TW200742965A TW095133840A TW95133840A TW200742965A TW 200742965 A TW200742965 A TW 200742965A TW 095133840 A TW095133840 A TW 095133840A TW 95133840 A TW95133840 A TW 95133840A TW 200742965 A TW200742965 A TW 200742965A
Authority
TW
Taiwan
Prior art keywords
value
state
reset
predetermined
counter value
Prior art date
Application number
TW095133840A
Other languages
Chinese (zh)
Other versions
TWI323404B (en
Inventor
Chun-Yen Chou
Original Assignee
Taiwan Semiconductor Mfg Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg Co Ltd filed Critical Taiwan Semiconductor Mfg Co Ltd
Publication of TW200742965A publication Critical patent/TW200742965A/en
Application granted granted Critical
Publication of TWI323404B publication Critical patent/TWI323404B/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Electronic Switches (AREA)
  • Retry When Errors Occur (AREA)

Abstract

A method and system is disclosed for creating a timing delay for power-on reset. A state machine is formed with three states. It resets a counter value to a predetermined number in an initial state, and increments the counter value for a predetermined number of reset cycles in a reset state until the counter value reaches a predetermined value for creating the timing delay, and ends the reset state in a finish state if the counter reaches the predetermined value and if a randomly generated value matches a predetermined signature, wherein if in the reset state the randomly generated value does not match the signature or if in the finish state either the counter value does not reach the predetermined value or the randomly generated value does not match the signature, the initial state starts and subsequently enters the reset state after resetting the counter value.
TW095133840A 2006-05-01 2006-09-13 System and method for power on-reset TWI323404B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/414,862 US7348815B2 (en) 2006-05-01 2006-05-01 All-digital power-on reset device

Publications (2)

Publication Number Publication Date
TW200742965A true TW200742965A (en) 2007-11-16
TWI323404B TWI323404B (en) 2010-04-11

Family

ID=38647756

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095133840A TWI323404B (en) 2006-05-01 2006-09-13 System and method for power on-reset

Country Status (2)

Country Link
US (1) US7348815B2 (en)
TW (1) TWI323404B (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7710105B2 (en) * 2006-03-14 2010-05-04 Atmel Corporation Circuit reset testing methods
US7519486B2 (en) * 2006-03-31 2009-04-14 Atmel Corporation Method and apparatus to test the power-on-reset trip point of an integrated circuit
US8198925B1 (en) 2008-12-12 2012-06-12 Marvell International Ltd. Digital power on reset
US8493109B2 (en) 2010-03-31 2013-07-23 Qualcomm Incorporated System and method to control a power on reset signal
US9081556B2 (en) 2012-06-26 2015-07-14 Apple Inc. Power on reset detector
US9218029B2 (en) * 2012-10-22 2015-12-22 Infineon Technologies Ag Method and system for resetting a SoC
FR3103069B1 (en) 2019-11-13 2021-10-01 Idemia Identity & Security France Device for delivering a signal passing from a first state to a second state
WO2021113787A1 (en) 2019-12-06 2021-06-10 Lattice Semiconductor Corporation Adaptive power-on-reset generator systems and methods for programmable logic devices

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6173436B1 (en) * 1997-10-24 2001-01-09 Vlsi Technology, Inc. Standard cell power-on-reset circuit
US6278302B1 (en) * 1999-06-03 2001-08-21 Agere Systems Guardian Corp. Digital power-up reset circuit
US8395426B2 (en) * 2005-05-19 2013-03-12 Broadcom Corporation Digital power-on reset controller

Also Published As

Publication number Publication date
US7348815B2 (en) 2008-03-25
TWI323404B (en) 2010-04-11
US20070252626A1 (en) 2007-11-01

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees