TW200741948A - Method and system for wafer backside alignment - Google Patents

Method and system for wafer backside alignment

Info

Publication number
TW200741948A
TW200741948A TW095132490A TW95132490A TW200741948A TW 200741948 A TW200741948 A TW 200741948A TW 095132490 A TW095132490 A TW 095132490A TW 95132490 A TW95132490 A TW 95132490A TW 200741948 A TW200741948 A TW 200741948A
Authority
TW
Taiwan
Prior art keywords
substrate
front side
wafer
wafer backside
backside alignment
Prior art date
Application number
TW095132490A
Other languages
Chinese (zh)
Other versions
TWI317981B (en
Inventor
Sheng-Chieh Liu
Chia-Hung Kao
Tzu-Yang Wu
Sheng-Liang Pan
Yuan-Bang Lee
Original Assignee
Taiwan Semiconductor Mfg Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg Co Ltd filed Critical Taiwan Semiconductor Mfg Co Ltd
Publication of TW200741948A publication Critical patent/TW200741948A/en
Application granted granted Critical
Publication of TWI317981B publication Critical patent/TWI317981B/en

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00555—Achieving a desired geometry, i.e. controlling etch rates, anisotropy or selectivity
    • B81C1/00603—Aligning features and geometries on both sides of a substrate, e.g. when double side etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

Disclosed is a method and a system for wafer alignment. A zero mark patterning is on front side of a substrate. A plurality of layers are deposited on the front side of the substrate. The wafer is flipped over with backside of the substrate facing up, and a through wafer etching is performed from the backside to an etch stop layer deposited over the front side of the substrate.
TW095132490A 2006-04-24 2006-09-01 Method and system for wafer backside alignment TWI317981B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/409,582 US7611960B2 (en) 2006-04-24 2006-04-24 Method and system for wafer backside alignment

Publications (2)

Publication Number Publication Date
TW200741948A true TW200741948A (en) 2007-11-01
TWI317981B TWI317981B (en) 2009-12-01

Family

ID=38619992

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095132490A TWI317981B (en) 2006-04-24 2006-09-01 Method and system for wafer backside alignment

Country Status (2)

Country Link
US (1) US7611960B2 (en)
TW (1) TWI317981B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102024689B (en) * 2009-09-11 2012-09-19 中芯国际集成电路制造(上海)有限公司 Method for improving aligning performance in polysilicon grid making technology

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7611960B2 (en) 2006-04-24 2009-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Method and system for wafer backside alignment
US7494830B2 (en) * 2007-04-06 2009-02-24 Taiwan Semiconductor Manufacturing Company Method and device for wafer backside alignment overlay accuracy
US8846494B2 (en) 2011-07-07 2014-09-30 Aptina Imaging Corporation Alignment marks and alignment methods for aligning backside components to frontside components in integrated circuits
TWI570873B (en) * 2013-02-20 2017-02-11 聯華電子股份有限公司 Semiconductor structure and manufacturing method for the same
US9105644B2 (en) 2013-07-23 2015-08-11 Analog Devices, Inc. Apparatus and method for forming alignment features for back side processing of a wafer
US11043437B2 (en) 2019-01-07 2021-06-22 Applied Materials, Inc. Transparent substrate with light blocking edge exclusion zone

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5354695A (en) 1992-04-08 1994-10-11 Leedy Glenn J Membrane dielectric isolation IC fabrication
US5757507A (en) 1995-11-20 1998-05-26 International Business Machines Corporation Method of measuring bias and edge overlay error for sub-0.5 micron ground rules
US5929997A (en) 1997-07-02 1999-07-27 Winbond Electronics Corp. Alignment-mark measurements on the backside of a wafer for synchronous wafer alignment
US6380554B1 (en) 1998-06-08 2002-04-30 Advanced Micro Devices, Inc. Test structure for electrically measuring the degree of misalignment between successive layers of conductors
US6393714B1 (en) 2000-02-25 2002-05-28 Xilinx, Inc. Resistor arrays for mask-alignment detection
US6383827B1 (en) 2000-04-17 2002-05-07 Advanced Micro Devices, Inc. Electrical alignment test structure using local interconnect ladder resistor
US6423555B1 (en) 2000-08-07 2002-07-23 Advanced Micro Devices, Inc. System for determining overlay error
US7068833B1 (en) 2000-08-30 2006-06-27 Kla-Tencor Corporation Overlay marks, methods of overlay mark design and methods of overlay measurements
US7099011B2 (en) 2000-12-08 2006-08-29 Litel Instruments Method and apparatus for self-referenced projection lens distortion mapping
US7261983B2 (en) 2000-12-08 2007-08-28 Litel Instruments Reference wafer and process for manufacturing same
US6833221B2 (en) 2001-01-05 2004-12-21 Litel Instruments Method and apparatus for proper ordering of registration data
US6525805B2 (en) 2001-05-14 2003-02-25 Ultratech Stepper, Inc. Backside alignment system and method
US6856029B1 (en) 2001-06-22 2005-02-15 Lsi Logic Corporation Process independent alignment marks
US6716559B2 (en) 2001-12-13 2004-04-06 International Business Machines Corporation Method and system for determining overlay tolerance
US6829814B1 (en) * 2002-08-29 2004-12-14 Delphi Technologies, Inc. Process of making an all-silicon microphone
JP4353685B2 (en) 2002-09-18 2009-10-28 株式会社ルネサステクノロジ Semiconductor device
SG121844A1 (en) 2002-12-20 2006-05-26 Asml Netherlands Bv Device manufacturing method
US7084427B2 (en) 2003-06-10 2006-08-01 International Business Machines Corporation Systems and methods for overlay shift determination
US6861186B1 (en) * 2003-09-25 2005-03-01 International Business Machines Corporation Method for backside alignment of photo-processes using standard front side alignment tools
US6952886B1 (en) 2003-11-10 2005-10-11 1St Silicon (Malaysia) Sdn Bhd Overlay vernier
US6967709B2 (en) 2003-11-26 2005-11-22 International Business Machines Corporation Overlay and CD process window structure
WO2005122262A1 (en) * 2004-06-09 2005-12-22 Koninklijke Philips Electronics N.V. Method of manufacturing an image sensor and image sensor
US7251018B2 (en) * 2004-11-29 2007-07-31 Asml Netherlands B.V. Substrate table, method of measuring a position of a substrate and a lithographic apparatus
US20060249859A1 (en) 2005-05-05 2006-11-09 Eiles Travis M Metrology system and method for stacked wafer alignment
US7898095B2 (en) 2006-03-20 2011-03-01 Tezzaron Semiconductor, Inc. Fiducial scheme adapted for stacked integrated circuits
US7611960B2 (en) 2006-04-24 2009-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Method and system for wafer backside alignment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102024689B (en) * 2009-09-11 2012-09-19 中芯国际集成电路制造(上海)有限公司 Method for improving aligning performance in polysilicon grid making technology

Also Published As

Publication number Publication date
TWI317981B (en) 2009-12-01
US20070249137A1 (en) 2007-10-25
US7611960B2 (en) 2009-11-03

Similar Documents

Publication Publication Date Title
TW200741948A (en) Method and system for wafer backside alignment
WO2005008745A3 (en) Selective etching of silicon carbide films
WO2008016650A3 (en) Methods of forming carbon-containing silicon epitaxial layers
TW200802536A (en) Method of manufacturing semiconductor device
TW200723440A (en) Method for forming trench using hard mask with high selectivity and isolation method for semiconductor device using the same
WO2011017339A3 (en) Methods of selectively depositing an epitaxial layer
WO2007117583A3 (en) Cluster tool for epitaxial film formation
TW200739972A (en) Light-emitting device and method for manufacturing the same
WO2006004693A3 (en) Method for bilayer resist plasma etch
TW200744241A (en) Method of making an encapsulated plasma sensitive device
WO2009076322A3 (en) Methods and devices for processing a precursor layer in a group via environment
WO2005091974A3 (en) Methods for the optimization of substrate etching in a plasma processing system
TW200629374A (en) Patterning substrates employing multi-film layers defining etch-differential interfaces
TW200618174A (en) Method of manufacturing semiconductor device
WO2008005377A3 (en) Selective spacer formation on transistors of different classes on the same device
TW200834245A (en) Method for manufacturing semiconductor device with four-layered laminate
WO2009077538A3 (en) Process of assembly with buried marks
WO2010009295A3 (en) Hybrid heterojunction solar cell fabrication using a metal layer mask
TW200741376A (en) Dynamic compensation system for maskless lithography
WO2009092799A3 (en) Object comprising a graphics element transferred onto a support wafer and method of producing such an object
MX2010007723A (en) Plasma-treated photovoltaic devices.
WO2009116830A3 (en) Semiconductor device and a fabrication method therefor
TW200644099A (en) Method of segmenting a wafer
WO2011028957A3 (en) Methods and devices for processing a precursor layer in a group via environment
WO2007147075A3 (en) Patterning 3d features in a substrate

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees