TW200728983A - Memory access request arbitration - Google Patents

Memory access request arbitration

Info

Publication number
TW200728983A
TW200728983A TW095145295A TW95145295A TW200728983A TW 200728983 A TW200728983 A TW 200728983A TW 095145295 A TW095145295 A TW 095145295A TW 95145295 A TW95145295 A TW 95145295A TW 200728983 A TW200728983 A TW 200728983A
Authority
TW
Taiwan
Prior art keywords
access request
memory access
memory
page
interval
Prior art date
Application number
TW095145295A
Other languages
English (en)
Inventor
Stevev J Kommrusch
Brett A Tischler
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of TW200728983A publication Critical patent/TW200728983A/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G06F13/1631—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests through address comparison
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
TW095145295A 2005-12-09 2006-12-06 Memory access request arbitration TW200728983A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/297,856 US7426621B2 (en) 2005-12-09 2005-12-09 Memory access request arbitration

Publications (1)

Publication Number Publication Date
TW200728983A true TW200728983A (en) 2007-08-01

Family

ID=37865831

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095145295A TW200728983A (en) 2005-12-09 2006-12-06 Memory access request arbitration

Country Status (8)

Country Link
US (1) US7426621B2 (zh)
JP (1) JP2009518753A (zh)
KR (1) KR20080075910A (zh)
CN (1) CN101326504B (zh)
DE (1) DE112006003358B4 (zh)
GB (1) GB2446997B (zh)
TW (1) TW200728983A (zh)
WO (1) WO2007067739A1 (zh)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7353317B2 (en) * 2004-12-28 2008-04-01 Intel Corporation Method and apparatus for implementing heterogeneous interconnects
JP5261993B2 (ja) * 2007-06-15 2013-08-14 富士通セミコンダクター株式会社 ディスプレイ制御回路およびディスプレイ装置
TWI385634B (zh) * 2008-04-02 2013-02-11 Novatek Microelectronics Corp 用於一液晶顯示器控制器之微處理器裝置及相關方法
US8266393B2 (en) * 2008-06-04 2012-09-11 Microsoft Corporation Coordination among multiple memory controllers
JP5380322B2 (ja) * 2010-02-17 2014-01-08 京セラドキュメントソリューションズ株式会社 メモリマスタデバイス
US8572322B2 (en) * 2010-03-29 2013-10-29 Freescale Semiconductor, Inc. Asynchronously scheduling memory access requests
US8560796B2 (en) * 2010-03-29 2013-10-15 Freescale Semiconductor, Inc. Scheduling memory access requests using predicted memory timing and state information
KR101292309B1 (ko) * 2011-12-27 2013-07-31 숭실대학교산학협력단 반도체칩 및 메모리 제어방법, 그리고 그 방법을 컴퓨터에서 실행시키기 위한 프로그램을 기록한 기록매체
CN104067309A (zh) * 2011-12-28 2014-09-24 英特尔公司 流水线化的图像处理序列发生器
US8751830B2 (en) * 2012-01-23 2014-06-10 International Business Machines Corporation Memory address translation-based data encryption/compression
WO2014147769A1 (ja) * 2013-03-19 2014-09-25 富士通株式会社 制御装置、デバイスアクセス方法、デバイスアクセスプログラム及び情報処理装置
GB2522653A (en) 2014-01-31 2015-08-05 Ibm Bridge and method for coupling a requesting interconnect and a serving interconnect in a computer system
TWI553483B (zh) * 2014-10-13 2016-10-11 瑞昱半導體股份有限公司 處理器及存取記憶體的方法
US10684969B2 (en) 2016-07-15 2020-06-16 Advanced Micro Devices, Inc. Command arbitration for high speed memory interfaces
US10402937B2 (en) 2017-12-28 2019-09-03 Nvidia Corporation Multi-GPU frame rendering
CN110729006B (zh) 2018-07-16 2022-07-05 超威半导体(上海)有限公司 存储器控制器中的刷新方案

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5440752A (en) * 1991-07-08 1995-08-08 Seiko Epson Corporation Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU
JPH0660008A (ja) * 1992-08-07 1994-03-04 Hitachi Cable Ltd ２ポートメモリ
US5822772A (en) 1996-03-22 1998-10-13 Industrial Technology Research Institute Memory controller and method of memory access sequence recordering that eliminates page miss and row miss penalties
US6145065A (en) * 1997-05-02 2000-11-07 Matsushita Electric Industrial Co., Ltd. Memory access buffer and reordering apparatus using priorities
US6088772A (en) * 1997-06-13 2000-07-11 Intel Corporation Method and apparatus for improving system performance when reordering commands
GB9719047D0 (en) 1997-09-08 1997-11-12 Sgs Thomson Microelectronics Arbitration system
JPH11165454A (ja) * 1997-12-04 1999-06-22 Canon Inc 画像処理装置及び画像処理システム
JPH11194995A (ja) * 1997-12-26 1999-07-21 Mitsubishi Electric Corp Ｄｒａｍ内蔵マイクロプロセッサ及びｄｒａｍ内蔵マイクロプロセッサのデータ転送方法
US6052756A (en) * 1998-01-23 2000-04-18 Oki Electric Industry Co., Ltd. Memory page management
JP2002049580A (ja) * 2000-08-02 2002-02-15 Mitsubishi Electric Corp バス管理装置、バス使用要求送信装置、バス管理方法、及びバス使用要求送信方法
US6564304B1 (en) * 2000-09-01 2003-05-13 Ati Technologies Inc. Memory processing system and method for accessing memory including reordering memory requests to reduce mode switching
US6625700B2 (en) * 2001-05-31 2003-09-23 Sun Microsystems, Inc. Arbitration and select logic for accessing a shared memory
EP1412864A1 (en) * 2001-07-18 2004-04-28 Koninklijke Philips Electronics N.V. Non-volatile memory arrangement and method in a multiprocessor device
US6785793B2 (en) * 2001-09-27 2004-08-31 Intel Corporation Method and apparatus for memory access scheduling to reduce memory access latency
US7035984B2 (en) * 2001-12-31 2006-04-25 Intel Corporation Memory arbiter with grace and ceiling periods and intelligent page gathering logic
US6799257B2 (en) 2002-02-21 2004-09-28 Intel Corporation Method and apparatus to control memory accesses
US6880028B2 (en) * 2002-03-18 2005-04-12 Sun Microsystems, Inc Dynamic request priority arbitration
JP4344163B2 (ja) * 2002-04-17 2009-10-14 パナソニック株式会社 資源要求調停装置、資源要求調停方法、及び、コンピュータプログラム
US7404047B2 (en) * 2003-05-27 2008-07-22 Intel Corporation Method and apparatus to improve multi-CPU system performance for accesses to memory

Also Published As

Publication number Publication date
CN101326504B (zh) 2012-04-25
JP2009518753A (ja) 2009-05-07
DE112006003358T5 (de) 2008-10-02
GB2446997B (en) 2010-11-10
CN101326504A (zh) 2008-12-17
GB0811767D0 (en) 2008-07-30
KR20080075910A (ko) 2008-08-19
GB2446997A (en) 2008-08-27
DE112006003358B4 (de) 2022-08-04
US20070136545A1 (en) 2007-06-14
US7426621B2 (en) 2008-09-16
WO2007067739A1 (en) 2007-06-14

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