TW200725850A - Chip package having a slot type metal film carrying a wire-bonding chip - Google Patents

Chip package having a slot type metal film carrying a wire-bonding chip

Info

Publication number
TW200725850A
TW200725850A TW094147665A TW94147665A TW200725850A TW 200725850 A TW200725850 A TW 200725850A TW 094147665 A TW094147665 A TW 094147665A TW 94147665 A TW94147665 A TW 94147665A TW 200725850 A TW200725850 A TW 200725850A
Authority
TW
Taiwan
Prior art keywords
chip
film substrate
metal core
patterned metal
wire
Prior art date
Application number
TW094147665A
Other languages
Chinese (zh)
Other versions
TWI283472B (en
Inventor
Ping-Hua Chu
Original Assignee
Walton Advanced Eng Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Walton Advanced Eng Inc filed Critical Walton Advanced Eng Inc
Priority to TW094147665A priority Critical patent/TWI283472B/en
Application granted granted Critical
Publication of TW200725850A publication Critical patent/TW200725850A/en
Publication of TWI283472B publication Critical patent/TWI283472B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Non-Reversible Transmitting Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

A chip package, which includes a film substrate with a slot carrying a wire-bonding chip to be Chip-On-Board (COB) packaging configuration. Therein, the slot is used for passing through bonding wires to electrically connect the chip and the film substrate. The film substrate includes a patterned metal core and at least a surface dielectric layer. The patterned metal core has a plurality of inner fingers disposed around the slot and a plurality of outer pads. Since the active surface of the chip is adhered to the film substrate to extremely adjacent to the patterned metal core, the patterned metal core can offer an excellent chip heat-dissipating path. In addition, the chip package utilizing the film substrate has the advantages of cost-down of substrate, reduction of package thickness, and improvement of resistance of thermal stress.
TW094147665A 2005-12-30 2005-12-30 Chip package having a slot type metal film carrying a wire-bonding chip TWI283472B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW094147665A TWI283472B (en) 2005-12-30 2005-12-30 Chip package having a slot type metal film carrying a wire-bonding chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW094147665A TWI283472B (en) 2005-12-30 2005-12-30 Chip package having a slot type metal film carrying a wire-bonding chip

Publications (2)

Publication Number Publication Date
TW200725850A true TW200725850A (en) 2007-07-01
TWI283472B TWI283472B (en) 2007-07-01

Family

ID=39428188

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094147665A TWI283472B (en) 2005-12-30 2005-12-30 Chip package having a slot type metal film carrying a wire-bonding chip

Country Status (1)

Country Link
TW (1) TWI283472B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI700786B (en) * 2018-03-28 2020-08-01 南茂科技股份有限公司 Chip-on-film package structure

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI416687B (en) * 2010-12-28 2013-11-21 Powertech Technology Inc Substrate strip with thinned plating layer at mold gate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI700786B (en) * 2018-03-28 2020-08-01 南茂科技股份有限公司 Chip-on-film package structure

Also Published As

Publication number Publication date
TWI283472B (en) 2007-07-01

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees