TW200725764A - Method of wire bonding the chip with a plurality of solder pads - Google Patents

Method of wire bonding the chip with a plurality of solder pads

Info

Publication number
TW200725764A
TW200725764A TW094146214A TW94146214A TW200725764A TW 200725764 A TW200725764 A TW 200725764A TW 094146214 A TW094146214 A TW 094146214A TW 94146214 A TW94146214 A TW 94146214A TW 200725764 A TW200725764 A TW 200725764A
Authority
TW
Taiwan
Prior art keywords
wire bonding
chip
pad
solder pads
pads
Prior art date
Application number
TW094146214A
Other languages
Chinese (zh)
Other versions
TWI282133B (en
Inventor
Sheng-Hsiung Chen
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW094146214A priority Critical patent/TWI282133B/en
Application granted granted Critical
Publication of TWI282133B publication Critical patent/TWI282133B/en
Publication of TW200725764A publication Critical patent/TW200725764A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

The present invention relates to a method of wire bonding, particularly relates to a method of wire bonding the chip with a plurality of solder pads. The inner solder pads can be wire bonded to the ground pads or power pads on the substrate by the method of wire bonding and without touching between the conductive metal lines. Thereof, in the present invention, the short caused by the touching between the conductive metal lines is also prevented. In the method of wire bonding of the present invention, a pad on the chip is used as a dummy pad and the inner pad on the chip is wiring bonded to the ground pad or power pad through the dummy pad.
TW094146214A 2005-12-23 2005-12-23 Method of wire bonding the chip with a plurality of solder pads TWI282133B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW094146214A TWI282133B (en) 2005-12-23 2005-12-23 Method of wire bonding the chip with a plurality of solder pads

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW094146214A TWI282133B (en) 2005-12-23 2005-12-23 Method of wire bonding the chip with a plurality of solder pads

Publications (2)

Publication Number Publication Date
TWI282133B TWI282133B (en) 2007-06-01
TW200725764A true TW200725764A (en) 2007-07-01

Family

ID=38777619

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094146214A TWI282133B (en) 2005-12-23 2005-12-23 Method of wire bonding the chip with a plurality of solder pads

Country Status (1)

Country Link
TW (1) TWI282133B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI715234B (en) * 2019-10-04 2021-01-01 瑞昱半導體股份有限公司 Chip package module
CN112271168A (en) * 2020-10-28 2021-01-26 广州立景创新科技有限公司 Circuit structure
TWI760708B (en) * 2019-03-13 2022-04-11 日商新川股份有限公司 Wire-bonding failure inspection system, wire-bonding failure detection device, and wire-bonding failure detection method
TWI816499B (en) * 2022-08-03 2023-09-21 矽品精密工業股份有限公司 Electronic package

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI760708B (en) * 2019-03-13 2022-04-11 日商新川股份有限公司 Wire-bonding failure inspection system, wire-bonding failure detection device, and wire-bonding failure detection method
TWI715234B (en) * 2019-10-04 2021-01-01 瑞昱半導體股份有限公司 Chip package module
US11424206B2 (en) 2019-10-04 2022-08-23 Realtek Semiconductor Corp. Chip package module including flip-chip ground pads and power pads, and wire-bonding ground pads and power pads
CN112271168A (en) * 2020-10-28 2021-01-26 广州立景创新科技有限公司 Circuit structure
TWI816499B (en) * 2022-08-03 2023-09-21 矽品精密工業股份有限公司 Electronic package

Also Published As

Publication number Publication date
TWI282133B (en) 2007-06-01

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees