TW200723298A - Multi-port memory device with serial input/output interface - Google Patents

Multi-port memory device with serial input/output interface

Info

Publication number
TW200723298A
TW200723298A TW095136055A TW95136055A TW200723298A TW 200723298 A TW200723298 A TW 200723298A TW 095136055 A TW095136055 A TW 095136055A TW 95136055 A TW95136055 A TW 95136055A TW 200723298 A TW200723298 A TW 200723298A
Authority
TW
Taiwan
Prior art keywords
data
memory device
port memory
serial
serial input
Prior art date
Application number
TW095136055A
Other languages
English (en)
Other versions
TWI340980B (en
Inventor
Chang-Ho Do
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020060032949A external-priority patent/KR100695432B1/ko
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200723298A publication Critical patent/TW200723298A/zh
Application granted granted Critical
Publication of TWI340980B publication Critical patent/TWI340980B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/107—Serial-parallel conversion of data or prefetch

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Information Transfer Systems (AREA)
TW095136055A 2005-09-28 2006-09-28 Multi-port memory device with serial input/output interface TWI340980B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR20050090858 2005-09-28
KR1020060032949A KR100695432B1 (ko) 2005-09-28 2006-04-11 직렬 입/출력 인터페이스를 가진 멀티 포트 메모리 소자

Publications (2)

Publication Number Publication Date
TW200723298A true TW200723298A (en) 2007-06-16
TWI340980B TWI340980B (en) 2011-04-21

Family

ID=37893726

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095136055A TWI340980B (en) 2005-09-28 2006-09-28 Multi-port memory device with serial input/output interface

Country Status (2)

Country Link
US (1) US8429319B2 (zh)
TW (1) TWI340980B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7443760B2 (en) * 2005-09-29 2008-10-28 Hynix Semiconductor Inc. Multi-port memory device with serial input/output interface
JP2014067241A (ja) * 2012-09-26 2014-04-17 Fujitsu Semiconductor Ltd 半導体記憶装置及び電子装置
US20140192601A1 (en) * 2013-01-09 2014-07-10 Chang-Ho Do Multi-port memory device with serial input/output interface
KR102251809B1 (ko) 2014-05-28 2021-05-13 삼성전자주식회사 메모리 시스템, 메모리 인터페이스 장치 및 메모리 시스템에서의 인터페이싱 방법
CN108564982B (zh) 2018-03-28 2023-10-13 长鑫存储技术有限公司 存储器装置及用于其的测试电路
US10635494B2 (en) * 2018-05-08 2020-04-28 Microchip Technology Incorporated Memory pool allocation for a multi-core system

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JPS5817508A (ja) * 1981-07-23 1983-02-01 Victor Co Of Japan Ltd 信号レベルの検出方式
JP3158286B2 (ja) 1991-04-30 2001-04-23 ソニー株式会社 マルチポートメモリ
JPH05334898A (ja) 1992-06-02 1993-12-17 Mitsubishi Electric Corp 半導体記憶装置
JPH0896596A (ja) 1994-09-20 1996-04-12 Fujitsu Ltd 半導体記憶装置，その試験方法及びその試験装置
US5657289A (en) 1995-08-30 1997-08-12 Micron Technology, Inc. Expandable data width SAM for a multiport RAM
US5796745A (en) 1996-07-19 1998-08-18 International Business Machines Corporation Memory array built-in self test circuit for testing multi-port memory arrays
JP2930029B2 (ja) 1996-09-20 1999-08-03 日本電気株式会社 半導体メモリ装置
KR100228339B1 (ko) 1996-11-21 1999-11-01 김영환 읽기 포트와 쓰기 포트를 공유하는 다중포트 액세스 메모리
US6016525A (en) * 1997-03-17 2000-01-18 Lsi Logic Corporation Inter-bus bridge circuit with integrated loopback capability and method for use of same
US6172935B1 (en) * 1997-04-25 2001-01-09 Micron Technology, Inc. Synchronous dynamic random access memory device
US6539488B1 (en) * 1999-11-30 2003-03-25 Agere Systems Inc. System with a plurality of media access control circuits with a shared memory for storing data and synchronizing data from a clock domain to a host clock domain
JP2002055879A (ja) 2000-08-11 2002-02-20 Univ Hiroshima マルチポートキャッシュメモリ
US6594196B2 (en) 2000-11-29 2003-07-15 International Business Machines Corporation Multi-port memory device and system for addressing the multi-port memory device
JP2002230977A (ja) 2001-01-26 2002-08-16 Seiko Epson Corp マルチポートメモリのアービタ装置及び半導体装置
US6877071B2 (en) * 2001-08-20 2005-04-05 Technology Ip Holdings, Inc. Multi-ported memory
KR100796795B1 (ko) 2001-10-22 2008-01-22 삼성전자주식회사 반도체 소자의 접촉부 및 그 제조 방법과 이를 포함하는표시 장치용 박막 트랜지스터 어레이 기판 및 그 제조 방법
US6848067B2 (en) * 2002-03-27 2005-01-25 Hewlett-Packard Development Company, L.P. Multi-port scan chain register apparatus and method
DE10219782C1 (de) * 2002-05-03 2003-11-13 Infineon Technologies Ag Verfahren und Hilfseinrichtung zum Testen einer RAM-Speicherschaltung
KR100546331B1 (ko) 2003-06-03 2006-01-26 삼성전자주식회사 스택 뱅크들 마다 독립적으로 동작하는 멀티 포트 메모리장치
US7006402B2 (en) * 2003-08-29 2006-02-28 Hynix Semiconductor Inc Multi-port memory device
KR100582821B1 (ko) 2003-08-29 2006-05-23 주식회사 하이닉스반도체 멀티-포트 메모리 소자
DE10345549B3 (de) * 2003-09-30 2005-04-28 Infineon Technologies Ag Integrierte Speicherschaltung
KR100609038B1 (ko) 2004-05-06 2006-08-09 주식회사 하이닉스반도체 직렬 입/출력 인터페이스를 가진 멀티-포트 메모리 소자
US7346819B2 (en) * 2004-10-29 2008-03-18 Rambus Inc. Through-core self-test with multiple loopbacks
US20060129740A1 (en) * 2004-12-13 2006-06-15 Hermann Ruckerbauer Memory device, memory controller and method for operating the same

Also Published As

Publication number Publication date
US8429319B2 (en) 2013-04-23
TWI340980B (en) 2011-04-21
US20070070795A1 (en) 2007-03-29

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees