TW200712872A - Watch dog circuit - Google Patents

Watch dog circuit

Info

Publication number
TW200712872A
TW200712872A TW094133117A TW94133117A TW200712872A TW 200712872 A TW200712872 A TW 200712872A TW 094133117 A TW094133117 A TW 094133117A TW 94133117 A TW94133117 A TW 94133117A TW 200712872 A TW200712872 A TW 200712872A
Authority
TW
Taiwan
Prior art keywords
data
power supply
counter
watch dog
dog circuit
Prior art date
Application number
TW094133117A
Other languages
Chinese (zh)
Other versions
TWI317872B (en
Inventor
Xian-Ming Wang
Guang-Dong Yuan
Chung-Chi Huang
Hsiu-Chang Lai
Original Assignee
Hon Hai Prec Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hon Hai Prec Ind Co Ltd filed Critical Hon Hai Prec Ind Co Ltd
Priority to TW94133117A priority Critical patent/TWI317872B/en
Publication of TW200712872A publication Critical patent/TW200712872A/en
Application granted granted Critical
Publication of TWI317872B publication Critical patent/TWI317872B/en

Links

Landscapes

  • Debugging And Monitoring (AREA)
  • Power Sources (AREA)

Abstract

A watch dog circuit for a computer system includes a data transform chip, a counter, a clock generator, a first power supply, and a second power supply. The data transform chip is connected to a System Management Bus (SMBUS) for transforming the data that received from the SMBUS. The counter counts the data received from the data transform chip, and outputs a reset signal to a South Bridge when the count is completed. The clock generator is connected to the counter. The first power supply is connected to the data transform chip and the counter. The second power supply is connected to the clock generator. The watch dog circuit monitors the output data of the SMBUS and outputs a reset signal to reset the computer system when the computer system is down.
TW94133117A 2005-09-23 2005-09-23 Watch dog circuit TWI317872B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW94133117A TWI317872B (en) 2005-09-23 2005-09-23 Watch dog circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW94133117A TWI317872B (en) 2005-09-23 2005-09-23 Watch dog circuit

Publications (2)

Publication Number Publication Date
TW200712872A true TW200712872A (en) 2007-04-01
TWI317872B TWI317872B (en) 2009-12-01

Family

ID=45073423

Family Applications (1)

Application Number Title Priority Date Filing Date
TW94133117A TWI317872B (en) 2005-09-23 2005-09-23 Watch dog circuit

Country Status (1)

Country Link
TW (1) TWI317872B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9621339B1 (en) 2016-05-11 2017-04-11 Quanta Computer Inc. Host devices and data transmission methods
CN107239356A (en) * 2016-03-28 2017-10-10 恩智浦有限公司 Watchdog circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107239356A (en) * 2016-03-28 2017-10-10 恩智浦有限公司 Watchdog circuit
CN107239356B (en) * 2016-03-28 2022-06-14 恩智浦有限公司 Watchdog circuit
US9621339B1 (en) 2016-05-11 2017-04-11 Quanta Computer Inc. Host devices and data transmission methods
TWI581104B (en) * 2016-05-11 2017-05-01 廣達電腦股份有限公司 Host devices and methods for transmitting data

Also Published As

Publication number Publication date
TWI317872B (en) 2009-12-01

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees