TW200638510A - Method for fabricating semiconductor device with metal line - Google Patents
Method for fabricating semiconductor device with metal lineInfo
- Publication number
- TW200638510A TW200638510A TW094146972A TW94146972A TW200638510A TW 200638510 A TW200638510 A TW 200638510A TW 094146972 A TW094146972 A TW 094146972A TW 94146972 A TW94146972 A TW 94146972A TW 200638510 A TW200638510 A TW 200638510A
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- openings
- forming
- inter
- barrier metal
- Prior art date
Links
- 239000002184 metal Substances 0.000 title abstract 7
- 238000000034 method Methods 0.000 title abstract 6
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 239000010410 layer Substances 0.000 abstract 14
- 230000004888 barrier function Effects 0.000 abstract 4
- 238000005530 etching Methods 0.000 abstract 4
- 238000009413 insulation Methods 0.000 abstract 4
- 239000011229 interlayer Substances 0.000 abstract 4
- 238000000059 patterning Methods 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020050036591A KR100649352B1 (ko) | 2005-04-30 | 2005-04-30 | 반도체소자의 제조 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200638510A true TW200638510A (en) | 2006-11-01 |
TWI283044B TWI283044B (en) | 2007-06-21 |
Family
ID=37195461
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW094146972A TWI283044B (en) | 2005-04-30 | 2005-12-28 | Method for fabricating semiconductor device with metal line |
Country Status (5)
Country | Link |
---|---|
US (2) | US7648909B2 (zh) |
JP (1) | JP5174321B2 (zh) |
KR (1) | KR100649352B1 (zh) |
CN (1) | CN100414683C (zh) |
TW (1) | TWI283044B (zh) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7670946B2 (en) * | 2006-05-15 | 2010-03-02 | Chartered Semiconductor Manufacturing, Ltd. | Methods to eliminate contact plug sidewall slit |
JP2008159651A (ja) * | 2006-12-21 | 2008-07-10 | Elpida Memory Inc | 多層配線、積層アルミニウム配線、半導体装置、及びそれらの製造方法 |
JP2008159951A (ja) * | 2006-12-25 | 2008-07-10 | Fujitsu Ltd | 半導体装置の製造方法 |
KR100853098B1 (ko) * | 2006-12-27 | 2008-08-19 | 동부일렉트로닉스 주식회사 | 반도체 소자의 금속 배선 및 이의 제조 방법 |
JP4685147B2 (ja) | 2008-10-14 | 2011-05-18 | エルピーダメモリ株式会社 | 半導体装置の製造方法 |
US20130224948A1 (en) * | 2012-02-28 | 2013-08-29 | Globalfoundries Inc. | Methods for deposition of tungsten in the fabrication of an integrated circuit |
CN103515294B (zh) * | 2012-06-26 | 2018-07-06 | 盛美半导体设备(上海)有限公司 | 钨插塞的制作方法 |
CN104064511B (zh) * | 2013-03-19 | 2017-03-29 | 上海华虹宏力半导体制造有限公司 | 硅片接触孔工艺方法 |
US10147782B2 (en) | 2016-07-18 | 2018-12-04 | International Business Machines Corporation | Tapered metal nitride structure |
CN110571189B (zh) * | 2018-06-05 | 2022-04-29 | 中芯国际集成电路制造(上海)有限公司 | 导电插塞及其形成方法、集成电路 |
CN109830460A (zh) * | 2019-02-22 | 2019-05-31 | 德淮半导体有限公司 | 制造半导体器件的方法 |
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JPH04225549A (ja) | 1990-12-27 | 1992-08-14 | Sony Corp | メタルプラグの形成方法 |
JPH0645326A (ja) * | 1992-04-08 | 1994-02-18 | Nec Corp | 半導体装置の製造方法 |
EP0741741B1 (en) * | 1994-01-26 | 2002-08-28 | Novartis AG | Modified oligonucleotides |
JPH07294280A (ja) * | 1994-04-27 | 1995-11-10 | Heiwa Tokei Seisakusho:Kk | 歩数計の歩数カウントスイッチ |
JP3301466B2 (ja) * | 1994-07-12 | 2002-07-15 | ソニー株式会社 | 半導体装置の製造方法 |
GB9511888D0 (en) * | 1995-06-12 | 1995-08-09 | Dalgety Plc | DNA markers for litter size |
JPH09232313A (ja) * | 1996-02-27 | 1997-09-05 | Fujitsu Ltd | 埋め込み導電層の形成方法 |
US5933756A (en) * | 1995-10-18 | 1999-08-03 | Ricoh Company, Ltd. | Fabrication process of a semiconductor device having a multilayered interconnection structure |
JPH09172017A (ja) * | 1995-10-18 | 1997-06-30 | Ricoh Co Ltd | 半導体装置の製造方法 |
JPH09275140A (ja) * | 1996-04-05 | 1997-10-21 | Sony Corp | 半導体装置における接続孔の形成方法 |
JPH10144790A (ja) * | 1996-11-08 | 1998-05-29 | Sony Corp | 半導体装置における配線形成方法 |
JPH10223608A (ja) * | 1997-02-04 | 1998-08-21 | Sony Corp | 半導体装置の製造方法 |
KR19990003106A (ko) * | 1997-06-24 | 1999-01-15 | 윤종용 | 반도체 장치의 콘택 및 배선 형성 방법 |
JPH1140668A (ja) * | 1997-07-18 | 1999-02-12 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JPH1197536A (ja) * | 1997-09-19 | 1999-04-09 | Nippon Steel Corp | 半導体装置の製造方法 |
JPH11265934A (ja) * | 1998-03-16 | 1999-09-28 | Mitsubishi Electric Corp | 接続部の形成方法 |
US6010966A (en) * | 1998-08-07 | 2000-01-04 | Applied Materials, Inc. | Hydrocarbon gases for anisotropic etching of metal-containing layers |
KR100272183B1 (ko) * | 1998-10-19 | 2001-02-01 | 황인길 | 반도체 소자 제조 공정에서 물질 매입을 위한 패턴 식각 방법 |
US6140227A (en) * | 1998-11-25 | 2000-10-31 | United Microelectronics Corp. | Method of fabricating a glue layer of contact/via |
JP3183341B2 (ja) * | 1998-12-09 | 2001-07-09 | 日本電気株式会社 | 半導体装置の製造方法 |
JP2001196289A (ja) * | 2000-01-12 | 2001-07-19 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
US20020106895A1 (en) * | 2001-02-08 | 2002-08-08 | Macronix International Co., Ltd. | Method for forming copper interconnect and enhancing electromigration resistance |
US6764940B1 (en) * | 2001-03-13 | 2004-07-20 | Novellus Systems, Inc. | Method for depositing a diffusion barrier for copper interconnect applications |
TW550642B (en) | 2001-06-12 | 2003-09-01 | Toshiba Corp | Semiconductor device with multi-layer interconnect and method fabricating the same |
KR20030002942A (ko) * | 2001-07-03 | 2003-01-09 | 삼성전자 주식회사 | 반도체 소자의 금속 배선 형성 방법 |
TW511860U (en) * | 2001-11-08 | 2002-11-21 | Wistron Corp | Electronic equipment with side-fixed apparatus for anti-deviation |
JP3780204B2 (ja) * | 2001-12-11 | 2006-05-31 | 株式会社アルバック | バリアメタル膜又は密着層形成方法及び配線形成方法 |
JP2003303882A (ja) * | 2002-04-09 | 2003-10-24 | Sony Corp | 半導体装置の製造方法及び半導体装置の製造装置 |
JP4285946B2 (ja) * | 2002-06-06 | 2009-06-24 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
KR100514523B1 (ko) * | 2003-06-27 | 2005-09-13 | 동부아남반도체 주식회사 | 반도체 소자의 금속배선 형성방법 |
US6794304B1 (en) * | 2003-07-31 | 2004-09-21 | Lsi Logic Corporation | Method and apparatus for reducing microtrenching for borderless vias created in a dual damascene process |
-
2005
- 2005-04-30 KR KR1020050036591A patent/KR100649352B1/ko not_active IP Right Cessation
- 2005-12-27 JP JP2005373977A patent/JP5174321B2/ja not_active Expired - Fee Related
- 2005-12-28 TW TW094146972A patent/TWI283044B/zh not_active IP Right Cessation
- 2005-12-30 CN CNB2005100975360A patent/CN100414683C/zh not_active Expired - Fee Related
- 2005-12-30 US US11/321,533 patent/US7648909B2/en not_active Expired - Fee Related
-
2009
- 2009-11-13 US US12/618,523 patent/US8030205B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20100062598A1 (en) | 2010-03-11 |
JP2006310752A (ja) | 2006-11-09 |
US8030205B2 (en) | 2011-10-04 |
CN100414683C (zh) | 2008-08-27 |
US7648909B2 (en) | 2010-01-19 |
KR20060113299A (ko) | 2006-11-02 |
KR100649352B1 (ko) | 2006-11-27 |
TWI283044B (en) | 2007-06-21 |
US20060246708A1 (en) | 2006-11-02 |
JP5174321B2 (ja) | 2013-04-03 |
CN1855423A (zh) | 2006-11-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |