TW200636570A - Reduction of power through disabling unused arithmetic logic units - Google Patents
Reduction of power through disabling unused arithmetic logic unitsInfo
- Publication number
- TW200636570A TW200636570A TW095112950A TW95112950A TW200636570A TW 200636570 A TW200636570 A TW 200636570A TW 095112950 A TW095112950 A TW 095112950A TW 95112950 A TW95112950 A TW 95112950A TW 200636570 A TW200636570 A TW 200636570A
- Authority
- TW
- Taiwan
- Prior art keywords
- arithmetic
- arithmetic logic
- logic units
- logic
- reduction
- Prior art date
Links
Landscapes
- Advance Control (AREA)
- Power Sources (AREA)
Abstract
The present invention is generally directed to method and apparatus for reducing power consumption in a processor through disabling unused arithmetic logic units. A typical processor has several arithmetic logic units (ALU) in the execute unit for executing arithmetic or logic operations. Logic units are implemented in each arithmetic logic unit to control which arithmetic logic unit needs to be activated for performing the arithmetic or logic operation. As a result, only the requisite arithmetic logic unit is activated to execute the instructed arithmetic or logic operation, while the other arithmetic logic units are prevented from receiving input data. Therefore, all unused arithmetic logic units are disabled to reduce power consumption in a processor.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US67068005P | 2005-04-13 | 2005-04-13 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200636570A true TW200636570A (en) | 2006-10-16 |
TWI315489B TWI315489B (en) | 2009-10-01 |
Family
ID=37015445
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW95112950A TWI315489B (en) | 2005-04-13 | 2006-04-12 | A processor and a system for reducing power through disabling unused arithmetic logic units |
Country Status (2)
Country | Link |
---|---|
CN (1) | CN100504725C (en) |
TW (1) | TWI315489B (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3657403A1 (en) | 2017-06-13 | 2020-05-27 | Shanghai Cambricon Information Technology Co., Ltd | Computing device and method |
CN109102073A (en) | 2017-06-21 | 2018-12-28 | 上海寒武纪信息科技有限公司 | A kind of sparse training method |
CN109117455A (en) | 2017-06-26 | 2019-01-01 | 上海寒武纪信息科技有限公司 | Computing device and method |
CN113449855A (en) * | 2017-06-13 | 2021-09-28 | 上海寒武纪信息科技有限公司 | Arithmetic device and method |
-
2006
- 2006-04-12 TW TW95112950A patent/TWI315489B/en active
- 2006-04-13 CN CNB2006100736186A patent/CN100504725C/en active Active
Also Published As
Publication number | Publication date |
---|---|
CN1838031A (en) | 2006-09-27 |
TWI315489B (en) | 2009-10-01 |
CN100504725C (en) | 2009-06-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW200834298A (en) | System, method, and computer program product for saving power in a multi-graphics processor environment | |
WO2009120981A3 (en) | Vector instructions to enable efficient synchronization and parallel reduction operations | |
IL206176A0 (en) | Apparatus and method for performing permutation operations on data | |
GB2467891A (en) | Mechanism for profiling program software running on a processor | |
GB2468461A (en) | Unified processor architecture for processing general and graphics workload | |
TW200701059A (en) | Data access and permute unit | |
WO2012009252A3 (en) | Dynamic enabling and disabling of simd units in a graphics processor | |
MY149803A (en) | Markup based extensibility for user interfaces | |
ATE554443T1 (en) | INSTRUCTION-DRIVEN DATA PROCESSING DEVICE AND METHOD | |
WO2005088443A3 (en) | Methods and apparatus for reducing power dissipation in a multi-processor system | |
PH12017550126A1 (en) | Bulk allocation of instruction blocks to a processor instruction window | |
MY160644A (en) | Controlling the Execution of Adjacent Instructions that are Dependent upon a Same Data Condition | |
TW200622683A (en) | Task-oriented processing as an auxiliary to primary computing environments | |
MY168503A (en) | Cryptographic support instructions | |
HK1051244A1 (en) | Method and apparatus for instruction set architecture having dyadic digital signal processing instructions | |
GB2511986A (en) | Performing arithmetic operations using both large and small floating point values | |
TW200713032A (en) | Methods and apparatus for dynamically switching processor mode | |
WO2006094196A3 (en) | Method and apparatus for power reduction in an heterogeneously- multi-pipelined processor | |
SG126073A1 (en) | Real-time control apparatus having a multi-thread processor | |
HK1097928A1 (en) | Processor, method and computer program products for execution of instructions for efficient bit stream extractions | |
TW200636570A (en) | Reduction of power through disabling unused arithmetic logic units | |
TW200709042A (en) | Apparatus and method for performing efficient multiply-accumulate operations in microprocessors | |
TW200709041A (en) | Computer system or processor with method of performing a shadow register operation | |
MX2008000623A (en) | System and method of controlling multiple program threads within a multithreaded processor. | |
WO2006075286A3 (en) | A processor and its instruction issue method |