TW200620598A - Flip-chip package structure with embedded chip in substrate - Google Patents

Flip-chip package structure with embedded chip in substrate

Info

Publication number
TW200620598A
TW200620598A TW093138303A TW93138303A TW200620598A TW 200620598 A TW200620598 A TW 200620598A TW 093138303 A TW093138303 A TW 093138303A TW 93138303 A TW93138303 A TW 93138303A TW 200620598 A TW200620598 A TW 200620598A
Authority
TW
Taiwan
Prior art keywords
heat sink
semiconductor chip
chip
insulating layer
substrate
Prior art date
Application number
TW093138303A
Other languages
Chinese (zh)
Other versions
TWI249231B (en
Inventor
Shih-Ping Hsu
Original Assignee
Phoenix Prec Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Phoenix Prec Technology Corp filed Critical Phoenix Prec Technology Corp
Priority to TW093138303A priority Critical patent/TWI249231B/en
Application granted granted Critical
Publication of TWI249231B publication Critical patent/TWI249231B/en
Publication of TW200620598A publication Critical patent/TW200620598A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

A flip-chip package structure with an embedded chip in a substrate is proposed. A heat sink having a plurality of cavities and openings is provided. At least one semiconductor chip is received in one of the cavities of the heat sink. An insulating layer is applied on upper and lower surfaces of the heat sink and the semiconductor chip, and fills a gap between the semiconductor chip and the heat sink, as well as covers walls of the openings of the heat sink. At least one circuit layer is formed on the insulating layer, and is electrically connected to the semiconductor chip by conductor structures formed in the insulating layer. A plurality of conductive vias are formed in the openings having their walls covered by the insulating layer, and electrically connect the circuit layers located above the upper and lower surfaces of the heat sink to each other. The heat sink provides good support and heat dissipation efficiency, such that the semiconductor chip can be embedded in the corresponding cavity of the heat sink to make good use of substrate space, and the semiconductor chip can be directly electrically connected to the circuit layers, thereby simplifying the semiconductor fabrication processes and the integration problem.
TW093138303A 2004-12-10 2004-12-10 Flip-chip package structure with embedded chip in substrate TWI249231B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW093138303A TWI249231B (en) 2004-12-10 2004-12-10 Flip-chip package structure with embedded chip in substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW093138303A TWI249231B (en) 2004-12-10 2004-12-10 Flip-chip package structure with embedded chip in substrate

Publications (2)

Publication Number Publication Date
TWI249231B TWI249231B (en) 2006-02-11
TW200620598A true TW200620598A (en) 2006-06-16

Family

ID=37429503

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093138303A TWI249231B (en) 2004-12-10 2004-12-10 Flip-chip package structure with embedded chip in substrate

Country Status (1)

Country Link
TW (1) TWI249231B (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI453877B (en) * 2008-11-07 2014-09-21 Advanced Semiconductor Eng Structure and process of embedded chip package
TWI453878B (en) * 2009-01-10 2014-09-21 Unimicron Technology Corp Package substrate and method for fabricating same
US8987830B2 (en) 2010-01-12 2015-03-24 Marvell World Trade Ltd. Attaching passive components to a semiconductor package
TWI495078B (en) * 2012-10-09 2015-08-01 Zhen Ding Technology Co Ltd Connecting substrate and package on package structure
CN112908943A (en) * 2021-01-12 2021-06-04 华为技术有限公司 Embedded packaging structure, preparation method thereof and terminal equipment
TWI738069B (en) * 2019-09-27 2021-09-01 恆勁科技股份有限公司 Flip-chip package substrate and preparation method thereof

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI340445B (en) 2007-01-10 2011-04-11 Advanced Semiconductor Eng Manufacturing method for integrating passive component within substrate
US20110175218A1 (en) 2010-01-18 2011-07-21 Shiann-Ming Liou Package assembly having a semiconductor substrate
US20110186960A1 (en) 2010-02-03 2011-08-04 Albert Wu Techniques and configurations for recessed semiconductor substrates
US8304878B2 (en) * 2010-05-17 2012-11-06 Advanced Semiconductor Engineering, Inc. Embedded component substrate, semiconductor package structure using the same and fabrication methods thereof
TWI517321B (en) 2014-12-08 2016-01-11 旭德科技股份有限公司 Package structure and manufacturing method thereof
TWI739027B (en) * 2018-08-30 2021-09-11 恆勁科技股份有限公司 Core structure of flip chip package substrate and preparation method thereof

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI453877B (en) * 2008-11-07 2014-09-21 Advanced Semiconductor Eng Structure and process of embedded chip package
TWI453878B (en) * 2009-01-10 2014-09-21 Unimicron Technology Corp Package substrate and method for fabricating same
US8987830B2 (en) 2010-01-12 2015-03-24 Marvell World Trade Ltd. Attaching passive components to a semiconductor package
US9171744B2 (en) 2010-01-12 2015-10-27 Marvell World Trade Ltd. Attaching passive components to a semiconductor package
TWI495078B (en) * 2012-10-09 2015-08-01 Zhen Ding Technology Co Ltd Connecting substrate and package on package structure
TWI738069B (en) * 2019-09-27 2021-09-01 恆勁科技股份有限公司 Flip-chip package substrate and preparation method thereof
CN112908943A (en) * 2021-01-12 2021-06-04 华为技术有限公司 Embedded packaging structure, preparation method thereof and terminal equipment

Also Published As

Publication number Publication date
TWI249231B (en) 2006-02-11

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