TW200619937A - System, apparatus and method for predicating various types of accesses to a memory and for managing predictions associated with a cache memory - Google Patents

System, apparatus and method for predicating various types of accesses to a memory and for managing predictions associated with a cache memory

Info

Publication number
TW200619937A
TW200619937A TW094128055A TW94128055A TW200619937A TW 200619937 A TW200619937 A TW 200619937A TW 094128055 A TW094128055 A TW 094128055A TW 94128055 A TW94128055 A TW 94128055A TW 200619937 A TW200619937 A TW 200619937A
Authority
TW
Taiwan
Prior art keywords
memory
accesses
speculator
predicating
various types
Prior art date
Application number
TW094128055A
Other languages
Chinese (zh)
Other versions
TWI348097B (en
Inventor
Ziyad S Hakura
Radoslav Danilak
Brad W Simeral
Brian Keith Langendorf
Stefano A Pescador
Dmitry Vyshetsky
Original Assignee
Nvidia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/920,610 external-priority patent/US7441087B2/en
Priority claimed from US10/920,682 external-priority patent/US7461211B2/en
Priority claimed from US10/920,995 external-priority patent/US7260686B2/en
Priority claimed from US10/921,026 external-priority patent/US7206902B2/en
Application filed by Nvidia Corp filed Critical Nvidia Corp
Publication of TW200619937A publication Critical patent/TW200619937A/en
Application granted granted Critical
Publication of TWI348097B publication Critical patent/TWI348097B/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/345—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G06F9/3832—Value prediction for operands; operand history buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Debugging And Monitoring (AREA)

Abstract

A system, apparatus, and method are disclosed for predicting accesses to memory. In one embodiment, an exemplary apparatus comprises a processor configured to execute program instructions and process program data, a memory including the program instructions and the program data, and a memory processor. The memory processor can include a speculator configured to receive an address containing the program instructions or the program data. Such a speculator can comprise a sequential predictor and a nonsequential predictor for generating a configurable number of sequential and nonsequential addresses respectively. In one embodiment, a prefetcher implements the apparatus. In various embodiments, the speculator can also include any of the following: an expediter, a suppressor, an inventory, an inventory filter, a post-inventory filter and a data return cache memory, which can include a short term and a long term cache, among other things.
TW094128055A 2004-08-17 2005-08-17 System, apparatus and method for predicating various types of accesses to a memory and for managing predications associated with a cache memory TWI348097B (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US10/920,610 US7441087B2 (en) 2004-08-17 2004-08-17 System, apparatus and method for issuing predictions from an inventory to access a memory
US10/920,682 US7461211B2 (en) 2004-08-17 2004-08-17 System, apparatus and method for generating nonsequential predictions to access a memory
US10/920,995 US7260686B2 (en) 2004-08-17 2004-08-17 System, apparatus and method for performing look-ahead lookup on predictive information in a cache memory
US10/921,026 US7206902B2 (en) 2004-08-17 2004-08-17 System, apparatus and method for predicting accesses to a memory

Publications (2)

Publication Number Publication Date
TW200619937A true TW200619937A (en) 2006-06-16
TWI348097B TWI348097B (en) 2011-09-01

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
TW094128055A TWI348097B (en) 2004-08-17 2005-08-17 System, apparatus and method for predicating various types of accesses to a memory and for managing predications associated with a cache memory

Country Status (4)

Country Link
JP (1) JP5059609B2 (en)
KR (1) KR100987832B1 (en)
TW (1) TWI348097B (en)
WO (1) WO2006038991A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI757539B (en) * 2017-08-30 2022-03-11 美商甲骨文國際公司 System, method, and apparatus for data prefetching

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US7636813B2 (en) * 2006-05-22 2009-12-22 International Business Machines Corporation Systems and methods for providing remote pre-fetch buffers
JP6252348B2 (en) * 2014-05-14 2017-12-27 富士通株式会社 Arithmetic processing device and control method of arithmetic processing device
WO2016097794A1 (en) 2014-12-14 2016-06-23 Via Alliance Semiconductor Co., Ltd. Prefetching with level of aggressiveness based on effectiveness by memory access type
US9817764B2 (en) 2014-12-14 2017-11-14 Via Alliance Semiconductor Co., Ltd Multiple data prefetchers that defer to one another based on prefetch effectiveness by memory access type
JP2017072929A (en) 2015-10-06 2017-04-13 富士通株式会社 Data management program, data management device, and data management method
US10509726B2 (en) 2015-12-20 2019-12-17 Intel Corporation Instructions and logic for load-indices-and-prefetch-scatters operations
US20170177349A1 (en) * 2015-12-21 2017-06-22 Intel Corporation Instructions and Logic for Load-Indices-and-Prefetch-Gathers Operations
US11281589B2 (en) 2018-08-30 2022-03-22 Micron Technology, Inc. Asynchronous forward caching memory systems and methods
KR102142498B1 (en) * 2018-10-05 2020-08-10 성균관대학교산학협력단 GPU memory controller for GPU prefetching through static analysis and method of control
KR102238383B1 (en) * 2019-10-30 2021-04-09 주식회사 엠투아이코퍼레이션 HMI having optimization function of communication

Family Cites Families (6)

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Publication number Priority date Publication date Assignee Title
JPH06103169A (en) * 1992-09-18 1994-04-15 Nec Corp Read data prefetching mechanism for central arithmetic processor
US5426764A (en) * 1993-08-24 1995-06-20 Ryan; Charles P. Cache miss prediction apparatus with priority encoder for multiple prediction matches and method therefor
US5561782A (en) * 1994-06-30 1996-10-01 Intel Corporation Pipelined cache system having low effective latency for nonsequential accesses
US5623608A (en) * 1994-11-14 1997-04-22 International Business Machines Corporation Method and apparatus for adaptive circular predictive buffer management
JP3741945B2 (en) * 1999-09-30 2006-02-01 富士通株式会社 Instruction fetch control device
US6789171B2 (en) * 2002-05-31 2004-09-07 Veritas Operating Corporation Computer system implementing a multi-threaded stride prediction read ahead algorithm

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI757539B (en) * 2017-08-30 2022-03-11 美商甲骨文國際公司 System, method, and apparatus for data prefetching

Also Published As

Publication number Publication date
WO2006038991A2 (en) 2006-04-13
WO2006038991A3 (en) 2006-08-03
JP2008510258A (en) 2008-04-03
KR100987832B1 (en) 2010-10-13
TWI348097B (en) 2011-09-01
KR20070050443A (en) 2007-05-15
JP5059609B2 (en) 2012-10-24

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