200532793 玫、發明說明： c 明屬貝】 技術領域 本發明一般係有關於蝕刻技術，特別是有關於一種用 5 在半導體裝置之製造之蝕刻裝置。 電漿敍刻在半導體裝置之製造中是不可或缺之技術， 且在一般半導體裝置之製造中使用的是以平行平板型蚀刻 裝置為主的各種蝕刻裝置。 於習知半導體裝置之製造程序中，I虫刻技術主要是使 10用在形成以Si〇2為主之絕緣膜之圖案，或是形成A1、w或 Ti等金屬膜之圖案。 另一方面，在最近之強介電體記憶體(FeRA]VI)等具有 如 PZT(Pb(Zr，Ti)03)、PLZT((Pb)(Zr，Ti)03)、BST(BiSrTi03) 或STO(SrTi〇3)之強介電體膜或高介電體膜，且具有由Pt、 I5 Ir或Ru之低蒸氣壓金屬材料所構成之電極膜之半導體裝置 製造中，為了蝕刻該等膜，必須具有高電子密度與電子能 量（電子溫度），因此，必須使用ECR型、螺旋子型或ICP(感 應耦合)型等之高密度電漿蝕刻裝置，其中，特別是由於ICP 型刻裝置之裝置構造較為簡單，因此常為人所使用。 20 【先前技術】 背景技術 第1A〜1D圖係顯示習知FeRAM之製造程序之一部 分，特別是強介電體電容器之製造程序。 參照第1A圖，於矽基板1上形成絕緣膜2以覆蓋省略圖 200532793 式之記憶胞電晶體，且透過Ti等密著層（未圖示），於前述絕 緣膜2上形成由Pt等貴金屬或Ir〇2、SrRu〇3等導電性氧化物 所構成之下部電極層3。再於前述下部電極層3上形成 PZT(Pb(Zr，Ti)〇3)等強介電體膜4，且於前述強介電體膜々上 5形成由Pt、Ir或Ru等貴金屬或是Ir〇2、SrRu〇3等導電性氧化 物所構成之上部電極層5。 其次，於第1B圖之程序中，前述上部電極層5係藉由微 影成像程序來形成圖案，且於前述強介電體膜4上形成上部 電極5A。 10 於第1B圖之程序甲更藉由於氧環境中之熱處理，補償 於前述強介電體膜4中在前述上部電極層5形成圖案時所形 成之氧缺損，再者，於第lc圖之程序中，藉由微影成像程 序使前述強介電體膜4形成圖案，並於前述下部電極層3上 形成強介電體電容器絕緣膜4A。 15 於第1C圖之程序中更藉由於氧化環境中將依前述所妒 成之強介魏電容⑽賴4縫行熱處理，來補償於前述 強介電體膜4形成圖案時在前述強介電體電容器絕緣膜4八 中所形成之氧缺損，再藉由Al2〇3等對氯之渗透具有障蔽性 之第1密封層6，覆蓋前述上部電極认及強介電體電容 2〇 緣膜4A。 再者’於第_之程序中，藉由微影成像程序使前述 下部電極層3及其下面之Ti密著層形成圖案，且形成下部電 極3A 〇 再者，於第1D圖之程序係形成由Al2〇3等所構成之第2 200532793 密封層7,以透過前述第1密封層6覆蓋依前述所形成之強介 電體電容器。 此種FeRAM之製造程序中，於使前述下部電極層3、強 介電體膜4及上部電極層5形成圖案之微影成像程序中係使 5用電漿蝕刻作業，但該等膜係含有蒸氣壓低之金屬元素， 且右僅藉由電漿激勵之自由基作用並無法得到充分之蝕刻 速度，故必須使用除了利用自由基之蝕刻作用外尚可產生 顯著之濺射作用之高密度電漿蝕刻作業。 第2圖係顯示習知於第^〜1]〇圖之高密度電漿蝕刻作 1〇業中所使用之ICP型蝕刻裝置1〇之構造。 參照第2圖，ICP型蝕刻裝置1〇係具有於排氣口 1〇A排 氣且區隔出作業空間11A之石英鐘罩丨丨以作為處理容器，且 於則述處理容器11内設置有用以保持被處理基板w之基板 保持台15。又，於前述處理容器u之外周係捲繞線圈12以 15 作為天線。 刖述線圈12係透過阻抗整合電路13與高頻電源丨斗連 接，且自電衆氣體供給口 u^Ar等電聚氣體導入前述處理 心器11中’更藉由自4述高頻電源14將高頻電力供給至線 圈12，使前述處理容Ε11内形成電聚。故，藉由自處理氣 20體導入口 nb將例如含有素之關氣體導入前述 處理容器u内，於前述被處理基板w之表面可藉由前述電 漿激勵蝕刻氣體之自由基。 再者刚述基板保持台！ 5係透過阻隔電容器i S及阻抗 整合電路17與高頻偏壓電源18連接，且藉由自前述高頻偏 200532793 壓電源18供給高頻偏壓電力，使負偏壓電位施加於前述基 板保持台15上。 施加前述偏壓電位之結果，前述電漿中之Ar+等陽離 子係與自由基同時與前述基板保持台15上之被處理基板碰 4里’且與姓刻同時產生錢射，並⑨與前述被處理基板料 玉垂直之方向實現有效之異方性蝕刻。 專利文獻1日本專利公開公報特開2000一 195841號 專利文獻2特開昭57_96528號公報 專利文獻3特開昭58一 16823〇號公報 1〇 專利文獻4特開平6 — 333881號公報 專利文獻5特開平6 — 243993號公報 專利文獻6特開平1〇—16318〇號公報 發明之揭示 然而’依此對被處理基板W進行附加有濺射作用之電 15裝1 虫刻時，濺射作用之結果會如第3圖所示，產生於前述處 理容器11之内壁面有自前述被處理基板霄濺射之粒子堆積 之問題。特別是若將高密度電漿蝕刻裝置使用在如第1A〜 1D圖中所說明之含有FeRAM等強介電體電容器之半導體 裝置之製造時，則容易產生蒸氣壓低之Pt、Ir或Ru等貴金屬 20 膜之堆積。 若為第2圖之ICP型電漿蝕刻裝置10,當前述處理容器 11之内壁面堆積此種導電性膜時，來自前述線圈12之高頻 電力會無法到達處理容器11内之作業空間11A，且無法進行 電聚钱刻。又，若此種處理容器11之内壁面之堆積物剝離， 200532793 則會變成碎屑，且半導體裝置之製造成品率降低。 若為一般之8丨02系絕緣膜或A卜W、Ti等金屬膜之電漿 钱刻’依此，即使於前述處理容器11之内壁面產生堆積物， 藉由將清掃氣體供給至前述處理容器11中，且自前述高頻 5源14供給高頻電力而於前述處理容器中誘發電漿，即可有 效地除去前述堆積物。又，若為近來之低介電常數層間絕 緣膜之電漿姓刻，則亦可將氧氣等氧化氣體供給至前述處 理谷器11中’且利用來自高頻源14之高頻電力驅動前述高 頻線圈12而於前述處理容器中誘發氧電漿，藉此，可有效 1〇地除去附著於處理容器11内壁之碳氫化合物等堆積物。 相對於此，在含有FeRAM等蒸氣壓低且蝕刻速度慢之 材料之半導體裝置製造中，由於附著在前述處理容器^内 壁面之堆積物多為貴金屬等蒸氣壓低之材料，因此，前述 電漿清掃作業並沒有效果，且為了有效且具有高成品率地 ;^行電姓刻，必須拆解電漿姓刻裝置1〇且頻繁地進行處 理谷為11之濕式清掃，然而，此種頻繁的保養會使半導體 裝置之製造效率降低。 【發明内容】 及鬲頻源，係與前述基板保持台結合者 本發明之一目的係提供一種基板處理裝置，該基板處 理裝置包含有··處理容器’係藉由排氣系統排氣，且具有 用以保持被處理基板之基板保持台，並於㈣區隔出作業 空間者；處理氣體供給路，係用以將_氣體導入前述處 理容器中者；電漿產生源，係於前述作t空間形成電聚者； 其特徵在於：前 20 200532793 述處理容器内具有遮蔽板，該遮蔽板係將前述作業空間分 告1J成包S別述被處理基板之表面之第1作業空間部分应由 前述作業空間剩餘之領域所構成之第2作業空間部分，又， 於鈾述遮蔽板上形成具有大於前述被處理基板之大小之開 5 口部0 若藉由本發明，則在使用高密度電漿將基板保持台上 之被處理基板進行電漿蝕刻時，可藉由前述遮蔽板有效地 捕捉因伴隨著電漿蝕刻產生之濺射作用而自前述被處理基 板放出之粒子，且可抑制堆積物堆積於前述處理容器内 10壁。此時，由於前述遮蔽板具有大於前述被處理基板之大 小之開口部，因此，即使堆積於前述遮蔽板上之堆積物剝 離，亦不會掉落至前述被處理基板上，且藉由使用前述遮 蔽板，而不會降低半導體裝置之製造成品率。又，藉由於 前述遮蔽板形成大於前述被處理基板之大小之開口部，於 15 前述基板前面可進行相同之電漿蝕刻處理。 本發明之其他目的及特徵可從一面參照圖式一面進行 之本發明之詳細說明中清楚明白。 圖式簡單說明 第1A〜1D圖係顯示習知強介電體電容器之製造程序 20 圖。 第2圖係顯示習知ICP型高密度電漿蝕刻裝置之構造 圖。 第3圖係說明第2圖之電漿蝕刻裝置之問題點之圖。 第4圖係顯示依據本發明第丨實施例之電漿蝕刻裝置之 10 200532793 構造圖° 第5圖係’示第4圖之電漿#刻裝置中所使用之遮蔽板 之構造圖。 第6圖係顯示第5圖之遮蔽板之一變形例之圖。 第7圖係_示依據本發明第2實施例之電聚姓刻裝置之 構造圖。 第8圖係顯示第7圖之電漿触刻裝置之1形例之圖。 第9圖係_示依據本發明第3實施例之電漿餘刻襄置之 構造圖。 第1〇圖係顯示依據本發明第4實施例之電漿蝕刻裝置 之構造圖。 C實施冷式】 發明之較佳實施態樣 〔第1實施例〕 第囷系·.、、員示依據本發明第丨實施例之電漿姓刻裝置2〇 之構造。 产 3，刚述1CP型蝕刻裝置2〇係具有於排氣口 20 —排&且H隔出作業空間21A之石英鐘罩21以作為處理 且於前述處理容器21内設置有用以將被處理基板W 二平地保持之基板保持台25…於前述處理容器21之 壁部2繞線圈22r作為*線。前述處理容器包含有：側 2 係由石英玻璃所構成，並區隔出前述作業允門 =且呈套筒狀者·，金屬蓋21C，係形成於前述石英側㈣ 上且於上部堵塞前述作業空間21A者·，及本體部21D， 200532793 係於前述石英側壁部21B之下部包圍前述基板保持台25，並 支持前述石英側壁部21B且進而形成前述排氣口 2〇A者。 月述線圈22係透過阻抗整合電路23與高頻電源24連 接’且自形成於前述金屬蓋21C之電漿氣體供給口 21a將 5 He'Ne'Ar、Kr、Xe等電漿氣體導入前述處理容器21中， 更藉由自前述高頻電源24將高頻電力供給至線圈22，使前 述處理容器21内形成電漿。故，藉由自形成於前述本體部 21D之處理氣體導入口 21b，將例如含有F*C1等鹵素，如 2 C；C14' CF4、CHF3專虫刻氣體導入前述處理容器21内， 於岫述被處理基板W之表面可藉由前述電漿激勵蝕刻氣體 之自由基。 再者，前述基板保持台25係透過阻隔電容器16及阻抗 整合電路27與高頻偏壓電源28連接，且藉由自前述高頻偏 壓電源28供給高頻偏壓電力，使負偏壓電位施加於前述基 15板保持台25上。 施加前述偏壓電位之結果，前述電漿中之Ar+等陽離 子係與自由基同時與前述基板保持台25上之被處理基板碰 才里，且於前述被處理基板冒上，與利用前述自由基之蝕刻 同吩地產生濺射，並於與前述被處理基板w略呈垂直之方 20向實現有效之異方性蝕刻。 第4圖之ICP型電漿蝕刻裝置2〇中，為了進一步捕獲因 _而自前述基板W放出之賤射粒子且盡可能地抑制於前 述處理容器21之内壁上形成堆積物，於前述被處理基板w 上係形成由石英或氧化銘等絕緣物所構成之遮蔽板26，以 12 200532793 覆蓋刖述被處理基板w，而前述遮蔽板26係構成為將前述 處理容器21内之作業空間21八分割成包含前述基板表面且 產生#刻及錢射之作業空間部分21、；與自前述線圈22供 給鬲頻電力且激勵高密度電漿之作業空間部分21A2，又， 5於則述遮蔽板26上形成比前述被處理基板W之直徑大之開 口部 26A。 第4圖之電漿姓刻裝置2〇中，於前述作業空間η、激勵 之姓刻氣體的自由基及離子係通過前述遮蔽板26中之開口 部26A而到達前述被處理基板w之表面，且於基板前面進行 10 相同而有效之蝕刻。 另一方面’於因隨著前述離子之碰撞所造成之濺射作 用而放出之賤射粒子中，朝前述處理容器21之側壁面飛散 者可利用前述遮蔽板26來捕獲，結果，不會產生於前述處 理容器21側壁面上之堆積物之形成。 15 再者’第4圖之電漿蝕刻裝置20中，由於前述遮蔽板26 中之開口部26A係以直徑大於前述被處理基板界之直徑形 成於前述被處理基板W之上方附近，因此，即使形成於前 述遮蔽板26上之堆積物剝離，業已剝離之堆積物亦不會掉 落至被處理基板W之表面，且可避免半導體裝置之製造成 20 品率降低之問題。 特別是若前述被處理基板W為直徑15至20cm之晶圓 時，藉由將前述開口部26A設定為比前述晶圓直徑大〇.5〜 5cm，且將前述被處理基板w之表面與前述遮蔽板26間之距 離Η設定為15cm或小於15crn，則即使自前述遮蔽板26剝離 13 200532793 之堆積物踏上不規則之路徑 理基板W表面之機率。 亦可降低其掉落至前述被處 #第4圖之電錄刻裝置2〇中，於進行餘刻作業時，本實 ^例係藉由將前述石英側壁部21Β上之金屬蓋21C接地，使 10 15 自高頻f源28錢職㈣料Μ絲於前述被處理基 ^上之負基板偏壓有效地作用，且可實現高㈣速度。 =時’藉由此種構造，通過開口部26A而堆積於前述金屬蓋 2lC下面之濺射粒子因通過前述開口部26八新進來之帶電 杈子而承受逆濺射作用，結果，於前述處理容器21中，位 2前述被處理基板W上方附近之部分所形成之堆積物只有 U即，右為箣述構造，則於前述金屬蓋21C下面中， 在前述被處理基板w之上方附近部分不會堆積厚堆積物。 欠即使則述開口部26A露出前述被處理基板w，堆積物透 過前述開口部26A而自前述金屬蓋21(：:掉落至前述基板界上 之虞亦少。 第5圖係顯示前述遮蔽板26之詳情。 芩照第5圖，於前述遮蔽板26之下面，藉由喷砂處理等 以0.1〜數毫米之間距形成微細凹凸26&。 藉由形成前述凹凸26a，使前述遮蔽板26下面之表面積 曰加’且自而述被處理基板W表面丨賤射之堆積物w‘可有效 地利用前述凹凸面26a來捕獲。又，依此，遮蔽板26下面之 表面積增加之結果，使平均單位面積之堆積物W‘厚度減少。 另’第5圖中係以具有矩形截面者來表示前述凹凸面， 但畢竟是模式圖，亦可如第6圖所示，具有鋸齒波狀截面或 14 200532793 不規則之截面。 第4圖之電祕理裝置20巾，由於基板保持台25係呈水 平地保持被處理基板W，因此，基板之拆卸容易，且可得 到可減輕來自基板上方之掉落物所造成之被處理基板w的 5 污染之理想效果。 〔第2實施例〕 第7圖係顯示依據本發明第2實施例之電聚餘刻裝置4〇 之構造。然』，第7圖中，對應於前述部分之部分係附上相 同之參照標號且省略說明。 10 參照第7圖’前述電襞姓刻裝置40係具有與第4圖之電 雜刻裝置20類似之構造’但具有遮蔽板扣以取代前述遮 蔽板26。 遮蔽板46亦與前述遮蔽板26相同，具有比前述被處理 基板W之直徑大之開口部46A，然而，於前述遮蔽㈣中， U包含前述開口部46A之内緣部係於接近前述開口部46八中 心之部分46B形成向上方彎曲之斜面。 第7圖之姓刻裝置40中，藉由依此於前述遮蔽板46上形 成向上方彎曲之斜面偷，增加自前述被處理基板W放出之 濺射粒子之捕獲面積，且可更有效地抑制於前述石英側壁 2〇部21B之濺雜子之堆積，以及除去因堆積物之剝離所造二 之碎屑。又’藉由形成前述斜面偏，則即使業已剝離之堆 積物掉落至前述遮蔽板46上，前述剝離物亦不會通過前述 開口部46A而掉落至被處理基板W之表面。 第8圖係顯示第7圖電漿㈣裝置40之-變形例之 15 200532793 電漿蝕刻裝置40A之構造。然而，第8圖中，對應於前述部 分之部分係附上相同之參照標號且省略說明。 茶照第8圖，電漿蝕刻裝置40A係於前述斜面46B之内 緣形成向上部延伸之延伸部46C，以區隔出前述開口部 5 46A。藉由形成前述延伸部46C，可進一步增加前述濺射粒 子之捕獲面積，且可有效地阻止剝離而掉落至遮蔽板如上 之堆積物掉落至前述被處理基板W之表面。 〔弟3實施例〕 第9圖係顯示依據本發明第3實施例之電漿蝕刻裝置6〇 10之構造。然而，第9圖中，對應於前述部分之部分係附上相 同之參照標號且省略說明。 +照第9圖’電漿蝕刻裝置60係具有與第4圖之電漿蝕 刻裝置20類似之構造，但於前述遮蔽板牝之一部分設置有 用以控制岫述遮蔽板46之溫度之加熱器等溫度控制部恥^^ 15 前述溫度控制部46H係將前述遮蔽板46之溫度進行常 時數十度至200 C之溫度之保持，1包含拆卸前述被處理基 板W時’藉此’可抑制前述遮蔽板46之溫度在例如更換被 處理基板W時下降，並因熱膨脹係數之差使前述遮蔽板46 上所捕獲之堆積物剝離而掉落至被處理基板W上。 2〇 另，刖述溫度調節部46H亦可設置於前述實施例及以下 說明之實施例中之任一者。 〔第4實施例〕 第1〇圖係顯示依據本發明第4實施例之電漿蝕刻裝置 8〇之構造。然而，第1〇圖中，對應於前述部分之部分係附 16 200532793 上相同之參照標號且省略說明。 例係於第4圖之電襞钱刻裝置中，將由石英或氧 化銘所構成之遮蔽板46置換為金屬遮蔽板86。、一 於前述處理容器21中設置有金屬遮蔽板晴， =器21中之電*形成會受到前述金— 故’於第U)圖之電漿姓刻裝置8〇中，為了控制前述全 屬遮敝板86之電位，與前述金屬遮蔽板％電連接而設 電壓控制電路86a。 1〇 #由前述構造，而不會對前述處理容H21中之電漿形 成造成實質上之影響，且可抑制麟粒子堆積於處理容器 21之内壁。 以上針對ICP型電漿蝕刻裝置說明本發明，然而本發明 並不限於前述特定之電漿蝕刻裝置，對於ECR型等其他形 15式之高密度電漿蝕刻裝置亦可同樣地適用。 可使用本發明之電漿蝕刻裝置，形成前面第1八〜1〇圖 中所說明之強介電體電容器。此時，藉由使用本發明之電 漿蝕刻裝置，則不僅是基板上所形成之PZT膜，亦可將 PLZT((Pb，La)(Zr，Ti)03)、SBT(SrBi2(Ta，Nb)2〇9)等其他強介 20 電體膜、BST(BaSrTi03)膜、ST0(SrTi03)膜、ΗίΌ2膜等高 介電體膜、含有A卜Ti等金屬元素之金屬氧化膜及含有pt、 Ir、Ru、Co、Fe、Sm、Ni中之任一者之金屬膜或化合物膜 以更有效率且具有高成品率地形成圖案。 產業上之可利用性 17 200532793 右错由本發明，則在使用高密度電漿將基板保持台上 之被處理基板進行電漿姑刻時，可藉由前述遮蔽板有效地 捕捉因伴隨著電聚钮刻產生之機射作用而自前述被處理基 板放出之粒子，且可抑制堆積物堆積於前述處理容器内 5壁。此日寺’由於前述遮蔽板具有大於冑述被處理基板之大 小之開口部，因此，即使堆積於前述遮蔽板上之堆積物剝 離，亦不會掉落至前述被處理基板上，且藉由使用前述遮 蔽板，而不會降低半導體裝置之製造成品率。又，藉由於 前述遮蔽板形成大於前述被處理基板之大小之開口部，於 10 前述基板前面可進行相同之電漿蝕刻處理。 I：圖式簡單說明2 第1A〜1D圖係顯示習知強介電體電容器之製造程序 圖。 第2圖係顯示習知ICP型高密度電漿蝕刻裝置之構造 15 圖。 第3圖係說明第2圖之電漿蝕刻裝置之問題點之圖。 第4圖係顯示依據本發明第1實施例之電漿蝕刻裝置之 構造圖。 第5圖係顯示第4圖之電漿蝕刻裝置中所使用之遮蔽板 20 之構造圖。 第6圖係顯示第5圖之遮蔽板之一變形例之圖。 第7圖係顯示依據本發明第2實施例之電漿蝕刻裝置之 構造圖。 第8圖係顯示第7圖之電漿姓刻裝置之一變形例之圖。 18 200532793 第9圖係顯示依據本發明第3實施例之電漿蝕刻裝置之 構造圖。 第10圖係顯示依據本發明第4實施例之電漿蝕刻裝置 之構造圖。 5 【圖式之主要元件代表符號表】 1.. .>5夕基板 14，24…高頻電源 2...絕緣膜 15，25…基板保持台 3...下部電極層 16...阻隔電容器 3A...下部電極 18，28...高頻偏壓電源 4...強介電體膜 21Ai，21A2·.·作業空間部分 4A...強介電體電容器絕緣膜 21B...側壁部 5...上部電極層 21C...金屬蓋 5A...上部電極 21D...本體部 6…第1密封層 26，46...遮蔽板 7...第2密封層 26A，46A··.開口部 10,20,40,40A，60,80".ICP 26a...凹凸 型電漿蝕刻裝置 46B...斜面 10A，20A·.·排氣口 46C...延伸部 11，21…處理容器 46H...溫度控制部 11A，21A…作業空間 86...金屬遮蔽板 11a，21a…電漿氣體供給口 86A...電壓控制電路 lib，21b…處理氣體導入口 W...被處理基板 12，22…線圈 W‘...堆積物 13，17，23，27...阻抗整合電路200532793 Rose, description of invention: c Mingbei] TECHNICAL FIELD The present invention relates generally to etching technology, and more particularly to an etching device for manufacturing semiconductor devices. Plasma engraving is an indispensable technology in the manufacture of semiconductor devices, and in the manufacture of general semiconductor devices, various etching devices, mainly parallel plate type etching devices, are used. In the manufacturing process of the conventional semiconductor device, the I engraving technique is mainly used to form a pattern of an insulating film mainly composed of SiO2, or a pattern of forming a metal film such as A1, w, or Ti. On the other hand, in the recent strong dielectric memory (FeRA) VI), there are PZT (Pb (Zr, Ti) 03), PLZT ((Pb) (Zr, Ti) 03), BST (BiSrTi03) or STO (SrTi〇3) ferroelectric film or high-dielectric film and semiconductor film with electrode film made of Pt, I5 Ir or Ru low-pressure metal materials, in order to etch these films , Must have high electron density and electron energy (electron temperature), therefore, must use ECR type, spiral sub type or ICP (inductive coupling) type high density plasma etching device, among them, especially because of ICP type etching device The device structure is relatively simple, so it is often used by people. 20 [Prior Art] Background Art Figures 1A to 1D show a part of the manufacturing process of the conventional FeRAM, especially the manufacturing process of the ferroelectric capacitor. Referring to FIG. 1A, an insulating film 2 is formed on a silicon substrate 1 to cover a memory cell of the type shown in FIG. 200532793, and a dense layer (not shown) such as Ti is formed on the insulating film 2 to form a precious metal such as Pt on the insulating film 2. The lower electrode layer 3 is made of a conductive oxide such as IrO2 or SrRuO3. A ferroelectric film 4 such as PZT (Pb (Zr, Ti) 03) is formed on the lower electrode layer 3, and a noble metal such as Pt, Ir, or Ru is formed on the ferroelectric film 5 or The upper electrode layer 5 is made of a conductive oxide such as IrO2 or SrRuO3. Next, in the procedure of FIG. 1B, the upper electrode layer 5 is patterned by a lithography imaging procedure, and an upper electrode 5A is formed on the ferroelectric film 4. 10 The procedure in FIG. 1B is compensated for the oxygen deficiency formed in the above-mentioned ferroelectric film 4 when the upper electrode layer 5 is patterned due to the heat treatment in the oxygen environment. Furthermore, in FIG. In the procedure, a pattern of the ferroelectric film 4 is formed by a lithography imaging program, and a ferroelectric capacitor insulating film 4A is formed on the lower electrode layer 3. 15 In the procedure of FIG. 1C, the strong dielectric capacitor according to the foregoing envy was subjected to heat treatment in the oxidizing environment to compensate for the strong dielectric during the formation of the pattern of the ferroelectric film 4. The oxygen deficiency formed in the bulk capacitor insulating film 48 is covered by the first sealing layer 6 which is barrier to chlorine permeation such as Al203 and covers the upper electrode and the ferroelectric capacitor 20 edge film 4A. . Furthermore, in the first procedure, the lower electrode layer 3 and the Ti adhesion layer below are patterned by the lithography imaging procedure, and the lower electrode 3A is formed. Furthermore, it is formed in the program system of FIG. 1D. The second 200532793 sealing layer 7 composed of Al203 and the like covers the ferroelectric capacitor formed as described above through the first sealing layer 6. In such a manufacturing process of FeRAM, in the lithography imaging process for patterning the lower electrode layer 3, the ferroelectric film 4 and the upper electrode layer 5, the plasma etching operation 5 is used, but these films contain Metal elements with low vapor pressure, and the right etching rate cannot be obtained only by the free radical action excited by the plasma, so a high-density plasma that can produce a significant sputtering effect in addition to the free radical etching effect must be used Etching operation. Fig. 2 shows the structure of the high-density plasma etching conventionally used in Figs. 1 to 10 as an ICP type etching apparatus 10 used in the industry. Referring to FIG. 2, the ICP-type etching apparatus 10 is a quartz bell cover which has a 10A exhaust at the exhaust port and separates the working space 11A. As a processing container, the processing container 11 is provided with The substrate holding stage 15 holding the substrate w to be processed. The coil 12 is wound around the outer periphery of the processing container u, and 15 is used as an antenna. The coil 12 is connected to the high-frequency power source through the impedance integration circuit 13 and the electropolymerized gas such as the electric gas supply port u ^ Ar is introduced into the processing core 11 described above. The high-frequency power is supplied to the coil 12 to form an electric convergence in the processing volume E11. Therefore, by introducing the processing gas 20 through the gas inlet nb, for example, an off-gas containing element is introduced into the processing container u, and free radicals of the etching gas can be excited on the surface of the substrate w to be processed by the plasma. Furthermore, the substrate holding stage has just been described! The 5 series is connected to the high-frequency bias power source 18 through a blocking capacitor i S and an impedance integration circuit 17, and a high-frequency bias power is supplied from the aforementioned high-frequency bias 200532793 voltage source 18 so that a negative bias potential is applied to the aforementioned substrate. Hold on the table 15. As a result of the application of the aforementioned bias potential, cations such as Ar + in the plasma and the radicals hit the substrate to be processed on the substrate holding table 15 at the same time, and simultaneously generate money shots at the same time as the last name. The anisotropic etching is effectively performed in the vertical direction of the substrate to be processed. Patent Document 1 Japanese Patent Laid-Open Publication No. 2000-195841 Patent Document 2 Japanese Patent Publication No. 57-96528 Patent Literature 3 Japanese Patent Publication No. 58-1682330 Japanese Patent Publication No. 4 Japanese Patent Application Laid-Open No. 6-333881 Patent Literature No. 5 Kaiping No. 6-243993 Patent Document 6 Japanese Patent Laid-Open No. 10-16318O Disclosure of Invention However, the result of the sputtering action is added to the substrate W to be processed in accordance with this method. As shown in FIG. 3, there is a problem that particles deposited on the inner wall surface of the processing container 11 are sputtered from the substrate to be processed. In particular, if a high-density plasma etching device is used in the manufacture of a semiconductor device containing a ferroelectric capacitor such as FeRAM as illustrated in FIGS. 1A to 1D, precious metals such as Pt, Ir, or Ru with a low vapor pressure are liable to be generated. 20 Film accumulation. In the case of the ICP plasma etching apparatus 10 shown in FIG. 2, when such a conductive film is deposited on the inner wall surface of the processing container 11, the high-frequency power from the coil 12 cannot reach the working space 11A in the processing container 11. And can not be engraved with electricity. In addition, if the deposit on the inner wall surface of such a processing container 11 is peeled off, 200532793 will become chips, and the manufacturing yield of the semiconductor device will be reduced. If it is a general plasma engraving of 8 丨 02 series insulation film or metal film such as AW, Ti, etc., even if deposits are generated on the inner wall surface of the processing container 11, the cleaning gas is supplied to the foregoing processing. In the container 11, high-frequency power is supplied from the high-frequency 5 source 14 and plasma is induced in the processing container, thereby effectively removing the deposit. In addition, if it is a plasma of a low-dielectric constant interlayer insulating film recently, an oxidizing gas such as oxygen can be supplied to the processing valleyr 11 'and the high-frequency coil is driven by high-frequency power from a high-frequency source 14 12 and by inducing the oxygen plasma in the processing container, deposits such as hydrocarbons adhering to the inner wall of the processing container 11 can be effectively removed. In contrast, in the manufacture of semiconductor devices containing materials with a low vapor pressure and a slow etching rate such as FeRAM, the deposits attached to the inner wall surface of the processing container ^ are mostly materials with low vapor pressure such as precious metals. Therefore, the aforementioned plasma cleaning operation It has no effect, and in order to be effective and have a high yield, it is necessary to disassemble the plasma engraving device 10 and frequently perform wet cleaning with a processing valley of 11. However, such frequent maintenance It will reduce the manufacturing efficiency of semiconductor devices. [Summary of the invention] and a high-frequency source, which are combined with the aforementioned substrate holding table. One object of the present invention is to provide a substrate processing apparatus including a processing container, which is exhausted by an exhaust system, and Those who have a substrate holding table to hold the substrate to be processed and separate the working space in the area; the processing gas supply path is used to introduce _ gas into the aforementioned processing container; the plasma generation source is based on the aforementioned operation The space is formed by electricity gathering; it is characterized in that the first 20 200532793 processing container has a shielding plate, the shielding plate is to divide the aforementioned working space into 1J into a package, and the first working space portion of the surface of the substrate to be processed shall be composed of The second working space portion formed by the remaining area of the foregoing working space is formed on the uranium shielding plate with an opening 5 having a size larger than that of the substrate to be processed. 0 According to the present invention, a high-density plasma is used. When plasma processing is performed on a substrate to be processed on a substrate holding table, the shielding plate can effectively capture the sputtering effect caused by the sputtering effect caused by the plasma etching. Releasing the processing substrate particles and deposits were suppressed in the inner wall of the processing chamber 10. At this time, since the shielding plate has an opening larger than the size of the substrate to be processed, even if the deposit deposited on the shielding plate is peeled off, it will not fall on the substrate to be processed, and by using the foregoing A shield plate without reducing the manufacturing yield of a semiconductor device. In addition, since the shielding plate forms an opening larger than the size of the substrate to be processed, the same plasma etching treatment can be performed in front of the substrate. Other objects and features of the present invention can be clearly understood from the detailed description of the present invention while referring to the drawings. Brief Description of Drawings Figures 1A to 1D are drawings showing the manufacturing process of a conventional ferroelectric capacitor. Fig. 2 is a diagram showing the structure of a conventional ICP-type high-density plasma etching apparatus. FIG. 3 is a diagram illustrating problems of the plasma etching apparatus of FIG. 2. FIG. 4 is a structural diagram of a plasma etching apparatus according to the first embodiment of the present invention. FIG. 5 is a structural diagram of a shielding plate used in the plasma #etching apparatus of FIG. 4. Fig. 6 is a view showing a modification of the shielding plate of Fig. 5; Fig. 7 is a diagram showing the structure of an electric gathering device according to a second embodiment of the present invention. FIG. 8 is a diagram showing a shape example of the plasma etching device of FIG. 7. Fig. 9 is a structural diagram showing a plasma according to the third embodiment of the present invention. Fig. 10 is a structural diagram showing a plasma etching apparatus according to a fourth embodiment of the present invention. C implementation of the cold type] The preferred embodiment of the invention [First Embodiment] The structure of the plasma surname engraving device 20 according to the first embodiment of the present invention is shown in the first line. Product 3, just described 1CP type etching device 20 is equipped with a quartz bell cover 21 at the exhaust port 20-row & H is separated from the working space 21A for processing, and is provided in the processing container 21 for processing the substrate to be processed W The substrate holding table 25 held on the flat surface is wound on the wall portion 2 of the processing container 21 as a * line. The processing container includes: the side 2 is composed of quartz glass, and is separated from the foregoing operation permit door = a sleeve-shaped one ·, a metal cover 21C is formed on the quartz side ㈣ and blocks the operation above The space 21A, and the main body portion 21D, 200532793 are those that surround the substrate holding table 25 below the quartz side wall portion 21B, and support the quartz side wall portion 21B and further form the exhaust port 20A. The monthly coil 22 is connected to the high-frequency power source 24 through the impedance integration circuit 23 and introduces plasma gas such as 5 He'Ne'Ar, Kr, Xe from the plasma gas supply port 21a formed in the metal cover 21C. The container 21 further supplies high-frequency power to the coil 22 from the high-frequency power source 24 to form a plasma in the processing container 21. Therefore, through the processing gas introduction port 21b formed in the main body portion 21D, for example, halogens such as F * C1, such as 2 C; C14 'CF4, CHF3, are introduced into the processing container 21, as described below. The surface of the substrate W to be processed may be excited by the aforementioned plasma to generate free radicals of the etching gas. In addition, the substrate holding table 25 is connected to the high-frequency bias power source 28 through the blocking capacitor 16 and the impedance integration circuit 27, and the high-frequency bias power is supplied from the high-frequency bias power source 28 to make the negative bias power The position is applied to the aforementioned base 15 plate holding table 25. As a result of applying the aforementioned bias potential, cations such as Ar + in the plasma and the radicals collide with the substrate to be processed on the substrate holding table 25 at the same time, and the substrate is raised on the substrate to be processed, and the aforementioned freedom is used. The base etching is sputtered in the same manner, and effective anisotropic etching is performed in a direction 20 that is slightly perpendicular to the substrate w to be processed. In the ICP-type plasma etching apparatus 20 shown in FIG. 4, in order to further capture the low-level particles emitted from the substrate W due to _ and to suppress the formation of deposits on the inner wall of the processing container 21 as much as possible, The substrate w is formed with a shielding plate 26 made of an insulator such as quartz or an oxide. The substrate w is covered with 12 200532793, and the shielding plate 26 is configured to form a working space 21 in the processing container 21. It is divided into a working space portion 21 including the surface of the substrate and generating #nicks and money; and a working space portion 21A2 that supplies high-frequency power from the coil 22 and excites high-density plasma, and the shielding plate 26 is described below. An opening portion 26A having a larger diameter than the substrate W to be processed is formed thereon. In the plasma plasma engraving device 20 shown in FIG. 4, the radicals and ions of the engraved gas in the working space η and the excitation gas reach the surface of the substrate w to be processed through the opening 26A in the shielding plate 26. And the same and effective etching is performed in front of the substrate. On the other hand, among the low-level particles emitted due to the sputtering effect caused by the collision of the ions, those who are scattered toward the side wall surface of the processing container 21 can be captured by the shielding plate 26. As a result, no Formation of deposits on the side wall surface of the aforementioned processing container 21. 15 Furthermore, in the plasma etching apparatus 20 shown in FIG. 4, the opening 26A in the shielding plate 26 is formed near the upper surface of the substrate W to be processed with a diameter larger than the boundary of the substrate to be processed. The deposits formed on the aforementioned shielding plate 26 are peeled off, and the peeled deposits will not fall on the surface of the substrate W to be processed, and the problem of a reduction in the yield of the semiconductor device during manufacture can be avoided. In particular, if the substrate W to be processed is a wafer having a diameter of 15 to 20 cm, the opening portion 26A is set to be larger than the diameter of the wafer by 0.5 to 5 cm, and the surface of the substrate W to be processed and the substrate W If the distance Η between the shielding plates 26 is set to 15 cm or less, the probability that even if the deposit 13 200532793 peeled off from the aforementioned shielding plate 26 steps on an irregular path, the surface of the substrate W will be treated. It can also be reduced to fall into the electric recording and engraving device 20 of the above-mentioned place # FIG. 4. In the remaining operation, this example is by grounding the metal cover 21C on the quartz side wall portion 21B. The negative substrate bias of the 10 15 from the high-frequency f source and the 28-year-old material M wire on the substrate to be processed effectively acts, and a high speed can be achieved. = 时 'With this structure, the sputtered particles deposited under the metal cover 21C through the opening 26A are subjected to the reverse sputtering effect because of the charged branch that newly entered through the opening 26A. As a result, in the aforementioned processing, In the container 21, the deposit formed near the upper part of the substrate W to be processed in position 2 is only U. That is, the right side is a structure described below. In the lower part of the metal cover 21C, the part near the upper part of the substrate w is not. Thick deposits can accumulate. Even if the opening portion 26A exposes the substrate to be processed w, the deposit may pass through the opening portion 26A and drop from the metal cover 21 (:: to the substrate boundary. Fig. 5 shows the shielding plate. Details of 26. According to FIG. 5, a fine unevenness 26 is formed below the aforementioned shielding plate 26 at a pitch of 0.1 to several millimeters by sandblasting or the like. By forming the aforementioned unevenness 26a, the lower surface of the aforementioned shielding plate 26 is formed. The surface area of the substrate W is increased, and the deposited material w 'on the surface of the substrate W to be processed can be effectively captured by the aforementioned uneven surface 26a. In addition, as a result, the surface area under the shielding plate 26 is increased to make the average The thickness of the deposit per unit area W 'is reduced. In addition, the aforementioned concave-convex surface is shown in FIG. 5 as having a rectangular cross-section, but it is a schematic diagram after all, as shown in FIG. 200532793 Irregular cross section. Since the substrate holding table 25 is used to hold the substrate W to be processed horizontally in the 20th figure of the electric secretion device of Fig. 4, the substrate can be easily disassembled, and the drop from the top of the substrate can be reduced. The ideal effect of 5 contamination of the processed substrate w caused by the object. [Second Embodiment] Fig. 7 shows the structure of an electro-polymerization etching device 40 according to the second embodiment of the present invention. Of course, Fig. 7 Among them, the parts corresponding to the aforementioned parts are given the same reference numerals and descriptions are omitted. 10 Referring to FIG. 7, the aforementioned electromechanical engraving device 40 has a structure similar to that of the electrotagging device 20 of FIG. 4 but has The shielding plate is replaced by the shielding plate 26. The shielding plate 46 is also the same as the shielding plate 26, and has an opening 46A larger than the diameter of the substrate W to be processed. However, in the shielding cymbal, U includes the opening 46A. The inner edge portion is formed on a portion 46B close to the eight center of the opening 46 to form an upwardly-curved slope. In the engraving device 40 of FIG. 7, the upwardly-curved inclined surface is formed on the shielding plate 46 according to this, Increasing the capture area of the sputtered particles released from the substrate W to be processed, and more effectively suppressing the accumulation of spatters on the quartz side wall 20B 21B, and removing the debris caused by the peeling of the deposit ... and 'borrowed If the inclined surface is formed, even if the peeled deposits drop onto the shielding plate 46, the peeled objects will not fall to the surface of the substrate W to be processed through the opening 46A. Fig. 8 shows the seventh Fig. 15-Modification of the plasma torch device 40 200532793 The structure of the plasma etching device 40A. However, in Fig. 8, parts corresponding to the aforementioned parts are given the same reference numerals and descriptions are omitted. The plasma etching device 40A is formed on the inner edge of the inclined surface 46B to form an extension 46C extending upward to separate the opening 5 46A. By forming the extension 46C, the capture of the sputtered particles can be further increased. Area, and can effectively prevent peeling off and the deposits falling onto the shielding plate from falling onto the surface of the substrate W to be processed. [Embodiment 3] Fig. 9 shows the structure of a plasma etching apparatus 6010 according to a third embodiment of the present invention. However, in FIG. 9, parts corresponding to the aforementioned parts are given the same reference numerals and descriptions are omitted. + According to FIG. 9 ', the plasma etching apparatus 60 has a structure similar to that of the plasma etching apparatus 20 of FIG. 4, but a heater etc. is provided in a part of the aforementioned shielding plate 有用 for controlling the temperature of the aforementioned shielding plate 46. Temperature control unit shame ^^ 15 The temperature control unit 46H maintains the temperature of the shielding plate 46 at a temperature of tens of degrees to 200 C for a while. 1 Including dismantling the substrate to be processed 'this can suppress the shielding' For example, the temperature of the plate 46 is lowered when the substrate W to be processed is replaced, and the deposit captured on the shielding plate 46 is peeled off due to the difference in thermal expansion coefficient and dropped on the substrate W to be processed. 2〇 The temperature adjusting unit 46H may be provided in any one of the foregoing embodiments and the embodiments described below. [Fourth Embodiment] Fig. 10 shows a structure of a plasma etching apparatus 80 according to a fourth embodiment of the present invention. However, in FIG. 10, the parts corresponding to the aforementioned parts are attached with the same reference numerals as in 2005200532793, and the description is omitted. For example, in the electric money engraving device shown in FIG. 4, a shielding plate 46 made of quartz or an oxide inscription is replaced with a metal shielding plate 86. 1. A metal shielding plate is provided in the processing container 21, and the electricity in the device 21 will be formed by the aforementioned gold. Therefore, in the plasma engraving device 8 in the figure U), in order to control the foregoing The potential of the shielding plate 86 is electrically connected to the metal shielding plate%, and a voltage control circuit 86a is provided. 1〇 #The foregoing structure does not substantially affect the formation of the plasma in the processing volume H21, and it is possible to suppress the accumulation of lin particles on the inner wall of the processing container 21. The present invention has been described above with reference to an ICP type plasma etching apparatus. However, the present invention is not limited to the specific plasma etching apparatus described above, and can be similarly applied to other high-density plasma etching apparatuses of 15 types such as ECR type. The plasma etching apparatus of the present invention can be used to form the ferroelectric capacitor described in the previous eighteenth to tenth figures. At this time, by using the plasma etching apparatus of the present invention, not only the PZT film formed on the substrate, but also PLZT ((Pb, La) (Zr, Ti) 03), SBT (SrBi2 (Ta, Nb ) 2 09) and other ferroelectric 20 film, BST (BaSrTi03) film, ST0 (SrTi03) film, high dielectric film such as Η 2 film, metal oxide film containing metal elements such as Al and Ti, and pt, A metal film or a compound film of any of Ir, Ru, Co, Fe, Sm, and Ni is patterned more efficiently and with a high yield. Industrial Applicability 17 200532793 The invention is right. When the high-density plasma is used to plasma-etch the substrate to be processed on the substrate holding stage, the shielding plate can effectively capture The particles emitted from the substrate to be processed by the mechanical radiation effect produced by the button engraving can prevent the accumulation of deposits on the 5 walls of the processing container. In this temple, because the aforementioned shielding plate has an opening larger than the substrate to be processed, even if the deposit deposited on the shielding board is peeled off, it will not fall on the substrate to be processed. The aforementioned shielding plate is used without reducing the manufacturing yield of the semiconductor device. In addition, since the shielding plate forms an opening larger than the size of the substrate to be processed, the same plasma etching process can be performed in front of the substrate. I: Brief description of the drawings 2 The first 1 to 1D drawings are the manufacturing process diagrams of conventional ferroelectric capacitors. Fig. 2 is a diagram showing the structure of a conventional ICP-type high-density plasma etching apparatus. FIG. 3 is a diagram illustrating problems of the plasma etching apparatus of FIG. 2. Fig. 4 is a structural diagram showing a plasma etching apparatus according to a first embodiment of the present invention. Fig. 5 is a structural view showing a masking plate 20 used in the plasma etching apparatus of Fig. 4. Fig. 6 is a view showing a modification of the shielding plate of Fig. 5; Fig. 7 is a structural diagram showing a plasma etching apparatus according to a second embodiment of the present invention. FIG. 8 is a diagram showing a modification of the plasma engraving device of FIG. 7. 18 200532793 Fig. 9 is a structural diagram showing a plasma etching apparatus according to a third embodiment of the present invention. Fig. 10 is a configuration diagram showing a plasma etching apparatus according to a fourth embodiment of the present invention. 5 [Representative symbol table of main components of the drawing] 1 ... ≫ 5th substrate 14, 24 ... high-frequency power supply 2 ... insulating film 15, 25 ... substrate holder 3 ... lower electrode layer 16. Blocking capacitor 3A ... Lower electrodes 18, 28 ... High-frequency bias power supply 4 ... Ferroelectric film 21Ai, 21A2 ... Work space part 4A ... Ferroelectric capacitor insulating film 21B ... side wall portion 5 ... upper electrode layer 21C ... metal cover 5A ... upper electrode 21D ... main body portion 6 ... first sealing layer 26, 46 ... shielding plate 7 ... second Sealing layers 26A, 46A ... Openings 10, 20, 40, 40A, 60, 80 ". ICP 26a ... Concave and convex plasma etching device 46B ... Slope 10A, 20A ... exhaust port 46C. .. extensions 11, 21 ... processing vessels 46H ... temperature control units 11A, 21A ... working space 86 ... metal shielding plates 11a, 21a ... plasma gas supply ports 86A ... voltage control circuits lib, 21b ... Process gas inlet W ... substrates 12,22 ... coil W '... stacks 13,17,23,27 ... impedance integration circuit
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