200531233 玫、發明說明： 【發明所屬之技術領域】 本發明係關於一種半導體積體電 4+狀丰此 w般电路之覆晶（flip Chip) 封衣，尤彳日-種適詩影像❹"之 裝結構與方法。 工間的後日日封 【先前技術】 10 ::導體積體電路(IC)的產品中，多層封裝為其中一 ::之一’其包含：擴大1C晶粒之電極間距，JL中 外部之應力；提供_適去之^ h曰粒免於受封裝内部與 埶量，m… 以傳送由晶粒發散之 …里，以及形成一電性内部連結。 於封裂所使用之系統，支配了 f衣的方法相 能、與可靠度。 了整個封▲晶粒的總成本、性 15 1C晶粒的封裝形式可大體分為兩類：… ㈣式封裝。一晶粒利用密封式封裝封裝二： 境係由—真空密封或特定氣體包圍之空間所p離界核 裳：為陶究封裝並採用高效能應用。換言;離二種封 用非松封式封裝封裝時，其並 、 曰曰；'立利 :式封裝較非密封式封裝製造成本高; :::特^用，例—200531233 Description of the invention: [Technical field to which the invention belongs] The present invention relates to a flip chip coating for a semiconductor integrated circuit, such as a W-shaped circuit, especially a day-special poetry image. &Quot; Installation structure and method. The day after tomorrow ’s work [prior art] In the product of 10 :: conducting volume circuit (IC), the multilayer package is one of the :: one ', which includes: increasing the electrode spacing of 1C die, external stress in JL Provide _ suitable to go ^ h said that the grain is free from the inside of the package and the volume, m ... to transfer the ... diverged from the grain, and to form an electrical internal connection. The system used for sealing cracks dominates the performance, reliability, and reliability of the f-coat method. The total cost and performance of the whole package 15 1C die package can be roughly divided into two categories: ... 封装 package. One die uses hermetically sealed packaging. Two: The environment is enclosed by a vacuum-seal or space surrounded by a specific gas. Out-of-bounds core: It is a ceramic package and uses high-performance applications. In other words, when the two types of packages are packaged in non-loose packages, they are combined; 'Lily: package is more expensive to manufacture than non-sealed packages; ::: 特 ^ 用 ， 例 —
口口然而，近來先進之宓扭斗#壯成7 ^ /MJ 其使用範圍盘財ώ 衣使用於塑膠封袈已擴大 處理，故塑膠封裳具有高成本效益。利於自動批次 20 200531233 近來發展之1c晶粒封裝為球狀閘陣列（Ball Grid Anray， BGA)封裝，其可用於陶瓷封裝與塑膠封裝，並影響不同形 式之之内部封裝結構。BGA封裝利用複數個焊接球或凸塊 作為1C晶粒與其他微電子元件間之電性、機械、或熱之内 5部連結。此焊接凸塊提供1C晶粒固定於電路板上，並使晶 粒電路圖與電路板上之導電圖樣產生電性上之内部連接。 BGA技術包含在接合技術之下，此接合技術廣泛定義為 C4(Controlled Collapse Chip Connection)或覆晶技術。 覆晶技術可用於各種不同形式之電路板接合，其包含 10陶瓷基材、印刷線路板、可撓式電路、與矽基材。焊接凸 塊般位於復晶之面積陣列（Area Array)之導電性接合墊 (bond pad)上，導電性接合墊係與覆晶上之電路圖在電性上 内部相連接。因在覆晶之微電路中一般會執行各種功能， 故相對地需要眾多之焊接凸塊。通常覆晶之各邊尺寸約在 15 13111111間，造成焊接凸塊沿覆晶之週緣擁塞。因此，覆晶之 導電圖樣由各種個別之導體組成，此導體通常之間距S約 等於或小於〇. 1 mm ° 圖1顯示為一般傳統之覆晶26，其包含一焊接凸塊 1〇,其直接焊接於凸塊接墊14之連續上表面，此凸塊接墊 20 14通常為一方形結構如圖1A所示，並且由保護層12部分覆 盍，此保護層12可為SiN或Si02。在保護層12之一圓形接 墊開口 13與凸塊接墊14相接觸，焊接凸塊1〇藉由此接墊開 口 13延伸至凸塊接墊14。而凸塊接墊14被覆晶26之介電層 15 (如氧化層）所包圍。 200531233 另外圖1還顯示凸塊接墊14與上導電層16電性接觸， 此上導電層16藉由絕緣層18與下導電層22分隔。導電層16 與22藉由在絕緣層18延伸貫穿之導電通孔2〇使其互相在電 11相連。不同之絕緣層1 8與導電層22係依照半導體製程之 5傳統方式依序沈積於矽晶粒基材24上。 在知接凸塊1〇形成於覆晶％之後，晶粒26即反轉（亦 所叫復晶）’此時焊接凸塊10隨即接合於基材28 (如印刷 電路板PCB上）之電性端點上。如圖1B所示，一般覆晶％ -提仏連串行列之焊接凸塊10。通常在覆晶26之行列間 10會有空乏區間11存在於相鄰之焊接凸塊10間，此乃由於製 造晶粒之積體電路結構或其他之考量所致。 在焊接凸塊10接合於PCB基材28後，覆晶26將接受一 1串之測試，例如：凸塊剪力測試與晶片剪力（die shear test) =測，在此測試下為施予一剪應力於覆晶26上，以測定在 15设日日26與接合1"0^基材28間之電性連接點的機械整合程 度。覆晶26亦會接受溫度檢測，在此檢測下覆晶％一般會 達到150°C之溫度。然而，無引線晶片承載（LeadiessMouth-mouth, however, recently, the advanced 宓 宓 斗斗 # 壮 成 7 ^ / MJ has been used to expand the use of clothes for plastic seals, so plastic seals are highly cost-effective. Facilitates automatic batching 20 200531233 The recently developed 1c die package is a Ball Grid Anray (BGA) package, which can be used for ceramic and plastic packaging, and affects different types of internal packaging structures. The BGA package uses a plurality of solder balls or bumps as the electrical, mechanical, or thermal connection between the 1C die and other microelectronic components. This solder bump provides 1C die to be fixed on the circuit board, and makes the chip circuit diagram and the conductive pattern on the circuit board to be electrically connected internally. BGA technology is included under the bonding technology, which is widely defined as C4 (Controlled Collapse Chip Connection) or flip-chip technology. The flip-chip technology can be used for various forms of circuit board bonding, including 10 ceramic substrates, printed circuit boards, flexible circuits, and silicon substrates. The solder bumps are located on the conductive bond pads of the area array of the compound crystal. The conductive bond pads are electrically connected internally with the circuit diagram on the flip-chip. Since various functions are generally performed in flip-chip microcircuits, a relatively large number of solder bumps are required. Usually the size of each side of the flip chip is between 15 13111111, causing the solder bumps to congest along the periphery of the flip chip. Therefore, the conductive pattern of the flip chip is composed of various individual conductors, and the distance S between the conductors is usually equal to or less than 0.1 mm. Figure 1 shows a general conventional flip chip 26, which includes a solder bump 10, which It is directly welded to the continuous upper surface of the bump pad 14. The bump pad 20 14 is generally a square structure as shown in FIG. 1A and is partially covered by a protective layer 12. The protective layer 12 may be SiN or SiO 2. A circular pad opening 13 in one of the protective layers 12 is in contact with the bump pad 14, and the solder bump 10 extends to the bump pad 14 through the pad opening 13. The bump pad 14 is surrounded by a dielectric layer 15 (such as an oxide layer) of the flip chip 26. 200531233 In addition, FIG. 1 also shows that the bump pad 14 is in electrical contact with the upper conductive layer 16, and the upper conductive layer 16 is separated from the lower conductive layer 22 by an insulating layer 18. The conductive layers 16 and 22 are electrically connected to each other by conductive vias 20 extending through the insulating layer 18. The different insulating layers 18 and conductive layers 22 are sequentially deposited on the silicon die substrate 24 according to the traditional method of the semiconductor process. After knowing that the bumps 10 are formed in the flip-chip%, the grains 26 are reversed (also called complex crystals). At this time, the solder bumps 10 are then bonded to the substrate 28 (such as on a printed circuit board PCB). Sexual endpoint. As shown in FIG. 1B, the general flip-chip soldering bumps 10 are arranged in series. Usually, there will be an empty section 11 between the rows and columns 10 of the flip chip 26 between adjacent solder bumps 10, which is due to the integrated circuit structure of the die or other considerations. After the solder bump 10 is bonded to the PCB substrate 28, the flip chip 26 will undergo a series of tests, such as: bump shear test and die shear test = test, which is given under this test A shear stress was applied to the flip chip 26 to determine the degree of mechanical integration of the electrical connection points between the 15 set date 26 and the bonding 1 " 0 ^ substrate 28. The flip chip 26 will also undergo a temperature test. Under this test, the flip chip% will generally reach a temperature of 150 ° C. However, leadless wafer loading (Leadiess
Camer，LCC)封裝一般使用於影像感測器中，如電荷耦合 凡件（Charge Coupled Device，CCD)或互補式金屬氧化半 2〇 導體（C0mplementary Metal Semic〇nduct〇r，cm 影像感測器。 電荷耗合元件（C C D)影像感測器為一可將光學圖樣或 影像轉換為電荷圖樣或電子影像之電子元件。ccd包含數 個感光單元’此感光單元具有修正、儲存、與傳輸電荷至 200531233 刀 〜从性買會影響影像感 計之材料選擇。每-感光單元代表_晝素。半導料= =規則支配晝素之行列結構與矩陣結構，並由位粒 邊緣之一或多個輸出放大器修正由咖傳出之訊號。 之脈衝獲得，此脈衝在另-脈衝傳輸至 刖出放大„。傳輸後依行列順序傳輸_畫素之電荷， 出放;大器轉換電荷為Μ。外部電路以―適當之形式傳^ 輸出訊號以偵測或榻取。 · j 10 15 互，，金屬氧化半導體影像感測器操作電壓低於 Γί元件(CCD)影像感測器’其為減少電量損耗利於攜 :二—CMOS主動式晝素感測單元本身具有暫存之放大 益，^可獨立做讀寫動作。—般使用之晝素感測單元具有 四個電晶體與一光感單元。此晝素感測單元 :隔’-介於洋擴散與電源供應之重置閘極(γ_ _). :共汲極組態f晶體（議rce_f〇11〇wer tr_ist〇r)係將讀出 暫存於浮擴散中；以及一列選擇閉極，以連接晝素 =早凡至讀出線。所有行連接之畫素均與一共同 大态相接。 2〇 目較於CCD影像感測器，CMOS影像感測器除具有低 耗=外丄由於其去耗與結晶特性，通常設計較為簡單。故 其设计容易小型化並具有較少之支撐電路需求。 傳統之無引線晶片承載封裝30如圖i C所示。此封裝 3〇 一般使用於CCD*cm〇s影像感測器之ic晶粒，其包^ 200531233 一透明覆蓋玻璃層32,其具有一支撐層35。一防反射塗覆 34介於覆蓋玻璃32與支撐層35之間。一多層基材％包含一 城堡狀結構4 2其上提供一影像感測器晶片3 8。上部鉛4 〇由 晶片38延伸而出並與底部鉛44電性上相連接，此底部鉛 5包覆於基材36之底部與侧邊。而透明覆蓋玻璃32利於將光 傳送至影像感測器晶片38。 10Camer (LCC) package is generally used in image sensors, such as Charge Coupled Device (CCD) or complementary metal oxide semiconductor conductor (cm) image sensor. A charge consumable device (CCD) image sensor is an electronic component that converts an optical pattern or image into a charge pattern or electronic image. The CCD contains several photosensitive units. 'This photosensitive unit has correction, storage, and transfer of charges to 200531233. Knife ~ Buy from sex will affect the material selection of the image sensor. Each-photosensitive unit represents _ day element. Semi-conductive material = = rule dominates the row structure and matrix structure of day element, and is output by one or more of the edge of the grain The amplifier corrects the signal transmitted by the coffee. The pulse is obtained. This pulse is transmitted to the output amplifier in another pulse. After the transmission, the charge of _ pixels is transmitted in the order of rows and columns. The output signal is transmitted in ―appropriate form ^ for detection or detection. · J 10 15 mutual, the operating voltage of metal oxide semiconductor image sensor is lower than the CCD image sensor In order to reduce power consumption, it is convenient to carry: 2. The CMOS active daylight sensing unit itself has a temporary amplification benefit, and can independently perform reading and writing. The general daylight sensing unit has four transistors and one Photosensing unit. This daylight sensing unit: separated by '-reset gate (γ_ _) between ocean diffusion and power supply.: Common drain configuration f crystal (Ne rce_f〇11〇wer tr_ist〇r) The readout is temporarily stored in the floating diffusion; and a column of closed electrodes is selected to connect the day element = the pre-fan to the readout line. The pixels connected in all the rows are connected to a common state. In addition to image sensors, CMOS image sensors have low power consumption. Besides, due to their de-consumption and crystallization characteristics, the design is usually simpler. Therefore, their designs are easy to miniaturize and have less support circuit requirements. Traditional leadless chips The carrier package 30 is shown in Fig. I. This package 30 is generally used for the ic die of a CCD * cms image sensor, and its package is 200531233 a transparent cover glass layer 32, which has a support layer 35. The anti-reflection coating 34 is interposed between the cover glass 32 and the support layer 35. A multilayer substrate% contains A castle-like structure 4 2 is provided with an image sensor chip 38. The upper lead 40 extends from the wafer 38 and is electrically connected to the bottom lead 44. The bottom lead 5 covers the substrate 36. Bottom and sides. The transparent cover glass 32 facilitates the transmission of light to the image sensor chip 38. 10
，，、、引線晶片承載封裝30 一般具有之厚度46為2mm。傾 用無引線W承載封裝娜料之封们G時需要相 間。而在許多狀況下，過大之影像感測器造成了 片承載封裝3〇之天生限制。因此，在影像感測器 封哀上，亟需一種新穎並經改良之封裝結構與方法。 【發明内容】 15 本發明之主要目 測器之封裝結構。 的係在提供一種新穎的用 於影像感 20 本發明之另一目的係在提供一 測器之封裝結構，俾能節省空間。 本發明之另一目的係在提供一 之影像感測器封裝結構。 種新穎的用於影像感 種新穎的球狀閘陣列The lead wafer carrier package 30 generally has a thickness 46 of 2 mm. It is necessary to use the leadless W to carry the sealing materials G of the packaging materials. In many cases, oversized image sensors have created a natural limitation of the chip carrier package 30. Therefore, there is an urgent need for a new and improved packaging structure and method for the sealing of image sensors. [Summary] 15 The package structure of the main visual device of the present invention. The purpose of the invention is to provide a novel image sensing device. Another object of the present invention is to provide a package structure of a detector, which can save space. Another object of the present invention is to provide an image sensor package structure. A novel spherical gate array for image sensing
本發明之另一 測器之封裝方法。 目的係在提供一 種新穎之 封裝影像感 種新穎之封裝結構與 測器之封裝。 、 本赉明之另一目的係在提供一 方法’其適用於CCD或CMOS影像感 10 200531233 ::。目的係在提供-種球狀-列之方法 5 10 15 結—^之封裝 為達成上述目的，本發明 之封裝結構’其包含—玻璃基材;—位測器 合塾層’其提供多個内部覆晶接合塾盘外部接：塾：接 :合t層所提供之視窗，使影像感測器晶粒J向破： 接於玻璃基材上之覆晶接合塾。位 接凸塊連 合塾湘焊接球，與印刷電路板之接合塾對i接:外部接 本發明之影像感測器封裝結構其特徵在於且有 ==更高之空間利用率，在傳統之影像感測器封裝-r ϊ=:=載封裝。本發明之影像感測器封i结： 度約為_〜1400_，而無引線晶片 厂子度約在2mm。故影像感測器元件相較於傳統 ： CMOS影像感測器封裝結構可減少建構之尺寸。 〇或 本發明更進-步針對封裝影像感測器之方法。 包含提供-玻璃基材；提供—接合塾層，其上 / 部覆晶接合墊與外部球狀閘陣列(BGA)接合墊:、該‘二 層位於該玻璃基材上；提供一焊接或非焊接凸塊於一： 感測器晶粒之接合塾上，並相對應於接合塾層之内部= 接合塾上；接合此反轉之影像感測器晶粒於該接合塾= 20 200531233 遠覆曰曰接合墊上；提供一BGA焊接球於該腿接合墊·以 及接合一印刷電路板於該BGA焊接球上。 【實施方式】 5 本發明係關於—封裝影像感測器μ粒之結構與方 法。此結構為一覆晶球狀閘陣列封裝結構，其特徵在於且 有比㈣影像感測器封裝結構更高之空間利用率。故影像 感測器70件相較於傳統之器封裝結構可減少建構之尺寸。 此封裝結構適用於CCD影像感測器或⑽卿像感測器。_ 10 圖2D與酬根據本發明之完整的影像感測器封褒結 構50。封裝結構50包含一玻璃基材52，其上具有一接合塾 =9 ’此接合塾層59包含-聚亞醯胺（p〇lyimide ρι)膠帶之 薄膜層54，亚利用黏貼方式黏著於玻璃基材μ。如圖扣所 示’此玻璃基材之基材厚度53一般約在彻陣至_降之 15門*薄膜層54之膜厚55約為loo# m多個内部覆晶接合墊 56與外部球狀閘陣列（BGA)接合墊58位在薄膜4 面。並在必要時，每一内部覆晶接合塾56係與外部球㈣ « 陣列（BGA)接合墊58利用薄膜層54之導電圖樣使兩者電性 上相接。 20 ^ 一反轉之CCD或CM0S影像感測器1C晶粒60係先形成 複數個内部凸塊62，再接合於每一内部覆晶接合塾％。内 部凸塊62可為焊接凸塊，其可由錫、錯、或錫錯混合物焊 接形成；或者為一非焊接凸塊，其可為金凸塊、或由耵材 料包设‘電金屬4之複合凸塊利用異方性導電膠或非導電 12 200531233 膠接合於内部覆晶接合墊56，一般來說，非焊接凸塊搭配 異方性導電膠或非導電膠較適合於CMOS影像感測1C晶 粒。而接合於每一外部球狀閘陣列（BGA)接合墊58之外部 焊接球70—般具有與内部焊接凸塊62相同之組成。如圖2D 5 所示，此1C晶粒60之厚度61 —般約在250μιη。此1C晶粒60 具有一光接收面60a朝向玻璃基材52之薄膜視窗57 (如圖 2B所示），此薄膜視窗57位於接合墊層59之中央。故此影 像感測器1C晶粒60透過玻璃基材52之薄膜視窗57以接收光 影像72。一 PCB基材66藉由其上相對應之接合墊68與外部 10 焊接球70接合。此PCB基材66包含一外部電路以在必要時 傳輸由影像感測器1C晶粒60所接收之光影像72，並傳輸輸 出訊號以作適當的偵測或擷取。一介於接合墊層59與1C晶 粒60之未填滿材料64其覆蓋於内部覆晶接合墊56與焊接凸 塊62上。 15 請參考圖2A-2E，首先於圖2A中，接合墊層59—般為 方形結構，其通常包含一聚亞Si胺（polyimide PI)膠帶之薄 膜層54，以便於黏著至透明基材52上。薄膜視窗57—般為 方形結構，並由接合墊層59之中央延伸。多個外部接合墊 58—般沿接合墊層59之四個外部邊緣排列為行列。多個内 20 部接合墊56—般沿薄膜視窗57之對邊排列為行列，其與外 部接合墊58之行列平行延伸。而接合墊層59通常利用聚亞 驢胺（polyimide PI)膠帶黏貼於玻璃基材52之上方表面 52a，故玻璃基材52可在黏貼合墊層59前，再包含額外之前 處理，例如在玻璃基材5 2上更可包含其他材料層，例如塗 13 200531233 覆防反射層、或去紅外線層等，以增強影像感測器ic晶粒 60所接收之光影像72或其他效能。 如圖2C所示，在接合墊層59形成於玻璃基材52上後， 一具有内部凸塊62 (例如錫、鉛、或複合凸塊）之影像感 5 測器1C晶粒60反轉並連接至相對應之每一内部接合墊56上 產生電性接觸。故1C晶粒60之光接受面60a透過薄膜視窗57 朝向玻璃基材52之上表面52a。其中内部凸塊62之形狀並非 受限於如圖2所示之圓球形，例如其為複合凸塊時，可為立 方體、圓錐體、圓柱體等。而一般焊接凸塊使用於CCD影 10 像感測器之1C晶粒，而非焊接凸塊用於CMOS影像感測器 之1C晶粒。 如圖2D所示，一介於接合墊層59與1C晶粒60之未填滿 材料64其覆蓋於每一内部焊接凸塊62上。未填滿材料64保 護内部接合墊56與内部焊接凸塊62防止其受到灰塵、水氣 15 或其他污染，以增強介於内部接合墊56與1C晶粒60之電性 連接可靠度。未填滿材料64可為任意適當之材料包含環氧 樹脂之小型填充料以增強散熱。此外，在1C晶粒60與接合 墊層59之間，可再包含一透光性材料於間隙區63中，以降 低其間光訊號之反射震盪雜訊。Another packaging method of the present invention. The purpose is to provide a novel package image sensor, a novel package structure and a sensor package. 2. Another purpose of the present invention is to provide a method, which is applicable to CCD or CMOS image sensing. 10 200531233 ::. The purpose is to provide a kind of spherical-column method. 5 10 15 Packaging of knots ^ In order to achieve the above-mentioned purpose, the packaging structure of the present invention 'comprises-a glass substrate;-a positioner coupling layer' which provides multiple Internal flip-chip bonding 外部 external connection: 塾: connected: the window provided by the t layer, so that the image sensor grain J is broken: a flip-chip bonding 接 connected to a glass substrate. The connecting bumps are connected with the Xiang solder balls, and are connected with the printed circuit board. Butt-to-i connection: The image sensor package structure of the present invention is externally connected, which is characterized by a higher space utilization ratio of ==. Sensor package -r ϊ =: = carrier package. The image sensor sealing junction of the present invention has a degree of about _ ~ 1400_, and a leadless wafer factory has a degree of about 2mm. Therefore, the image sensor element is compared with the traditional: CMOS image sensor package structure can reduce the size of the construction. 〇 Or The present invention is further directed to a method for packaging an image sensor. Contains a supply-glass substrate; a supply-bonding layer, the top / bottom flip-chip bonding pads and external ball-gate array (BGA) bonding pads: the 'two layers are located on the glass substrate; a welding or non- The solder bumps are on one: the joint of the sensor chip and the inside of the joint layer = the joint; the joint of the inverted image sensor chip on the joint 塾 = 20 200531233 A bonding pad is provided; a BGA solder ball is provided to the leg bonding pad, and a printed circuit board is bonded to the BGA solder ball. [Embodiment] 5 The present invention relates to the structure and method of encapsulating μ-particles of an image sensor. This structure is a flip-chip spherical gate array package structure, which is characterized by a higher space utilization rate than a tritium image sensor package structure. Therefore, compared with the traditional package structure, the image sensor 70 can reduce the construction size. This package structure is suitable for a CCD image sensor or an image sensor. _ 10 FIG. 2D is a complete image sensor sealing structure 50 according to the present invention. The packaging structure 50 includes a glass substrate 52 having a bonding layer 9 thereon. The bonding layer 59 includes a film layer 54 of polyimide tape, which is adhered to the glass substrate by an adhesive method.材 μ。 Material μ. As shown in the figure, the substrate thickness 53 of this glass substrate is generally about 15 gates to the bottom of the array * The film thickness 55 of the thin film layer 54 is about loo # m multiple internal flip-chip bonding pads 56 and external balls The gate array (BGA) bonding pads 58 are located on the four sides of the film. When necessary, each of the internal flip-chip bonding pads 56 and the external ball bonding array 58 (BGA) bonding pads 58 are electrically connected to each other using the conductive pattern of the thin film layer 54. 20 ^ An inverted CCD or CM0S image sensor 1C die 60 is formed with a plurality of internal bumps 62, and then bonded to each internal flip-chip bond 塾%. The internal bump 62 may be a solder bump, which may be formed by welding of tin, tin, or a tin tin mixture; or a non-weld bump, which may be a gold bump, or a composite of 'electric metal 4' covered with a rhenium material. The bumps are bonded to the internal flip-chip bonding pads 56 using anisotropic conductive adhesive or non-conductive 12 200531233 glue. Generally speaking, non-welded bumps with anisotropic conductive glue or non-conductive glue are more suitable for CMOS image sensing 1C crystals. grain. The outer solder ball 70 bonded to each outer ball gate array (BGA) bonding pad 58 generally has the same composition as the inner solder bump 62. As shown in FIG. 2D 5, the thickness 61 of the 1C grain 60 is generally about 250 μm. The 1C die 60 has a thin film window 57 (as shown in FIG. 2B) with a light receiving surface 60 a facing the glass substrate 52, and the thin film window 57 is located in the center of the bonding pad layer 59. Therefore, the crystal grain 60 of the image sensor 1C passes through the thin film window 57 of the glass substrate 52 to receive the light image 72. A PCB substrate 66 is bonded to the external 10 solder balls 70 through the corresponding bonding pads 68 thereon. The PCB substrate 66 includes an external circuit to transmit the light image 72 received by the image sensor 1C die 60 when necessary, and transmit the output signal for proper detection or capture. An unfilled material 64 between the bonding pad layer 59 and the 1C crystal grain 60 covers the internal flip-chip bonding pad 56 and the solder bump 62. 15 Please refer to FIGS. 2A-2E. First, in FIG. 2A, the bonding pad layer 59 is generally a square structure, which usually includes a thin film layer 54 of polyimide PI tape for easy adhesion to the transparent substrate 52. on. The film window 57 is generally a square structure and extends from the center of the bonding pad 59. A plurality of external bonding pads 58 are generally arranged in rows and columns along the four outer edges of the bonding pad layer 59. The plurality of inner 20 bonding pads 56 are generally arranged in rows and columns along the opposite sides of the film window 57 and extend parallel to the rows and columns of the outer bonding pads 58. The bonding pad layer 59 is usually adhered to the upper surface 52a of the glass substrate 52 with a polyimide PI tape. Therefore, the glass substrate 52 may include additional pre-treatment before the pad 59 is adhered, for example, glass The substrate 52 may further include other material layers, such as coating 13 200531233 with an anti-reflection layer, or an infrared-ray removing layer, etc., so as to enhance the light image 72 or other performance received by the image sensor ic die 60. As shown in FIG. 2C, after the bonding pad layer 59 is formed on the glass substrate 52, an image sensor 5 having internal bumps 62 (such as tin, lead, or composite bumps) 1C grain 60 is inverted and Electrical contact is made on each of the corresponding internal bonding pads 56. Therefore, the light receiving surface 60a of the 1C die 60 passes through the thin film window 57 and faces the upper surface 52a of the glass substrate 52. The shape of the inner bump 62 is not limited to the spherical shape shown in FIG. 2, and for example, when it is a composite bump, it may be a cube, a cone, a cylinder, or the like. Generally, solder bumps are used for the 1C die of a CCD image sensor, while solder bumps are used for the 1C die of a CMOS image sensor. As shown in FIG. 2D, an unfilled material 64 between the bonding pad layer 59 and the 1C die 60 covers each of the internal solder bumps 62. The underfill material 64 protects the internal bonding pads 56 and the internal solder bumps 62 from dust, moisture 15 or other contamination, so as to enhance the reliability of the electrical connection between the internal bonding pads 56 and the 1C die 60. The underfill material 64 may be any suitable material including a small filler containing epoxy resin to enhance heat dissipation. In addition, between the 1C die 60 and the bonding pad layer 59, a translucent material may be further included in the gap region 63 to reduce the reflection vibration noise of the optical signal in between.
20 如圖2E所示，在未填滿材料64沈積於接合墊層59與1C 晶粒60間後，外部焊接球70對應形成於每一外部接合墊58 上。隨後位在PCB基材66之多個接合墊68相對應接合於外 部焊接球70上，以完成影像感測元件74。 14 200531233 再參相2D，其f彡㈣測器之㈣結構观為本發明 之技術内合，其具有之總厚度51_般介於彻卿。 其遠小於—般習知之像感測器之封裝結構，其f知技ϋ 一般厚度約為2mm。故相較於使用傳統之CCD或cm〇1影 像感測器之封裝結構，影像感測元件7 4可具有更小之尺寸。 圖3係為-般製作影像感測器封裝結構製程步驟之概 括流程圖。在製程步驟S1中，内部接合墊與外部接合塾提 供於接合塾層上。在製程步驟㈣，此接合㈣提 10 玻璃基材上。在製程步驟幻中，提供一具有内部凸塊之影 像感測ifIC晶粒。在製程步驟以中，反轉此影像感測器使 其接合於接合塾層之内部接合塾上。在製程步驟則，提 供-未填滿材料於IC晶粒與接合塾層之間，防止内部接人 塾與内部焊接凸塊受到灰塵、水氣與其他之污染。在梦程 步驟S6中，相對應於接合塾層之外部接合塾提供外部 15球。在製程步驟S7中，裝置一 pcB於外部焊接球。 上述實施例僅係為了方便說明而舉例而已，本發明所 主張之權利範圍自應以申請專利範圍所述為準，而非僅限 於上述實施例。 旧 20【圖式簡單說明】 之結構剖視 圖1係習知之半導體霜a + m Μ 设_之力干接凸塊與接合墊 圖0 圖1Α係習知之半導Β 之結構俯 體覆日日之焊接凸塊與接合墊 視圖。 15 200531233 圖1B係習知之霜曰由曰 視圖。 “曰中-粒上仃列中之多個焊接凸塊之俯 圖ic係習知之用於封裝影像 裝之剖視W。 承载封 圖2A係本發明之位於—玻璃基材上之接合塾層膠帶， 多個内部覆晶接合塾與外部球狀閉陣列（bga)接合塾^ 合墊層之***透視圖。 圖2Β係本發明之位於玻璃基材上之接合㈣之透視圖。 ίο 15 圖2C係本發明之影像感測器之封裝結構之示意圖，係為一 反轉之影像感測器晶粒接合於接合墊層上之覆晶接合塾。 圖2D係本發明之影像感測器之封裝結構之示意圖，係為利 用未填滿材料包覆於覆晶接合墊與凸塊。 圖2Ε係本發明之影像感測器之封裝結構之示意圖，係為將 PCB接合於影像感測器之封裝結構上。 圖3係為依據本發明之方法的封裝步驟流程圖。 【圖號說明】 10 焊接凸塊 11 空乏區間 12 保護層 13 圓形接墊開口 14 凸塊接墊 15 介電層 16 導電層 18 絕緣層 20 導電通孔 22 下導電層 24 石夕晶粒基材 26 晶粒 28 基材 30 無引線晶片承 載封裝 32 玻璃層 34 防反射塗覆 16 200531233 35 支撐層 36 多層基材 38 影像感測器晶 片 40 上部鉛 42 城堡狀結構 44 底部鉛 46 厚度 50 影像感測器封5 1 總厚度 52 玻璃基材 裝結構 52a 上表面 53 基材厚度 54 薄膜層 55 膜厚 56 内部覆晶接合57 薄膜視窗 塾 58 外部球狀閘陣59 接合墊層 60 1C晶粒 列接合墊 60a 光接收面 61 厚度 62 内部凸塊 63 間隙區 64 未填滿材料 66 PCB基材 68 接合墊 70 外部焊接球 72 光影像 74 影像感測元件 17As shown in FIG. 2E, after the unfilled material 64 is deposited between the bonding pad layer 59 and the 1C die 60, external solder balls 70 are correspondingly formed on each of the external bonding pads 58. Subsequently, a plurality of bonding pads 68 located on the PCB substrate 66 are correspondingly bonded to the external solder balls 70 to complete the image sensing element 74. 14 200531233 Re-reference phase 2D. The structure of the f-detector is the technical integration of the present invention. It is much smaller than the package structure of a conventional image sensor, and its thickness is generally about 2mm. Therefore, compared with the packaging structure using a conventional CCD or cm01 image sensor, the image sensing element 74 can have a smaller size. FIG. 3 is an outline flow chart of the general manufacturing process steps for manufacturing an image sensor package structure. In process step S1, an internal bonding pad and an external bonding pad are provided on the bonding pad layer. In the process step, this bonding is carried out on a glass substrate. In the process step, an ifIC die is provided with an image with internal bumps. In the process steps, the image sensor is inverted and bonded to the internal bonding pad of the bonding pad layer. In the process step, provide-unfilled material between the IC die and the bonding pad layer to prevent internal access pads and internal solder bumps from being contaminated by dust, water vapor and others. In step S6 of the dream process, an external 15 ball is provided corresponding to the external joint of the joint layer. In process step S7, a pcB is mounted on an external solder ball. The above embodiments are merely examples for the convenience of description. The scope of the rights claimed in the present invention should be based on the scope of the patent application, rather than being limited to the above embodiments. Old 20 [Simplified illustration of the structure] A sectional view of the structure 1 is a conventional semiconductor cream a + m Μ Design _ force dry contact bumps and bonding pads Figure 0 Figure 1A is the structure of the conventional semiconducting B View of solder bumps and bonding pads. 15 200531233 Fig. 1B is a view of the familiar frost. "The top view ic of the plurality of solder bumps in the middle-upper row is a conventional cross-section W for packaging image packaging. The bearing seal 2A is the bonding layer on the glass substrate of the present invention. Adhesive tape, multiple internal flip-chip joints and external spherical closed array (bga) joints exploded perspective view of the bonding pad. Figure 2B is a perspective view of the joint of the present invention on a glass substrate. Ίο 15 Figure 2C is a schematic diagram of the packaging structure of the image sensor of the present invention, which is a flip-chip bonder in which the inverted image sensor die is bonded to the bonding pad layer. Figure 2D is an image sensor of the present invention. The schematic diagram of the package structure is to cover the flip-chip bonding pads and bumps with unfilled materials. Figure 2E is a schematic diagram of the package structure of the image sensor of the present invention, which is a method of bonding a PCB to the image sensor. Figure 3 is a flowchart of the packaging steps of the method according to the present invention. [Illustration of the drawing number] 10 Welding bumps 11 Empty space 12 Protective layer 13 Round pad openings 14 Bump pads 15 Dielectric layer 16 Conductive layer 18 insulating layer 20 conductive via 22 Lower conductive layer 24 Shi Xi die substrate 26 Die 28 Substrate 30 Leadless wafer carrier package 32 Glass layer 34 Anti-reflection coating 16 200531233 35 Support layer 36 Multilayer substrate 38 Image sensor wafer 40 Upper lead 42 Castle Shaped structure 44 Bottom lead 46 Thickness 50 Image sensor seal 5 1 Total thickness 52 Glass substrate mounting structure 52a Upper surface 53 Substrate thickness 54 Thin film layer 55 Film thickness 56 Internal flip-chip bonding 57 Thin film window 塾 58 External ball gate Array 59 bonding pad layer 60 1C die row bonding pad 60a light receiving surface 61 thickness 62 internal bump 63 gap area 64 unfilled material 66 PCB substrate 68 bonding pad 70 external solder ball 72 light image 74 image sensing element 17