TW200527815A

TW200527815A - Soft-start charge pump circuit

Info

Publication number: TW200527815A
Application number: TW93102336A
Authority: TW
Inventors: Tien-Tzu Chen; Guang-Nan Tzeng
Original assignee: Aimtron Technology Corp
Priority date: 2004-02-02
Filing date: 2004-02-02
Publication date: 2005-08-16
Also published as: TWI229500B

Abstract

A charge pump is driven by at least one clock signal, for converting a supply voltage source into a pumping voltage. The pumping voltage is a function of an amplitude of the at least one clock signal such that an absolute value of the pumping voltage is larger when the amplitude of the at least one clock signal is larger. The amplitude of the at least one clock signal is so modulated as to gradually change from an activation value during an amplitude modulation period. The amplitude modulation period lasts longer than a period of the at least one clock signal by one or more metric orders. The charge pump is activated by the at least one clock signal with the amplitude of the activation value. After the activation, the charge pump is controlled in such a way that the absolute value of the pumping voltage gradually changes along with the modulation of the amplitude of the at least one clock signal.

Description

200527815 玫、發明說明：【發明所屬之技術領域】本t明係關於一種電荷泵電路（Charge Pump Circuit) 尤其關於一種可產生緩啟動泵電壓（Soft-Start Pumping Voltage)之電荷泵電路，用以適當地驅動功率開關（p〇wer SW tCh)而達成抑制啟動時湧入電流（Inrush Current)之效果0 【先前技術】電何泵電路’或稱為電容性電壓多重增加器 (Capacity Voltage MultipUer) ’係一種用以產生比供應至其本身之電壓源更高的職之電路。藉著此—升壓能力，在内卩各、’且成單元需要各種不同的操作電壓之電子系統中，例如可攜式電腦（Portable c〇mputer)，電荷泵電路可 =來從供應電壓源（Supply VGltage “)提供所需之升南的電壓，而減少額外設置獨立的高壓電壓源之需求。另—方面，藉由USB(Universal Serial Bus，通用串列匯，排）連接埠或其他類型連接埠而連接於可攜式電腦之迕夕週邊裝置也需要從供應電壓源汲取能量。在此情況 :由電電路可應用來驅動功率開關，該功率開關通常邊穿置門t晶體所實施且設置來控制供應電壓源與週邊：曰1之切換操作。藉由使NM〇s功率開關電晶體之閘極電壓比其汲極電壓高出畔多# NM0S功率開關雷θ: !何泵電路可完全地導通力羊開關電晶體以便在週邊裳置之正常操作中提供 200527815 最小的導通電阻。兹參照圖1⑷詳細說明習知的電荷果功率開關之電路區塊圖。由於驅動關之汲極D盘源極的功率開轸_ 為功㈣關1G之輸入端與 ^知。功率開1。线極D連接於供應電㈣、，而八源極S則提供輸出電壓vout至外界負载（未具有USB連接埠之週邊裝浐二歹1 功康此外，輸出電容C。連接於力=關1〇之源極S與地面電位間。電荷泵電路" ^壓源Vin轉換成—升高的泵電-I用以控制功率開二〇之間極G。當閑極〇之泵電壓Vpp相當高於沒極D 之众應電壓源vin時，功率開關被凡全導通而提供最的*通電阻’藉而使功率開關10之源極s處之壓V〇ut幾乎等於汲極D處之供鹿電摩源vin得有安文率地供庫^ ln °結*，供應於導通狀態時，從二載。當功率開關1〇處 ^ t 攸供應電壓源Vin流經功率開關10之汲極。源極S之導通電流I〇n即供應至外界負載與輪出電容 C 〇 0 電荷泵電路U之升遂操作係由時鐘產生器12所輸出的至少-個重疊或非重疊的固定振幅時鐘信號13加以控制。習知上，固定振幅時鐘信號13之每—個互為同步的工 =㈣’其頻率係由㈣器14所輸出之具有一預定頻 2振盈信號15來決定。舉例而言’電荷栗電路U得為眾:週知的Dickson型電荷果，如圖1(b)所示。具體而言，電何泵電路11得包括複數個串聯的電荷泵級（sta㈣，其 200527815 中一級係標示著參考編號i 10。每一電荷泵級包括一個二極體m以及一系電容112’並且具有—輸入節點⑴以及一輸出節點114。在此Dickson型電荷泵中，從時鐘產生器12所輸出的固定振幅時鐘信號13係一對互補時鐘信號CLK1與CLK2,用以驅動各級泵電容。時鐘信號驅動奇數泵級，而時鐘信號CLK^驅動偶數果級。第一級串聯電荷泵之輸入節，點115經常連接於供應電塵源 Vin。最末端隔絕二極體116得視為最末級串聯電荷泵之一部分，且從其可獲得電荷泵電路u之泵電壓Vpp。，鐘信號CUU與CLK2得為具有振幅之重疊或非重$的時鐘信號’用以驅動每—級電荷I使傳送至盆輸入節點之電壓升高了 (Velk—Vd)，亦_ U去二極體順向壓降Vd。倘若考慮最末端隔絕二極體116之效用，㈣1(b)所示之電荷菜電路n可達成的理論上最大系電壓VPP為N. Vclk-(N+1). Vd，此處N為電荷泵級之數目。圖2⑷至2⑷顯示圖！⑷所示之習知的電荷果電路" f用於驅動功率開1G之操作時序圖，其中圖2(a)係電 :7泵電路U之泵電壓Vpp之時序圖；圖2(b)係功率開關 =之輸出電壓之時序圖；並且圖2(c)係功率開關ι〇通電流1。„之時序圖。參照圖2⑷，在時間L之前，，為電荷泵電路11處於未賦能⑽齡)狀態，所以其栗電二：。P為零。電荷泵電路u於時間Τα啟動，開始 ^乍用。從_ΤΑ至時間Τβ之過渡時㈣，電荷泵電路之泵電M Vpp從零迅速增加至穩定的最大值，例如前文 200527815 所述的Ν· Vclk—(N+1) · %。電荷泵電路u在時間h處達成穩定的操作狀態，使得泵電壓Vpp維持穩定。多、圖2(b)與2(c)，在啟動時間Ta之前，電荷泵電之泵電壓Vpp小於閥值電μ，所以功率開_玉〇未導通二使得其輪出電壓V-為零並且導通電流1。„亦為零。電荷栗電路11之栗電壓V ρ Ρ達到㈣電難即可導通功率開關:〇而開始對輸出電容C。充電，使得功率開關10之輸出電壓Vout上升。由於電荷粟電路i i之泵電壓使功率開關被驅動成提供最小的導通電阻，故功率開M10之輸出電壓Vout於時間Tc處達成幾乎等於供應電壓源Vin。當應用於驅動功率開關丨〇時，習知的電荷泵電路Η 會造成一問題。因為電荷泵電路u之泵電壓迅速升高，所以功率開關10於啟動初期即提供了最小的導通電阻:然而，由於輸出電壓^於啟動初期為零，亦即輪出電容C。尚未充電，故供應電壓源Vin產生一相當大的導通電流1。„流經功率開關10,此即湧入電流。倘若最大湧= 電流Ipeak不適當地抑制的話，可能造成供應電壓源Vin 烈下降，或是燒毀功率開關i 0。 1η Θ 【發明内容】有鑒於前述問題，本發明之一目的在於提供一種電荷果電路’可產生緩慢上升之緩啟動泵電壓。 σ 本發明之另一目的在於提供一種電荷泵電路，可適去地驅動功率開關而達成抑制最大湧入電流之效果。 200527815 依據本發明電荷泵由至少一時鐘信號所驅動，用以轉換-供應電壓源成為一泵電s。該泵電壓為該至少一時鐘信號之振幅之一函數，使得當該至少一時鐘信號之該振幅愈大時該泵電壓之一絕對值則愈大。該至少一時鐘信號之該振幅係調變成在一振幅調變時期内從一啟動值逐漸變化。該振幅調變時期係比該至少一時鐘信號之一週期更延長一個或更多個數量級。該電荷泵係由該至少一時鐘信號於其振幅為該啟動值時所啟動，使其所產生的該泵電壓之該絕對值相對小。在該啟動後，該電荷泵被控制成所產生的該泵電壓之該絕對值隨著該至少一時鐘信號之該振幅之調變而逐漸變化，藉以抑制該泵電壓之該絕對值之上升速率。較佳地，該至少一時鐘信號之該振幅在該振幅調變時期後達到一穩定值。較佳地，該穩定值係等於該供應電壓源。較佳地，該至少一時鐘信號之該振幅係由一電容在充電過程中所呈現的跨於該電容之一逐漸升高的電位差所決定。較佳地，該泵電壓係用以控制一功率開關。較佳地，該至少一時鐘信號係由一時鐘振幅調變器所產生。該時鐘振幅調變器包含：一緩啟動控制器，用以產生一緩啟動控制信號；以及一位準偏移器，回應於該緩啟動控制信號而調變該至少一時鐘信號之該振幅。較佳地，該緩啟動控制信號係一具有逐漸變化的位準 200527815 之電壓信號。。較佳地，該至少一振幅調變時鐘信號之該振幅係由該緩啟動控制信號之該逐漸變化的位準所決定。較佳地，該緩啟動控制器包含：_切換電容等效電阻’具有第一與第二端點，該第一端點係連接於該供應電 f源；以及一充電電容，連接於該第二端點與地面間，使得該緩啟動控制信號呈現於該第二端點。較佳地，該位準偏移器包含：至少一時鐘通道，分別用於產生：至少一振幅調變時鐘信號’其中該至少一時鐘通道中之每一個具有一輪出級反相器，該輸出級反相器之 -電源供應端係用以接收該缓啟動控制信號，藉以控制該至少一振幅調變時鐘信號中之各個之該振幅。么較佳地’該至少—時鐘通道之每-個更包含：一輸入 =反相器’具有—電源供應端來接收該供應電壓源，用以共—具有固定振幅的時鐘信號至該輸出級反相器。【實施方式】的、：Γ中之說明與附圖將使本發明之前述與其他目發明之較佳更明顯。兹將參照圖式詳細說明依據本於驅發明之緩啟動電荷粟電路31應用可知，之電路區塊圖。比較圖3(a)與圖l(a) 要將依據本發明繞啟勤 w 屮)之習知的何栗電路31取代圖電何泵電路11，即可獲得圖3(a)所示之電路 200527815 區塊圖。圖3(a) % - 功率開關1〇。因：之功率開關30係等同於圖1⑷所示之之電路部分之說明。下文將^略圖3(a)中相同於®⑽ 振幅之:啟動電荷果電路31在至少-個固定啟動特徵的泵電壓：制下將供應電壓源^轉換成具有緩具有緩啟動特制功率開關3G之閘極G。 Y 亡、$ 、7電壓VPPS係指··相較於習知的泵電壓 PP而g ’緩啟動泵電壓V ^ ^ ^ ^ x ^ 所需之過渡時間被相•地延：二動值…達成穩定值過渡時間内之辨力二二緩啟動泵電壓Vp，電路31勺括一曰/、^較緩慢。具體而言，緩啟動電荷泵電荷装：守鐘振幅調變器3"與-時鐘振幅相依型泵電路31。時鐘振幅調變器3U係對於輸入緩啟動電荷變，：至：一個固定振幅時鐘信號13進行振幅調相依 i少：個振幅調變時鐘信號313。時鐘振幅之果312係指其果電壓Vpp之值取決於時鐘振幅典型：：路，！即泵電壓Vpp為時鐘振幅％之函數。 i §時鐘信號之振幅愈大時，時鐘振幅相依型電荷 ^ 之果電壓Vpp即愈大。舉例而言，® Ub)所示的紗型電何果U即為一種時鐘振幅相依型電荷泵，既 :目;泵電星.Vd且時繼大則泵電壓VPP愈大。基於時鐘振幅相依 = =，依據本發明之緩啟動電荷果電…達成具；啟叙、特徵的泵電壓V，。具體而言，在依據本發明之緩啟動電荷泵電路31之一實施例中，至少一個振幅調變時 10 200527815 鐘號3 1 3被設計成其振幅從電荷果電路3 1啟動時之最小值緩慢增加至穩定的最大值而成為連續變化的振幅之時鐘信號。因此，緩啟動電荷泵電路3 1之緩啟動泵電壓200527815 Description of the invention: [Technical field to which the invention belongs] This invention relates to a charge pump circuit, in particular to a charge pump circuit capable of generating a soft-start pumping voltage, which is used to: Properly drive the power switch (p〇wer SW tCh) to achieve the effect of suppressing the inrush current at startup 0 [Prior art] The electric pump circuit 'or Capacitive Voltage MultipUer 'It is a circuit used to generate higher duties than a voltage source supplied to itself. With this—boosting capability, in electronic systems that require various operating voltages in each unit, such as a portable computer (Portable Computer), the charge pump circuit can be used to supply voltage from a source (Supply VGltage ") provides the required voltage in the south, and reduces the need for additional independent high-voltage voltage source. On the other hand, through the USB (Universal Serial Bus, universal serial bus, row) port or other types Port and peripheral devices connected to the portable computer also need to draw energy from the supply voltage source. In this case: an electrical circuit can be applied to drive the power switch, which is usually implemented by passing through a gate t crystal and Set to control the supply voltage source and the surroundings: switching operation of 1. By making the gate voltage of the NM0s power switch transistor higher than its drain voltage # NM0S power switch Thunder θ:! Pump circuit can Completely turn on the power switching transistor to provide the minimum on-resistance of 200527815 in the normal operation of the peripheral device. The circuit of the conventional charge fruit power switch is described in detail with reference to FIG. 1 Block diagram. Because the power of the source D of the drain D drive of the drive switch _ is the input terminal of the power switch 1G and ^. Power is 1. The line D is connected to the supply power, and the eight source S is Provide output voltage vout to the external load (peripheral equipment without USB port 2) 1 Gongkang In addition, the output capacitor C. Connected between the source S of the force = OFF 10 and the ground potential. Charge pump circuit " ^ The voltage source Vin is converted into-a raised pump power -I to control the power to open between the poles G. When the pump voltage Vpp of the idle pole 0 is considerably higher than the corresponding voltage source vin of the pole D, the power switch is Where the full on-resistance is used to provide the most on-resistance, the voltage Vout at the source s of the power switch 10 is almost equal to the supply for the electric motor source vin at the drain D. It must be provided at a safe rate ^ ln ° Junction *, when it is supplied in the on state, it is from the second load. When the power switch 10 is connected, the supply voltage source Vin flows through the drain of the power switch 10. The conduction current Ion of the source S is supplied to the external load. The ascending operation with the wheel-out capacitor C 0 0 charge pump circuit U is at least one overlapping or non-overlapping fixed output by the clock generator 12 The amplitude clock signal 13 is controlled. Conventionally, each of the fixed-amplitude clock signals 13 is synchronized with each other and its frequency is determined by the vibration signal 15 having a predetermined frequency 2 and output by the amplifier 14. For example, the 'charge pump circuit U' is well known: a well-known Dickson-type charge fruit is shown in Figure 1 (b). Specifically, the electric pump circuit 11 must include a plurality of charge pump stages (sta㈣, Its 200527815 middle stage is marked with reference number i 10. Each charge pump stage includes a diode m and a series of capacitors 112 'and has-an input node ⑴ and an output node 114. In this Dickson-type charge pump, the fixed-amplitude clock signal 13 output from the clock generator 12 is a pair of complementary clock signals CLK1 and CLK2, which are used to drive the capacitors of the pumps at various stages. The clock signal drives the odd-numbered pump stages, and the clock signal CLK ^ drives the even-numbered fruit stages. The input node of the first-stage series charge pump, the point 115 is often connected to the supply dust source Vin. The terminal isolation diode 116 can be regarded as part of the final series charge pump, and the pump voltage Vpp of the charge pump circuit u can be obtained therefrom. The clock signals CUU and CLK2 must be overlapping or non-heavy clock signals with amplitudes to drive each stage of charge I to increase the voltage transmitted to the input node of the basin (Velk-Vd). The forward voltage drop Vd of the polar body. If the effect of blocking the diode 116 at the extreme end is considered, the theoretical maximum voltage VPP that the charge dish circuit n shown in 所示 1 (b) can achieve is N. Vclk- (N + 1). Vd, where N is the charge Number of pump stages. Figures 2⑷ to 2⑷ display diagrams! The conventional charge-effect circuit shown in Figure ff is used to drive a 1G operation timing diagram. Figure 2 (a) is a timing diagram of the pump voltage Vpp of the 7-pump circuit U; Figure 2 (b) It is a timing diagram of the output voltage of the power switch =; and FIG. 2 (c) is the power switch 1 passing current 1. The timing diagram of „. Referring to FIG. 2 ⑷, before time L, the charge pump circuit 11 is in an unpowered state), so its electric power 2: P is zero. The charge pump circuit u starts at time Tα and starts ^ First use. At the transition from _ΤΑ to time Tβ, the pumping voltage M Vpp of the charge pump circuit rapidly increases from zero to a stable maximum value, such as N · Vclk— (N + 1) ·% as described in 200527815. The charge pump circuit u achieves a stable operating state at time h, so that the pump voltage Vpp remains stable. Figure 2 (b) and 2 (c). Before the start time Ta, the pump voltage Vpp of the charge pump is less than the valve The value is μ, so the power is not turned on so that its output voltage V- is zero and the conduction current is 1. It is also zero. When the voltage V ρ ρ of the charge pump circuit 11 reaches the electric difficulty, the power switch can be turned on: 0 and the output capacitor C starts. Charging causes the output voltage Vout of the power switch 10 to rise. Because the pump voltage of the charge pump circuit ii causes the power switch to be driven to provide the smallest on-resistance, the output voltage Vout of the power on M10 reaches a time Tc almost equal to the supply voltage source Vin. The conventional charge pump circuit 造成 causes a problem when applied to drive a power switch. Because the pump voltage of the charge pump circuit u rises rapidly, the power switch 10 provides the smallest on-resistance in the early stage of startup: However, since the output voltage ^ is zero in the early stage of startup, that is, the capacitor C is rotated out. It has not yet been charged, so the supply voltage source Vin generates a considerable on-current 1. „Flowing through the power switch 10, this is the inrush current. If the maximum surge = the current Ipeak is unduly suppressed, it may cause the supply voltage source Vin to drop drastically, or the power switch i 0 may be burned. 1η Θ [Contents of the invention] In view of the foregoing problems, one object of the present invention is to provide a charge fruit circuit that can generate a slowly rising slow-start pump voltage. Σ Another object of the present invention is to provide a charge pump circuit that can appropriately drive a power switch to achieve maximum suppression The effect of inrush current. 200527815 According to the present invention, the charge pump is driven by at least one clock signal for converting-supplying a voltage source to become a pump. The pump voltage is a function of the amplitude of the at least one clock signal. The larger the amplitude of the at least one clock signal is, the larger the absolute value of the pump voltage is. The amplitude modulation of the at least one clock signal is gradually changed from a start value within an amplitude modulation period. The amplitude modulation The variable period is one or more orders of magnitude longer than a period of the at least one clock signal. The charge pump is controlled by the at least one clock signal When the amplitude is the starting value, the absolute value of the pump voltage generated by the pump is relatively small. After the starting, the charge pump is controlled so that the absolute value of the pump voltage generated by the The modulation of the amplitude of a clock signal gradually changes to suppress the rising rate of the absolute value of the pump voltage. Preferably, the amplitude of the at least one clock signal reaches a stable value after the amplitude modulation period. Preferably, the stable value is equal to the supply voltage source. Preferably, the amplitude of the at least one clock signal is determined by a gradually increasing potential difference that appears across a capacitor during charging of the capacitor. Preferably, the pump voltage is used to control a power switch. Preferably, the at least one clock signal is generated by a clock amplitude modulator. The clock amplitude modulator includes a slow start controller, Used to generate a slow-start control signal; and a quasi-offset, which is responsive to the slow-start control signal to modulate the amplitude of the at least one clock signal. Preferably, the slow-start control signal is A voltage signal having a gradually changing level 200527815. Preferably, the amplitude of the at least one amplitude-modulated clock signal is determined by the gradually changing level of the slow-start control signal. Preferably, the The start-up controller includes: _switching capacitor equivalent resistance 'having first and second terminals, the first terminal is connected to the power supply source f; and a charging capacitor connected between the second terminal and the ground So that the slow-start control signal is presented at the second endpoint. Preferably, the level shifter includes: at least one clock channel for generating at least one amplitude-modulated clock signal 'wherein the at least one clock Each of the channels has a round of phase-out inverter. The power supply terminal of the output-stage inverter is used to receive the slow-start control signal to control the amplitude of each of the at least one amplitude-modulated clock signal. It is better that 'the at least-each of the clock channels further includes: an input = an inverter' has-a power supply terminal to receive the supply voltage source for a total-clock signal with a fixed amplitude No. to this output stage inverter. [Embodiment] The description and drawings in Γ will make the aforementioned and other objects of the present invention better and more obvious. The circuit block diagram of the application of the slow-start charge circuit 31 according to the invention will be described in detail with reference to the drawings. Comparing FIG. 3 (a) with FIG. 1 (a). To replace the conventional He Li circuit 31 around the Qi Qin W 屮) according to the present invention instead of the electric circuit of the pump and pump 11, the circuit shown in FIG. 3 (a) can be obtained. Circuit block 200527815. Figure 3 (a)%-Power switch 10. Because: the power switch 30 is equivalent to the description of the circuit part shown in FIG. The following is the same as in Figure 3 (a). The amplitude is the same as the following: The start charge circuit 31 converts the supply voltage source into a special power switch with a slow start and a slow start at a fixed voltage of at least one fixed starting characteristic: 3G Gate G. The voltage VPPS of Y, $, and 7 refers to ... Compared to the conventional pump voltage PP, g 'slowly starts the pump voltage V ^ ^ ^ ^ x ^. The required transition time is phase-delayed: the second action value ... Discrimination within the transition time to reach a stable value 22 Slowly start the pump voltage Vp, the circuit 31 is slower. Specifically, the charge pump is started slowly. The charge device: the clock-keeping amplitude modulator 3 " clock-dependent amplitude type pump circuit 31. The clock amplitude modulator 3U responds to the input slow-start charge change: to: a fixed amplitude clock signal 13 performs amplitude modulation. There are fewer i: an amplitude modulation clock signal 313. The result 312 of the clock amplitude means that the value of the fruit voltage Vpp depends on the clock amplitude. Typical :: Road ,! That is, the pump voltage Vpp is a function of the clock amplitude%. i § The larger the amplitude of the clock signal, the greater the voltage Vpp of the clock amplitude-dependent charge ^. For example, ® Ub) is a type of clock-amplitude-dependent charge pump, that is, mesh; pump electric star .Vd, and the larger the pump voltage VPP is. Based on the clock amplitude dependence = =, according to the invention, the slow-start charge fruit electricity ... achieves a characteristic pump voltage V, which is described in detail. Specifically, in one embodiment of the slow-start charge pump circuit 31 according to the present invention, at least one amplitude modulation time 10 200527815 clock number 3 1 3 is designed to have a minimum amplitude when the amplitude starts from the charge fruit circuit 31 A clock signal that gradually increases to a stable maximum and becomes a continuously changing amplitude. Therefore, the slow start pump voltage of the slow start charge pump circuit 31 is 1

Vpps會隨著振幅調變時鐘信號313之振幅緩慢升高而緩慢增加。圖3 (b)顯示依據本發明之振幅調變時鐘信號3丨3之一例子之波形時序圖。參照圖3(b)，振幅調變時鐘信號clks 1 與振幅調變時鐘信號CLKS2構成一對互補的振幅調變時鐘信號313。振幅調變時鐘信號CLKS1與CLKS2可藉由使用時鐘振幅調變器311轉換圖1(b)所示的具有固定振幅 Vw之時鐘信號CLK1與CLK2而產生。結果，振幅調^ 時鐘信號CLKS1與CLKS2於電荷泵啟動時具有振幅最小值，隨後振幅緩慢增加，經過一預定的振幅調變時期丁後振幅達到穩定的最大值Veik。在依據本發明之一實施^^ 中，穩定的最大值Vclk係設定成等於供應電壓源。振幅調變時期Tamp可依據實際電路應用之需要而調整至適當值。振幅調變時期Tamp之長短將直接影響緩啟動泵電壓 VPPS之從啟動值達到穩定值所需的過渡時間之長短。在依據本發明之一實施例中，振幅調變時期八叩設定成比時鐘週期Tclk至少更延長了一個數量級。在依據本發明之另一實施例中，時鐘週期uA 10毫微秒，而振幅調㈣期Tamp則約為2 · 5微秒。 ' 請注意在依據本發明之緩啟動電荷泵電路3 1中，時鐘振幅相依型電荷泵312於振幅調變時期Tamp内即已啟= 11 200527815 而進行升麼操作，並非等到定的最大值velk後才進行升 \ = 達到穩 T-内，由於時鐘振幅相依型電荷泵312之：二 vpps取決於振幅調變時鐘 / ^ ^ 幅相依型電荷纟312之缓H之振幅大小，故時鐘振斤…” 故啟動泵電壓V-會隨著振幅調變 T鐘仏唬313之振幅緩慢升高而緩慢增加。Vpps increases slowly as the amplitude of the amplitude-modulated clock signal 313 increases slowly. FIG. 3 (b) shows a waveform timing diagram of an example of an amplitude-modulated clock signal 3 丨 3 according to the present invention. Referring to Fig. 3 (b), the amplitude modulated clock signal clks 1 and the amplitude modulated clock signal CLKS2 constitute a pair of complementary amplitude modulated clock signals 313. The amplitude-modulated clock signals CLKS1 and CLKS2 can be generated by using the clock amplitude modulator 311 to convert the clock signals CLK1 and CLK2 having a fixed amplitude Vw as shown in FIG. 1 (b). As a result, the amplitude-modulated clock signals CLKS1 and CLKS2 have a minimum amplitude when the charge pump is started, and then the amplitude slowly increases. After a predetermined amplitude modulation period, the amplitude reaches a stable maximum Veik. In one implementation according to the present invention, the stable maximum value Vclk is set equal to the supply voltage source. The amplitude modulation period Tamp can be adjusted to an appropriate value according to the needs of the actual circuit application. The length of the amplitude modulation period Tamp will directly affect the length of the transition time required for the slow-start pump voltage VPPS to reach a stable value. In one embodiment according to the present invention, the amplitude modulation period is set to be at least an order of magnitude longer than the clock period Tclk. In another embodiment according to the present invention, the clock period uA is 10 nanoseconds, and the amplitude modulation period Tamp is about 2.5 microseconds. 'Please note that in the slow-start charge pump circuit 31 according to the present invention, the clock amplitude-dependent charge pump 312 is turned on within the amplitude modulation period Tamp = 11 200527815 to perform the ascent operation, rather than waiting for a fixed maximum value velk Only after the rise \ = to reach a stable T-, because the clock amplitude-dependent charge pump 312: two vpps depends on the amplitude modulation clock / ^ ^ amplitude-dependent charge 纟 312 slow H amplitude, so the clock vibrates … ”Therefore, the starting pump voltage V- will increase slowly as the amplitude of the amplitude modulation T clock bluff 313 increases slowly.

。圖4⑷顯示依據本發明之時鐘振幅調變器3ιι之電路區塊圖。參照圖4(a)，時鐘振幅調變器3ιι包括一緩啟動控制器41以及一位準偏移器42。緩啟動控制器41輸出一㈣㈣㈣Mss至位準偏移器42。回應於緩啟動控制 ^號VSS，位準偏移器42藉由改變時鐘信號13之固定振幅而將其轉換成振幅調變時鐘㈣313。該緩啟動控制信號vss係用以決定振幅調變時鐘信號313之振幅調變，亦即啟動時之最小值、穩定時之最大值、振幅調變時期Lp、以及/或者在振幅調變時期Tamp内振幅之變化方式。. Fig. 4 (b) shows a block diagram of a circuit of a clock amplitude modulator 3m according to the present invention. Referring to Fig. 4 (a), the clock amplitude modulator 3m includes a slow-start controller 41 and a one-bit quasi-shifter 42. The slow start controller 41 outputs a ㈣㈣㈣Mss to the level shifter 42. In response to the slow start control ^, the level shifter 42 converts the fixed amplitude of the clock signal 13 into an amplitude modulation clock ㈣313. The slow start control signal vss is used to determine the amplitude modulation of the amplitude modulation clock signal 313, that is, the minimum value at startup, the maximum value at stability, the amplitude modulation period Lp, and / or the amplitude modulation period Tamp How the internal amplitude changes.

圖4(b)顯示依據本發明之時鐘振幅調變器3丨丨之一例子之詳細電路圖。參照圖4(b)，緩啟動控制器41包括二個開關s!與S2以及二個電容Ci與c2。開關Sl與S2係控制成彼此交錯地處於導通狀態且不會同時皆處於不導通狀悲。當開關Si導通時，供應電壓源Vin對電容C!充電。當開關S2導通時，電容C!經由開關S2放電。從眾所週知的切換電容（Switch Capacitor)技術可推知，開關S!與S2 以及電容Ci之電路係等效於一等效電阻Req，耦合於供應電壓源vin與電容C2間。因此，供應電壓源vin經由等效 12 200527815 電阻Req對電容c2充電，導致跨在電容c2上之電漸升高且具有時間常數Req.C2。跨在電容Μ上之電：差即得應用作為緩啟動控制信號^。在圖州所示之實施例中，跨在電容C2之上之雷杨IΛ 、 2之上之電位差係經由一輸出緩衝電路 43而輸出至位準偏蒋哭42，莛丨、；從π w 糟以獲侍驅動能力增強的啟動控制信號V s s。輪屮罐徐雷玫/，輸出緩衝電路43包含一緩衝電流源Ib 與-緩衝電晶體1。緩衝電流源Ib連接於供應電壓界Fig. 4 (b) shows a detailed circuit diagram of an example of the clock amplitude modulator 3 丨丨 according to the present invention. Referring to Fig. 4 (b), the slow-start controller 41 includes two switches s! And S2 and two capacitors Ci and c2. The switches S1 and S2 are controlled to be in a conducting state staggered with each other and not to be in a non-conducting state at the same time. When the switch Si is turned on, the supply voltage source Vin charges the capacitor C !. When the switch S2 is turned on, the capacitor C! Is discharged via the switch S2. From the well-known Switch Capacitor technology, it can be inferred that the circuit of switches S !, S2 and capacitor Ci is equivalent to an equivalent resistance Req, which is coupled between the supply voltage source vin and capacitor C2. Therefore, the supply voltage source vin charges the capacitor c2 via the equivalent 12 200527815 resistor Req, which causes the electricity across the capacitor c2 to gradually rise and has a time constant Req.C2. Electricity across capacitor M: The difference must be applied as a slow start control signal ^. In the embodiment shown in the figure, the potential difference across the thunder Yang IΛ, 2 above the capacitor C2 is output to the level bias Jiang Ku 42, 莛丨, through π w through an output buffer circuit 43; from π w It is worse to start the control signal V ss with enhanced driving capability. The output buffer circuit 43 includes a buffer current source Ib and a buffer transistor 1. The buffer current source Ib is connected to the supply voltage boundary

Vin，用以提供所需要的驅動電流。緩衝電晶體仏係由一 PMOS電晶體所實施，使得跨在電容c2之上之電位差與杏際使用的缓啟動控制信號Vss間約略相差—固定值，= 緩衝電晶體Qb之閥值電壓。圖4⑻所示的位準偏移器42係應用於調變圖_所示的二個具有固定振幅Veik的時鐘信號Cm *咖2, 因此對應地設有二個時鐘通道。具體而言，反相器渠與inv2以級聯（Caseade)方式構成—時鐘通道，1中反相器戰作為輸人級而反相器INV2作為輪出級。同樣地，反相器聊3與mvw級聯方式構成另_時鐘通道，其中反相器inv3作為輸人級而反相器INV4作為輸出級。輸人級反相器INVl與INV3之電源供應端 vin’而輸出級反相器購2與咖4之電源供應端則皆柄合於缓啟動控制信號Vss。由於每—時鐘通道係由二個反相器所構成，故當時鐘信號通料鐘通道後相位p改變。然而，因為輸出級反相器請2與咖4之電源供應端皆搞合於綾啟動控制信號Vss，所以位準偏移器42輸出如圖3㈨ 13 200527815 所不的振幅隨著緩啟動控制信號作铗ΓΤ 1C 1 Λ η 欠動之振幅调交時鐘 = CLKSUCLKS2。在此例子中’振幅調變時期Τ p由緩啟動控制信號Vss之時間常數、· c2所決定。叫應注意雖然在前文所述之實施例中，緩啟路31係使用二個時鐘信阳 ^ “ _ 知乃不限於此而得靡用於緩啟動電荷泵電路31你田. 心、属u壬田使用一個時鐘信號或三個以上重 =非重豐的時鐘信號。在緩啟動電荷泵電路個時鐘信號之情況中，位準使用n 個睥铲ϋ V 得對應地設置有Π 移二通道’分別用以調變η個時鐘信號之振幅。位準偏。士之η個時鐘通道亦得建構成不相同，因而對於二?=號提供不同的調變方式。或者，緩啟動控制器、4: =::ΓΓ同的緩啟動控制信…位準偏移器曰^於11個時鐘信號提供不同的調變方式。應用:Γ:)至5(d)顯示依據本發明之緩啟動電荷泵電路啟動控制…緩啟動；:：Γν Γ 、緩係緩啟動電荷泵電路之圖；圖5(b) 电仃汞電路31之緩啟動泵電壓¥_之圖:⑷係功率開關3〇之輸出電昼之時序圖；並：圖 5⑷：功ί:關30之導通電流U之時序圖。在圖5(b)至而虛線則用以表示圖2(·2⑷所示之習知的二 =: Ζ相f比較而突顯依據本發明所達成的實用性與優良 :果。請注意圖小)中僅顯示實線，因為習知技蓺中並I 提供依據本發明之緩啟動控制信號Vss。 ^ 14 200527815 ☆ ^恥圖5(a)，緩啟動控制信號Vss從時間ΤΑ處之啟動么緩k上升至到穩定值（在本實施例中此穩定值係設定成 ^為νιη) ’使得振幅調變時鐘信號313之振幅隨著緩啟動工制信號Vss而緩慢增加至約為^，如前所述。參照圖5(b)，在時間Ta之前，因為緩啟動電荷系電處於未賦此狀態，所以其緩啟動果電壓Vpp為零。田啟動電荷栗電路31⑨時間TA啟動，開始進行升壓作由於振巾田n周變時鐘信號3 i 3之振幅係從啟動時間 =慢增加，故緩啟動電荷栗電路3i之緩啟㈣電壓v s ^白知的電荷泵電路i i之泵電壓Vpp以更緩慢的速率升 :太習知的粟電磨Vpp在時間〜處即已達成穩定，然而依到穩定。泵電壓vPPS仍需要相當長的時間才能達慢與5⑷，因為緩啟動泵電壓V…上升較緩 M…開關3G比功率開關1G更晚導通，導致功率開關30之輪屮當厫+ 干少 ¥_較晚上升。如前所述，緩啟動泵 vpps係控制功率開關3〇之間極。既然功率開關川之、電:且係正比於其閘極電壓，因此功率開關3〇之導通 “阻隨著緩啟動泵電壓V 之Ji # π、ά、ί π a pps之上升而減小。因為緩啟動泵 PPS比習知的泵電a ^以更緩慢的速率功率開關30之導通雷阳又合扒w 所以值玄 t阻不曰於啟動初期就減小至最小告丨功率開關30之緩慢減小的導通電阻成功地抑制了功率開關30之導通雷泣j 士甘m 战力地抑 c ^ ^ ^ ^ * 、電/爪Ι〇η，尤其對於啟動初期輸出电合C。尚未充電時之湧入電流更是如 15 200527815Vin is used to provide the required drive current. The buffer transistor is implemented by a PMOS transistor, so that the potential difference across the capacitor c2 is slightly different from the slow-start control signal Vss used by the circuit-a fixed value, = the threshold voltage of the buffer transistor Qb. The level shifter 42 shown in FIG. 4A is applied to the modulation diagram _ shown in the two clock signals Cm * Ka2 having a fixed amplitude Veik, so two clock channels are provided correspondingly. Specifically, the inverter channel and inv2 are formed in a cascade (clockwise) manner—the clock channel, the inverter in 1 is used as the input stage and the inverter INV2 is used as the output stage. Similarly, the cascade of the inverter 3 and the mvw constitutes another clock channel, where the inverter inv3 is used as the input stage and the inverter INV4 is used as the output stage. The power supply terminals vin 'of the input stage inverters INV1 and INV3, and the power supply terminals of the output stage inverters 2 and 4 are all connected to the slow start control signal Vss. Since each clock channel is composed of two inverters, the phase p changes when the clock signal passes through the clock channel. However, since the power supply terminals of the output stage inverter 2 and 4 are all compatible with the start-up control signal Vss, the level shifter 42 outputs the amplitude shown in Figure 3㈨ 13 200527815 with the slow-start control signal.铗 ΓΤ 1C 1 Λ η Under-active amplitude modulation clock = CLKSUCLKS2. In this example, the 'amplitude modulation period T p is determined by the time constant of the slow start control signal Vss, · c2. It should be noted that although in the embodiment described earlier, the slow start circuit 31 uses two clocks Xinyang ^ "_ Zhi Na is not limited to this and is used to slowly start the charge pump circuit 31 you Tian. Xin, belongs to u 壬Tian uses one clock signal or three or more clock signals that are not heavy and heavy. In the case of slowly starting the clock signals of the charge pump circuit, the level uses n chirps, V, and Π shift two channels are set accordingly. They are used to modulate the amplitudes of n clock signals. The level is biased. The n clock channels can also be constructed differently, so different modulation methods are provided for the two? = Numbers. Or, the controller, 4 : = :: ΓΓ Same slow-start control signal ... The level shifter provides different modulation methods on 11 clock signals. Applications: Γ :) to 5 (d) show the slow-start charge pump according to the present invention Circuit start control ... slow start ;: Γν Γ, slow start charge pump circuit diagram; Figure 5 (b) slow start pump voltage ¥ of electro-mercury circuit 31: output of ⑷ series power switch 30 Timing diagram of electric day; and: Figure 5⑷: Timing diagram of on current U of power 30: off 30. In Fig. 5 (b) to, the dotted line is used to represent the conventional two shown in Fig. 2 (· 2⑷ =: Z phase f is compared to highlight the practicability and goodness achieved according to the present invention: fruit. Please note that the figure is small ) Only the solid line is shown, because the conventional technology does not provide the slow start control signal Vss according to the present invention. ^ 14 200527815 ☆ ^ Figure 5 (a), is the slow start control signal Vss started from time TA? Slowly k rises to a stable value (in this embodiment, the stable value is set to ^ is νιη), so that the amplitude of the amplitude modulation clock signal 313 slowly increases to about ^ with the slow start work signal Vss, such as Referring to FIG. 5 (b), before the time Ta, since the slow-start charge system is not in this state, the slow-start fruit voltage Vpp is zero. The field-start charge circuit 31 starts at time TA and starts Step-up operation Because the amplitude of the clock signal 3 i 3 of the vibration cycle n increases from the start time = slowly, the slow start voltage of the charge pump circuit 3i vs. the pump voltage Vpp of Baizhi's charge pump circuit ii Rising at a slower rate: the too familiar millet electric mill Vpp has been reached in time ~ The pump voltage vPPS still takes quite a long time to reach the slow and 5⑷, because the pump voltage V is slowly started, the rise is slower, M, and the switch 3G is turned on later than the power switch 1G, resulting in the wheel of the power switch 30.屮当厫 + dry less ¥ _ higher than at night. As mentioned before, slowly start the pump vpps to control the pole between power switch 30. Since the power switch Kawayuki, electricity: and is proportional to its gate voltage, so the power The “on” resistance of the switch 3〇 decreases as the Ji # π, ά, ί π a pps of the slow-starting pump voltage V increases. Because the slow-starting pump PPS is slower than the conventional pumping power ^ at a slower rate, the power switch 30 is turned on and the power switch 30 is turned on again. Therefore, the value of the resistance t is not reduced to the minimum before the start of the power switch 30. The slowly decreasing on-resistance successfully suppresses the conduction of the power switch 30, and the stag m m combat strength c ^ ^ ^ ^ *, electricity / claw IOη, especially for the initial output of the electric C. The inrush current when it is not charged is even more like 15 200527815

在本發明之一膏力/¾丨rK 伏特，習知的ΦΓ·，，假設供應電壓源ν-約為ί 為細毫微秒，而依據^攸啟動達到5伏特所需時間約 5伏特所需時間則約為8 y啟動達到最大湧入雷泣T 、笔微^。在此例子中，習知的電"丨l Ipeak約為5 4容4：立，品分认[ 入雷、、☆ T 日丨 ·女口而依據本發明之最大湧In one embodiment of the present invention, ¾rK volts, the conventional ΦΓ ·, assumes that the supply voltage source ν- is about ί is a fine nanosecond, and the time required to start to reach 5 volts is about 5 volts. The time required is about 8 y to start to reach the maximum inrush thunder T, pen micro ^. In this example, the conventional electricity " 丨 Ipeak is about 5 4 capacity 4: standing, product identification [into the thunder ,, ☆ T day 丨 · female mouth and the largest surge according to the invention

八軍/瓜1peaks則約為1 1安拉 ^ lL # r φ , .1女坨。因此，依據本發明之緩啟動 ^ ^ ^ 丨市j，男入電机，可有效地應用於驅動功率開關30。Eight Army / Melon 1peaks are about 11 Allah ^ lL # r φ, .1 son-in-law. Therefore, according to the slow start of the present invention, the male motor can be effectively applied to drive the power switch 30.

圖6⑷至6⑻顯示依據本發明之時鐘振幅相依型電荷泵3U之三個例子。參照圖6⑷，電荷系級η係等同於圖Hb)所示之Dickson型電荷泵之一級ιι〇，只是其使用一極體耦合方式的NMOS電晶體611來實施圖1(b)所示之二極體1U。泵電容612得由振幅調變時鐘信號CLKSl或 LKS 2所驅動，視其為奇數栗級或偶數栗級而定。參照圖6(b)，電荷泵級62係包括二個NM〇s電晶體6 (a) to 6 (c) show three examples of the clock amplitude-dependent charge pump 3U according to the present invention. Referring to FIG. 6 (a), the charge system stage η is equivalent to the first stage of the Dickson type charge pump shown in FIG. Hb), except that it uses a pole-coupled NMOS transistor 611 to implement the second shown in FIG. 1 (b). Polar body 1U. The pump capacitor 612 must be driven by the amplitude-modulated clock signal CLKS1 or LKS 2 depending on whether it is an odd or even pump stage. Referring to FIG. 6 (b), the charge pump stage 62 series includes two NMOS transistors.

621與622以及二個泵電容623與624。當時鐘信號clks 1 為低且時鐘信號CLKS2為高時，NMOS電晶體622導通而泵電容623被充電至供應電壓源vin。此時NM0S電晶體 621為不導通。當時鐘信號CLKS1轉變為高且時鐘信號 CLKS2轉變為低時，泵電容624使NMOS電晶體622之閘極電壓下降而造成NMOS電晶體622不導通，並且泵電容 62 3使NMΟS電晶體62 1之閘極電壓上升高過供應電壓源 Vin而造成NMOS電晶體621導通。結果，泵電容624在無任何二極體順向壓降之損失下被充電至完整的供應電 16 200527815 壓源Vin。當時鐘信號CLKS1轉變為低且時鐘信號CLKS2 轉變為高時，NMOS電晶體621因閘極電壓下降而不導通，並且泵電壓vpp即被升壓至供應電壓源Vin加上時鐘振幅Vcik。參照圖6(c)，電荷泵級63包括二個NMOS電晶體63 J 與633以及一個PMOS電晶體632與634，建構成一交又耦合的閉鎖電路。電荷泵級63更包括由時鐘信號CLKS1 與CLKS2所分別驅動的二個泵電容635與636。當時鐘作號CLKS1為高且時鐘信號CLKS2為低時，nm〇s電晶體 631導通而泵電容636被充電至供應電壓源Vin。當時鐘俨號CLKS1轉變為低且時鐘信號CLKS2轉變為高時，電晶體632導通而使泵電壓Vpp被升壓至供應電壓源加上時鐘振幅Velk。此時，NMOS電晶體633也導通而使泵電容635被充電至供應電壓源Vu。當時鐘信號。則轉變為咼且時鐘信號CLKS2轉變為低時，PM〇s電晶體 634導通而使泵電壓Vpp被升壓至供應電壓源ν;η加上$鐘振幅VeIk。雖然本發明業已藉由較佳實施例作為例示加以說明’應瞭解者為：本發明不限於此被揭露的實施例。相反地，本發明意欲涵蓋對於熟習Λ項技藝之人士而言係明顯料種修改與相似配置。因此’申請專利範圍之範圍應根據最廣的詮釋，以包容所有此類修改與相似配置。【圖式簡單說明] 17 200527815 圖Ua)顯示習知的電荷泵電路應用於電路區塊W。 I _之圖1 (b)顯示習知的電荷泵電路之詳細電路圖。圖2⑷至2(c)顯示習知的電荷果電路應用於 =操作時序圖，其中圖2⑷係電荷泵電路之栗= ^回，圖2(b)係功率開關之輸出電壓之時序jg . # 2⑷係功率開關之導通電流之時序圖。之4圖，並且圖動功==依據本發明之緩啟動電荷果電路應用於驅勑功羊開關之電路區塊圖。呢圖3(b)顯示依據本發明之波形時相。㈣時鐘㈣之-例子圖4(a)顯示依據本發圖。之呀鐘振幅調變器之電路區塊圖4(b)顯示依據本發明之詳細電路圖。、、里振幅調變器之一例子之圖 5(a)至 5(d)龜- 用於動玄 ”、不依據本發明之緩啟動電荷泵電踗施用於駆動功率開關之操㉟“了泵電路應制器之緩啟動控制 β /、圖5(a)係緩啟動控電路之緩啟動泵缓啟動電荷栗電壓之時序圖；^之時序圖；圖5(C)係功率開關之輪出圖。目5⑷係功率開關之導通電流之時序圖6(a)至6(b)顯示泵之三個例子，、本毛明之時鐘振幅相依型電荷 18 200527815 元件符號說明： ίο 功率開關 11 電荷泵電路 12 時鐘產生器 13, CLK1，CLK2 固定振幅時鐘信號 14 振盪器 15 振盪信號 3 0 功率開關 31 緩啟動電荷泵電路 41 緩啟動控制器 42 位準偏移器 43 輸出緩衝電路 6 1〜63 時鐘振幅相依型電荷泵級 110 電荷泵級 111 二極體 112 泵電容 113 輸入節點 114 輸出節點 115 第一級串聯電荷泵之輸入節點 116 最末端隔絕二極體 311 時鐘振幅調變器 312 時鐘振幅相依型電荷泵 3 13, CLKS1，CLKS2 振幅調變時鐘信號 611 二極體耦合方式的NMOS電晶體 19 200527815 612, 623, 624, 635, 636 泵電容 621，622, 631，633 NMOS 電晶體 632, 634 PMOS 電晶體 Ci9 C2 電容 D 汲極 G 閘極 INVi〜INV4 反相器 I b 緩衝電流源 I on 導通電流621 and 622 and two pump capacitors 623 and 624. When the clock signal clks 1 is low and the clock signal CLKS2 is high, the NMOS transistor 622 is turned on and the pump capacitor 623 is charged to the supply voltage source vin. At this time, the NMOS transistor 621 is not conducting. When the clock signal CLKS1 transitions to high and the clock signal CLKS2 transitions to low, the pump capacitor 624 causes the gate voltage of the NMOS transistor 622 to drop, causing the NMOS transistor 622 to become non-conductive, and the pump capacitor 62 3 causes the NMOS transistor 62 1 to The gate voltage rises above the supply voltage source Vin and causes the NMOS transistor 621 to turn on. As a result, the pump capacitor 624 is charged to the complete power supply without any loss of forward voltage drop of the diode 16 200527815 voltage source Vin. When the clock signal CLKS1 transitions to low and the clock signal CLKS2 transitions to high, the NMOS transistor 621 does not turn on due to the gate voltage drop, and the pump voltage vpp is boosted to the supply voltage source Vin plus the clock amplitude Vcik. Referring to FIG. 6 (c), the charge pump stage 63 includes two NMOS transistors 63 J and 633 and one PMOS transistor 632 and 634 to form a cross-coupled latch circuit. The charge pump stage 63 further includes two pump capacitors 635 and 636 driven by the clock signals CLKS1 and CLKS2, respectively. When the clock signal CLKS1 is high and the clock signal CLKS2 is low, the nmos transistor 631 is turned on and the pump capacitor 636 is charged to the supply voltage source Vin. When the clock signal CLKS1 goes low and the clock signal CLKS2 goes high, the transistor 632 is turned on and the pump voltage Vpp is boosted to the supply voltage source plus the clock amplitude Velk. At this time, the NMOS transistor 633 is also turned on and the pump capacitor 635 is charged to the supply voltage source Vu. When the clock signal. When it changes to 咼 and the clock signal CLKS2 goes low, the PMOS transistor 634 is turned on and the pump voltage Vpp is boosted to the supply voltage source ν; η plus the clock amplitude VeIk. Although the present invention has been explained by way of preferred embodiments as examples, it should be understood that the present invention is not limited to the disclosed embodiments. On the contrary, the invention is intended to cover modifications and similar arrangements that are obvious to those skilled in the art Λ. Therefore, the scope of the patent application should be interpreted in the broadest sense to encompass all such modifications and similar configurations. [Brief description of the figure] 17 200527815 Figure Ua) shows the conventional charge pump circuit applied to circuit block W. I _ of Figure 1 (b) shows a detailed circuit diagram of a conventional charge pump circuit. Figures 2 (a) to 2 (c) show the application of the conventional charge fruit circuit = operation timing diagram, where Figure 2 (series) of the charge pump circuit = ^ back, Figure 2 (b) is the timing sequence of the output voltage of the power switch jg. # 2⑷The timing diagram of the on-current of the power switch. Figure 4 and the diagram. Dynamic work == A block diagram of a circuit for a slow-start charge circuit according to the present invention to drive a power switch. Fig. 3 (b) shows a waveform phase according to the present invention. "Clock Clock"-Example Figure 4 (a) shows a diagram according to the present invention. Circuit block diagram of a clock amplitude modulator Fig. 4 (b) shows a detailed circuit diagram according to the present invention. Figures 5 (a) to 5 (d) of an example of an amplitude modulator-Turtle-for moving mystery ", the slow-start charge pump electricity applied according to the present invention is not applied to the operation of the automatic power switch" Slow start control β of pump circuit controller β /, Figure 5 (a) is the timing chart of the slow start pump slow start charge pump voltage of the slow start control circuit; ^ timing chart; Figure 5 (C) is the wheel of the power switch Plot. Table 5 shows the timing of the on-current of the power switch. Figures 6 (a) to 6 (b) show three examples of pumps. The clock amplitude-dependent charge of this Maoming 18 200527815 Symbol description of the components: ίο Power switch 11 Charge pump circuit 12 Clock generator 13, CLK1, CLK2 Fixed amplitude clock signal 14 Oscillator 15 Oscillation signal 3 0 Power switch 31 Slow-start charge pump circuit 41 Slow-start controller 42 Level shifter 43 Output buffer circuit 6 1 ~ 63 Clock amplitude dependent Charge pump stage 110 charge pump stage 111 diode 112 pump capacitor 113 input node 114 output node 115 input node of the first stage series charge pump 116 terminal diode 311 clock amplitude modulator 312 clock amplitude dependent charge Pump 3 13, CLKS1, CLKS2 Amplitude-modulated clock signal 611 Diode-coupled NMOS transistor 19 200527815 612, 623, 624, 635, 636 Pump capacitors 621, 622, 631, 633 NMOS transistors 632, 634 PMOS electric Crystal Ci9 C2 Capacitor D Drain G Gate INVi ~ INV4 Inverter I b Buffer current source I on On current

Ipeak 最大勇入電流Ipeak

Ipeaks 緩啟動最大湧入電流Ipeaks Slow Start Maximum Inrush Current

Qb 緩衝電晶體Qb buffer transistor

Req 切換電容等效電阻 S 源極Req Switched Capacitor Equivalent Resistance S Source

Si? s2 開關Si? S2 switch

Tamp 振幅調變時期 T C1 k 時鐘週期 V elk 時鐘振幅 vin 供應電壓源 vout 輸出電壓Tamp amplitude modulation period T C1 k clock period V elk clock amplitude vin supply voltage source vout output voltage

Vpp 泵電壓Vpp pump voltage

Vpps 緩啟動泵電壓 vss 緩啟動控制信號 20Vpps slow start pump voltage vss slow start control signal 20

Claims

200527815 拾、申請專利範圍： 1· 一種緩啟動電荷泵電路，包含：，一電荷泵，由至少一時鐘信號所驅動，用以轉換一供應電壓源成為-泵電壓’該果電塵為該至少一時鐘信號之 ’ 振巾田之函數’使得當該至少一時鐘信號之該振幅愈大時該泵電壓之一絕對值則愈大，其中：該至少一時鐘信號之該振幅係調變成在一振幅調變時期内從一啟動值逐漸變化，該振幅調變時期係比該至少馨一打鉍^嬈之一週期更延長一個或更多個數量級，該電荷泵係由該至少一時鐘信號於其振幅為該啟動值時所啟動，使其所產生的該泵電壓之該絕對值相對小，在該啟動後該電荷果被控制成所產生的該泵電壓之該絕對值隨著該至）¥鐘^ ^虎之該振幅之調變而逐漸變化，藉以抑制該泵電壓之該絕對值之上升速率。 2·如申請專利範圍第丨項之緩啟動電荷泵電路，其中·· · 該至少一時鐘信號之該振幅在該振幅調變時期後達到一穩定值。 3·如申請專利範圍第2項之緩啟動電荷泵電路，其中該穩定值係等於該供應電壓源。 4·如申請專利範圍第1項之緩啟動電荷泵電路，其中電容在充電過程該至少一時鐘信號之該振幅係由_ 21 200527815 中所主現的跨於该電谷之一逐漸升高的電位差所決定。 5·如申請專利範圍第1項之緩啟動電荷泵電路，其中：該振幅調變時期之數量級係微秒。 6·如申請專利範圍第1項之緩啟動電荷泵電路，其中：該泵電壓係用以控制一功率開關。 7· —種緩啟動電荷泵電路，包含·· 一時鐘振幅調變器，用以產生至少一振幅調變時鐘信號，該至少一振幅調變時鐘信號之振幅係在一振幅調變時期内從一啟動值逐漸變化，該振幅調變時期係比該至少一振幅調變時鐘信號之一週期更延長一個或更多個數量級；以及電何泵由°亥至夕一振幅調變時鐘信號所驅動，用以轉換一供應電壓源成為—泵電壓，其中：該電荷泵係由該至少一振幅調變時鐘信號於其振幅為該啟動值時所啟動，使其所產生的該泵電壓之一絕對值相對小’在5亥啟動後忒電荷泵被控制成所產生的該泵電壓之讜絕對值卩通著讜至少一時鐘信號之該振幅之調變而逐渐變化。200527815 The scope of patent application: 1. A slow-start charge pump circuit, comprising: a charge pump driven by at least one clock signal for converting a supply voltage source into a -pump voltage; the fruit electric dust is at least The 'vibration field function' of a clock signal makes the absolute value of the pump voltage larger when the amplitude of the at least one clock signal is larger, wherein: the amplitude of the at least one clock signal is tuned to a The amplitude modulation period gradually changes from a starting value. The amplitude modulation period is one or more orders of magnitude longer than one period of the at least one dozen bismuths. The charge pump is controlled by the at least one clock signal. It is started when its amplitude is the starting value, so that the absolute value of the pump voltage generated by it is relatively small. After the start, the charge result is controlled to the absolute value of the pump voltage generated by the to) \ Zhong ^^ The modulation of the amplitude of the tiger gradually changes, thereby suppressing the rising rate of the absolute value of the pump voltage. 2. The slow-start charge pump circuit according to item 丨 of the patent application scope, wherein the amplitude of the at least one clock signal reaches a stable value after the amplitude modulation period. 3. The slow-start charge pump circuit according to item 2 of the patent application scope, wherein the stable value is equal to the supply voltage source. 4. The slow-start charge pump circuit according to item 1 of the scope of patent application, wherein the amplitude of the at least one clock signal during the charging process of the capacitor is gradually increased across one of the electric valleys, which is mainly in _ 21 200527815. Determined by the potential difference. 5. The slow-start charge pump circuit according to item 1 of the scope of patent application, wherein: the magnitude of the amplitude modulation period is in the order of microseconds. 6. The slow-start charge pump circuit according to item 1 of the patent application scope, wherein: the pump voltage is used to control a power switch. 7. A slow-start charge pump circuit, including a clock amplitude modulator for generating at least one amplitude modulation clock signal, the amplitude of the at least one amplitude modulation clock signal is within a period of amplitude modulation from A start value is gradually changed, the amplitude modulation period is one or more orders of magnitude longer than a period of the at least one amplitude modulation clock signal; and the electric pump is driven by an amplitude modulation clock signal To convert a supply voltage source into a pump voltage, wherein: the charge pump is started by the at least one amplitude-modulated clock signal when its amplitude is the starting value, so that one of the pump voltages it generates is absolute After the value is relatively small ', the charge pump is controlled to generate an absolute value of the pump voltage which is gradually changed by adjusting the amplitude of at least one clock signal.

如申請專利範圍第7 一時鐘產生器，用項之緩啟動電荷泵電路，更包含：以產生至少一固定振幅時鐘信號使 22 200527815 得該時鐘振幅調變器回應於該至少一固定振幅時鐘信號而產生該至少一振幅調變時鐘信號。 9·如申請專利範圍第7項之缓啟動電荷泵電路，更包含：一振盪器，用以產生一振盪信號至該時鐘產生器，以決定該至少一固定振幅時鐘信號之頻率。 1 〇·如申睛專利範圍第7項之緩啟動電荷泵電路，其中：該時鐘振幅調變器係藉由一電容在充電過程中所呈現的跨於該電容之一逐漸升高的電位差而決定該至少一振幅調變時鐘時鐘信號之該振幅。 11·如申請專利範圍第7項之緩啟動電荷栗電路，其中·· 該時鐘振幅調變器包含：緩啟動控制器，用以產生一緩啟動控制信號；以及一位準偏移器，回應於該緩啟動控制信號而調變該至少一振幅調變時鐘信號之該振幅。 12.如申/專利範圍第u項之緩啟動電荷泵電路，其中·· j緩啟動控制信號係_具有逐漸變化的位信號。干心电座電路，其中 13·如中請專利範圍第12項之緩啟動電荷泵 23 200527815 該至少一振幅調變時鐘信號之該振幅係由該緩啟控制信號之該逐漸變化的位準所決定。 1 4.如申請專利範圍第丨丨項之緩啟動電荷泵電路，其中：該緩啟動控制器包含：一切換電容等效電阻，具有第一與第二端點’ 5亥第一端點係連接於該供應電壓源；以及一充電電容，連接於該第二端點與地面間，使得該緩啟動控制信號呈現於該第二端點。 1 5·如申請專利範圍第11項之緩啟動電荷泵電路，其中：該位準偏移器包含·· 至少一時鐘通道，分別用於產生該至少_择幅調變時鐘信號，其中該至少一時鐘通道中之每一個具有一輪出級反相器，該輸出級反相器之一電源供應端係用以接收該緩啟動控制信號，藉以控制該至少一振幅調變時鐘信號中之各個之該振幅。 16.如申明專利範圍第丨5項之緩啟動電荷泵電路，其中：該至少一時鐘通道之每一個更包含：一輸入級反相器，具有一電源供應端來接收該供應電壓源’用以提供一具有固定振幅的時鐘信號至該輸出級反相器。 24 200527815 1 7. —種啟動電荷泵電路之方法，包含：產生至少-時鐘信號，該至少一時鐘信號之振幅係在 -振幅調變時期内從-啟動值逐漸變化，該振幅調變時期係比該至少-時鐘信號之一週期更延長_個或更多個數量級；動值時，使用該供應電壓源成為For example, the seventh clock generator in the scope of patent application, the slow start charge pump circuit with the item, further includes: generating at least one fixed amplitude clock signal so that the clock amplitude modulator responds to the at least one fixed amplitude clock signal The at least one amplitude-modulated clock signal is generated. 9. The slow-start charge pump circuit according to item 7 of the patent application scope, further comprising: an oscillator for generating an oscillating signal to the clock generator to determine the frequency of the at least one fixed-amplitude clock signal. 10. The slow start charge pump circuit as described in item 7 of the patent scope, wherein: the clock amplitude modulator is formed by a capacitor gradually increasing the potential difference across one of the capacitors during charging. Determine the amplitude of the at least one amplitude-modulated clock signal. 11. The slow start charge pump circuit according to item 7 of the scope of patent application, wherein the clock amplitude modulator includes: a slow start controller for generating a slow start control signal; and a quasi-offset device that responds The amplitude of the at least one amplitude-modulated clock signal is modulated at the slow-start control signal. 12. The slow-start charge pump circuit of item u in the scope of claim / patent, where the slow-start control signal j has a gradually changing bit signal. The dry heart electric base circuit, among which 13. The slow-start charge pump of item 12 in the patent scope of the patent application 23 200527815 The amplitude of the at least one amplitude-modulated clock signal is determined by the gradually changing level of the slow-start control signal Decide. 1 4. The slow-start charge pump circuit according to item 丨丨 in the scope of patent application, wherein: the slow-start controller includes: a switching capacitor equivalent resistor having first and second terminals; Connected to the supply voltage source; and a charging capacitor connected between the second terminal and the ground, so that the slow start control signal is presented at the second terminal. 15. The slow-start charge pump circuit according to item 11 of the scope of patent application, wherein: the level shifter includes at least one clock channel for generating the at least _selective modulation clock signal, wherein the at least Each of the clock channels has a round of phase-out inverters, and a power supply terminal of the output-stage inverter is used to receive the slow-start control signal to control each of the at least one amplitude-modulated clock signal The amplitude. 16. The slow-start charge pump circuit according to claim 5 of the patent scope, wherein: each of the at least one clock channel further includes: an input stage inverter having a power supply terminal for receiving the supply voltage source. To provide a clock signal with a fixed amplitude to the output stage inverter. 24 200527815 1 7. A method for starting a charge pump circuit, including: generating at least a clock signal whose amplitude is gradually changed from a start value during an amplitude modulation period, and the amplitude modulation period is Longer than one period of the at least-clock signal by an order of magnitude or more; when the value is constant, the supply voltage source becomes

於該至少一時鐘信號之該振幅為該啟至少一時鐘#號啟動一電荷泵，而轉換一一泵電壓；以及在該啟動後，使該泵電壓之一絕對值隨著該至少一時鐘信號之該振幅之調變而逐漸變化，以抑制該泵電壓之該絕對值之上升速率。 18.如申請專利範圍第17項之啟動電荷泵電路之方法，更包含： / 使該至少一時鐘信號之該振幅在該振幅調變時期後達到一穩定值。 ^ 19·如申請專利範圍第18項之啟動電荷泵電路之方法，其中： / ’ ’、該穩定值係等於該供應電壓源。 20·如申請專利範圍第17項之啟動電荷泵電路中·· 乃法，其在產生至少一時鐘信號之該步驟中，藉由一電容在充 25 200527815 電過程中所呈現的跨於該電容之一逐漸升高的電位差而決定該至少一時鐘信號之該振幅。A charge pump is started when the amplitude of the at least one clock signal is at least one clock #, and a pump voltage is converted; and after the start, an absolute value of the pump voltage is followed by the at least one clock signal The modulation of the amplitude gradually changes to suppress the rising rate of the absolute value of the pump voltage. 18. The method for starting a charge pump circuit according to item 17 of the patent application scope, further comprising: / making the amplitude of the at least one clock signal reach a stable value after the amplitude modulation period. ^ 19. The method for starting a charge pump circuit according to item 18 of the scope of patent application, wherein: / '', the stable value is equal to the supply voltage source. 20 · As in the start charge pump circuit of the scope of application for patent No.17, it is law, in the step of generating at least one clock signal, a capacitor appears in the process of charging 25 200527815 across the capacitor. A gradually increasing potential difference determines the amplitude of the at least one clock signal.

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