TW200427026A

TW200427026A - Flip-chip package substrate and process thereof

Info

Publication number: TW200427026A
Application number: TW092114346A
Authority: TW
Inventors: Kwun-Yao Ho; Moriss Kung
Original assignee: Via Tech Inc
Priority date: 2003-05-28
Filing date: 2003-05-28
Publication date: 2004-12-01
Also published as: TWI226685B

Abstract

A flip-chip package substrate comprises a laminated layer, a patterned conductive layer, and a dielectric layer, wherein the conductive layer is deposed on the top surface of the laminated layer and the conductive layer forms a plurality of bump pads and traces. The dielectric layer is also deposed on the top surface of the laminated layer exposed by the conductive layer. The top surfaces of the conductive layer and the dielectric layer form a level surface. Hence, after the chip connects to the flip-chip package substrate by flip-chip bonding, the level surface may smoothes the flow of the underfill material in the space formed by the chip and the substrate to reduce the happenings of voids. The yield and the reliability of the underfill process can be raised.

Description

200427026 五、發明說明Ο) 【發明所屬之技術領域】本發明是有關於一種覆晶封裝基板（n i p c h i p package substrate)，且特別是有關於一種可^升底膠填充製程（underfill dispensing process)之良率及可靠度的覆晶封裝基板及其製程。【先前技術】覆晶接合技術(Flip Chip Bonding Technology )主要是利用面陣列（a r e a a r r a y )的排列方式’在晶片 (die)之主動表面（active surface)上配置多個晶片墊（die pad )，並分別在這些晶片塾上形成凸塊（bump )，接著在將晶片翻面（f 1 i p )之後，可利用晶片之晶片彳塾上的凸塊來電性（e 1 e c t r i c a 1 1 y )及結構性 (structurally)連接至承載器（carrier)之表面上的凸塊墊（bump pad ) ’其中承載器例如是基板 (substrate)或疋印刷電路板（print circuit board， P C B )等。值得注意的是，由於覆晶接合技術可應用於高接腳數（High Pin Count )之晶片封裝結構，並具有縮小封裝面積及縮短訊號傳輸路徑等諸多優點，使得覆晶接合技術目前已被廣泛地應用在晶片封裝領域。請參考第1圖’其繪示習知之一種覆晶封裝結構的剖面示意圖。覆晶封裝結構1 〇〇主要包括晶片丨i 〇、覆晶封裝基板120、多個凸塊130及—底膠層（underfU1 layer) 140。晶片110具有一主動表面ι12、多個晶片墊114及一保護層1 1 6 ’其中主動表面1 1 2係泛指晶片丨丨〇之具有主動元200427026 V. Description of the invention 0) [Technical field to which the invention belongs] The present invention relates to a nipchip package substrate, and in particular, to a good underfill dispensing process. And reliability of flip-chip package substrate and its manufacturing process. [Prior technology] Flip Chip Bonding Technology mainly uses an area array to arrange multiple die pads on the active surface of a die, and Bumps are formed on these wafers respectively, and after the wafer is turned over (f 1 ip), the electrical properties (e 1 ectrica 1 1 y) and structure of the bumps on the wafers of the wafer can be used (Structured) a bump pad connected to the surface of the carrier, wherein the carrier is, for example, a substrate or a printed circuit board (PCB). It is worth noting that, because the flip-chip bonding technology can be applied to high-pin count chip packaging structures, and has many advantages such as reducing the package area and shortening the signal transmission path, the flip-chip bonding technology has been widely used. Ground applications in the field of chip packaging. Please refer to FIG. 1 'for a schematic cross-sectional view of a conventional flip-chip package structure. The flip-chip package structure 1 00 mainly includes a wafer 1i0, a flip-chip package substrate 120, a plurality of bumps 130, and an underfU1 layer 140. The wafer 110 has an active surface 12, a plurality of wafer pads 114, and a protective layer 1 1 6 ', wherein the active surface 1 1 2 refers to a wafer in general.

10925twf.ptd 第7頁 200427026 五、發明說明（2) 件(active component )的一面，且這些晶片塾114係、分別配置於晶片1 1 〇之主動表面1 1 2之上，而保護層1 1 6亦配置於晶片110之主動表面112之上，並暴露出這些晶片墊 114 ’ 且凸塊底金属層（Under Bump Metallurgy layer ， U B Μ 1 a y e r ) 1 1 8係分別配置於這些晶片墊1 1 4之表面，用以作為這些晶片墊1 1 4與這些凸塊1 3 0之間的接合媒介。清同樣參考弟1圖’覆晶封裝基板120具有一基板表面 122、圖案化之一導電層124及一銲罩層（solder mask layer )126，其中導電層124係配置於覆晶封裝基板120之基板表面122，且導電層124更形成多個凸塊墊124a及多條導線（t r a c e ) 1 2 4 b，而銲罩層1 2 6亦配置於覆晶封裝基板 120之基板表面122，並覆蓋這些線路124b，但藉由銲罩層 126之多個開口126a來分別暴露出這些凸塊墊124a。因此，晶片1 1 0將可經由這些凸塊1 3 0，而電性及結構性連接至覆晶封裝基板1 2 〇之這些凸塊墊1 2 4 a。然後，進行一底膠填充製程，利用毛細現象（c a p i 1 1 a r i t y )，將底膠材料（underfill material )緩慢地填入（dispense)於晶片1 10、覆晶封裝基板120及這些凸塊130所圍成之空間，因而形成一底膠層1 4 〇，用以緩衝晶片1 1 0與覆晶封裝基板 120之間所產生熱應力（thermal stress)。請同樣參考第1圖’當導電層124之凸塊墊1 24a的型態係為非銲罩層定義（Non-s〇ider Mask Defined，NSMD) 時，此種類型之凸塊墊1 2 4 a所暴露的表面積並未由銲罩層 1 2 6之開口 1 2 6 a所定義，使得凸塊1 3 0之底部能夠完全地包10925twf.ptd Page 7 200427026 V. Description of the invention (2) One side of the active component, and these wafers 系 114 are respectively arranged on the active surface 1 1 2 of the wafer 1 1 0, and the protective layer 1 1 6 is also disposed on the active surface 112 of the wafer 110, and the wafer pads 114 'are exposed, and an under-bump metallurgy layer (UBM 1 ayer) 1 1 8 is respectively disposed on the wafer pads 1 1 The surface of 4 is used as a bonding medium between the wafer pads 1 1 4 and the bumps 1 3 0. Qing also refers to FIG. 1 'The flip-chip package substrate 120 has a substrate surface 122, a patterned conductive layer 124, and a solder mask layer 126. The conductive layer 124 is disposed on the flip-chip package substrate 120. The substrate surface 122, and the conductive layer 124 further forms a plurality of bump pads 124a and a plurality of traces 1 2 4 b, and the solder mask layer 1 2 6 is also disposed on the substrate surface 122 of the flip-chip package substrate 120 and covers These lines 124b, but the bump pads 124a are exposed through the openings 126a of the solder mask layer 126, respectively. Therefore, the wafer 110 can pass these bumps 130, and can be electrically and structurally connected to the bump pads 12a of the flip-chip package substrate 1220. Then, a primer filling process is performed, and an underfill material (capi 1 1 arity) is used to slowly fill the wafer 1 10, the flip-chip package substrate 120, and the bumps 130. The enclosed space thus forms a primer layer 140 for buffering thermal stress generated between the wafer 110 and the flip-chip package substrate 120. Please also refer to FIG. 1 'When the type of the bump pad 1 24a of the conductive layer 124 is a non-solder mask defined (NSMD), this type of bump pad 1 2 4 The exposed surface area a is not defined by the opening 1 2 6 a of the solder mask layer 1 2 6 a, so that the bottom of the bump 1 3 0 can completely cover

10925twf.ptd 第8頁 200427026 五、發明說明（3) 覆凸塊墊1 2 4 a之頂面及側面。然而，當凸塊1 3 0接合至凸塊墊1 2 4 a之後，銲罩層1 2 6之開口 1 2 6 a的側壁與凸塊墊 1 2 4 a之間將形成多個縫隙1 2 8。因此，在進行底膠填充製程的期間，將底膠材料填入晶片1 1 0、覆晶封裝基板1 2 0及這些凸塊1 3 0之間所構成的空間時，底膠材料將不易流入這些縫隙1 2 8之内，如此將導致底膠層1 4 0容易在這些縫隙 1 2 8之處產生空孔（v ◦ i d )，如此將降低底膠填充製程之良率。此外，非銲罩層定義（NSMD )型態之凸塊墊1 24a需要面積較大的開口126a，如此將會導致這些凸塊墊124a之排列密度的降低。另外，受到熱膨脹係數差異的影響，銲罩層126與底膠層140之間可能會產生剝離（delamination )的現象，因而降低覆晶封裝結構1 0 0之可靠度。【發明内容】有鑑於此，本發明之目的係在於提出一種覆晶封裝基板及其製程，可藉由在覆晶封裝基板之頂面形成一平整面，使得底膠材料在注入晶片與覆晶封裝基板之間時，能夠讓底膠材料之流動更加地平順，因而提高底膠填充製程的良率及可靠度。為達本發明之上述目的，本發明提出一種覆晶封裝基板，其至少包括一疊合層、圖案化之一導電層及一介電層，其中圖案化之第一導電層係配置於疊合層之頂面，並構成多個凸塊墊及多個導線，且圖案化之介電層亦配置於疊合層之頂面，並覆蓋疊合層之由導電層所暴露出的局部表面，但未覆蓋導電層之表面，且導電層所形成之多個凸10925twf.ptd Page 8 200427026 V. Description of the invention (3) Cover the top and sides of the bump pad 1 2 4 a. However, after the bump 1 3 0 is bonded to the bump pad 1 2 4 a, a plurality of gaps 1 2 will be formed between the sidewall of the opening 1 2 6 a of the solder mask layer 1 2 6 a and the bump pad 1 2 4 a. 8. Therefore, during the primer filling process, when the primer material is filled into the space formed between the wafer 110, the flip-chip package substrate 120, and the bumps 130, the primer material will not easily flow in. Within these gaps 1 2 8, this will cause the primer layer 1 40 to easily generate voids (v ◦ id) in these gaps 1 2 8, which will reduce the yield of the primer filling process. In addition, the non-solder mask layer definition (NSMD) type bump pads 1 24a require larger openings 126a, which will result in a reduction in the arrangement density of these bump pads 124a. In addition, affected by the difference in thermal expansion coefficients, delamination may occur between the solder mask layer 126 and the primer layer 140, thereby reducing the reliability of the flip-chip package structure 100. [Summary of the Invention] In view of this, the object of the present invention is to propose a flip-chip package substrate and a process for forming a flat surface on the top surface of the flip-chip package substrate, so that the primer material is injected into the wafer and the flip-chip. When the substrates are packaged, the flow of the primer material can be made smoother, thereby improving the yield and reliability of the primer filling process. In order to achieve the above object of the present invention, the present invention provides a flip-chip package substrate, which at least includes a laminated layer, a patterned conductive layer, and a dielectric layer, wherein the patterned first conductive layer is disposed in the laminated layer The top surface of the layer constitutes a plurality of bump pads and a plurality of wires, and the patterned dielectric layer is also disposed on the top surface of the laminated layer and covers a partial surface of the laminated layer exposed by the conductive layer. But does not cover the surface of the conductive layer, and the multiple protrusions formed by the conductive layer

10925twf.ptd 第9頁 200427026 五、發明說明（4) 塊塾的表面為達本板製程。首導電層係配導線。接著電層所暴露導電層之表整面。因此，別是平坦化面，故當底空間而形成之流動更為率，進而提形成介電層疊合層之多知之填充貫間的對位要覆晶封裝基為讓本懂，下文特明如下：【實施方式請參考表面共同形成一平整面。的，本發明提出一種覆晶封裝基先，提供一疊合層及圖案化之一導電層，其中一面，並構成多個凸塊墊及多個介電層，其覆蓋於疊合層之由導，但未覆蓋導電層之表面，使得係與介電層之發明之上述目置於疊合層之，形成一第一出的局部表面面係與該第一介電層之表面共同形成一第一平本發覆晶膠材底膠平順南底於覆個貫孔的求，板之發明舉一明乃封裝料注層時，因膠填晶封孔，步驟因而製作之上較佳是平基板入晶，上而降充製裝基而形，且簡化成本述目實施坦化在之與晶片與覆述之平低底膠程之良板時，成多個可省略覆晶封覆晶片作晶封整面層之率〇同時介電習知裝基封裝覆晶裝基將有内部此外將介柱，之銲板之基板接合板之助於形成，本電材如此罩層製程之表的局間所讓底空孔發明料一將可與凸，進面，特部表圍成的膠材料的機更可於併填入省略習塊墊之而降低的、特徵、和優點能更明顯易例，並配合所附圖式，作詳細說第2 A〜2 G圖，其分別繪示本發明之較佳實施例10925twf.ptd Page 9 200427026 V. Description of the invention (4) The surface of the block is made up to this board. The first conductive layer is a wire. Then the entire surface of the conductive layer exposed by the electrical layer. Therefore, not only is the flat surface, so the flow formed in the bottom space is more efficient, and the well-known filling position of the dielectric laminated composite layer is required. As follows: [For implementation, please refer to the surface together to form a flat surface. In the present invention, a flip-chip packaging substrate is provided. First, a laminated layer and a patterned conductive layer are provided, one side of which forms a plurality of bump pads and a plurality of dielectric layers, which cover the laminated layer. Conductive, but does not cover the surface of the conductive layer, so that the above-mentioned purpose of the invention with the dielectric layer is placed in the superimposed layer to form a first partial surface surface and the surface of the first dielectric layer together forms a The first flat-panel chip-on-silicone rubber primer is required to cover a through hole. The invention of the board is one of the encapsulation materials. Because the glue fills the hole and seals the hole, the steps are better. When the flat substrate is inserted into the crystal, the substrate is shaped up and down, and the cost profile is simplified. When the wafer and the wafer are covered with a flat low-bottom rubber process, a good number of wafers can be omitted. The rate of the whole surface layer of the crystal seal. At the same time, the conventional dielectric substrate mounting package will have an internal substrate and a bonding board and a bonding board to help the formation of this substrate. This electrical material is the result of the overlay process. Give way The hole invention material can be used with the convex, entrance surface, and special rubber materials enclosed by the special surface. The machine can be filled with the reduced features, advantages, and advantages of the omission of the block. In the drawings, 2A to 2G are described in detail, which respectively illustrate the preferred embodiments of the present invention.

10925twf.ptd 第10頁 200427026 五、發明說明（5) - 之四層導電層覆晶封裝基板之製作流程的局部剖面圖。本較佳實施例並不限於四層導電層之覆晶封裝基板，亦可應用於其他多層導電層的覆晶封裝基板。首先，如第2八圖戶^ 示，提供一疊合介電層212a及二疊合導電層214a、2l4b，其中豐合導電層214a、214b係分別配置於疊合介電層2i2a 之兩面，並且疊合導電層214a、214b均已圖案化，用以形成線路。 y 如第2 B圖所示，接著分別形成疊合介電層2丨2 b及疊合介電層212c於疊合介電層212a之兩面，並分別覆蓋叠^導電層214a、214b。並且這些疊合介電層212a、212b、212c 及疊合導電層214a、214b將共同構成一疊合層210。其丨中，疊合介電層2 1 2 a之材質例如是添加玻璃纖維（g丨a s s fiber)之樹脂（resin)，用以提升疊合介電層2l2a之本身的結構強度，而另二疊合介電層2 1 2 b、2 1 2 c之材質則例如是高分子聚合物（polymer)、聚醯亞胺（p〇iyimide， PI)或液晶聚合物（Liquid Crystal Polymer)等介電材質’而圖案化疊合導電層214a、214b之材質例如銅、其他金屬或合金。如第2 C圖所示’接著利用機械鑽孔（m e c h a n i c a 1 drilling)或雷射鑽孔（laser drilling)等方式，形成多個貫孔216於疊合層210，其中這些貫孔216係連接疊合層210之第一面210a及第二面21〇b。如第2 D圖所示’接著利用例如電鍵（p 1 a t i n g )等方式，將導電材料形成至疊合層210之第一面210a及第二面10925twf.ptd Page 10 200427026 V. Description of the Invention (5)-Partial cross-sectional view of the manufacturing process of the four-layer conductive-chip flip-chip package substrate. This preferred embodiment is not limited to a flip-chip package substrate with four conductive layers, but can also be applied to other flip-chip package substrates with multiple conductive layers. First, as shown in FIG. 28, a superposed dielectric layer 212a and two superposed conductive layers 214a and 21b are provided. The rich conductive layers 214a and 214b are respectively disposed on both sides of the superposed dielectric layer 2i2a. And the superposed conductive layers 214a, 214b have been patterned to form a circuit. As shown in FIG. 2B, a laminated dielectric layer 2b and a laminated dielectric layer 212c are then formed on both sides of the laminated dielectric layer 212a and cover the laminated conductive layers 214a and 214b, respectively. And these superposed dielectric layers 212a, 212b, and 212c and superposed conductive layers 214a, 214b together form a superposed layer 210. Among them, the material of the laminated dielectric layer 2 1 2 a is, for example, a resin added with glass fiber (g 丨 ass fiber) to improve the structural strength of the laminated dielectric layer 212a, and the other two The material of the stacked dielectric layers 2 1 2 b, 2 1 2 c is, for example, a dielectric such as a polymer, a polyimide (PI), or a liquid crystal polymer (Liquid Crystal Polymer). The material of the patterned conductive layer 214a, 214b is, for example, copper, other metals or alloys. As shown in FIG. 2C, 'mechanical 1 drilling or laser drilling is then used to form a plurality of through holes 216 in the superposed layer 210, where these through holes 216 are connected to the superposed layer. The first surface 210a and the second surface 210b of the bonding layer 210. As shown in FIG. 2D ′, a conductive material is then formed on the first surface 210a and the second surface of the superposition layer 210 by using a method such as a key (p 1 a t i n g).

10925twf,ptd 第11頁 200427026 五、發明說明（6) 、2 2 0 b，並同時將導電材料形用以形成多個貫孔導電層 * 2 2 0 b係可經由這些貫孔導電 210b ，用以形成導電層220a 成至這些貫孔216之内壁面， 220c ，其中這些導電層22 0a 層2 2 0 c，而彼此作電性連接。如第2 E圖所示，接著例如以微影（p h 〇 t ο 1 i t h 〇 g r a p h y )及蝕刻（etching)的方式，圖案化導電層22〇a、 220b ，其中已圖案化之導電層220a係形成多個凸塊墊222a 及多條導線2 2 4 a ，而已圖案化之導電層2 2 0 b則形成多個接合墊222b及多條導線224b，其中這些接合墊222b係用以連接外界之接點，例如導電球、導電針腳或導電塊等。如第2 F圖所示，接著將介電材料填充或覆蓋於疊合層1 210之由導電層220a所暴露出的局部表面，也就是將介電材料填充或覆蓋於疊合層210之未受到導電層220a所遮蓋的局部表面，而得到圖案化之一介電層230a，且介電層 230a並未覆蓋到導電層220a之較遠離疊合層210的表面。值得注意的是，導電層2 2 0 a及介電層2 3 0 a所分別形成之圖案剛好互補，並且導電層220a之這些凸塊墊2 22a的表面係與介電層230a之較遠離疊合層210的表面形成一平整面 2 0 2 a 〇同樣如第2F圖所示，.在形成介電層230a之同時，更可將介電材料一併填充於疊合層210之由導電層220b所暴露出的局部表面，而得到圖案化之一介電層230b，且介電層 230b並未覆蓋到導電層220b之較遠離疊合層210的表面。同樣地，導電層2 2 0 b及介電層2 3 0 b所分別形成之圖案剛好10925twf, ptd Page 11 200427026 V. Description of the invention (6), 2 2 0 b, and simultaneously forming a conductive material to form a plurality of through-hole conductive layers * 2 2 0 b can be conducted through these through-holes 210b, using A conductive layer 220a is formed to the inner wall surfaces, 220c of the through holes 216, wherein the conductive layers 22 0a and 2 2 0 c are electrically connected to each other. As shown in FIG. 2E, the conductive layers 22a, 220b are then patterned, for example, in the manner of lithography (ph ο 1 ith 〇graphy) and etching, wherein the patterned conductive layer 220a is A plurality of bump pads 222a and a plurality of conductive wires 2 2 4 a are formed, and a patterned conductive layer 2 2 0 b forms a plurality of bonding pads 222b and a plurality of conductive wires 224b. These bonding pads 222b are used to connect the outside world. Contacts, such as conductive balls, conductive pins, or blocks. As shown in FIG. 2F, the dielectric material is then filled or covered on the partial surface of the laminated layer 1 210 exposed by the conductive layer 220a, that is, the dielectric material is filled or covered on the uncovered layer 210. A part of the surface covered by the conductive layer 220a obtains a patterned dielectric layer 230a, and the dielectric layer 230a does not cover the surface of the conductive layer 220a farther from the superposition layer 210. It is worth noting that the patterns formed by the conductive layer 220a and the dielectric layer 230a are exactly complementary, and the surface of the bump pads 22a of the conductive layer 220a and the dielectric layer 230a are relatively far from each other. The surface of the bonding layer 210 forms a flat surface 2 0 2 a. Similarly as shown in FIG. 2F, while the dielectric layer 230a is formed, a dielectric material can be filled in the conductive layer of the stacked layer 210 together. A partial surface of 220b is exposed, and a patterned dielectric layer 230b is obtained, and the dielectric layer 230b does not cover the surface of the conductive layer 220b farther from the superposition layer 210. Similarly, the patterns formed by the conductive layer 2 2 0 b and the dielectric layer 2 3 0 b are just right

I0925twf.ptd 第12頁 200427026 五、發明說明（7) 互補’並且導電層22〇b之這些凸塊墊222b的表面係與介電層230b之較遠離疊合層210的表面形成一平整面202b。 ^樣如第2F圖所示，在形成介電層230a及介電層230b 之同時’更可將介電材料一併填入這些貫孔導電層2 2 0 c所圍成f多個狀空間，用以形成多個介電柱2 3 0 c。值得注意的疋’為了預防在介電層230a、介電層230b及介電柱 230c之内部產生空孔，特別是在介電柱23〇c之内部產生空孔’上达之介電材料例如是環氧樹脂（e ρ ο X y )，或是具有自我消泡能力的樹脂等。同，如第2F圖所示，在形成介電層230a及介電層230b 之後’若局部之介電層230a覆蓋至導電層220a之頂面，可利用例如以機械研磨或電漿餘刻的方式，移除局部之介電層230a，直到完全暴露出導電層22〇a之這些凸塊墊222&的頂面。同樣地，若局部之介電層23 Ob覆蓋至導電層220b之表面’可利用例如以機械研磨或電漿餘刻的方式，移除局部之介電層230b，直到完全暴露出導電層220b之這些接合墊2 2 2 b的頂面。值得注意的是，在本較佳實施例之中，介電層230a '介電層230b及這些介電柱230c#可一併形成。如第2G圖所示，為了保護在晶片接合區域a以外之局部導電層220a ’更可選擇性地形成一介電層240a於平整面 202a上，且介電層240a具有一開口242，而開口242係暴露出晶片接合區域A ’而介電層2 4 0 a係用以保護在晶片接合區域A以外之局部導電層2 2 0 a。此外，更可選擇性地形成一介電層240b於平整面202b上，且介電層24〇b更具有多個I0925twf.ptd Page 12 200427026 V. Description of the invention (7) Complementary and the surface of the bump pads 222b of the conductive layer 22b and the surface of the dielectric layer 230b farther from the laminated layer 210 form a flat surface 202b . ^ As shown in FIG. 2F, at the same time when the dielectric layer 230a and the dielectric layer 230b are formed, a dielectric material can also be filled into these through-hole conductive layers 2 2 0 c to form multiple f-shaped spaces. To form a plurality of dielectric pillars 2 3 0 c. It is worth noting that 'to prevent voids from being generated inside the dielectric layer 230a, the dielectric layer 230b, and the dielectric post 230c, especially to generate voids inside the dielectric post 23c', a dielectric material such as a ring Oxygen resin (e ρ ο X y), or resin with self-defoaming ability. Similarly, as shown in FIG. 2F, after the dielectric layer 230a and the dielectric layer 230b are formed, 'if the local dielectric layer 230a covers the top surface of the conductive layer 220a, for example, mechanical polishing or plasma etching may be used. In this way, the local dielectric layer 230a is removed until the top surfaces of the bump pads 222 & of the conductive layer 22a are completely exposed. Similarly, if the local dielectric layer 23 Ob covers the surface of the conductive layer 220b, the local dielectric layer 230b can be removed by, for example, mechanical grinding or plasma etching, until the conductive layer 220b is completely exposed. The top surfaces of these bonding pads 2 2 2 b. It is worth noting that, in the preferred embodiment, the dielectric layer 230a ', the dielectric layer 230b, and the dielectric pillars 230c # can be formed together. As shown in FIG. 2G, in order to protect the local conductive layer 220a 'outside the wafer bonding area a, a dielectric layer 240a can be selectively formed on the flat surface 202a, and the dielectric layer 240a has an opening 242, and the opening The 242 series exposes the wafer bonding area A ′, and the dielectric layer 2 4 0 a is used to protect the local conductive layer 2 2 0 a outside the wafer bonding area A. In addition, a dielectric layer 240b can be selectively formed on the flat surface 202b, and the dielectric layer 240b has a plurality of layers.

Μ 10925twf.ptd 第13頁 200427026 五、發明說明（8) 開口，而這些開口更分別暴露出導電層220b之這些接合墊 222b的局部表面，其中介電層240b係可為一銲罩層。最終，本較佳實施例之覆晶封裝基板製程將可製作出覆晶封裝基板2 0 0。請參考第3圖，其繪示本發明之較佳實施例的一種覆晶封裝基板，其應用於覆晶封裝一晶片的剖面示意圖。在晶片31 0經由這些&塊3 3 0而連接至覆晶封裝基板2 0 0之後，接著進行一底膠填充製程，將底膠材料緩慢地填入於晶片3 1 0、覆晶封裝基板2 0 0及這些凸塊3 3 0所圍成之空間，因而形成一底膠層3 4 0 ，用以緩衝晶片3 1 0與覆晶封裝基板2 0 0之間所產生熱應力。值得注意的是，由於覆晶封裝基板2 0 0之位於晶片接合區域A (如第2 G圖所示）的頂面係為一平整面2 0 2 a，故當底膠材料在注入晶片3 1 0與覆晶封裝基板200之間時，覆晶封裝基板2 0 0之平整面2 0 2a能夠讓底膠材料之流動更加地平順，因而大幅降低底膠層3 4 0 之内部產生空孔的機率，進而提高底膠填充製程的良率。綜上所述，本發明之覆晶封裝基板及其製程至少具有下列優點： (1 )本發明之覆晶封裝基板並非利用銲罩層來定義凸塊墊，而佔據基板表面之過多面積，而是利用圖案與導電層互補之介電層來電性隔絕相鄰之凸塊墊或導線，如此將有助於提高覆晶封裝基板之佈線密度。 (2 )本發明之覆晶封裝基板乃是利用介電層取代銲罩層之定義凸塊墊的作用，由於介電層之可靠度係優於銲Μ 10925twf.ptd Page 13 200427026 V. Description of the invention (8) Openings, and these openings respectively expose partial surfaces of the bonding pads 222b of the conductive layer 220b, wherein the dielectric layer 240b can be a solder mask layer. Finally, the flip-chip package substrate manufacturing process of this preferred embodiment will be able to produce a flip-chip package substrate 2000. Please refer to FIG. 3, which is a schematic cross-sectional view of a flip-chip package substrate applied to a flip-chip package according to a preferred embodiment of the present invention. After the wafer 3 10 is connected to the flip-chip package substrate 2000 via these & blocks 3 3 0, then a primer filling process is performed, and the primer material is slowly filled in the wafer 3 1 0, the flip-chip package substrate 2 0 and the space surrounded by these bumps 3 3 0, so a primer layer 3 4 0 is formed to buffer the thermal stress generated between the wafer 3 1 0 and the flip-chip package substrate 2 0. It is worth noting that, because the top surface of the flip-chip package substrate 2000 located in the wafer bonding area A (as shown in FIG. 2G) is a flat surface 2 0 2a, when the primer material is injected into the wafer 3 Between 10 and the flip-chip packaging substrate 200, the flat surface 2 0 2a of the flip-chip packaging substrate 2 0 2a can make the flow of the primer material more smooth, thereby greatly reducing the voids generated in the primer layer 3 4 0 Probability, thereby improving the yield of the primer filling process. In summary, the flip-chip package substrate of the present invention and its manufacturing process have at least the following advantages: (1) The flip-chip package substrate of the present invention does not use a solder mask layer to define a bump pad, but occupies an excessive area of the substrate surface, and The dielectric layer complementary to the pattern and the conductive layer is used to electrically isolate adjacent bump pads or wires, which will help increase the wiring density of the flip-chip package substrate. (2) The flip-chip package substrate of the present invention uses the dielectric layer instead of the bump pad to define the solder mask layer. The reliability of the dielectric layer is better than that of the solder layer.

10925twf.ptd 第14頁 200427026 五、發明說明（9) 罩層，所以本發明之覆晶封裝基板的表面與底膠層之間的接合性較好。 (3 )由於本發明乃是平坦化在覆晶封裝基板之表面，特別是平坦化覆晶封裝基板之與晶片作覆晶接合的局部表面，故當底膠材料注入晶片與覆晶封裝基板之間所圍成的空間而形成底膠層時，上述之平整面將有助於讓底膠材料之流動更為平順，因而降低底膠層之内部形成空孔的機率，進而提高底膠填充製程之良率。 (4 )本發明之覆晶封裝基板乃是利用介電層來隔絕由導電層所形成之這些凸塊墊，在覆晶接合的過程中，此介電層將可有效地電性隔絕鄰近之凸塊墊。 (5 )本發明在形成介電層於覆晶封裝基板之兩面的過程中，可同時將介電材料一併填入疊合層之由多個貫孔導電層之内面所圍成的多個柱狀空間，而形成多個介電柱，如此將可省略習知之填充貫孔的步驟，因而簡化覆晶封裝基板之製程，進而降低覆晶封裝基板之製作成本。雖然本發明已以一較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍内，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。10925twf.ptd Page 14 200427026 V. Description of the invention (9) The cover layer, so the bonding between the surface of the flip-chip package substrate of the present invention and the primer layer is better. (3) Since the present invention planarizes the surface of the flip-chip package substrate, especially the partial surface of the flip-chip package substrate that is bonded to the wafer, the primer material is injected into the wafer and the flip-chip package substrate. When the primer layer is formed by the space enclosed by the space, the above-mentioned flat surface will help to make the flow of the primer material smoother, thereby reducing the probability of forming voids inside the primer layer, thereby improving the primer filling process. The yield. (4) The flip-chip package substrate of the present invention uses a dielectric layer to isolate the bump pads formed by the conductive layer. During the flip-chip bonding process, this dielectric layer can effectively electrically isolate the adjacent pads. Bump pad. (5) In the process of forming a dielectric layer on both sides of a flip-chip package substrate in the present invention, a dielectric material can be simultaneously filled into multiple layers surrounded by the inner surfaces of a plurality of through-hole conductive layers. A plurality of dielectric pillars are formed in the columnar space, so that the conventional step of filling through holes can be omitted, thereby simplifying the manufacturing process of the flip-chip packaging substrate, thereby reducing the manufacturing cost of the flip-chip packaging substrate. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.

!0925twf.ptd 第15頁 200427026 圖式簡單說明第1圖繪示習知之一種覆晶接合型態之晶片封裝於覆晶封裝基板的剖面示意圖。第2 A〜2 G圖分別繪示本發明之較佳實施例之四層導電層覆晶封裝基板之製作流程的局部剖面圖。覆第3圖繪示本發明之一種覆晶接合型態之晶片封裝於晶封裝基板的剖面示意圖。圖式標示說明】 100 112 116 120 124 124b 126a 130 200 2 0 2b 210a 212a 212c 214b 2 2 0 a 2 2 0 c 2 2 2b 覆晶封裝結構主動表面保護層覆晶封裝基板導電層導線開口凸塊覆晶封裝基板平整面第一面疊合介電層疊合介電層疊合導電層導電層貫孔導電層接合墊 110 114 118 122 124a 126 128 140 2 0 2a 210 210b 212b 214a 216 2 2 0 b 2 2 2 a 2 24 a 晶片晶片墊凸塊底金屬層基板表面：凸塊墊銲罩層縫隙底膠層 :平整面疊合層第二面疊合介電層疊合導電層貫孔 :導電層：凸塊墊 :導線! 0925twf.ptd Page 15 200427026 Brief Description of Drawings Figure 1 shows a schematic cross-sectional view of a conventional flip-chip bonding type chip package on a flip-chip package substrate. Figures 2A to 2G respectively show partial cross-sectional views of a manufacturing process of a four-layer conductive-chip flip-chip package substrate according to a preferred embodiment of the present invention. FIG. 3 is a schematic cross-sectional view of a flip-chip bonding type wafer package on a wafer package substrate according to the present invention. Description of diagrams] 100 112 116 120 124 124b 126a 130 200 2 0 2b 210a 212a 212c 214b 2 2 0 a 2 2 0 c 2 2 2b flip-chip packaging structure active surface protection layer flip-chip packaging substrate conductive layer wire opening bumps Flip-chip package substrate flat surface first surface laminated dielectric laminated dielectric laminated laminated conductive layer conductive layer through hole conductive layer bonding pad 110 114 118 122 124a 126 128 140 2 0 2a 210 210b 212b 214a 216 2 2 0 b 2 2 2 a 2 24 a wafer wafer pad bump bottom metal layer substrate surface: bump pad welding cover layer gap bottom adhesive layer: flat surface laminated layer second surface laminated dielectric laminated conductive layer through hole: conductive layer: Bump pad: wire

10925twf.ptd 第16頁 200427026 圖式簡單說明 2 2 4b 2 3 0 b 2 4 0 a 2 4 2 ： 3 3 0 ：導線介電層介電層開口凸塊 2 3 0 a :介電層 230c :介電柱 2 4 0 b :介電層 3 1 0 ·晶片 3 4 0 :底膠層 A :晶片接合區域 Φ10925twf.ptd Page 16 200427026 Brief description of the drawing 2 2 4b 2 3 0 b 2 4 0 a 2 4 2: 3 3 0: wire dielectric layer dielectric layer opening bump 2 3 0 a: dielectric layer 230c: Dielectric post 2 4 0 b: Dielectric layer 3 1 0 · Wafer 3 4 0: Primer layer A: Wafer bonding area Φ

10925twf.ptd 第17頁10925twf.ptd Page 17

Claims

200427026 申請專利範圍 1 · 少一貫及該第圖面，且線；一種疊合，二面案化該第第一覆晶封裝基板，至少包括：層，具有一第一面及對應之一第二面，具有至其貫穿該疊合層，而連接該疊合層之該第一面之一第一導電層，配置於該疊合層之該第一導電層係構成複數個凸塊墊及複數個第導介電層，配置於該疊合層之該第一面，並覆蓋該疊合層之由該第一導電層所暴露出的局部表面，但未覆蓋該第一導電層之表面，且該第一導電層之表面係與該第一介電層之較遠離該疊合層的表面共同形成一第一平整面；以圖面，且線。 2. 該疊合 3. 該疊合層之及案化該第導電之一第二導電層，配置於該疊合層之該第二二導電層係構成複數個接合墊及複數個第二導如申請專利範圍第1項所述之覆晶封裝基板，其中層至少包括一疊合介電層。如申請專利範圍第1項所述之覆晶封裝基板，其中層至少包括一疊合介電層及圖案化之一疊合導電其中該些疊合介電層係配置介於該疊合導電層及該第層之間。請專利範圍第1項所述之覆晶封裝基板，更包罩層，其配置於該第一介電層及該第一導電層且該第一銲罩層更具有一開口，而該開口係完全暴 4 ·如申括一第一銲之上200427026 The scope of patent application 1 · Less consistent with the first drawing and line; a kind of superimposition, two sides of the first flip chip package substrate, including at least: a layer having a first side and a corresponding one of the second The surface has a first conductive layer that penetrates the overlay layer and connects to the first surface of the overlay layer, and the first conductive layer disposed on the overlay layer constitutes a plurality of bump pads and a plurality of A second conductive dielectric layer is disposed on the first side of the laminated layer and covers a partial surface of the laminated layer exposed by the first conductive layer, but does not cover the surface of the first conductive layer, And the surface of the first conductive layer and the surface of the first dielectric layer farther from the superposition layer together form a first flat surface; the drawing surface is a line. 2. The overlay 3. The overlay and the first conductive second conductive layer, and the second and second conductive layers disposed on the overlay constitute a plurality of bonding pads and a plurality of second conductive layers. The flip-chip package substrate according to item 1 of the scope of patent application, wherein the layer includes at least one stacked dielectric layer. The flip-chip package substrate according to item 1 of the scope of patent application, wherein the layer includes at least a laminated dielectric layer and a patterned one of the laminated conductive layers, wherein the laminated dielectric layers are disposed between the laminated conductive layers. And between that first layer. The flip-chip package substrate described in item 1 of the patent scope, and a cover layer, is disposed on the first dielectric layer and the first conductive layer, and the first solder cover layer further has an opening, and the opening is Completely violent 4 · As stated above a first welding

10925twf.ptd 第18頁 200427026 六、申請專利範圍露出該些第一凸塊墊。 5 .如申請專利範圍第1項所述之覆晶封裝基板，更包括圖案化之一第二銲罩層，其覆蓋於該疊合層之該第二面，且該第二銲罩層更具有複數個開口，而該些開口係分別暴露出該些接合墊之至少局部表面。 6 .如申請專利範圍第1項所述之覆晶封裝基板，其中該疊合層至少包括一疊合介電層。 7.如申請專利範圍第1項所述之覆晶封裝基板，其中該疊合層至少包括一疊合介電層及圖案化之一疊合導電層，且該疊合介電層係配置介於該疊合導電層、該第一導電層及該第二導電層所組成族群之任二相鄰者之間。 8 .如申請專利範圍第1項所述之覆晶封裝基板，更包括一第二介電層，其配置於該疊合層之該第二面，並覆蓋該疊合層之由該第二導電層所暴露出的局部表面，但未覆蓋該第二導電層之表面，且該第二導電層之表面係與該第二介電層之表面共同形成一第二平整面。 9 .如申請專利範圍第1項所述之覆晶封裝基板，更包括：一貫孔導電層，配置於該貫孔之内面，且該貫孔導電層之内面係更圍成一柱狀空間；以及至少一介電柱，容納於該柱狀空間。 1 0 .如申請專利範圍第1項所述之覆晶封裝基板，其中該第一介電層之材質係為具有自我消泡能力之樹脂。 1 1 . 一種覆晶封裝基板製程，至少包括下列步驟：10925twf.ptd Page 18 200427026 6. Scope of Patent Application These first bump pads are exposed. 5. The flip-chip package substrate according to item 1 of the scope of the patent application, further comprising a patterned second solder mask layer covering the second surface of the laminated layer, and the second solder mask layer is more There are a plurality of openings, and the openings respectively expose at least a partial surface of the bonding pads. 6. The flip-chip package substrate according to item 1 of the scope of patent application, wherein the laminated layer includes at least one laminated dielectric layer. 7. The flip-chip package substrate according to item 1 of the scope of the patent application, wherein the laminated layer includes at least a laminated dielectric layer and a patterned laminated conductive layer, and the laminated dielectric layer is configured with a dielectric Between any two adjacent groups of the superposed conductive layer, the first conductive layer, and the second conductive layer. 8. The flip-chip package substrate as described in item 1 of the scope of patent application, further comprising a second dielectric layer disposed on the second side of the laminated layer and covering the laminated layer by the second layer. A part of the surface exposed by the conductive layer, but not covering the surface of the second conductive layer, and the surface of the second conductive layer and the surface of the second dielectric layer together form a second flat surface. 9. The flip-chip package substrate described in item 1 of the scope of patent application, further comprising: a through-hole conductive layer disposed on the inner surface of the through-hole, and the inner surface of the through-hole conductive layer is further enclosed into a columnar space; And at least one dielectric post is accommodated in the post space. 10. The flip-chip package substrate according to item 1 of the scope of patent application, wherein the material of the first dielectric layer is a resin having a self-defoaming ability. 1 1. A flip-chip package substrate manufacturing process, including at least the following steps:

10925twf.ptd 第19頁 200427026 六、申請專利範圍 (a) 提供一疊合層、圖案化之一第一導電層及圖案化之一第二導電層，其中該疊合層具有一第一面及對應之一第二面，而該第一導電層係配置於該疊合層之該第一面，並構成複數個凸塊墊及複數個第一導線，且該第二導電層係配置於該疊合層之該第二面，並構成複數個接合墊及複數個第二導線；以及 (b) 形成一第一介電層，其中該第一介電層係覆蓋於該疊合層之由該第一導電層所暴露出的局部表面，但未覆蓋該第一導電層之表面，使得該第一導電層之表面係與該第一介電層之表面共同形成一第一平整面。 1 2 .如申請專利範圍第1 1項所述之覆晶封裝基板製程，其中該第一介電層之材質係採用具有自我消泡能力之樹脂。 1 3 .如申請專利範圍第1 1項所述之覆晶封裝基板製程，更包括形成一第一銲罩層於該第一介電層及該第一導電層之上，且該第一銲罩層更具有一開口，而該開口係完全暴露出該些第一凸塊塾。 1 4 .如申請專利範圍第1 1項所述之覆晶封裝基板製程，其中該疊合層至少包括一疊合介電層。 1 5 ·如申請專利範圍第1 1項所述之覆晶封裝基板製程，其中該疊合層至少包括一疊合介電層及圖案化之一疊合導電層，且該些疊合介電層係配置介於該疊合導電層、該第一導電層及該第二導電層所組成族群之任二相鄰者之間。10925twf.ptd Page 19 200427026 6. Scope of patent application (a) Provide a superimposed layer, a patterned first conductive layer and a patterned second conductive layer, wherein the superposed layer has a first surface and Corresponding to a second surface, and the first conductive layer is disposed on the first surface of the superposition layer, and constitutes a plurality of bump pads and a plurality of first wires, and the second conductive layer is disposed on the The second side of the superposed layer constitutes a plurality of bonding pads and a plurality of second wires; and (b) forms a first dielectric layer, wherein the first dielectric layer covers the layer of the superposed layer. A partial surface of the first conductive layer is exposed, but the surface of the first conductive layer is not covered, so that the surface of the first conductive layer and the surface of the first dielectric layer together form a first flat surface. 12. The process for manufacturing a flip-chip package substrate according to item 11 of the scope of patent application, wherein the material of the first dielectric layer is a resin with self-defoaming ability. 13. The process for manufacturing a flip-chip package substrate as described in item 11 of the scope of patent application, further comprising forming a first solder mask layer on the first dielectric layer and the first conductive layer, and the first solder The cover layer further has an opening, and the opening completely exposes the first bumps 塾. 14. The process for manufacturing a flip-chip package substrate according to item 11 of the scope of patent application, wherein the laminated layer includes at least one laminated dielectric layer. 15 · The flip-chip package substrate manufacturing process according to item 11 of the scope of patent application, wherein the laminated layer includes at least a laminated dielectric layer and a patterned laminated conductive layer, and the laminated dielectrics The layer system is arranged between any two adjacent groups of the superposed conductive layer, the first conductive layer and the second conductive layer.

1092 51 w f.p t d 第20頁 200427026 六、申請專利範圍 1 6 ·如申請專利範圍第1 1項所述之覆晶封裝基板製程，其中於步驟（b )之時，更包括形成一第二介電層於該疊合層之該第二面，並覆蓋該疊合層之由該第二導電層所暴露出的局部表面，但未覆蓋該第二導電層之表面，且該第二導電層之表面係與該第二介電層之表面共同形成一第二平整面。 1 7 .如申請專利範圍第1 6項所述之覆晶封裝基板製程，更包括形成圖案化之一第二銲罩層於該第二介電層及該第二導電層之上，且該第二銲罩層係暴露出該些接合墊之至少局部表面。 1 8 .如申請專利範圍第1 6項所述之覆晶封裝基板製程，其中該叠合層更具有至少一貫孔及至少一貫孔導電層，且該貫孔係貫穿該疊合層、該第一導電層及該第二導電層，而該貫孔導電層係配置於該貫孔之内面，且該第一導電層係經由該貫孔導電層，而電性連接至該第二導電層，且該貫孔導電層之内面係更圍成一柱狀空間。 1 9 .如申請專利範圍第1 8項所述之覆晶封裝基板製程，其中在形成該第一介電層之時，更包括將形成該第一介電層之相同材料同時填入該柱狀空間，用以形成至少一介電柱。1092 51 w fp td Page 20 200427026 6. Scope of patent application 16 · The flip-chip package substrate manufacturing process described in item 11 of the scope of patent application, in step (b), further includes forming a second interface An electrical layer is on the second surface of the superposed layer and covers a partial surface of the superposed layer exposed by the second conductive layer, but does not cover the surface of the second conductive layer, and the second conductive layer The surface thereof and the surface of the second dielectric layer together form a second flat surface. 17. The process for manufacturing a flip-chip package substrate as described in item 16 of the scope of patent application, further comprising forming a patterned second solder mask layer on the second dielectric layer and the second conductive layer, and the The second solder mask layer exposes at least a partial surface of the bonding pads. 18. The process for manufacturing a flip-chip package substrate according to item 16 of the scope of the patent application, wherein the superposition layer further has at least one through hole and at least one through hole conductive layer, and the through hole penetrates the superposition layer, the first A conductive layer and the second conductive layer, and the through-hole conductive layer is disposed on the inner surface of the through-hole, and the first conductive layer is electrically connected to the second conductive layer through the through-hole conductive layer, Moreover, the inner surface of the through-hole conductive layer is further enclosed into a columnar space. 19. The process for manufacturing a flip-chip package substrate as described in item 18 of the scope of patent application, wherein when the first dielectric layer is formed, it further includes simultaneously filling the same material forming the first dielectric layer into the pillar. A space is used to form at least one dielectric post.

10925twf.ptd 第21頁10925twf.ptd Page 21