TW200421801A - Receiving and transmitting signals having multiple modulation types using sequencing interpolator - Google Patents
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- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
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Abstract
Description
200421801 五、發明說明（1) 發明所屬之技術領域 本發明係關於一種無線區域網路（WLAN)裝置，其能接 收和傳送多重調變型態之信號，本發明尤其是關於一種序 列内插器’其能提供一種一預設調變型態信號之有理數的 比例（整數/整數）内插器，藉其減少相鎖迴路（PLLs)之數 置’其係用於5亥無線區域網路裝置中。 發明背景 無線區域網路（WLANs)在通訊網路方面變得越來越受 歡迎，IEEE 802.11標準提供於無線區域網路運作之裝置 運作的準則。具體地說 802.1 1 a標準定義在5 GHz頻寬下 使用6、12、18、24、36和54 Mbps之資料率的通訊， 802.1 lb標準定義在2.4 GHz頻寬下使用j、2、5. 5和η = 率的甘通訊，最近提出新增至8〇2.U標準的稱為 使用8G2.Ua之高料率於8()2」lb之 頻寬中傳輸，亦即2. 4 GHz。 8U2.11g標準的展望在於8〇2llb 線區域網路中運作之8n9 n 护罢置此/、在同一個無 岭τ連作之8〇2· llg裝置通訊，而不須 。在一公共通訊模式中，客戶端透過一存取點"\ 汛，換句話說，一存取點之作用是 :目、 互相通訊。當在文中使用到「裝置」日;中盆=端能直接 取點，就是作為一客戶端。 f ，、不疋作為一存 200421801 五、發明說明（2) 當允許貝料率增加時，為了確保與之前8〇2· nb之相 容性，802· llg標準合併了8〇2· Ua及8〇2· ub標準之調變 結構，-般來說，調變即表示資訊增加至載波，典型地調 變技術包含了頻率調變，其中載波波形之頻率是多樣化 1 :8〇2.llb標準使用一種稱為互補碼移位鍵（cck)之調變 t 反之’ 8〇2· 1 U標準使用另一種稱為正交頻率多重 分割（0FDM)之調變妹爐，s# 夕里 _皆提# 了 1 μ = t 補碼移位鍵和正交頻率多重分 割白徒供了特殊的頻率調變觀點。 碉變ί ^ 802·…標準提供了相容性之指導方針，允許雙 置提供去处枯田夕从式執订’因此一些無線區域網路妒 交頻率多重分割調變接收或傳幹‘ ：f補碼移位鍵或正 是重建。然而，這此= 能正確地被解譯或 丄/ 二夕餘的几件令人不快蚰i场知7 / ，和功率損耗’因此，便有一曰：，馬路成 = 〇2.llg標準操作之一無 二要-=地減 及/或客戶端)之多餘元件和功率的方法。路裝置(存取點 發明内容 ^無線區域網路（WLAN)+，接收 二構之k號能請求多重時脈率率二^有夕重調 寺:=係由一相鎖迴路(pu)提 /在型地，每— …線區域網路裝置中，就需要多重相鎖迴路在不-幸傳:是的 第8頁 200421801200421801 V. Description of the invention (1) The technical field to which the invention belongs The present invention relates to a wireless local area network (WLAN) device capable of receiving and transmitting signals of multiple modulation types. The present invention particularly relates to a sequence interpolator 'It can provide a rational number ratio (integer / integer) interpolator of a preset modulation type signal, by which the number of phase-locked loops (PLLs) can be reduced.' It is used in 5H wireless LAN devices. in. BACKGROUND OF THE INVENTION Wireless local area networks (WLANs) are becoming more and more popular in communication networks. The IEEE 802.11 standard provides guidelines for the operation of devices operating on wireless local area networks. Specifically, the 802.1 1 a standard defines communication using data rates of 6, 12, 18, 24, 36, and 54 Mbps at 5 GHz, and the 802.1 lb standard defines j, 2, 5, and 2.4 GHz. 5 and η = the rate of communication, recently proposed to be added to the 802.U standard is called the use of 8G2.Ua high data rate transmission in the bandwidth of 8 () 2 "lb, that is 2.4 GHz. The prospect of the 8U2.11g standard lies in the 8n9 n protection device operating in the 802llb line area network, and to communicate with 802 · llg devices in the same continuous τ continuous cropping without the need. In a public communication mode, the client communicates with each other through an access point " \ Xun, in other words, an access point serves as a purpose. When the "device" day is used in the text; Zhongpen = the terminal can directly take the point, which is used as a client. f ,, as a deposit 200421801 V. Description of the invention (2) When the shell material rate is allowed to increase, in order to ensure compatibility with the previous 802 · nb, the 802 · llg standard incorporates 802 · Ua and 8 〇2 · The modulation structure of the ub standard. Generally speaking, modulation means that information is added to the carrier. Typically, modulation technology includes frequency modulation, in which the frequency of the carrier waveform is diversified 1: 8〇2.llb The standard uses a modulation t called complementary code shift key (cck) and vice versa '802 · 1 U standard uses another type of modulation called orthogonal frequency multiple division (0FDM). S # 夕 里 _ 都The # 1 1 = t-complement shift key and orthogonal frequency multi-segment white apprentice provide a special view of frequency modulation.碉 Change ^ 802 · ... The standard provides guidelines for compatibility, allowing dual-sets to provide a place to go, and to subscribe to 'therefore some wireless LANs are jealous of frequency, multiple division, modulation, reception or transmission': f Complement shift key or reconstruction. However, this = can be interpreted correctly or 丄 / more than a few pieces of unpleasant 蚰 i know 7 /, and the power loss' Therefore, there is a saying:, road into = 〇2.llg standard operation One of them is the method of-= ground reduction and / or client side redundant components and power). Device (access point of the invention ^ wireless local area network (WLAN) +, receiving the k number of the second structure can request multiple clock rate two) Youxi readjustment temple: = is provided by a phase-locked loop (pu) / In the type of ground, each-… line LAN device requires multiple phase-locked loops. No-fortunately: page 8 200421801
兩者在 的面…功率損耗’ 於本發明之一方向，一單一相鎖迴路（PLL)能被用 I以二線區域網路裝置中，其係以一多重調變結構模式操 歹，如8 0 2 · 11 g。在一實施例中，該相鎖迴路能以11 的倍數執行，例如176 MHz，因此在該無線區域網路裝 人之70件能以來自該相鎖迴路之11 MHz之倍數執行。包 3在該8〇2·11模式之一調變結構，稱作正交頻率多重分割 (0FDM) ’需要使用4〇 MHz以重建其調變信號，在本例中， 一序列内插器能以44 MHz輸入接收信號，且較佳地以4〇 MHz輸出信號，從而消除增加另一相鎖迴路之需求。 七序列内插器在概念上能被想成如同複數個内插器，其 中每一内插器施加一定程度的係數至該接收之信號上，亦 即樣本。一最小均方差（MMSE)技術能用以決定該内插器之 係數，可以選擇係數以確保在頻率區域中的誤差是在一給 予可忍受的範圍之内，依此方式，該内插器在通頻之内之 頻率區域總誤差就可確保是在一給予可忍受的範圍之内。 内插器能用於基於一什數器值之一預設序列中，該計數值 稱為一計數，在一預設計數中，一内插輸出樣本係被摒棄 (如果該輸出率小於輸入率）或是附加上去（如果該輸入率 小於該輸出率），且該計數器係被重新設定。The two aspects ... power loss' In one aspect of the present invention, a single phase-locked loop (PLL) can be used in a two-wire LAN device, which operates in a multiple modulation structure mode. Such as 8 0 2 · 11 g. In one embodiment, the phase-locked loop can be executed at a multiple of 11, such as 176 MHz, so 70 pieces installed in the wireless LAN can be performed at a multiple of 11 MHz from the phase-locked loop. The modulation structure of packet 3 in one of the 802 · 11 modes is called orthogonal frequency multiple division (0FDM). It needs to use 40MHz to reconstruct its modulation signal. In this example, a sequence interpolator can Receive signals at 44 MHz input, and preferably output signals at 40 MHz, thereby eliminating the need to add another phase-locked loop. The seven-sequence interpolator can be conceptually thought of as a plurality of interpolators, each of which applies a certain degree of coefficient to the received signal, that is, the sample. A minimum mean square error (MMSE) technique can be used to determine the coefficients of the interpolator. The coefficients can be selected to ensure that the error in the frequency region is within a tolerable range. In this way, the interpolator is in The total error in the frequency region within the pass frequency can be guaranteed to be within a tolerable range. The interpolator can be used in a preset sequence based on a count value. The count value is called a count. In a preset count, an interpolated output sample is discarded (if the output rate is less than the input rate). ) Or added (if the input rate is less than the output rate) and the counter is reset.
200421801 發明說明 nw 在一貫施例中，複數個内插器與一具有多個内插期之 單 内插器一起實施，該序列内插器之每一配置在一計數 $間，為一内插期，該序列内插器能包含一閥門延遲線、 :乘异網路、_多工器網路及一總和區塊，該閥門延遲線 儲存N個樣本’其中N能基於一所需之信號雜訊比（SNR)選 擇/該乘算網路將每一樣本乘上一係數。依據本發明之一 特徵該夕工器網路之優勢係在於減少硬體需求以執行該 序列内插器。在一實施例中，該多工器網路能由一計數器 值f制’如果該計數器值到達一預設值，則該序列内插器 之一輸出樣本係被摒棄（如果該輸出率小於輸入率）或是附 =上去（如果該輸入率小於該輸出率），該總和區塊加總由 該多工器網路產生之乘積。 夕在一實施例中，該多工器網路及該乘算網路能藉由一 =路傳輸之部分乘積網路執行，該多路傳輸之部分乘積網 可包含預設之多工器組，每一多工器接收基於該樣本之 :之複數個位元位移值，且提供其輸出至—加法器，該加 法器接著提供其輸出總和至該總和區塊，在本實施例中， 所有多工器可藉由該計數控制。 一種減少相鄰輸出樣本之 樣本係藉由複數個内插器提供 差（MMSE)技術能用以選擇該複 設係數組能用於每一延遲。 非線性的方法亦被提供，該 。在本方法中，一最小均方 數個内插器之預設係數，預200421801 Description of the invention nw In a conventional embodiment, a plurality of interpolators are implemented together with a single interpolator having multiple interpolation periods. Each configuration of the sequence interpolator is within a count of $, which is an interpolation. In the future, the sequence interpolator can include a valve delay line, a multiplier network, a multiplexer network, and a sum block. The valve delay line stores N samples, where N can be based on a desired signal. Noise ratio (SNR) selection / The multiplication network multiplies each sample by a factor. An advantage of the router network according to a feature of the invention is that it reduces hardware requirements to perform the sequence interpolator. In an embodiment, the multiplexer network can be controlled by a counter value f. If the counter value reaches a preset value, one of the output samples of the sequence interpolator is discarded (if the output rate is less than the input Rate) or appended (if the input rate is less than the output rate), the sum block adds up the product generated by the multiplexer network. In an embodiment, the multiplexer network and the multiplication network can be implemented by a partial product network of one transmission, and the partial product network of the multiplex may include a preset multiplexer group. Each multiplexer receives a plurality of bit shift values based on the sample and provides its output to an adder, which then provides its output sum to the sum block. In this embodiment, all The multiplexer can be controlled by this count. A sample that reduces adjacent output samples is provided by a plurality of interpolators. The difference (MMSE) technique can be used to select the set of reset coefficients that can be used for each delay. Non-linear methods are also provided, the. In this method, the preset coefficients of a minimum mean square number of interpolators are
第10頁 五、發明說明（5) 以以-發送器亦被提供。該發送器能包含用 之，本係由接收裝置而來，以-本，且在一斗二处^貢料樣本成為内插過之資料樣 料樣本：i以一第二$率摒冑或附加預言史之内插資 之；Γ器更進一步包含-裝置1以選擇在-； 樣本。^理貝科樣本之H第二速率之内插資料 種一 WLAN 放大器， 信號；用 内之基頻 頻率及輪 基於其調 該時脈率 符合時脈 元件能較 處理區塊 處理區塊 位信號 塊能轉 號。依此方法 一單一時脈率 述之序列内插 ，且提供該信 變增益 之無線 接收器 該基頻 地處理 未符合 號成為 接收器 中，該 接收該 裝置之 例如RF 以混合 頻率； 出數位 變型式 ，則該 率之信 佳地於 包含上 之輸出 接收器 、IF及 該無線 類比數 信號； 之該數 處理區 亦被提 基頻放 信號之 位轉換 一處理 供。該接收器包含可 大器，用以放大輸入 裝置能用以提供在該 器（ADC)能用以接收 區塊能被用以選擇性 ，如果該調變型式並 換該非符合時脈率信 ，該處理區塊及其他 上運作，在一實施例 器，一解碼器可用以 號精確的重建。 一種一WLAN裝置之收發器亦被提供。該收發器包含— 接收器區塊及一發送器區塊，該接收器區塊以一第—時舰Page 10 V. Description of the invention (5) The I-transmitter is also provided. The transmitter can be used for this. It is from the receiving device. It is-this, and the sample in two places in the bucket becomes an interpolated data sample: i is rejected at a second $ rate or Additional prophecies are interpolated within the history; the Γ device further includes -device 1 to select at-; samples. ^ Interpolation data of H second rate of Ribecco sample: a WLAN amplifier, signal; using the internal fundamental frequency and round to adjust the clock rate based on it, the clock component is in line with the clock component, which can process the block bit signal more than the processing block. Blocks can be renumbered. According to this method, a sequence of a single clock rate is interpolated, and a wireless receiver that provides the signal gain gain is processed into a receiver at the fundamental frequency, and the receiver receives, for example, RF at a mixed frequency; In the variant, the rate of the signal is better including the output receiver, IF and the wireless analog signal; the digital processing area is also converted to a baseband signal for processing. The receiver includes a magnifier, which can be used to amplify the input device can be used to provide the ADC (ADC) can be used to receive the block can be used to select, if the modulation type and the non-compliant clock rate signal, The processing block and others operate on one embodiment, and a decoder can be used for accurate reconstruction. A transceiver for a WLAN device is also provided. The transceiver includes a receiver block and a transmitter block. The receiver block is a first-time ship.
第11頁 200421801 五、發明說明（6) 送器之Lf 1 t以-第二時脈率輪出信號至該發 -或多個i: !，該發送器區塊能從該發送器之 第-時脈率提供系統輸出信號。虎，且以-及該發送器區塊^ 、疋該接收器區塊 率成第二時ί率；内插器，其轉換該第 實施方式 WLAN裝置使用一相鎖迴路（ 「 維持於該裝置中瘂你叙a 一从 ；W鎖住」，亦即 當以兮私#中彳呆作數位70件之一基礎時脈率。一pll通 乂該數位元件之該所需時脈率之 該PLL能即時在任一點僅以A $玄私丁 （思 果需I 其中之—速率執行），然而，如 ^ . 而時脈率之一非整數倍數，則在該WLAN裝置典 型地係提供多路PLL。 π i /、 舉例來說，在802· llg WLAN裝置中，分析CCK封包的 數位兀件需要一為1 1 MHz的主要時脈率，反之，分析〇FM 封包之數位元件需要一為40 MHz之主要時脈率，因此，因 為40並被11的整數倍數，典型地就必須提供不同的pLL以 產生11 MHz和40 MHz，藉此確保於8〇2.llg WLAN裝置中之 CCK和OFDM封包能精確地重建，然而，使用這種解決方 案’於一積體電路（1C)上與這些PLLs相關的面積以及用以 操作多路PLL的功率將會令人不滿地增加。Page 11 200421801 V. Description of the invention (6) The transmitter's Lf 1 t signals out to the transmitter at-the second clock rate-or multiple i:!, The transmitter block can -Clock rate provides system output signal. And the transmitter block ^ and the receiver block rate become the second time rate; the interpolator converts the WLAN device of the first embodiment using a phase-locked loop ("maintained in the device In the middle of you, you will follow the instructions from “W Lock”, that is, when Xixi # 中 彳 呆 is used as one of the basic 70 digital clock rates. A pll will pass the required clock rate of the digital component. The PLL can only be used at any point at A $ xuan sing Ding (think of I need to be-the rate of execution), however, such as ^. And the clock rate is a non-integer multiple, the WLAN device typically provides multiple channels PLL. Π i /. For example, in the 802.1ll WLAN device, the digital component of the CCK packet needs a main clock rate of 1 1 MHz. On the contrary, the digital component of the 0FM packet needs a 40. The main clock rate of MHz. Therefore, because 40 is multiplied by an integer of 11, typically different pLLs must be provided to generate 11 MHz and 40 MHz, thereby ensuring CCK and OFDM in 802.llg WLAN devices. Packets can be accurately reconstructed, however, using this solution 'on a integrated circuit (1C) with these The area associated with PLLs and the power used to operate multiple PLLs will increase unsatisfactorily.
第12頁 200421801 五、發明說明（7) " 时因此，依據本發明之一特徵，便能使用一序列内插濾 波器（亦稱為一序列内插器），有了這種序列内插器，於 802.、llg WLAN裝置所需的pLL數量便能明顯地減少，舉例 來說’僅需要一個PLL，而不需要兩個，便能使CCK *0FDM 封包精確地重建，依此方法，該序列内插器較佳地減少了 在8 02· llg WLAN裝置的矽面積且降低其功率損耗。 在一 802.11g裝置之實施例中，該pLL可以n mhz之一 整數倍數執行，例如176 MHz，當該裝置之數位元件需要 時即可分除之’因此，在本實施例中，該(：(：1(封包之取樣 即可以11 MHz執行。較佳地，該序列内插器能提供複數個 獨特延遲以便，舉例來說，於44 MHz所接收之0FDM封包 (例如176 MHz劃分成4χ之樣本）能以4〇 MHz取樣（亦即所需 速率）’除此之外’如同另一個優點，該序列内插器能提 供使用比習知非整數分量率内插器還要低之功率的功能。 如第一圖所示之一習知非整數分量率内插器2〇〇 ,在 步驟101決定該起始（亦即11 MHz)及結束（亦即40 MHz)取 樣率之最小公倍數，在本例中，11 MHz和40 MHz之最小公 布數即為440 ( 1 1 X 40 ) MHz，在該點上，一上行取樣會 典型地在步驟102中由44 MHz執行至440 MHz(亦即一為10 之上行取樣）’在該上行取樣步驟中，每一對在44 MHz樣 本之間會加入9個零，依此方法，1 〇個樣本係提供給每一 1 原始樣本，因此，該濾波器現在係以440 MHz執行，在步Page 12 200421801 V. Description of the invention (7) Therefore, according to a feature of the present invention, a sequence interpolation filter (also known as a sequence interpolation device) can be used. With this sequence interpolation It can significantly reduce the number of pLLs required by 802. and llg WLAN devices. For example, 'only one PLL is needed instead of two, so that CCK * 0FDM packets can be accurately reconstructed. According to this method, The serial interpolator preferably reduces the silicon area of the 802.11g WLAN device and reduces its power loss. In an embodiment of an 802.11g device, the pLL can be performed at an integer multiple of n mhz, such as 176 MHz, which can be divided when the digital components of the device require it. Therefore, in this embodiment, the (: (: 1 (Sampling of packets can be performed at 11 MHz. Preferably, the sequence interpolator can provide a plurality of unique delays in order to, for example, receive 0FDM packets at 44 MHz (for example, 176 MHz divided into 4 × Sample) can be sampled at 40 MHz (ie, the required rate). In addition to this, the sequence interpolator can provide lower power than the conventional non-integer component rate interpolator. Function: As shown in the first figure, a conventional non-integer component rate interpolator 200 is used. At step 101, the least common multiple of the start (ie, 11 MHz) and end (ie, 40 MHz) sampling rate is determined. In this example, the minimum number of announcements for 11 MHz and 40 MHz is 440 (1 1 X 40) MHz. At this point, an uplink sample is typically performed from 44 MHz to 440 MHz in step 102 (that is, One is the upsampling of 10) 'In this upsampling step, each pair is sampled at 44 MHz 9 will be added between zero, so the method, a square-based sample 1 is supplied to each of the original sample, and therefore, the filter system is now executed to 440 MHz, at step
第13頁 200421801 五、發明說明（8) 驟1 0 3中，一低通濾波操作接著能於該結果樣本上執行， 該濾波器於使用該新加入零之樣本支援使樣本間產生一流 暢的轉換，接著，一下行取樣會於步驟104中從440 MHz執 行至40 MHz，（亦即一為11之下行取樣），在本例中，每一 第11樣本係被選取而其他樣本則被捨棄’這種習知的内插 器，雖然提供一種精確的解決方案，但是需要系統於44〇 MHz運作，這種高時脈率相對地需要高功率損耗，這使得 這種内插器結構在WLAN應用上就商業上而言是不實用的。 «月注思其他内插能不需精確地改變該取樣率即可提 供補償。舉例來說，第二圖說明一波形，其中樣本2〇1Α 一 201Ε係被接收，儘管較佳地樣本2 0 2Α - 202Ε將被分析， 在本例中，一内插器係被用來以同樣速率取樣，但對每一 樣本201Α - 201Ε使用一時間補償2 03以確保理想的（亦即 最尚/最低值）202A - 202Ε樣本係被分析，然而，更重要 的，這種形式之間差器無法對0FDM封包提供所需之44 ΜΗζ 至40 MHz之取樣轉換。 依據本發明之一貫施例，十個内插器（亦即一個係為 了所需輸出之每一相）能用以提供該所需取樣，舉例來 說，請參照第三圖，十個内插器可用以提供預設延遲0在 44 MHz 接收樣本300(亦即〇、！、2、3、4、5、6、7、8、 9、1〇、0) ’以便輸出樣本5ΐι(亦即〇、ι、3、4、5、 6、7、8、9、0)能降為所需的4〇 MHz取樣率，舉例來說，Page 13 200421801 V. Description of the invention (8) In step 103, a low-pass filtering operation can then be performed on the result sample. The filter uses the newly added zero sample support to generate a smooth between samples. The conversion, then, the next line sampling will be performed from 440 MHz to 40 MHz in step 104 (that is, a downsampling of 11). In this example, every 11th sample is selected and the other samples are discarded. 'This conventional interposer, although providing an accurate solution, requires the system to operate at 44MHz. This high clock rate requires relatively high power loss, which makes this interposer structure suitable for WLANs. It is not practical in terms of application. «Monthly note that other interpolations can provide compensation without the need to change the sampling rate accurately. For example, the second figure illustrates a waveform in which samples 201A-201E are received, although preferably samples 202-2A-202E will be analyzed. In this example, an interpolator system is used to Sampling at the same rate, but using a time compensation of 2 03 for each sample 201A-201Ε to ensure that the ideal (ie, the highest / lowest) 202A-202E samples are analyzed, however, more importantly, between this form The differentiator cannot provide the required 44 MHz to 40 MHz sampling conversion for an 0FDM packet. According to one embodiment of the present invention, ten interpolators (that is, one for each phase of the required output) can be used to provide the required sampling. For example, referring to the third figure, ten interpolators The device can be used to provide a preset delay of 0 to receive samples 300 (ie 0,!, 2, 3, 4, 5, 6, 7, 8, 9, 10, 0) at 44 MHz in order to output samples 5ΐι (ie 〇, ι, 3, 4, 5, 6, 7, 8, 9, 0) can be reduced to the required 40MHz sampling rate, for example,
第14頁 200421801 五、發明說明（9) 第一内插器能提供樣本1 一個〇 · 1樣本之一内插補償 501 ’ 一第二内插器能提供能提供樣本2 一個〇·2樣本之一 内插補償502，一第三内插器會提供樣本3 一個〇·3樣本之 一=插補償5 03，第四個亦同。注意最長的接收樣本9之延 遲月b有效地接到接收樣本〇 (第二實例）及輸出樣本〇 (亦為 第二實例），因此，取樣能以接收樣本3〇〇之樣本〇(有效地 樣本11 )接續。 依據本發明之一特徵，為在内插器中之閥門選擇適當 的係數能產生所需之補償（亦即0 · 1 - 〇 · 9 )。有趣的是， 一 〇，1之内插補償之該内插器具有與一 〇·9内插補償之一内 插相相同的閥門，只是其排序剛好相反，類似的情況， 〇· 2、0· 3及0· 4内插補償之内插器具有分別與〇. 8、〇· 7及 0 · 6内插補償之一内插相相同的閥門，只是其排序剛好相 反。因此’在一實施例中，五組内插器係數能提供所需之 補償（注意任何接收之樣本〇不需要補償），此減少技術係 於一文早中討論過’其標題為「量化於内插濾波器中之分 篁間隙之效應」’作者為jussi Vesma等，由Tampere University of Technology 出版 。 第四圖說明一示範性的内插器4〇 0，其能提供所需樣 本從44 MHz轉換至40 MHz，其係藉由透過内插器階段序列 内插。在序列内插器4 0 0中，一閥門延遲線4 0 1能裝載五個 樣本，一般來說，閥門延遲線4〇1能如同一FIF0(首進首Page 14 200421801 V. Description of the invention (9) The first interpolator can provide samples 1 one 0.1 sample interpolation compensation 501 'one second interpolator can provide samples 2 one 0.2 samples An interpolation compensation 502, a third interpolator will provide samples 3, one of the 0.3 samples = interpolation compensation 503, and the fourth is the same. Note that the longest delay month b of the received sample 9 is effectively received by the receiving sample 0 (second example) and the output sample 0 (also the second example). Therefore, the sampling can receive the sample 3 of the receiving sample 0 (effectively Sample 11) continued. According to a feature of the invention, selecting the appropriate coefficients for the valves in the interposer can produce the required compensation (i.e., 0 · 1-0 · 9). It is interesting that the interpolator with 10,1 interpolation compensation has the same valve as the interpolation phase with one of the interpolation compensation of 10.9, but its order is just the opposite, similar situation, 〇 2, 0 The interpolator for 3 and 0.4 interpolation compensation has the same valve as one of the interpolation compensation for 0.8, 0.7, and 0.6 interpolation, respectively, except that the ordering is exactly the opposite. Therefore, 'in one embodiment, five sets of interpolator coefficients can provide the required compensation (note that no compensation is required for any received samples). This reduction technique was discussed earlier in the article' and its title is "Quantize within Effect of Tiller Gap in Interpolation Filters "by jussi Vesma et al., Published by Tampere University of Technology. The fourth figure illustrates an exemplary interpolator 400, which can provide the required sample conversion from 44 MHz to 40 MHz by interpolation through a sequence of interpolator stages. In the sequence interpolator 400, a valve delay line 401 can load five samples. In general, the valve delay line 401 can be the same FIF0 (first in first
第15頁 200421801 五 出）裝置一樣的執行，其中每一樣本能透過N儲存裝置4〇2 定時（例如觸發器402A - 40 2E)，基於一所需信號雜訊比 (SNR)計算N之近似值係於由John Wiley & Sons公司於 1998年出版，Heinrich Meyr等所著之「數位通訊接收 器」第511 - 533頁中討論，注意N值能基於該實際的倍數器 係數使用及内插器階段之最小均方差（MMSE )做調整（皆在 下文討論），藉此最佳化該序列内插器4 〇 〇。 在閥門延遲線401之裝載之後，每一樣本（包儲存在在 儲存元件402E之輸出的樣本）係乘上404A - 404F其中之一 係數’其係於乘算網路4 〇 4之一閥門中，這些乘積接著使 用一總和區塊4 0 5加總，多工器網路4 0 3較佳地對於某些在 乘算網路404中具有適當係數的成對樣本提供最理想的彈 性，舉例來說，一乘算累積計算能將儲存裝置4 〇 2 B之樣本 與一第一係數組成一對，反之另一乘算累積計算能將同一 樣本與一第二係數組成一對，該第二係數係與該第一係數 不同。 在一實施例中，一個從1計算到1 0之計算器4 〇 6 (例如 一四位元計算器）能控制該多工器網路403之多工器，其中 母一計算選擇一預設係數（更詳細的細節於第六圖中解 釋），因此，序列内插器4 0 0能如同多重（亦即1 〇 )離散時間 慮波器運作’在一計數期間，序列内插器4 〇 〇之每一配置 係為一内插階段，當計數器4 0 6達到1 〇，其便能輸出一預Page 15 200421801 five-out) device, where each sample can pass through the N storage device at a 402 timing (for example, trigger 402A-40 2E), and the approximate value of N is calculated based on a desired signal-to-noise ratio (SNR). Discussed in "Digital Communication Receivers", pages 511-533, published by John Wiley & Sons in 1998, Heinrich Meyr et al. Note that the value of N can be based on the actual multiplier coefficients used and the interpolator stage. The minimum mean square error (MMSE) is adjusted (both discussed below) to optimize the sequence interpolator 400. After the valve delay line 401 is loaded, each sample (the sample stored in the output of the storage element 402E) is multiplied by one of the coefficients 404A-404F, which is included in a valve of the multiplication network 4 04 These products are then summed up using a sum block 405. The multiplexer network 403 preferably provides the best flexibility for some paired samples with appropriate coefficients in the multiplication network 404. For example For example, one multiplying cumulative calculation can pair a sample of storage device 402 B with a first coefficient, while another multiplying cumulative calculation can pair the same sample with a second coefficient, and the second The coefficient is different from the first coefficient. In an embodiment, a calculator 4 0 (for example, a four-bit calculator) that calculates from 1 to 10 can control the multiplexer of the multiplexer network 403, wherein the mother-one calculation selects a preset Coefficients (explained in more detail in Figure 6), so the sequence interpolator 4 0 0 can behave as a multiple (ie 10) discrete-time wave filter. 'During a count, the sequence interpolator 4 0. Each configuration of 〇 is an interpolation phase. When the counter 406 reaches 1 〇, it can output a preliminary
第16頁 200421801 五、發明說明（11) "" 設信號407，其係指示下一個產生自加總區塊4〇5之輸出樣 本（亦即第1 1個樣本）將不會被使用。 在一實施例中，多工器網路4 0 3及乘算網路4 〇 4能使用 I部分乘積來執行，舉例來說，不執行S X 17，其中s係為 一樣本’取而代之的是計算一部份乘積S + (S X 16)，一 部份乘積計算會比一單一乘算更有效率，因為S X 16乘積 (亦即在不同的内插階段）比S X 1 7 (舉例來說，請見表一） 更韦被使用’因此較佳地減少需要產生序列内插器4 〇 〇之 係數之該元件總數量，注意該整數值能藉由一二位元相移 表示’更具體地，<< η表示一 η位元左移，因此整數1能表 不為<< 0，整數2能表示為<< 1，整數4能表示為〈< 2，整 數8能表示為<< 3，整數16表示為<< 4等等。 第五圖說明一示範性的序列内插器5 〇 〇，其以一多工 部分乘積網路501取代了多工器網路4〇3及乘算網路4〇4， 多工部分乘積網路501包含五個閥門5〇1Α — 5〇1Ε。第上圖 說明一示範性的閥門501Ε，其能使用兩個多工器6〇1Α^ 6〇1Β =二加法器6〇2執行，在閥門5〇1£中，多工器“Μ 一 t ;其現打樣本5接收輸入，多工器601Α選擇一特定 冲數」），同樣地，多工器6〇1B選擇一特定的部 輸入（通常是PP1)，其係基於同一計齡，一 ^ „ 積 其能表示多重加法器，分別加上來 ^器602， 木自多工！§601B及601A之Page 16 200421801 V. Description of the invention (11) " " Set signal 407, which indicates that the next output sample (ie, the 11th sample) generated from the summing block 405 will not be used . In an embodiment, the multiplexer network 403 and the multiplication network 404 can be performed using a partial I product. For example, SX 17 is not performed, where s is the same sample. Instead, calculations are performed. Partial product S + (SX 16). Partial product calculations are more efficient than a single multiplication, because the SX 16 product (that is, at different interpolation stages) is better than SX 1 7 (for example, please (See Table 1.) More is used 'so it is better to reduce the total number of elements that need to generate the coefficient of the sequence interpolator 4 00, note that the integer value can be expressed by a two-bit phase shift' more specifically, < < η means a shift of n bits, so integer 1 can be expressed as < 0, integer 2 can be expressed as < 1, integer 4 can be expressed as << 2, and integer 8 can be expressed as Expressed as < < 3, integer 16 is expressed as < < 4 and so on. The fifth figure illustrates an exemplary sequence interpolator 500, which replaces the multiplexer network 403 and the multiplication network 404 with a multiplexed partial product network 501. The multiplexed partial product network The path 501 contains five valves 501A-501E. The figure above illustrates an exemplary valve 501E, which can be executed using two multiplexers 601A ^ 6〇1B = two adders 602. In the valve 501 £, the multiplexer "M 1t ; Its current sample 5 receives the input, and the multiplexer 601A selects a specific punch number "). Similarly, the multiplexer 601B selects a specific partial input (usually PP1), which is based on the same age, one ^ „Product can represent multiple adders, add ^, 602, Muzi multiplexing! §601B and 601A
200421801 五、發明說明C12) :斤二擇的部分乘積PP1和PP2。在一實施例中，加法器6〇2 ΓΓΛ執^可藉^合成玉具產生，像是⑽Psys公司 佳化該，$個合成工具使用一攜帶儲存技術以最 ^月匕° 數之ΐΐί=每一計ϊ之閥門5〇ιε之一實施例，亦即該計 ’及不範性的實施細節以產生該所需係數。200421801 V. Description of the invention C12): Partial product PP1 and PP2. In one embodiment, the adder 602 ΓΓΛ can be generated by ^ synthetic jade, such as ⑽Psys company to optimize it, $ synthesis tools using a carry storage technology to the maximum number of months ΐΐ = = each One embodiment of the valve 50m, that is, the implementation of the meter and irregularities to generate the required coefficient.
200421801 五、發明說明（13) 基於該所需係數值及精密度。 依據本發明之一特徵，係數值能被選擇以確保介於來 自加總區塊405之鄰接輸出樣本之間之線性（第四圖及第五 圖），更具體地說，鄰接樣本係有效地通過不同（亦即數學 上地相異）内插器，因為不同係數能用於每一計數之該序 列内插器之每一閥門。因為每一内插階段（亦即該具有所 選擇係數之序列内插器對於每一計數）在強度或是相位方 面具有明顯不同的頻率響應特徵，於該内插波形中之非線 性旎產生於輸出樣本之間，換句話說，每一内插階段之運 作會因某些量而變得不理想化。 ▲ 因此，依據本發明之一特徵，一總最小均方差（MMSE 能基於該WLAN裝置所需之已知信號雜訊比（SNR)而計算， 在此同時，每一雜訊來源之一雜訊貢獻，包含每一内插^ 丰又都冑b被決疋，藉此有效地設定每一内插階段之一誤差 「預算」，每一内插階段之該閥門係數接著能被選擇以^ 小化該誤差，其係來自一等化分佈之通頻之一完美内插 器。在此選擇期間，一MMSE計算典型地使用實部和虛部 值，能由每一内插階段執行，以確保其落在該特定容許度 之間，依此方法，不管介於鄰接輸出樣本之間非線性，於200421801 V. Description of the invention (13) Based on the required coefficient value and precision. According to a feature of the invention, the coefficient values can be selected to ensure linearity between adjacent output samples from the summing block 405 (Figures 4 and 5). More specifically, the adjacent samples are effectively By different (i.e., mathematically distinct) interpolators, because different coefficients can be used for each valve of the sequenced interpolator for each count. Because each interpolation stage (that is, the sequence interpolator with the selected coefficients has a distinct frequency response characteristic in terms of intensity or phase for each count), the non-linearity in the interpolation waveform is generated in Between the output samples, in other words, the operation of each interpolation stage can be suboptimal by some amount. ▲ Therefore, according to a feature of the present invention, a total minimum mean square error (MMSE) can be calculated based on a known signal-to-noise ratio (SNR) required by the WLAN device. At the same time, one noise from each noise source Contributions, including each interpolation ^ and 胄 b are determined, thereby effectively setting an error "budget" for each interpolation stage, and the valve coefficient of each interpolation stage can then be selected to be ^ small This error is a perfect interpolator from the pass frequency of the equalized distribution. During this selection, an MMSE calculation typically uses real and imaginary values, which can be performed at each interpolation stage to ensure It falls between the specified tolerances. In this way, regardless of the non-linearity between adjacent output samples,
該通頻内之該頻率範圍之該總誤差即可被確保在一給予的 容許渡之内。（注意拒頻並未被分析，因為這不是我們關 注的領域。）The total error of the frequency range in the pass frequency can be ensured within a given allowable crossing. (Note that rejection is not analyzed, as this is not our area of focus.)
第19頁 200421801 五、發明說明（14) 示範性碼，以MATLAB撰寫（一個常見的數學語言），用 以執行一序列内插器及該碼以最佳化該係數，其係被提供 用以作為說明目的。（注意此碼並未模擬基於内插器或結 構其他部分之部分乘積，然而，此碼對於該實施例來說是 達到位元精確的。）依據本發明之一特徵，使用虛擬反矩 陣的方式以找出MMSE解決方案可以最佳化該序列内插器之 該係數。Page 19, 200421801 V. Description of the invention (14) The exemplary code, written in MATLAB (a common mathematical language), is used to implement a sequence interpolator and the code to optimize the coefficient. It is provided for For illustrative purposes. (Note that this code does not simulate partial products based on interpolators or other parts of the structure, however, this code is bit-accurate for this embodiment.) According to one feature of the present invention, a virtual inverse matrix is used. To find out the MMSE solution can optimize the coefficient of the sequence interpolator.
% make—interp_vec.m % script used to generate MMSE interpolator coefficients °/o % Perforin MMSE filter creation via the following equations: % The following function， i.e. the filter frequency response, should be minimized:% make—interp_vec.m% script used to generate MMSE interpolator coefficients ° / o% Perforin MMSE filter creation via the following equations:% The following function, i.e. the filter frequency response, should be minimized:
% integral (-2 pi B:2 pi B) { (exp (j w Ts mu) - % sum (n=-Il : 12) {h[n] exp (-j w Ts η) })Λ2} % where: integral is the ideal response, w is the phase (2 f),% integral (-2 pi B: 2 pi B) {(exp (jw Ts mu)-% sum (n = -Il: 12) {h [n] exp (-jw Ts η))) Λ2}% where: integral is the ideal response, w is the phase (2 f),
TsTs
第20頁 200421801 五、發明說明（15)Page 20 200421801 V. Description of the invention (15)
Is the samp ling frequency, mu is the fractional delay (0.1, 0.2，etc. ), B is the bandwidth, and sum is the actual frequency response % This can be done by examining many w values wO, and creating an % over-defined matrix equation Xh = y, where:Is the samp ling frequency, mu is the fractional delay (0.1, 0.2, etc.), B is the bandwidth, and sum is the actual frequency response% This can be done by examining many w values wO, and creating an% over- defined matrix equation Xh = y, where:
% X is an MxN matrix of rotating exponent i a 1s for DFT computation of h% X is an MxN matrix of rotating exponent i a 1s for DFT computation of h
% h is the desired vector for a given mu % y is the desired frequency domain calue for a given wO % M is the number of frequency values to exmine % N is the number of taps in the filter % We can then compute the MMSE calue for h via: % h = pinv(X) * y N = 8; %Number of taps M = 1001; %Number of frequency points to check% h is the desired vector for a given mu% y is the desired frequency domain calue for a given wO% M is the number of frequency values to exmine% N is the number of taps in the filter% We can then compute the MMSE calue for h via:% h = pinv (X) * y N = 8;% Number of taps M = 1001;% Number of frequency points to check
第21頁 200421801 五、發明說明（16) (using largePage 21 200421801 V. Description of the Invention (16) (using large
Number of points is easier than computing with a continuous integral) rx = 0; if rx BW = 9/44; %Given single sided bandwidth / sampling rate mu^vec = [.1 .2 .3 .4 .5]; % Fractional sample to advance else BW = 9/40; %Given single sided bandwidth / sampling rate mu—vec = [1/11 2/11 3/11 4/11 5/11]; 0/〇 Fractional sample to advance end quant i ze = o; quant_b i ts = 7; for mu = mu_vecNumber of points is easier than computing with a continuous integral) rx = 0; if rx BW = 9/44;% Given single sided bandwidth / sampling rate mu ^ vec = [.1 .2 .3 .4 .5];% Fractional sample to advance else BW = 9/40;% Given single sided bandwidth / sampling rate mu—vec = [1/11 2/11 3/11 4/11 5/11]; 0 / 〇Fractional sample to advance end quant i ze = o; quant_b i ts = 7; for mu = mu_vec
Nvec = -N/2:N/2-l; % N is number of taps X = zeros(2氺M+l，N); for index=l:2*M+lNvec = -N / 2: N / 2-l;% N is number of taps X = zeros (2 氺 M + l, N); for index = l: 2 * M + l
第22頁 200421801 五、發明說明（17) % Create ideal vector wO = (index-Μ- 1V(M) * BW * 2 * pi; X(index， ：） = exp(-li * wO ·* Nvec); end %Use pseudo-inverse to find best MMSE interpolator y = exp(li * linspace (-BW，BW，2木M+l) * 2 * pi .* mu). ;Page 22 200421801 V. Description of the invention (17)% Create ideal vector wO = (index-M- 1V (M) * BW * 2 * pi; X (index, :) = exp (-li * wO · * Nvec) ; end% Use pseudo-inverse to find best MMSE interpolator y = exp (li * linspace (-BW, BW, 2 wood M + l) * 2 * pi. * mu).;
h = real(pinv(x)氺 y); fprintf(,Filter for mu = %6.4f\n’， mu); if quantize format short h = round(h 氺 2 Λ quant_bi ts) else format long h endh = real (pinv (x) 氺 y); fprintf (, Filter for mu =% 6.4f \ n ’, mu); if quantize format short h = round (h 氺 2 Λ quant_bi ts) else format long h end
end %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% Name : rx_i nterp.m %% Purpose: Receiver interpolator structure forend %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% Name: rx_i nterp.m %% Purpose : Receiver interpolator structure for
第23頁 200421801 五、發明說明（18) 802. llg %% Converts from 44 MHz to 40 MHz %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% function out = rx—interp(in，parms ); %Subst i tude when fixed point model ready use_fp_mode1 = 0 ; % Show figures of interpolation show_figures = 0 %¥ind ideal floating point taps (i.e. coefficients) if use_fp_mode 1 % Initialize filters fiItO = [ 0 0 0 0 1 0 0 0 ]; filtl = [-.00196 .01091 -.03599 .10792 .96819 06157 • 01481 …- · 0 0 2 4 0 ]; filt2 = [-.00376 .02118 -.07127 .22795 .90965 - · 10614 .02662 •••-•00439];Page 23 200421801 V. Description of the invention (18) 802.llg %% Converts from 44 MHz to 40 MHz %%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%% function out = rx—interp (in, parms);% Subst i tude when fixed point model ready use_fp_mode1 = 0;% Show figures of interpolation show_figures = 0% ¥ ind ideal floating point taps (ie coefficients) if use_fp_mode 1% Initialize filters fiItO = [0 0 0 0 1 0 0 0]; filtl = [-.00196 .01091 -.03599 .10792 .96819 06157 • 01481…-· 0 0 2 4 0 ]; filt2 = [-.00376 .02118 -.07127 .22795 .90965-· 10614 .02662 •••-• 00439];
200421801 五、發明說明（19) filt3 = [-.00526 .02990 -.10281 .35522 .82755 -·13381 .03480 ··· -.0 0582 ]; filt4 = [-.00630 .03622 -.12758 .48438 .72600 14545 .03908 •••-•00 663 ]; filt5 = [-.00768 .03946 -.14266 .60984 .60984 -·14266 .03946 …-· 00 678 ]; i η 1 = i η %¥i nd quantized floating point taps in integers (i · e· coefficients) else f i ItO = :[〇 0 0 0 128 0 〇 〇]; f i ltl = :[〇 1 -4 14 123 - 7 1 〇]； f i lt2 : :[0 2 - 8 29 115 -12 2 〇]； f i 113 = :[0 2 -12 46 105 -15 2 0]; f i lt4 : :[0 2 -15 61 92 -16 4 〇]； f i 115 = :[0 4 -16 76 76 -16 4 〇]；200421801 V. Description of the invention (19) filt3 = [-.00526 .02990 -.10281 .35522 .82755-· 13381 .03480 ··· -.0 0582]; filt4 = [-.00630 .03622 -.12758 .48438 .72600 14545 .03908 •••-• 00 663]; filt5 = [-.00768 .03946 -.14266 .60984 .60984-· 14266 .03946…-· 00 678]; i η 1 = i η% ¥ i nd quantized floating point taps in integers (i · e · coefficients) else fi ItO =: [〇0 0 0 128 0 〇〇]; fi ltl =: [〇1 -4 14 123-7 1 〇]; fi lt2: : [0 2-8 29 115 -12 2 〇]; fi 113 =: [0 2 -12 46 105 -15 2 0]; fi lt4:: [0 2 -15 61 92 -16 4 〇]; fi 115 =: [0 4 -16 76 76 -16 4 〇];
第25頁 200421801 五、發明說明（20) i η 1 = i η/8 ; end %Make 0.6 - 0.9 delay interpolators filt6=fliplr (filt4); filt7=fliplr (filt3); filt8=fliplr (filt2); filt9=fliplr (filtl); % Filter input with all interpolators out0=conv (ini, filtO); out 1=conv (ini, filtl); out2=conv (inl，filt2); out3=conv (inl，filt3); out4=conv (inl，filt4); out5=conv (ini, filt5); out6=conv (inl，filt6); ou17 = conv (inl，filt7); out8=conv (inl，filt8); out9=conv (inl，filt9); %Choose correct filtered output for ideal choice of mu (i.e. instead of running a different interpolator atPage 25 200421801 V. Description of the invention (20) i η 1 = i η / 8; end% Make 0.6-0.9 delay interpolators filt6 = fliplr (filt4); filt7 = fliplr (filt3); filt8 = fliplr (filt2); filt9 = fliplr (filtl);% Filter input with all interpolators out0 = conv (ini, filtO); out 1 = conv (ini, filtl); out2 = conv (inl, filt2); out3 = conv (inl, filt3); out4 = conv (inl, filt4); out5 = conv (ini, filt5); out6 = conv (inl, filt6); ou17 = conv (inl, filt7); out8 = conv (inl, filt8); out9 = conv (inl, filt9);% Choose correct filtered output for ideal choice of mu (ie instead of running a different interpolator at
第26頁 200421801 五、發明說明（21) each sampling point, input is run through all interpolators to determine best interpolator) if (〇) 〇ut=[]; for i = 0:f1oor((1 ength(in) -9) /11) ill = I* 11 out 二[out … out0(ill+6)… outl(ill+7)… out2(ill+8)… out3(ill+9)… out4(ill+10)… out5(ill+ll)… out6(ill+12)… out7(ill+13)… out8(ill+14)… out9(ill + 15)]; end else % to remove the for-loop, WJC, 10/17/02 Ns = f 1 oor((1 ength(in) -9) /11); o u t 一 t m p = [ o u 10 ( 6 : 11 : 11 * N s + 6 );… outl(7:ll:ll*Ns+7);…Page 26 200421801 V. Description of the invention (21) each sampling point, input is run through all interpolators to determine best interpolator) if (〇) 〇ut = []; for i = 0: f1oor ((1 ength (in)- 9) / 11) ill = I * 11 out two [out… out0 (ill + 6)… outl (ill + 7)… out2 (ill + 8)… out3 (ill + 9)… out4 (ill + 10)… out5 (ill + ll)… out6 (ill + 12)… out7 (ill + 13)… out8 (ill + 14)… out9 (ill + 15)]; end else% to remove the for-loop, WJC, 10 / 17/02 Ns = f 1 oor ((1 ength (in) -9) / 11); out a tmp = [ou 10 (6: 11: 11 * N s + 6); ... outl (7: ll: ll * Ns + 7); ...
第27頁 200421801 五、發明說明（22) out2(8:11:1l*Ns+8);… out 3(9:11:11*Ns + 9 );… out4(10:ll:ll*Ns+10);… out5(ll:ll:ll*Ns+ll);… out6(12:ll:ll*Ns+12);… out7(13:ll:ll*Ns+13);… out8(14:ll:ll*Ns+14);… out9(15:ll:ll*Ns+15);… out = reshape(out—tmp，l，prod(size(out—tmp))); end %Check computations if (0) % just test % check if both implementations are same or not if isequal (out,out2) fprintf(l，’two implementations in rx_interp are same\n’ ） else error(’ two implementations are not equivalent in rx_i nterp\nJ ) endPage 27 200421801 V. Description of the invention (22) out2 (8: 11: 1l * Ns + 8); ... out 3 (9: 11: 11 * Ns + 9); ... out4 (10: ll: ll * Ns + 10); ... out5 (ll: ll: ll * Ns + ll); ... out6 (12: ll: ll * Ns + 12); ... out7 (13: ll: ll * Ns + 13); ... out8 (14: ll: ll * Ns + 14); ... out9 (15: ll: ll * Ns + 15); ... out = reshape (out—tmp, l, prod (size (out—tmp))); end% Check computations if (0)% just test% check if both implementations are same or not if isequal (out, out2) fprintf (l, 'two implementations in rx_interp are same \ n') else error ('two implementations are not equivalent in rx_i nterp \ nJ) end
第28頁 200421801 五、發明說明（23) end % Quantize out to ADC output values if use_fp_mode1 out = saturation(round(out), 256*8); else out = saturation(floor(out/16+0.5+0.5i), 256* 8 ) ; floor dropsPage 28 200421801 V. Description of the invention (23) end% Quantize out to ADC output values if use_fp_mode1 out = saturation (round (out), 256 * 8); else out = saturation (floor (out / 16 + 0.5 + 0.5i ), 256 * 8); floor drops
LSBs, saturate out MSBsLSBs, saturate out MSBs
End %Pr i nt output if show」i gur es f i gure(1) c 1 f hold onEnd% Pr i nt output if show 」i gur es f i gure (1) c 1 f hold on
psd(i n,2048, 44e6) psd(out，2048, 40e6) figure(2) c 1 f plot(real(out)) hold onpsd (i n, 2048, 44e6) psd (out, 2048, 40e6) figure (2) c 1 f plot (real (out)) hold on
第29頁 200421801 五、發明說明（24) plot(real(resample(in(7:end)， 10， 11))， ’r’） f i gure(4 ) ; psd(resamp1e(in， 10， 11，10)) end %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% Name : tx_i nterp.m %% Purpose: Transmitter interpolator structure for I 802. llg %% Converts from 40 MHz to 44 MHz %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% function out = tx_interp(in); % Substitute when fixed point model ready use_fp_mode1 二 1 ; % Show figures of interpolation show」i gures = 0 ; %¥i nd ideal floating point taps (i. e. coefficients) if use_fp_mode1 ^Initialize filters f i 110 = [ 0 0 0 0 1 0 0 0 ];Page 29 200421801 V. Explanation of the invention (24) plot (real (resample (in (7: end), 10, 11)), 'r') fi gure (4); psd (resamp1e (in, 10, 11, 10)) end %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% Name: tx_i nterp.m %% Purpose: Transmitter interpolator structure for I 802. llg %% Converts from 40 MHz to 44 MHz %%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%% function out = tx_interp (in);% Substitute when fixed point model ready use_fp_mode1 2 1;% Show figures of interpolation show 」i gures = 0;% ¥ i nd ideal floating point taps (ie coefficients) if use_fp_mode1 ^ Initialize filters fi 110 = [0 0 0 0 1 0 0 0];
第30頁 200421801 五、發明說明（25) filtl= [ -0.00146829481856 0.00806014446191 -0·03171766834449 0·09737897194633 0. 97115288240108 -0.05504875193986 0.01242649782772 -0. 00 1 8 1 765426884 ]; filt2 = [ -0.00284152607157 0.01769213363283 -0.006304281016311 0.20494388732203 0. 92030529169635 -0.09636727670195 0.02259974834117 -0. 0 0335358 1 64280 ]; filt3 = [ -0.00402087196301 0.02527332694133 -0.9179993554821 0.31914295582077 0.84976766025265 -0.12401486890575 0.03008823533490 -0. 0 04525 255 0 0 3 1 2 ]; filt4 = [ -0.00491753302646 0.03121968778787 -0.11578586197789 0.43609064272421 0. 76246973569618 -0.13856083366959 0.03465655747194 -0. 0 0527850 5 90 1 72 ];Page 30 200421801 V. Description of the invention (25) . 92030529169635 -0.09636727670195 0.02259974834117 -0. 0 0335358 1 64280]; filt3 = [-0.00402087196301 0.02527332694133 -0.9179993554821 0.31914295582077 0.84976766025265 -0.12401486890575 0.03008823533490 -0. 0 04525 255 0 0 3302 1 0 2 1907 = 1960 76246973569618 -0.13856083366959 0.03465655747194 -0. 0 0527850 5 90 1 72];
200421801 五、發明說明（26) filt5 = [ -0.00545791489469 0.03501817630485 -0· 1 3285 98944 8990 0· 55 1 7 0390483427 0.66184543876714 -0.14103409448039 0.03625756165818 0.00558825677733]; %Find quantized floating point taps in intgers (i · e· coefficients)200421801 V. Description of the invention (26) filt5 = [-0.00545791489469 0.03501817630485 -0 · 1 3285 98944 8990 0 · 55 1 7 0390483427 0.66184543876714 -0.14103409448039 0.03625756165818 0.00558825677733];% Find quantized floating point taps in intgers (i · e · coefficients)
fi ItO = [ 0 0 0 0 1 28 0 0 0 ]; fi ltl = [ 0 1 -4 1 2 1 24 -7 2 0 ]; filt2 = [0 2 -8 26 118 -12 2 0]; fi lt3 = [ 0 2 - 1 2 4 1 1 0 9 -26 4 0 ]; fi lt4 = [ 0 4 - 1 5 56 97 - 1 8 4 0 ]; fi lt5 = [ 0 4 - 1 7 70 85 - 1 8 4 0 ];fi ItO = [0 0 0 0 1 28 0 0 0]; fi ltl = [0 1 -4 1 2 1 24 -7 2 0]; filt2 = [0 2 -8 26 118 -12 2 0]; fi lt3 = [0 2-1 2 4 1 1 0 9 -26 4 0]; fi lt4 = [0 4-1 5 56 97-1 8 4 0]; fi lt5 = [0 4-1 7 70 85-1 8 4 0];
filt 6=fliplr(filt5); filt 7=fliplr(filt4); filt 8=f1iplr(filt3)； filt 9=fliplr(filt2); filt 10=fliplr(filtl)； out0 = conv(in, f i 11 0 ) out 1=conv(in, f i 111) out2 = conv(in, f i 112 )filt 6 = fliplr (filt5); filt 7 = fliplr (filt4); filt 8 = f1iplr (filt3); filt 9 = fliplr (filt2); filt 10 = fliplr (filtl); out0 = conv (in, fi 11 0) out 1 = conv (in, fi 111) out2 = conv (in, fi 112)
第32頁 200421801 五、發明說明（27) out 3 = conv(in, fi lt3); out 4 = conv(i n, fi lt4); out 5 = conv(i n, f i 115 ); out 6 二 conv(i n, fi lt6); ou17 = conv(i n, fi lt7); out 8 = conv(i n, fi lt8); out 9 = conv(in, fi lt9); outlO = conv(i n, fi ltlO)Page 32 200421801 V. Description of the invention (27) out 3 = conv (in, fi lt3); out 4 = conv (in, fi lt4); out 5 = conv (in, fi 115); out 6 two conv (in , fi lt6); ou17 = conv (in, fi lt7); out 8 = conv (in, fi lt8); out 9 = conv (in, fi lt9); outlO = conv (in, fi ltlO)
%Choose correct filtered output for ideal choice of mu (i.e. instead of running a different interpolator at each sampling point, input is run through all interpolators to determine best interpolator) if (〇) 〇ut=[];% Choose correct filtered output for ideal choice of mu (i.e. instead of running a different interpolator at each sampling point, input is run through all interpolators to determine best interpolator) if (〇) 〇ut = [];
for i-0:floor(length(in)/10) -l+floor(mod(length(in), 10) /7); ill = i*10; out = [out … ([outO (ill+5)… outlO (ill+5)…for i-0: floor (length (in) / 10) -l + floor (mod (length (in), 10) / 7); ill = i * 10; out = (out… ([outO (ill + 5 ) ... outlO (ill + 5) ...
第33頁 200421801 五、發明說明（28) out 9 (i 11 + 6 )… out8 (ill+7)… out7 (ill+8)… out6 (ill+9)… out5 (ill + 10)… out4 (ill+11)… out3 (ill+12)… out2 (ill+13)… outl (ill+14)])]; end else % to remove the for-loopPage 33 200421801 V. Description of the invention (28) out 9 (i 11 + 6) ... out8 (ill + 7) ... out7 (ill + 8) ... out6 (ill + 9) ... out5 (ill + 10) ... out4 ( ill + 11)… out3 (ill + 12)… out2 (ill + 13)… outl (ill + 14)])]; end else% to remove the for-loop
Ns = f loor(length(in) /10)-l+floor(mod(length(in), 10) /7); ill = Ns*10; % for later use out一tmp = [outO (5:10:10*Ns+5); outlO (5:10:10*Ns+5);… out9 (6:10:10*Ns+6);… o u 18 ( 7 : 1 0 : 1 0 * N s + 7 );… out7 (8:10:10*Ns+8);… out6 (9:10:10*Ns+9);… out5 (10:10:10*Ns+10);… out4(ll:10:10*Ns+ll);— out3 (12: 10: 10*Ns+12);… out2 (13:10:10*Ns+13);… 200421801 五、發明說明（29) outl (14:10: 10*Ns+14)]; out = reshape (out^tmp, 1，prod (sizeout — tmp))); end %Check computations if (0) % just test % check if both implementations are same or not if isequal (out,out 2) fprintf(l，’two implementations in tx—interp are same\n’ ） else error(J two implementations are not equivalent in tx_i nterp\n’） end end % A d j u s t bit accuracy for shutdown switch mod (1 ength(i n), 10) case 1 out = [out out0(ill + 15) ou11 0(i11 + 1 5 ) out9Ns = f loor (length (in) / 10) -l + floor (mod (length (in), 10) / 7); ill = Ns * 10;% for later use out one tmp = (outO (5:10 : 10 * Ns + 5); outlO (5: 10: 10 * Ns + 5); ... out9 (6: 10: 10 * Ns + 6); ... ou 18 (7: 1 0: 1 0 * N s + 7); ... out7 (8: 10: 10 * Ns + 8); ... out6 (9: 10: 10 * Ns + 9); ... out5 (10: 10: 10 * Ns + 10); ... out4 (ll: 10: 10 * Ns + ll); — out3 (12: 10: 10 * Ns + 12); ... out2 (13: 10: 10 * Ns + 13); ... 200421801 V. Description of the invention (29) outl (14: 10: 10 * Ns + 14)]; out = reshape (out ^ tmp, 1, prod (sizeout — tmp))); end% Check computations if (0)% just test% check if both implementations are same or not if isequal (out, out 2) fprintf (l, 'two implementations in tx—interp are same \ n') else error (J two implementations are not equivalent in tx_i nterp \ n ') end end% A djust bit accuracy for shutdown switch mod (1 ength (in), 10) case 1 out = (out out0 (ill + 15) ou11 0 (i11 + 1 5) out9
第35頁 200421801 五、發明說明（30) (ill+16) out8(ill + 17) out7(ill + 18)]; case 2 out = [out out0(ill + 15) ou110(i 1 1 + 1 5 ) out 9 (ill+16) out8(ill + 17) out7(ill + 18) ou16(i 11 + 1 9 )]; case 3 out = [out out0(ill + 15) ou110(i11 + 1 5 ) out9 (ill+16)Page 35 200421801 V. Description of the invention (30) (ill + 16) out8 (ill + 17) out7 (ill + 18)]; case 2 out = [out out0 (ill + 15) ou110 (i 1 1 + 1 5 ) out 9 (ill + 16) out8 (ill + 17) out7 (ill + 18) ou16 (i 11 + 1 9)]; case 3 out = [out out0 (ill + 15) ou110 (i11 + 1 5) out9 (ill + 16)
out8(ill+17) out7(ill+18) out6(ill+19) out5(ill+20)]; case 4 out = [out out0(ill + 15) ou110(i11 + 1 5 ) out9 (ill+16) out8(ill+17) out7(ill+18) out6(ill+19) out5(ill+20) out4(ill+21)]; case 5out8 (ill + 17) out7 (ill + 18) out6 (ill + 19) out5 (ill + 20)]; case 4 out = [out out0 (ill + 15) ou110 (i11 + 1 5) out9 (ill + 16 ) out8 (ill + 17) out7 (ill + 18) out6 (ill + 19) out5 (ill + 20) out4 (ill + 21)]; case 5
out = [out out0(ill + 15) ou110(i 1 1 + 1 5 ) out9 (ill+16) out8(ill+17) out7(ill+18) out6(ill+19) out5(ill+20) out4(ill + 21) out3(ill + 22)]; case 6out = [out out0 (ill + 15) ou110 (i 1 1 + 1 5) out9 (ill + 16) out8 (ill + 17) out7 (ill + 18) out6 (ill + 19) out5 (ill + 20) out4 (ill + 21) out3 (ill + 22)]; case 6
第36頁 200421801 五、發明說明（31) out = [out out0(ill+15) out10(i11+15) out9 (ill+16) out8(ill+17) out7(ill+18) out6(ill+19) 〇ut5(ill+20) out4(ill+21) out3(ill+22) out2(i11+23)]; case 7 out = [out out0(ill + 15) out 10(i11 + 15) out9 (ill+16)Page 36 200421801 V. Explanation of the invention (31) out = [out out0 (ill + 15) out10 (i11 + 15) out9 (ill + 16) out8 (ill + 17) out7 (ill + 18) out6 (ill + 19 ) 〇ut5 (ill + 20) out4 (ill + 21) out3 (ill + 22) out2 (i11 + 23)]; case 7 out = [out out0 (ill + 15) out 10 (i11 + 15) out9 (ill +16)
out8(ill+17) out7(ill+18) out6(ill+19) out5(ill+20) out4(ill+21) out3(ill+22) out2(ill+23) outl(ill+24)]; case 9 out = [out out0(i11+15) out10(i11+15) out9 (ill+16) out8(ill+17)]; case 0out8 (ill + 17) out7 (ill + 18) out6 (ill + 19) out5 (ill + 20) out4 (ill + 21) out3 (ill + 22) out2 (ill + 23) outl (ill + 24)]; case 9 out = [out out0 (i11 + 15) out10 (i11 + 15) out9 (ill + 16) out8 (ill + 17)]; case 0
out = [out out0(ill+15) out10(i11+15) out9(ill+ 16)]; end end %0uant i z e out to ADC output valuesout = [out out0 (ill + 15) out10 (i11 + 15) out9 (ill + 16)]; end end% 0uant i z e out to ADC output values
第37頁 200421801 五、發明說明（32) out = saturation(fl〇〇r(out/128+0.5+0.5i)， 256* 8); %Pr i nt output if show」i gur es f i gure(1) c 1 f hold on psd(in,2048,44e6) psd(out,2048,40e6) f i gure(2) elf plot(real(out)) hold on plot(real(resample(in(7:end)，11，i〇))，，r，） figure(4); psd(resample(in，11，l〇，η)) end 雖然實施例已經在此參照伴隨的圖式做詳細的說明， 必須瞭解的是發明並未受限於這些精確的實施例，其並 打异詳盡說明或是限制本發明於所揭示之精確的形式 '，就 其本身而論，許多修改和變化對於熟習此技藝人士都是顯Page 37 200421801 V. Description of the invention (32) out = saturation (fl〇〇r (out / 128 + 0.5 + 0.5i), 256 * 8);% Pr i nt output if show ”i gur es fi gure (1 ) c 1 f hold on psd (in, 2048,44e6) psd (out, 2048,40e6) fi gure (2) elf plot (real (out)) hold on plot (real (resample (in (7: end), 11, i〇)) ,, r,) figure (4); psd (resample (in, 11, 10, η)) end Although the embodiment has been described in detail with reference to the accompanying drawings, it must be understood It is to be understood that the invention is not limited to these precise embodiments, and does not specifically explain or limit the invention to the precise forms disclosed. 'As such, many modifications and changes will be apparent to those skilled in the art. Show
第38頁 200421801Page 38 200421801
舉例來說，該序列内插器能用於一8〇2· Ug裝置之一 接收器和一發送器中。第七A圖說明一簡單的接^器7〇〇， 其能包含一序列内插器。在接收器7〇〇中，一帶通濾波器 702從一天線701接收該輸入信號，且輸出一預設頻率之頻 帶（同持排除那些高於或低於預設頻帶之頻率），一可變的 RF放大器704能提供一初始放大給該頻率之預設頻帶，一 混合器7 0 6轉換那些放大的信號成為中間頻率（I f )信號， 其係接著由一 IF放大器708放大，在此同時，混合器709及 低通濾波器7 1 0 (包含I和Q分支）能於所需通道中產生信號 (稱為基頻信號），放大器712接著放大這些基頻信號，於 此同時’類比數位轉換器71 4 (提供給低通濾波器71 〇之I及 Q分支）轉換該放大的基頻信號成為數位信號，其可由一處 理區塊71 6分析，該處理區塊71 6包含一序列内插器（參照 第七B圖之說明）。 一旋轉裝置720接收處理區塊716之輸出，且如果需要 的話，提供一頻率補償校正，增益控制電路7丨8偵測強度 以調整該RF放大器702、IF放大器708及BB放大器712之增 益’一信號定時電路722，其亦接收該處理區塊716及旋轉 裝置7 2 0之輸出，決定在一實際符號離開期間之間隙，而 不是一保護間隙，且提供一定時輸出至一FFT 724。依此 方法，FFT 724能即時被限制出閘以接收該接收信號資For example, the sequence interpolator can be used in a receiver and a transmitter of a 802. Ug device. The seventh diagram A illustrates a simple connector 700, which can include a sequence of interpolators. In the receiver 700, a band-pass filter 702 receives the input signal from an antenna 701, and outputs a frequency band of a preset frequency (same as excluding those frequencies above or below the preset frequency band), a variable The RF amplifier 704 can provide an initial amplification to a preset frequency band of that frequency. A mixer 706 converts those amplified signals into intermediate frequency (I f) signals, which are then amplified by an IF amplifier 708, at the same time , The mixer 709 and the low-pass filter 7 1 0 (including the I and Q branches) can generate signals (called fundamental frequency signals) in the desired channel, and the amplifier 712 then amplifies these fundamental frequency signals, and at the same time 'analog digital A converter 71 4 (provided to the I and Q branches of the low-pass filter 71 〇) converts the amplified fundamental frequency signal into a digital signal, which can be analyzed by a processing block 71 6 which includes a sequence Plug (refer to the description of Figure 7B). A rotary device 720 receives the output of the processing block 716, and if necessary, provides a frequency compensation correction, and the gain control circuit 7 and 8 detect the intensity to adjust the gain of the RF amplifier 702, IF amplifier 708, and BB amplifier 712. The signal timing circuit 722, which also receives the output of the processing block 716 and the rotating device 7 2 0, determines a gap during an actual symbol leaving period, instead of a guard gap, and provides a certain time output to an FFT 724. In this way, the FFT 724 can be restricted from starting immediately to receive the received signal.
第39頁 200421801 五、發明說明 料，而不是由介面引起的雜訊，其係在一保護間隙期間離 開。注意該FFT 724之限制出閘也基於該計數被用來摒棄/ 附加輸出樣本（請見第六圖），FFT 724提供其輸出至一通 道預估/引導相追蹤電路728及一通道校正電路726。 通道預估/引導相追蹤電路728能於該長訓練符號序列 期間獲得一通道預估，.且提供該通道預估給通道校正電路 726，通道杈正電路726接著能使用該通道預估以補償剩餘 封包之決定的通道特性，而且，如果包含在内，一引導相 追蹤器將基於由追蹤引導狀態獲得之通道資訊來調整該通 道預估，其係在該剩餘封包傳輸期間。該通道校正過之信 號接著提供給一解映像/交錯電路73〇及一FEC解 (立典型地為一 Viterbi解碼器）用以以一習知方式解碼。（注 意FFT 724典型地係需要用於0FDM信號之處理，然而，本 發明之其他實施例也能包含其他裝置用以提供這些處理功 能。) 一 第七B圖以更多細節說明處理區塊716，對於具環境定 址之内文來說，ADCs 714和FFT 72 4係為已知，於處理區 ,716中，一多工器748接收來自一根餘弦率（RRC) nR濾 ，，740、一渦輪信號線742、一有限脈衝響應（fir丨）濾 :裔744及一内插器746之輸入，多工器748能藉由產生自 ，擇式區塊752之輸出控制，其基於不同調變相關器之 /刀析選擇最近似的調變。Page 39 200421801 V. Explanation of the invention, not the noise caused by the interface, is separated during a protection gap. Note that the limit trip of the FFT 724 is also used to discard / add output samples based on the count (see Figure 6). The FFT 724 provides its output to a channel estimation / lead phase tracking circuit 728 and a channel correction circuit 726. . The channel estimation / guide phase tracking circuit 728 can obtain a channel estimation during the long training symbol sequence, and provide the channel estimation to the channel correction circuit 726, and the channel branching circuit 726 can then use the channel estimation to compensate The channel characteristics of the remaining packets are determined, and if included, a lead phase tracker will adjust the channel estimate based on the channel information obtained by tracking the lead status during the remaining packet transmission. The channel-corrected signal is then provided to a demapping / interleaving circuit 73 and a FEC solution (typically a Viterbi decoder) for decoding in a conventional manner. (Note that FFT 724 is typically required for processing OFFDM signals. However, other embodiments of the present invention can also include other devices to provide these processing functions.) A seventh B diagram illustrates processing block 716 in more detail. For the context of environmental addressing, ADCs 714 and FFT 72 4 are known. In the processing area, 716, a multiplexer 748 receives from a cosine rate (RRC) nR filter, 740, a Turbine signal line 742, a finite impulse response (fir 丨) filter: the input of the 744 and an interpolator 746, the multiplexer 748 can be controlled by the output generated from the optional block 752, which is based on different modulations The correlator / analysis selects the closest modulation.
200421801 五、發明說明（35) •濾波器740之使用係當一CCK調變形式被識別時，該接 收貝料率係被識別為44 MHz ’且所需資料率係被識別為2 2 MHz，如果採用了，濾波器740確保其後的信號係正確地由 44 MHz轉換成所需的22 MHz ’且接著提供給一CCK解碼器 區塊741(注意如果一CCk信號係於選擇中被識別，貝彳CCK解 碼器區塊741係被啟動，否則在封包持續期間都是關閉 的），渦輪、號線7 4 2能被選擇（藉由來自一渦輪模式暫存 器743之一信號），其係當一0FDM調變模式被識別，且該資 料接收和所需皆為80 MHz時（亦即標準8〇2 Ua信號的兩倍 快速度），濾波器744能被選擇，其係當一〇FDM調變模式被 識別’且該接收資料率係識別為8〇 MHz，而該所需資料率 被識別為40 MHz ’内插器746能被選擇，其係當一ofdm調 變模式被識別，且該接收資料率係識別為44，而該所需資 料率被識別為40 MHz，内插器60 3能使用舉例來說第四、 五及/或六圖之序列内插器配置執行。 由多工器748所選擇之該處理信號接著能提供給旋轉 裝置720 ’旋轉裝置720能提供其輸出給!?!^ 724，其係與 在接收器700中之其他元件一起（如第七a圖所示），運作用 以精確地重建該接收信號。 第八圖說明一簡化發送器8〇〇，其包含一序列内插200421801 V. Description of the invention (35) • The use of filter 740 is that when a CCK modulation form is identified, the received data rate is identified as 44 MHz and the required data rate is identified as 2 2 MHz. Used, the filter 740 ensures that the subsequent signal is correctly converted from 44 MHz to the required 22 MHz 'and is then provided to a CCK decoder block 741 (note that if a CCk signal is identified in the selection, the彳 The CCK decoder block 741 is activated, otherwise it will be closed during the duration of the packet). The turbo and line 7 4 2 can be selected (by a signal from a turbo mode register 743). When a 0FDM modulation mode is identified, and the data is received and required at 80 MHz (that is, twice as fast as a standard 802 Ua signal), the filter 744 can be selected, which is regarded as a 10FDM 'Modulation mode is identified' and the received data rate is identified as 80 MHz, and the required data rate is identified as 40 MHz 'Interpolator 746 can be selected, which is when an ofdm modulation mode is identified, and The received data rate is identified as 44 and the required data rate is identified 40 MHz, the interpolator 603 can be for example the fourth, fifth and / or the sequence of FIG six interpolator configured to perform the use. The processed signal selected by the multiplexer 748 can then be provided to the rotating device 720 'the rotating device 720 can provide its output to!?! ^ 724, which is together with other components in the receiver 700 (such as the seventh a (Shown in the figure), which operates to accurately reconstruct the received signal. The eighth figure illustrates a simplified transmitter 800, which includes a sequence of interpolations
200421801 五、發明說明（36) 接收資料以便被發送。（注意IFFT典型地係需要用以⑽ 信號之處理，然而，本發明之其他實施例也能包含其他 置用以提供該處理功能）。舉例來說，這些資料能以4 〇 i MHz提供’序列内插器8〇2能將取樣率由4〇 MHz增加至44 MHz ’其係藉由實質上反轉上述的轉換程序，_多工界⑽ 能決定以40 MHz或以44 MHz速率之資料是否被選擇用°°以 輸。在一實施例中，如果傳輸係於一8〇2· u g環境中 行，則該資料會被選擇以44 MHz速率傳輸，否則兄該 會被選擇以40 MHz速率傳輸。於此同時，一第一 ^嗆= 器，亦即Tx FIR1 804，於該所選擇之資料上執行一2 = ^ 取樣，藉此有效地雙倍增由多工器8〇3所選擇之資丁 脈率。依類似的方法，一第二傳輸濾波器，亦即τχ fir Λ該/斤選擇之資料上執行另一個2上行取樣，藉此四 倍增加由多工器803所選擇之資料的時脈率。因此，如 多工器803選擇資料為44 MHz，則一多工器8〇6會以m果 ==»’接收資料，相反地，如果該多工器803選擇資 S t香則該多卫器806會以160 MHz或80 MHz接收資、 以8。02 1: a?〗中’一WLM裝置能於一渦輪模式(有效地 二!^ Λ 兩倍速率），在本例中，1FFT 801謂 二二且，器803選擇該非内插輸入(亦即該資料 夕工器806選擇以160 MHz之TxFiri 804之 雙倍輸出，依此方法，爷用以叩⑽产咕 αι eu4之 統較佳地能使用一單一 MATLAB碼能用以計算發送哭8〇〇^^而日，脈率，上述 T斤毛送器800之係數，且提供一結構獨 第42頁 1 200421801 五、發明說明（37) 立執行方式之模型。200421801 V. Description of the Invention (36) Receive the data to be sent. (Note that IFFT is typically required to process the signal, however, other embodiments of the present invention can also include other means to provide this processing function). For example, these data can be provided at 40 MHz. 'Sequence interpolator 802 can increase the sampling rate from 40 MHz to 44 MHz.' This is achieved by essentially inverting the conversion process described above. The industry can determine whether data at 40 MHz or 44 MHz is selected for input. In one embodiment, if the transmission is performed in a 802.ug environment, the data will be selected to be transmitted at a rate of 44 MHz, otherwise the brother will be selected to be transmitted at a rate of 40 MHz. At the same time, a first ^ 呛 = device, that is, Tx FIR1 804, performs a 2 = ^ sampling on the selected data, thereby effectively doubling the data selected by the multiplexer 803. Pulse rate. In a similar manner, a second transmission filter, that is, another 2 up-sampling is performed on the data selected by τχ fir Λ, which increases the clock rate of the data selected by the multiplexer 803 by four times. Therefore, if the data selected by the multiplexer 803 is 44 MHz, a multiplexer 806 will receive the data with m result == »'. Conversely, if the multiplexer 803 selects a data source, the multi-processor The receiver 806 will receive data at 160 MHz or 80 MHz. At 8.02 1: a ?, 'a WLM device can be used in one turbo mode (effectively two! ^ Λ twice the rate). In this example, 1FFT 801 In other words, the device 803 selects the non-interpolated input (that is, the data device 806 selects a double output at 160 MHz TxFiri 804. According to this method, the system used to produce αι eu4 is better. The ground can use a single MATLAB code, which can be used to calculate the transmission time, pulse rate, and coefficient of the above-mentioned T-hair feeder 800, and provide a structure alone. Page 42 1 200421801 V. Description of the invention (37 ) Models of execution methods.
At 一種收發器，其提供於一WLAN裝置中接收和發送的功 能，亦能包含一序列内插器，該收發器能包含一接收器區 塊及一發送器區塊（舉例來說，第七A圖所示之接收器1^ 7^1’一以主及第八圖所示之發送器8〇〇)，該接收器區塊能以 夕伽二脈率接收系統輸人信號，且提供輸出信號至-或 多個於第二時脈率夕麻1^ t b王 ^ 接此i V, 發込器之數位元件，該發送器區塊能 =數位元件於該第二時脈率之= 接收器區塊及該發送琴ί統輸出，重要的是，該 _轉換該第-時脈;之=列 注意儘管該8 0 2 1 1 a壬班泣人Γ 該8〇2.Π g環境於2 4 Gh/兄於^.0 GHz頻寬中運作，而At A transceiver, which provides the function of receiving and transmitting in a WLAN device, can also include a serial interpolator, the transceiver can include a receiver block and a transmitter block (for example, the seventh The receiver 1 ^ 7 ^ 1 'shown in Figure A is the main and the transmitter shown in Figure 8 is 800). The receiver block can receive the input signal of the system at two pulse rates, and provide Output signal to-or more than the second clock rate at night 1 ^ tb King ^ Connect this i V, the digital component of the transmitter, the transmitter block can = the digital component at the second clock rate = The receiver block and the output of the sender are important. The important thing is that the _ transforms the -clock; the = column. Note that although the 8 0 2 1 1 a Operates in 2 4 Gh / brother than ^ .0 GHz bandwidth, and
封包實質上係等同於一8 ^寬中運作，一802· 11 a 0FDM 合頻寬時，這些封包實· 0FDM封包，因此，當混 I買上還是相同的。 重要的是，儘管關於80 序列内插器同樣可應用於· U S WLAN裝置之描述，該 一第一時脈率轉換成一-何系統，其係對複數個樣本從 率除以該第二時脈率係:時脈率有利，其中該第一時脈 範圍打算藉由下列的申有理數，因此，本發明之保護 甲％專利範圍及其裝備定義。 200421801 圖式簡單說明 第一圖所示為一習知非整數之分量速率内插器。 第二圖所示為一波形，其十某些樣本係被接收，雖然其他 樣本必須被分析，在本例中，一内插器必須用來以相同速 率取樣，但利用每一原始樣本之一時間補償以確保理想 (+亦即最高/最低值）的樣本係被分析。 “ 第三圖所示為可變補償，其可應用於複數個樣本輸入（上 排以44 MHz接收）以確保該樣本輸出（底排）係以適 率（例如40 MHz)提供。 第四圖所示為一序列内插器實施例， 轉換，其係於一 802· llg WLAN裝置中 之相鎖迴路（PLLs)運作。 第五圖所示為另一序列内插 工部分乘積網路之該所需樣 第六圖所示為第五圖之該多 施例。 其可提供一所需樣本 ，該裝置以減低數量 器實施例，其可提供使用一多 本轉換。 工部分乘積網路之一閥門之實 第 器 第 圖 第 含 其中該接收 七八_圖所示為一WLAN裝置之一簡化接收器 之元件可利用一單一相鎖迴路運作。 圖所示為該接收器之一處理區塊之更多細節之方塊 該處理區塊包含一序列内插器。 八圖所示為一WLAN裝置之一發逆考，使士 _ 一序列内插器。 贯达窃J υ 元件符號說明： 201A - 201E > 2 0 2A - 20 2E 樣本Packets are essentially equivalent to operating in a 8 ^ wide. When a 802.11 a 0FDM combined bandwidth, these packets are real 0FDM packets. Therefore, it is still the same when mixed I buy. Importantly, although the 80-sequence interpolator is equally applicable to the description of US WLAN devices, the first clock rate is converted to a one-ho system, which divides the number of samples from the rate by the second clock Rate system: The clock rate is favorable, in which the first clock range is intended to be applied by the following rational number. Therefore, the scope of protection of the invention and the patent scope of the invention are defined. 200421801 Brief description of the diagram The first diagram shows a conventional non-integer component rate interpolator. The second figure shows a waveform in which ten samples are received. Although other samples must be analyzed, in this example, an interpolator must be used to sample at the same rate, but one of each original sample is used. Time compensation to ensure that ideal (+ ie highest / minimum) samples are analyzed. "The third diagram shows variable compensation, which can be applied to multiple sample inputs (received at 44 MHz in the upper row) to ensure that the sample output (bottom row) is provided at an appropriate rate (for example, 40 MHz). The fourth diagram Shown is an embodiment of a sequence interpolator. The conversion is based on the operation of phase-locked loops (PLLs) in an 802.llg WLAN device. The fifth figure shows another part of the product network of a sequence interpolator. The sixth example of the required sample shows the multiple embodiment of the fifth. It can provide a required sample, the device to reduce the number of embodiments, it can provide the use of multiple conversions. The figure of a real device of a valve contains the receiving seven or eight. The figure shows a WLAN device. The components of a simplified receiver can be operated by a single phase-locked loop. The figure shows a processing area of the receiver. A block with more details. The processing block contains a sequence of interpolators. Figure 8 shows a reverse test of a WLAN device, a sequence of interposers. 201A-201E > 2 0 2A-20 2E samples
200421801 圖式簡單說明 2 03 時間補償 300 接收樣本 400 序列内插器 401 閥門延遲線 40 2A -402E 觸發器 403 多工器網路 404A - 404F 係數 405 加總區塊 406 計算器 407 預設信號 5 0 0 ^ 746 内插器 501 多工部分乘積網路 501E 閥門 601A 、601B 多工器 602 加法器 702 BP濾波器 704 R F放大器 706 混合器 708 I F放大器 710 低通渡波器 712 基頻放大器 716 處理區塊 720 旋轉裝置 722 信號定時 732 FEC解碼器 741 CCK解碼器區塊 742 渴輪線 748 多工器 752 選擇區塊 743 渴輪模式暫存Is 802 序列内插器 800 發送器200421801 Brief description of the diagram 2 03 Time compensation 300 Received samples 400 Sequence interpolator 401 Valve delay line 40 2A-402E Trigger 403 Multiplexer network 404A-404F Coefficient 405 Total block 406 Calculator 407 Preset signal 5 0 0 ^ 746 Interpolator 501 Multiplexed Partial Product Network 501E Valves 601A, 601B Multiplexer 602 Adder 702 BP Filter 704 RF Amplifier 706 Mixer 708 IF Amplifier 710 Low Pass Amplifier 712 Base Frequency Amplifier 716 Processing Area Block 720 rotation device 722 signal timing 732 FEC decoder 741 CCK decoder block 742 thirsty line 748 multiplexer 752 selection block 743 thirsty mode temporary storage Is 802 sequence interpolator 800 transmitter
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| US8315662B2 (en) | 2003-08-13 | 2012-11-20 | Qualcomm Incorporated | User specific downlink power control channel Q-bit |
| US8755313B2 (en) | 2007-01-11 | 2014-06-17 | Qualcomm Incorporated | Using DTX and DRX in a wireless communication system |
| US9674786B2 (en) | 2007-01-11 | 2017-06-06 | Qualcomm Incorporated | Using DTX and DRX in a wireless communication system |
Also Published As
| Publication number | Publication date |
|---|---|
| US20040160346A1 (en) | 2004-08-19 |
| WO2004075443A3 (en) | 2005-10-06 |
| TWI321421B (en) | 2010-03-01 |
| WO2004075443A2 (en) | 2004-09-02 |
| US7098821B2 (en) | 2006-08-29 |
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