TW200416974A - Semiconductor package with lead frames having ground studs formed on the die pad thereof - Google Patents

Semiconductor package with lead frames having ground studs formed on the die pad thereof Download PDF

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Publication number
TW200416974A
TW200416974A TW092103186A TW92103186A TW200416974A TW 200416974 A TW200416974 A TW 200416974A TW 092103186 A TW092103186 A TW 092103186A TW 92103186 A TW92103186 A TW 92103186A TW 200416974 A TW200416974 A TW 200416974A
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Taiwan
Prior art keywords
ground
semiconductor package
wafer
lead frame
chip
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TW092103186A
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Chinese (zh)
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TWI244730B (en
Inventor
Nelson Shi
Ya-Yi Lai
Yung-Kang Chu
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Siliconware Precision Industries Co Ltd
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Priority to TW092103186A priority Critical patent/TWI244730B/en
Publication of TW200416974A publication Critical patent/TW200416974A/en
Application granted granted Critical
Publication of TWI244730B publication Critical patent/TWI244730B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85439—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

A lead frame-type semiconductor package is composed of a lead frame with a die pad and a plurality of leads, a die attached to the die pad, wires for grounding the die to the lead frame, and an encapsulant for enclosing the die and the ground wires; wherein the central area of a surface of the die pad is predefined with a die attached area and a grounding area is formed outside the die attached area of the die pad. Then, a plurality of metal studs used to be solder jointed to the ground wires are formed on the grounding area, allowing the exemption of using a sputtering process of forming silver layer. The arrangement structure can thus prevent delamination between silver-plating area of the die pad and the encapsulant, and the quality of packaging product can be enhanced.

Description

200416974 五、發明說明（1) [發明所屬之技術領域】： 本發明關於一種導線架型態之半導體封裝件，尤指一 種於晶片座（Die Pad)周圍形成接地線（Ground Wires )銲結部之導線架以供晶片載接之半導體封裝件 (Semiconductor Package) 〇 【先前技術】： 傳統導線架（Lead Frame)型態之半導體封裝件，如 四方扁平式半導體封裝件（Quad Flat Package， QFP)或 四方扁平無導腳式（Quad Flat Non-leaded，QFN)半導 I封1件等，其製作方式均在一具晶片座及多數導腳之導 I:上黏接一晶片’並藉由複數條金線電性連接晶片表面 ί二銲墊（Eiectr〇de pads)至對應導腳，復以一封 衣.肢包覆晶片及金線而形成一半導體封裝件。 ^維持半導體封裝件的電性品質，晶二銲墊裡包含有 接i 、干墊（Gr〇und pad)，以藉多數接地令 w . 、、 秋 w 吧綠(G r 〇 u n d s連接各接地銲墊至晶片座，而為晶片提供一接地 功:°然為能於導線架及晶片座上銲接金線，業界一般| 在晶片座表面及導腳銲接墊（Lead Flngers) i喷鍵 曰 (=二t Plating)或電沉積一如金、銀或金錄合二二鍍層 p徒供金線的銲接。 ^惟該銀層與封裝膠體之間的表面結合力甚差，因此若 按照:統噴鍍方法（Sp〇t Platlng)，如第丄級ΐβ圖所 不’僅於導線架底部及外導腳部設置夾戽18 ( Ciamper )則1鍍完成後，晶片座1 1頂面Π 3、側緣1丨4及内導腳200416974 V. Description of the invention (1) [Technical field to which the invention belongs]: The present invention relates to a semiconductor package in the form of a lead frame, in particular to forming a ground wire (Ground Wires) bonding portion around a die pad. Lead package for semiconductor package (Semiconductor Package) for chip mounting 〇 [Previous technology]: Traditional lead frame (Lead Frame) type semiconductor package, such as Quad Flat Package (QFP) Or quad flat non-leaded (QFN) semi-conducting I-seals, 1 piece, etc., the manufacturing methods are all in a chip holder and most of the guide pins I: a chip is bonded to the A plurality of gold wires are electrically connected with two pads on the surface of the wafer to corresponding guide pins, and a semiconductor package is formed by covering the wafer and gold wires with a piece of clothing. ^ Maintain the electrical quality of the semiconductor package. The bonding pads for crystals 2 include i and dry pads (Ground pads), so that most of the grounding orders w.. Pad to wafer holder, and provide a grounding work for the wafer: ° In order to weld gold wires on the lead frame and wafer holder, the industry generally | on the surface of the wafer holder and the lead pad (Lead Flngers) i spray key ( = T Plating) or electrodeposition, such as gold, silver, or gold-plated two-layer plating p gold wire welding. ^ However, the surface adhesion between the silver layer and the packaging colloid is very poor, so if you follow: Sputtering method (Sp0t Platlng), as shown in the second stage ΐβ diagram, only the bottom of the lead frame and the outer guide feet are provided with a clip 18 (Ciamper). After the plating is completed, the chip holder 1 1 top surface Π 3 , Side edges 1 丨 4 and inner guide feet

200416974 五、發明說明（2) 120( Inner Leads)各表面均有銀層17分佈。而銀層1 7之 熱月彭脹係、數（Coefficient of Thermal Expansion, CTE )遠大於樹脂材質之封裝膠體（未圖示），故銀層與封裝 i膠體間之接合介面於封膠時會產生很大的熱應力而導致與 i 封裝膠體（未圖示）的表面結合力不佳，極易使銀層1 7與 封裝膠體介面層發生脫層（Delamination)而損及產品信 賴性。 為減少導線架脫層問題，如第2圖所示，美國專利第 5，153，70 6號案提出一種環型喷鍵方法（Ring Type S p o 11 i n g)，亦即改變夾具型態，使銀層1 7僅鍍設於晶片 座1 1周圍及内導腳1 2 0，藉此減少鍍銀面積俾降低脫層發 生率。然而，以環型喷鍍方法沉積銀層1 7至導線架1 0，如 第3圖所示，晶片座1 1背面以及側壁亦會如傳統導線架發 生漏銀（指銀層珍入晶片座底部）而產生銀層1 7與封裝膠 體1 6之間的脫層問題；同時，此法亦無法徹底改善封裝膠 體1 6與銀層1 7表面結合力不良，及銀層1 7與封裝膠體1 6介 面因熱應力而導致脫層等缺失。是故，業者亟需開發出二 種避免脫層、漏銀發生，兼能提高封裝成品電性品質與作 業信賴性之接地方式。 【發明内容】： 本發明之主要目的在於提供一種得為導線架型態之半 導體封裝件增加接地線銲接功能，以提昇產品電性品質之 半導體封裝件。 本發明之另一目的在於提供一種避免晶片座背面出現200416974 V. Description of the invention (2) 120 (Inner Leads) Each surface has a silver layer 17 distribution. The thermal expansion coefficient (CTE) of the silver layer 17 is much larger than that of the resin-based packaging gel (not shown), so the bonding interface between the silver layer and the packaging i colloid will be sealed during the sealing process. A large thermal stress is generated, resulting in poor adhesion to the surface of the i-package gel (not shown), which can easily cause delamination of the silver layer 17 and the package colloid interface layer, and damage the reliability of the product. In order to reduce the problem of delamination of the lead frame, as shown in FIG. 2, US Patent No. 5,153,70 6 proposes a ring type spraying method (Ring Type S po 11 ing), that is, changing the type of the fixture so that The silver layer 17 is only plated around the wafer holder 11 and the inner guide pins 120, thereby reducing the silver plating area and reducing the occurrence of delamination. However, the silver layer 17 to the lead frame 10 are deposited by a ring-type spraying method. As shown in FIG. 3, the back of the wafer holder 11 and the side wall of the wafer holder 11 will also experience silver leakage as in a conventional lead frame (referring to the silver layer cherished into the wafer holder). (Bottom) and the delamination problem between silver layer 17 and packaging gel 16; at the same time, this method can not completely improve the poor bonding between the surface of packaging gel 16 and silver layer 17, and the silver layer 17 and packaging gel 16 The interface is missing due to thermal stress. Therefore, there is an urgent need for the industry to develop two grounding methods to avoid delamination and silver leakage and improve the electrical quality of the packaged product and the reliability of the operation. [Summary of the Invention]: The main object of the present invention is to provide a semiconductor package which can increase the soldering function of a ground wire for a semiconductor package in the form of a lead frame, so as to improve the electrical quality of the product. Another object of the present invention is to provide a method for preventing the back of the wafer holder from appearing.

17152.ptd 第 7 頁 200416974 五、發明說明（3) 漏銀而損及封 本發明之 之間結合不良 本發明之 間之接合介面 為達成上 接結構之導線 封裝件。此半 片座及多數導 裝件信 再一目 而產生 又 4 出 緣 置區 接元 銲墊 導線 為導 封裝 塗佈 I罾而 ’件之 【實 件之 一晶 之接 上， 件， 電j生 架。 於晶 線架 件具 ，亦 產生 信賴 施方 以下 半導 片接 地區 且與 係形 連接 片座 型態 有較 能完 與封 性品 式】 即以 體封 不致因 揭及其 架，及 導體封 腳所構 置區及 :至少 該導腳 成於該 ;以及 賴性之半導體 的在於提供一 脫層問題之半 的在於 熱應力 他目的 以該導線架作 裝件包 提供一 引發脫 ，本發 含一導 成，其中，該 一形成於€亥晶 一晶片，係黏 間形成電性連 接地區上，以 一封裝膠體， 封裝件 種防止 導體封 種防止 層之半 明揭露 為晶片 線架， 晶片座 片接置 置於該 接關係 與該晶 用以包 銀層與封裝膠體 裝件。 銀層與封 導體封裝 一種具接 承載件之 其係由至 一表面上 區外靠近 晶片座之 ;複數個 片上形成 覆該晶片 裝膠體 件。 地線銲 半導體 少一晶 預先定 晶片座 晶片接 接地銲 之接地 及部分 周緣設置金屬銲塊來取代傳統鍍銀技術，可 之半導體封裝件提供接地線銲結功能，俾i 佳的電性品質；再一方面，晶片座上無銀層 全杜絕漏銀’以免晶片座或導腳背面珍入銀 裝膠體接合不良或脫層等問題，以提高封裝 質。 第4圖至第7圖詳細說明本發明具接地銲接元 裝件。惟該所附圖式僅簡單繪示與本發明實17152.ptd Page 7 200416974 V. Description of the invention (3) Silver leakage damages the seal The connection between the present invention is poor The connection interface between the present invention is a wire package to achieve the upper structure. This half-piece seat and most of the guide assembly letters are generated at a glance, and 4 lead edge pads are connected to the bonding pad wires. The lead package is coated and the “pieces of the real piece are connected. frame. For the crystal wire frame, it also generates trust. The semi-conductor connection area below the formula is reliable and can be completed and sealed with the form of the connection base.] That is, the body is sealed without causing the frame and the conductor. The area where the foot seal is constructed and: at least the guide foot is formed there; and the semi-conductive semiconductor is to provide a half of the delamination problem is to thermal stress. The purpose is to use the lead frame as a package to provide a delamination. The device contains a guide, wherein the first is formed on a wafer, and the electrical connection area is formed between the adhesives. A sealing gel is used to expose the semi-expanded layer of the package to prevent the conductor from being sealed. The wafer holder is placed in the connection relationship with the crystal for covering the silver layer and encapsulating the colloidal component. Silver layer and encapsulating conductor package A connected carrier, which is connected to a wafer holder outside a surface area; a plurality of wafers are formed on the wafer to form a plastic component. The ground wire is one less semiconductor. The ground of the wafer holder is grounded and a metal pad is set on some peripheral edges to replace the traditional silver plating technology. The semiconductor package can provide the function of ground wire bonding, which has good electrical quality. On the other hand, there is no silver layer on the chip holder to completely prevent silver leakage, so as to prevent problems such as poor bonding or delamination of silver colloids on the back of the chip holder or the guide pins, so as to improve the packaging quality. Figures 4 to 7 illustrate in detail the grounded welding element of the present invention. However, the drawings are only for simple illustration with the present invention.

17152. ptd 第8頁 200416974 五、發明說明（4) 施方式有關之元件及組成態樣，該半導體封裝件實際實施 時其元件數量、元件種類以及佈局型態將更為複雜。 第一實施例： 如第4圖所不，本發明第一實施例之半導體封裝件2係 包含一具至少一晶片座2 1及多數導腳2 2之導線架2 0，至少 一黏置於該晶片座2 1上之晶片2 3，複數個形成於該晶片座 2 1周圍之金屬銲塊2 4，多數提供晶片2 3與導線架2 0接地連 接之接地線251 ( Ground Wires)，以及一用以包覆該晶 片2 3、金屬銲塊2 4及接地線2 5 1之封裝膠體2 6。 如第4圖及第5圖所示，該導線架2 0係一由銅、銅合金 等金屬材質製成，每一導線架2 〇包含有至少一藉複數條繫 ir、2 1 0 ( T i e Bar s)樓設之晶片座2 1 ( D i e Pad)及環置於 該晶片座2 1周圍之多數導腳22 (本實施例僅繪示部分接地 導腳及訊號導腳）所構成。該晶片座2 1一表面2 〇 〇之中央 部上預先定義出至少一晶片接置區2 i丨，該晶片接置區2 i i 外靠近晶片座2 1周緣處復定義出一接地區2 1 2，惟該導線 架2 〇界定該晶片接置區2 1 1及接地區2 1 2等區域時，並未^ 設有銀層，故不致出現漏銀或脫層等問題。 如第5圖所示，該晶片座2 1之接地區2 1 2上形成複數個 金屬銲塊24( Metal Studs)提供接地線（Ground Wires )詳接，該金屬銲塊24係為金質銲塊（Golden Studs)， 以供金線材質之接地線（如第4圖2 5 1所示）電性連接至晶 片座2 1。此外，該金屬銲塊2 4係採用傳統銲線作業（w i r e B〇ndlng)之熱熔壓接技術（Thermal compressi〇n17152. ptd page 8 200416974 V. Description of the invention (4) The components and composition of the semiconductor package will be more complicated when the semiconductor package is actually implemented. First Embodiment: As shown in FIG. 4, the semiconductor package 2 according to the first embodiment of the present invention includes a lead frame 20 having at least one chip holder 21 and a plurality of lead pins 22. The wafers 2 3 on the wafer base 21, a plurality of metal soldering pads 2 4 formed around the wafer base 21, and most of them provide ground wires 251 (Ground Wires) for ground connection between the wafers 23 and the lead frame 20, and An encapsulant 2 6 for covering the wafer 2 3, the metal soldering block 24, and the ground wire 2 51. As shown in FIG. 4 and FIG. 5, the lead frame 20 is made of metal materials such as copper and copper alloy, and each lead frame 20 includes at least one borrowed plurality of lines ir, 2 1 0 (T ie Bar s) is composed of a chip pad 21 (Die Pad) and a plurality of guide pins 22 (only a part of ground guide pins and signal pins) are placed around the chip holder 21. At least one wafer receiving area 2 i 丨 is defined in the central part of the surface of the wafer holder 2 1 on the surface 2000, and the wafer receiving area 2 ii is further defined near the periphery of the wafer holder 2 1 to define a contact area 2 1 2. However, when the lead frame 20 defines the areas such as the chip receiving area 2 1 1 and the connecting area 2 12, there is no silver layer ^, so no problems such as silver leakage or delamination will occur. As shown in FIG. 5, a plurality of metal studs 24 (Metal Studs) are provided on the connection area 2 1 2 of the wafer base 21 to provide ground wires. The metal studs 24 are gold welding. The block (Golden Studs) is electrically connected to the chip holder 2 1 with a ground wire made of gold wire (as shown in Fig. 4 2 5 1). In addition, the metal soldering block 24 is a thermal welding compression technique (Thermal compressi〇n) using a conventional wire bonding operation (w i r e Böndlng).

17152. ptd 200416974 五、發明說明（5)17152. ptd 200416974 V. Description of the invention (5)

Bond i ng)製造，以銲線機（Bonder)(未圖示）定位至 晶片座2 1上方來實施銲接，惟此等製程均為習知，故不另 行贅述。 如第6圖所示，該晶片2 3具有一作用表面2 3 0 (佈設有 夕數電子電路及電子元件之表面）及一相對之非作用表面 2 31，該作用表面2 3 0上形成有多數訊號銲墊2 3 2a ( Signal Pads)及接地銲塾232b( Ground Pads)，每一接地銲墊 2 3 2 b各與形成於該晶片座2 1接地區2 1 2上之金屬銲塊2 4同 側對應。因此，當晶片2 3黏置到晶片座2 1上並完成銲線作 (W i r e B〇n d i n g)後，晶片2 3作用表面2 3 0上之訊號銲 曰2 3 2 a藉由多條訊號線2 5 0電性連接至各訊號導腳2 2 1，而 晶片接地銲墊2 3 2 b則以接地線2 5 1及2 5 1，分別銲連晶片座 21周圍之金屬銲塊24以及接地導腳22〇上，使接地=上 所有金，屬銲塊24經由晶片座2 1彼此電性連接後 °° 接地線2 5 1 ’及接地導腳2 2 0電性連接至外部。.于匕" /晶片座周緣設置金屬銲塊來取代傳統銀層 ^架型態之半導體封裝件提供一地線詳#1力能以J 進曰曰片電性品質；而晶片座上無銀層佈覆，除a p、曰 外，更能避免銀層與封裝膠體之間因熱應力而=m艮 _封裝膠體間的接合面出現脫層’從而增進封穿件2。上 施例： 第7圖係顯示本發明半導體封裝件一者 货·— 一 乃 貝施例，此 弟二貫施例之半導體封裝件3結構大致同於前述第一實施Manufactured by Bond i ng, and a bonding machine (not shown) is positioned above the wafer holder 21 to perform welding, but these processes are all known, so they will not be described in detail. As shown in FIG. 6, the wafer 2 3 has an active surface 2 3 0 (a surface on which electronic circuits and electronic components are arranged) and an opposite non-active surface 2 31. The active surface 2 3 0 is formed on the wafer. Most of the signal pads 2 3 2a (Signal Pads) and ground pads 232b (Ground Pads), each of the ground pads 2 3 2 b and the metal pad 2 formed on the chip holder 2 1 contact area 2 1 2 4 corresponds to the same side. Therefore, after the wafer 2 3 is adhered to the wafer base 21 and the bonding wire is completed (Wire Bonding), the signal on the active surface 2 3 0 of the wafer 2 is welded 2 3 2 a through multiple signals. The wire 2 50 is electrically connected to each signal lead 2 2 1, and the chip ground pad 2 3 2 b is connected to the metal pads 24 around the chip holder 21 with the ground wires 2 5 1 and 2 5 1 respectively. The ground guide pin 22 is connected to the ground = all gold, and the solder bumps 24 are electrically connected to each other via the wafer holder 21. The ground wire 2 5 1 ′ and the ground guide pin 2 2 0 are electrically connected to the outside. . Set metal pads on the periphery of the chip holder to replace the traditional silver-layered semiconductor package. Provide a ground wire. # 1 The power can be used to improve the electrical quality of the chip; The silver layer coating, in addition to ap and y, can further prevent delamination of the bonding surface between the silver layer and the packaging colloid due to thermal stress, thereby improving the seal-through 2. The above embodiment: Fig. 7 shows one of the semiconductor packages of the present invention. The first package is the embodiment. The structure of the semiconductor package 3 of the second embodiment is substantially the same as that of the first embodiment.

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第10頁Page 10

200416974 五、發明說明（6) 例，其不同處在於形成於晶片座3 1接地區3 1 2上之金質銲 塊3 4與晶片3 3接地銲墊3 3 2 b以接地線3 5 1電性銲接後，另 以多條金線3 5 2直接銲接晶片座3 1及接地導腳3 2 0，使晶片 3 3接地銲墊3 3 2 b無須以銲線銲接至接地導腳3 2 0，更無須 為顧及兩條以上接地線連接而變更銲墊之大小，晶片接地 得以透過該接地鲜塾3 3 2 b、接地線3 5 1、金質鲜塊3 4、晶 片座3卜金線3 5 2電性連接至接地導腳3 2 0，再與外部接地 裝置（未圖示）電性連接。 以上所述僅為本發明之較佳實施例而已，並非用以限 制本發明之實質技術内容範圍。本發明之實質技術内容範 圍係廣義地定義於下述之申請專利範圍中。任何他人所完 成之技術實體或方法，若是與下述之申請專利範圍所定義 者為完全相同，或是為一種等效之變更，均將被視為涵蓋 於此專利範圍之中。200416974 V. Description of the invention (6) Example, the difference lies in the gold pads 3 4 formed on the wafer holder 3 1 contact area 3 1 2 and the wafer 3 3 ground pads 3 3 2 b with the ground wire 3 5 1 After the electrical welding, another gold wire 3 5 2 is directly welded to the wafer holder 3 1 and the ground guide pin 3 2 0, so that the wafer 3 3 ground pad 3 3 2 b does not need to be welded to the ground guide pin 3 2 0, and no need to change the size of the solder pad to take into account the connection of more than two ground wires, the chip ground can pass through the ground connection 3 3 2 b, ground wire 3 5 1, gold block 3 4, chip holder 3 gold The wire 3 5 2 is electrically connected to the ground guide pin 3 2 0 and then electrically connected to an external grounding device (not shown). The above descriptions are merely preferred embodiments of the present invention, and are not intended to limit the scope of the essential technical content of the present invention. The essential technical content scope of the present invention is broadly defined in the scope of patent applications described below. Any technical entity or method completed by others, if it is exactly the same as defined in the scope of patent application below, or an equivalent change, will be deemed to be covered by this patent scope.

17152. ptd 第11頁 200416974 '圖式簡單說明 【_圖式簡單說明】： 第1 A圖係習知具地線銲接銀層之導線架上視示意圖； 第1 B圖係於習知導線架上形成地線銲接銀層之動作示 .意圖， 第2圖係美國專利第5，1 5 3，7 0 6號案之導線架上視示意 圖； 第3圖係習知導線架發生漏銀及脫層部位之局部放大 示意圖； 第4圖係本發明半導體封裝件中形成有地線銲接元件 導線架上視示意圖； 第5圖係本發明第一實施例之半導體封裝件之剖面示 意圖； 第6圖係第5圖所示之半導體封裝件於銲線作業完成後 之上視示意圖；以及 第7圖係本發明第二實施例之半導體封裝件於銲線完 成後之上視示意圖。 114 晶片座側緣 17 銀層 20,10導線架 2 1，1 1，3 1晶片座 211 晶片接置區 2 2 導腳 2 2 1 訊號導腳 113 晶片座頂面 12 0 内導腳 L·, 3 半導體封裝件 2 0 0 晶片座表面 210 繫條 2 1 2，3 1 2接地區 2 2 0，3 2 0接地導腳17152. ptd Page 11 200416974 'Schematic description [_Schematic description]: Figure 1 A is a top view of a conventional lead frame with ground wire and silver layer; Figure 1 B is a conventional lead frame The operation of forming a silver wire layer on the ground wire is shown. Intent, Figure 2 is a schematic top view of a lead frame in the US Patent No. 5,15 3,7 06; Figure 3 is a conventional lead frame with silver leakage and Partially enlarged schematic view of the delamination part; FIG. 4 is a schematic top view of a lead frame having a ground wire bonding element formed in the semiconductor package of the present invention; FIG. 5 is a schematic cross-sectional view of the semiconductor package of the first embodiment of the present invention; FIG. 5 is a schematic top view of the semiconductor package shown in FIG. 5 after the bonding wire is completed; and FIG. 7 is a schematic top view of the semiconductor package of the second embodiment of the present invention after the bonding wire is completed. 114 Chip holder side edge 17 Silver layer 20, 10 Lead frame 2 1, 1 1, 3 1 Chip holder 211 Chip receiving area 2 2 Guide pin 2 2 1 Signal guide 113 Chip holder top surface 12 0 Inner guide pin L · , 3 Semiconductor package 2 0 0 Wafer surface 210 Tie 2 1 2, 3 1 2 Ground area 2 2 0, 3 2 0 Ground lead

17152. ptd 第12頁 200416974 圖式簡單說明 23,33 晶片 231 非作用表面 2 3 2 b，3 3 2 b接地銲墊 2 5 0 訊號線 2 6，1 6封裝膠體 2 3 0 作用表面 2 3 2 a，3 3 2 a訊號銲墊 2 4，3 4金屬銲塊（金質銲塊 2 5 1，2 5 1 ’，3 5 1 接地線 3 5 2 金線17152. ptd Page 12 200416974 Brief description of the drawings 23,33 Chip 231 Non-active surface 2 3 2 b, 3 3 2 b Ground pad 2 5 0 Signal line 2 6, 1 6 Encapsulant 2 3 0 Active surface 2 3 2 a, 3 3 2 a signal pads 2 4, 3 4 metal solder bumps (gold solder bumps 2 5 1, 2 5 1 ', 3 5 1 ground wire 3 5 2 gold wire

II

17152.ptd 第13頁17152.ptd Page 13

Claims (1)

200416974 、六、申請專利範圍 1二一種半導體封裝件，係包含： 一導線架，係由一晶片座及多數導腳所構成，且 令該晶片座之一表面上形成一晶片接置區及一形成於 . 該晶片接置區外之接地區， 至少一晶片，係黏置於該晶片座之晶片接置區上 ~ ，並與該導腳形成電性連接關係； 複數個接地銲接元件，係形成於該接地區上，以 與該晶片接地連接；以及 一封裝膠體，用以包覆該晶片及部分之導線架。 2 .如申請專利範圍第1項之半導體封裝件，其中，該導線 架係由銅材質製成。 3. 如申請專利範圍第1項之半導體封裝件，其中，該接地 區係形成於該晶片座之周緣。 4. 如申請專利範圍第1項之半導體封裝件，其中，該晶片 座之接地區與部分導腳間係以多數金線電性連接。 5 .如申請專利範圍第1項之半導體封裝件，其中，該晶片 之一表面上形成有複數個可與各接地銲接元件電性連~ 接之接地銲墊（Ground Pads)。 6 .如申請專利範圍第1或5項之半導體封裝件，其中，該 I 晶片之接地銲墊係藉複數條接地線（G r 〇 u n d W i r e s) p 銲結連接至各接地銲接元件。 7.如申請專利範圍第1項之半導體封裝件，其中，該接地 銲接元件係以銲線（W i r e Β ο n d i n g)之熱溶壓接技術 , (Thermal Compression Bonding)形成於該晶片座之200416974 6. The scope of application for patents includes a semiconductor package including: a lead frame, which is composed of a wafer base and a plurality of guide pins, and a wafer receiving area is formed on one surface of the wafer base and One is formed in the connection area outside the wafer connection area, and at least one wafer is glued on the wafer connection area of the wafer holder ~, and forms an electrical connection relationship with the guide pin; a plurality of ground welding components, It is formed on the connection area for ground connection with the chip; and a packaging gel for covering the chip and part of the lead frame. 2. The semiconductor package according to item 1 of the patent application scope, wherein the lead frame is made of copper. 3. The semiconductor package of claim 1, wherein the ground region is formed on the periphery of the wafer holder. 4. For example, the semiconductor package of the scope of the patent application, wherein the connection area of the chip holder and some of the lead pins are electrically connected by most gold wires. 5. The semiconductor package according to item 1 of the scope of patent application, wherein a plurality of ground pads (ground pads) are formed on one surface of the chip and can be electrically connected to the ground welding elements. 6. The semiconductor package of claim 1 or 5, wherein the ground pad of the I chip is connected to each grounded welding element by a plurality of ground wires (G r oo n d W i r e s) p solder joints. 7. The semiconductor package according to item 1 of the scope of patent application, wherein the ground soldering element is formed by a hot-melt compression bonding technique of bonding wire (W i r e Β ο n d i n g), and (Thermal Compression Bonding) is formed on the wafer base. 17152.ptd 第14頁 200416974 六、申請專利範圍 接地區上。 8 .如申請專利範圍第1項之半導體封裝件 鋅接元件係一金屬銲塊（M e t a 1 S t u d s. 9 .如申請專利範圍第8項之半導體封裝件 銲塊之材質係為金。 iiii 其中 〇 其中 該接地 該金屬 17152.ptd 第15頁17152.ptd Page 14 200416974 6. Scope of patent application Connected to the region. 8. If the zinc package of the semiconductor package item 1 in the scope of the patent application is a metal pad (Meta 1 Stud s. 9). If the material of the semiconductor package package in the 8th category of the patent application is made of gold. iiii where 〇 where the ground is 17152.ptd page 15
TW092103186A 2003-02-17 2003-02-17 Semiconductor package with lead frames having ground studs formed on the die pad thereof TWI244730B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10269733B2 (en) 2016-02-17 2019-04-23 Realtek Semiconductor Corp. Integrated circuit device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10269733B2 (en) 2016-02-17 2019-04-23 Realtek Semiconductor Corp. Integrated circuit device
TWI690043B (en) * 2016-02-17 2020-04-01 瑞昱半導體股份有限公司 Integrated circuit device

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