玖、發明說明 【韻^明所屬技摘^領域^】 t明領域 本發明係關於一種供液晶顯示器用之薄膜電晶體基材 及其製造方法，更特別地說，係關於一供液晶顯示器用之 薄膜電晶體基材及其製造方法，於該電晶體基材中藉由使 用相同的光罩形成黑色矩陣層（其形成在該薄膜電晶體基 材上）及閘極線（其形成在該黑色矩陣層上）。 發明背景 在現今資訊導向之社會，電子顯示器的角色愈形重要 。各種電子顯示器廣被使用於工業領域中。因電子顯示器 技術領域的㈣進步’“了各式具有新功㈣電子顯示 器以滿足資訊導向社會的多元需求。 一般而言，電子顯示器係一傳遞視覺資訊於個人的裝 置。亦gp，電子顯不器可被定義為一種電子裝f，其將來 自各式電子備的m號轉換為視覺可辨識的光訊信號 電子顯示器亦可被疋義為一種供作連結個人及電子設備 橋樑的電子裝置。 這些電子顯示器被分為二大類：發射型顯示器，其經 由光發射方法顯示光訊信號；非發射型顯示器，其經由光 學調整方法（如光反射、光分散、及光干涉等現象）顯示 光訊信號。發射型顯示器稱作主動式顯示器，其含有如 CRT (陰極射線管）、PDp (電滎顯示器面板）、(發光 二極體）及ELD (電激發光顯示器）等。非發射型顯示器 稱作被動式顯示器，其含有 (電泳影像顯示器）等。发明 Description of the invention [Yun ^ Ming's technical abstract ^ Field ^] The present invention relates to a thin film transistor substrate for a liquid crystal display and a method for manufacturing the same, and more particularly, it relates to a liquid crystal display for a liquid crystal display. A thin film transistor substrate and a manufacturing method thereof, in which a black matrix layer (which is formed on the thin film transistor substrate) and a gate line (which is formed on the thin film transistor substrate) are formed by using the same photomask Black matrix layer). BACKGROUND OF THE INVENTION In today's information-oriented society, the role of electronic displays is increasingly important. Various electronic displays are widely used in the industrial field. Due to the "progress in the field of electronic display technology," various electronic displays have new functions to meet the diverse needs of information-oriented society. Generally speaking, electronic displays are devices that transmit visual information to individuals. Also, GP, electronic display The device can be defined as an electronic device f, which converts the m number from various electronic devices into a visually recognizable optical signal. The electronic display can also be defined as an electronic device for connecting personal and electronic devices. These electronic displays are divided into two categories: emissive displays that display optical signals via light emission methods; non-emissive displays that display optical signals through optical adjustment methods such as light reflection, light dispersion, and light interference. Signal. Transmissive displays are called active displays, which include, for example, CRT (cathode ray tube), PDp (electrical display panel), (light emitting diode), and ELD (electrically excited light display). Non-emissive displays are called As a passive display, it contains (electrophoretic image display) and the like.
LCD (液晶顯示器）及EPID 、^吏用於影像顯示器（如電視或顯示器等）已歷經 極為長久的時間。在顯示器品質及經濟效率方面，CRT有 S 、市努佔有率，但亦有如笨重、太佔空間及耗能過高 等缺點。 現今，因各式電子構件隨著一致化而更小更輕以及由 於半導體科技快速進展而更省電更省能源，所以為呼應此 新壤境也有需求更纖細更輕薄與更省電更省能源之平面形 面版顯示器的呼聲。 於各式已發展的平面形面版顯示器中，LCD較其他顯 示器更薄更輕與更省電更省能源，而且其亦有與CRT近似 的顯示品質，所以LCD被廣用於各式電子構件中。此外， LCD可以輕易製造，故其使用將更為廣泛。 液晶顯示器係由兩基材組成，電極形成於基材内且液 晶置於兩基材間。液晶顯示器係一種藉由對電極施加電壓 ’使液晶分子重新排列來控制通過液晶之光線量以實施顯 示操作的構件。 在這些LCD中，廣被使用的一般構造包括兩基材，在 每一基材上形成一電極並有一薄膜電晶體（TFT)來開關 施加於該電極的電壓。一般而言，該電極形成於該兩基材 中之一者的上面。 當這些LCD面版的解析度增加，閘極線的冗餘亦隨之 增加，此等閘極線冗餘的增加提高了閘極線開啟發生的可 玖、發明說明 能性，由此可能引起失效的像素。 【明内】 發明概要 因此，本發明即針對供液晶顯示器用之薄膜電晶體基 材及其製造方法來具體地排除由於相關技藝的限制及缺點 所造成的一個或多個問題。 本發明目標之一係當閘極線開啟發生時，藉由允許黑 色矩陣作為閘極線以代替該開啟的閘極線來防止因閘極線 開啟所導致之失效像素數目的增加。 本發明之另一目標係將閘極圖樣及閘極絕緣膜間的界 線保持於良好狀態。 本發明之其他特性及優點將於以下的敘述中呈現，其 中一部分將可由敘述中清楚得知或經由實行本發明而學習 到。藉由文字敘述、申請專利範圍及附加圖示中所特別指 明的構造，本發明的目標及其他優點將可被明瞭與達成。 為達到這些及其他優點且為與本發明之目的相一致， 吾人提供了供液晶顯示器用之薄膜電晶體基材以作為具體 實施例及概括地描述。該薄膜電晶體基材包括：一個在一 透明絕緣基材上被排列於鄰接單元像素間的黑色矩陣，其 用於防止光由鄰接單元像素間洩漏；一個在該黑色矩陣上 形成的第一氧化膜；一個在該第一氧化膜上之主動部位形 成的主動多晶矽層圖樣；一個在一所得基材上形成的第二 氧化膜，此所得基材包括該主動多晶矽層圖樣及一曝露嗜 黑色矩陣之預定部分的第一接觸孔；一個在該第二氧化膜 200410416 玖、發明說明 之選定區域上形成的閘極線，且其經由該第一接觸孔與該 黑色矩陣為電接觸；一個在包括該閘極線之所得基材上形 成的第二氧化膜，一個在該第三氧化膜上形成且與該閘極 線垂直的資料線；一個在包括該資料線之該第三氧化膜上 5形成的平坦化膜及一個在該平坦化膜上形成的像素電極。 較佳地，該黑色矩陣與該閘極線有相同的圖樣形狀。 較佳地，該第一氧化膜與形成於該主動多晶矽層圖樣 上的该苐二氧化膜有相同的厚度。 任擇地，該黑色矩陣或該閘極線其中之一者具有一島 1〇 狀構造。 為進一步達到這些及其他優點且為與本發明目的相一 致，吾人提供了供液晶顯示器用之薄膜電晶體基材的製造 - 方法。此方法包括下述步驟：在一透明絕緣基材上鄰接單 ' 元像素間形成一黑色矩陣，用於防止光由鄰接單元像素間 15洩漏；在該黑色矩陣上形成一第一氧化膜；在該第一氧化 膜上的主動部位形成一主動多晶矽層圖樣；在一包括該主 · 動多晶石夕層圖樣的所得基材上形成一第二氧化膜；在該第 二氧化膜之一選定部分上形成一曝露該黑色矩陣之一選定 部分的第一接觸孔；在該第二氧化膜的一選定區域上及該 - 2〇第一接觸孔上形成一閘極線；在一包括該閘極線的所得基 ‘ 材上形成-第三氧化膜；在該第三氧化膜之一預定部分形 成-曝露該主動多晶石夕層圖樣之一預定部分的第二接觸孔 ;在該第三氧化膜及其預定部分上形成-資料線；在包括 該資料線的該第三氧化膜上形成一平坦化膜及在該平坦化 8 玖、發明說明 「丨 膜上形成一像素電極。 較佳地，該黑色矩陣及該閘極線藉由使用一相同的光 罩形成。 為進一步達到這些及其他優點且為與本發明目的相一 致，吾人提供了供液晶顯示器用之薄膜電晶體基材。此薄 膜電晶體基材包括··一個在一透明絕緣基材上鄰接單元像 素間的黑色矩陣，其用於防止光由鄰接單元像素間浅漏； —個在該黑色矩陣上形成且帶有一曝露該黑色矩陣之一預 定部分之第一接觸孔的第一氧化膜；一個包括有一第一與 一第二主動多晶矽層圖樣的主動多晶矽層圖樣，該第一主 動多晶矽層圖樣形成於該第一氧化膜上的一主動部位，該 第二主動多晶矽層圖樣形成於該第一接觸孔内且與該黑色 矩陣相接觸；一個在該主動多晶矽層圖樣上形成的第二氧 化膜；一個在該第二氧化膜之選定區域上形成的閘極線； 一個在一包括該閘極線之所得基材上形成的第三氧化膜； 個在δ亥第二氧化膜上形成的資料線，其與該閘極線垂直 且經由形成於該第二氧化膜内的該第二接觸孔與該第一主 動多晶矽層圖樣的一源極部位相接觸；一個在該第三氧化 膜上形成的金屬圖樣且其經由該第三接觸孔及一第四接觸 孔與该第一主動多晶石夕層圖樣為電連結，該第三接觸孔形 成於該閘極線上的該第三氧化膜内，該第四接觸孔形成於 該第二主動多晶矽層圖樣及其下之該第二氧化膜上的該第 三氧化膜内，·一個在包括該資料線之該第三氧化膜上形成 的平坦化膜及一個在該平坦化膜上形成的像素電極。 200410416 玖、發明說明 I 丨 ^ ^ 幸乂佳地’该閘極線有一島狀構造或有一被該金屬線所 跨接的構造。 為進一步達到這些及其他優點且為與本發明目的相一 致，吾人提供了供液晶顯示器用之薄膜電晶體基材的製造 5方法。此方法包括下述步驟：在一透明絕緣基材上的鄰接 單元像素間形成一黑色矩陣，用於防止光由鄰接單元像素 間洩漏；在該黑色矩陣上形成一第一氧化膜；在該第一氧 化膜之一預定部分形成一曝露該黑色矩陣之一預定部分的 · 第接觸孔，在該第一氧化膜上的一主動部位形成一第一 主動夕s曰石夕層圖樣及在該第一接觸孔内形成一與該黑色矩 陣相接觸的一第二主動多晶矽層圖樣；在該第一及第二主 動多晶矽層圖樣上形成一第二氧化膜；在該第二氧化膜的 · 預疋部分上形成一閘極圖樣；在一包括該閘極圖樣的所 得基材上形成一第三氧化膜；在該第三氧化膜及其下之第 15二氧化膜内形成一曝露該主動多晶矽層圖樣之一源極部位 的第二接觸孔，一曝露該閘極圖樣之一預定部分的第三接 · 觸孔及一曝露該第二主動多晶矽層圖樣之一預定部分的第 四接觸孔；形成一經由在該第三氧化膜上之該第二接觸孔 與該源極部位相接觸的第一資料圖樣及一經由在該第三氧 - 20化膜上之該第三及第四接觸孔將該閘極圖樣與該第二主動 - 多晶矽層圖樣連結的第二資料圖樣；在包括該第一及第二 資料圖樣的該第三氧化膜上形成一平坦化膜及在該平坦化 膜上形成像素電極。 10 200410416 屬式簡單說明 ‘藉由詳細說明具體實施例及參考附加圖式，本發明的 則述及其他優點將更加清楚。圖式如下： 第1圖至第3圖係依據本發明之一具體實施例所表示 5之供LCD用之薄膜電晶體基材的製造過程的平視圖。 第4圖係沿著第3圖之4-4，、線的剖視圖。 第5圖係依據本發明之另一具體實施例所表示之供 LCD用之薄膜電晶體基材的構造及製造過程的剖視圖。 【實施方式3 10 魏J圭具體實施例之詳細說明 現在，吾人將參考附加圖式來詳細說明本發明之較佳 具體實施例。 具體實施例1 第1圖至第3圖係依據本發明之一具體實施例所表示 15之供LCD用之薄膜電晶體基材的製造過程的平視圖，第4 圖係沿著第3圖之線4-4,的剖視圖。 參考第1圖’藉由黃光微影過程在一透明絕緣基材 100 (如石英（Si〇2)或玻璃）上形成一較低黑色矩陣圖樣 102，如此該較低黑色矩陣圖樣1〇2在單元像素部位之邊界 2〇 線上被朝單一方向排列（第一光罩）。 任擇地，該黑色矩陣圖樣102並未被每一單元像素所 分離而是被繼續地形成。 在包括該黑色矩陣圖樣102之該基材100的全部表面 上形成一高溫氧化物（HTO)來當作第一氧化膜。 11 200410416 玖、發明說明 參考第2圖，在第一氧化膜1〇4上形成一主動層圖樣 106，換言之，藉由黃光微影過程形成一重度摻雜之多晶矽 圖樣106，如此該多晶矽圖樣106與一單元像素部位的該 黑色矩陣圖樣102有部分地重疊（第二光罩）。 5 每一單元像素部位形成該主動圖樣106。 非結晶矽可代替前述的重度摻雜之多晶矽用來作為該 主動層圖樣106。該主動層圖樣1〇6包括源極部位、汲極 部位及閘極部位。這些源極及汲極部位係藉由三價或五價 雜質離子的離子注入過程或離子摻雜過程而形成（第三、 10第四光罩）。於應用離子注入過程時，下述之閘極線可當作 一離子注入光罩。 任擇地，該主動層圖樣106可具有一輕度摻雜的汲極 (LDD)構造。 其次，在一包括該主動層圖樣1〇6的所得基材上形成 15 一第二氧化膜（如氧化矽膜）。 然後，如第3圖所示，為了將該黑色矩陣圖樣1〇2及 該主動層圖樣106以電連結，在該第二氧化膜⑽内形成 每一單7L像素至少有一第一接觸孔第五光罩 )，形成之該第一接觸孔位於該黑色矩陣圖樣1〇2之上。 2〇 較佳地，在該主動多晶矽層圖樣10ό上形成的該第二 氧化膜108以與該第一氧化膜1〇4相同的厚度形成。 其次，在包括該第一接觸孔的第二氧化膜1〇8上形成 間極圖樣11 〇 (第六光軍）。藉由沉積一雜質摻雜的多晶 矽膜或一金屬膜及圖樣化該多晶矽膜或該金屬膜來形成閘 12 200410416 玖、發明說明 極圖樣110。因該閘極圖樣11〇係藉由一使用該第二光罩 之黃光微影過程為圖樣化，且該第二光罩亦用於形成該黑 色矩陣圖樣102，故圖樣化的閘極圖樣11〇與該黑色矩陣 圖樣102有相同的形狀。 5 該閘極圖樣110包括一朝著該草圖的寬度方向被排列 的閘極線及一閘極電極；此閘極電極由該閘極線分支且與 該主動層圖樣1〇6的閘極部位相重疊。 任擇地，該閘極圖樣110或該黑色矩陣圖樣1〇2其中 · 之一者可以用島狀構造形成。 10 其次，在一包括該閘極圖樣110之所得基材的全部表 面上形成一第三氧化膜112。 然後，形成一曝露該第三氧化膜丨丨2之一預定部分（ - 如該主動層圖樣1〇6之源極部位）的第二接觸孔（第七光 - 罩）。 15 後來，一用作該資料線的金屬膜被沉積在包括該第二 接觸孔之該第三氧化膜112的全部表面上，此用作該資料 · 線的金屬膜藉由黃光微影過程而圖樣化以形成一資料線（ 未有圖式）（第八光罩）。 其次，在包括該資料線的該第三氧化膜112上形成一 、 20平坦化膜，該平坦化膜藉由黃光微影過程而圖樣化以形成 _ 一曝露主動層圖樣106之汲極部位的第三接觸孔（未有圖 式）（第九光罩）。 此犄，單位像素部位藉由該閘極線丨1〇及該資料線 118相互交錯而界定。為了在該界定的單位像素部位上形 13 200410416 玖、發明說明 、象素電極 透明的導電膜（如氧化銦錫（IT〇 )膜或 氧化I□鋅（ΙΖΟ)膜）以一預定的厚度被沉積，然後被圖 t 4匕乂幵7成、、星由δ亥第三接觸孔與該沒極電極相接觸的像素 電極。 5 在藉由前述過程形成的薄膜電晶體基材中，該主動層 圖樣106及該像素電極含有一經由該資料線注人的資料電 位，且因為該黑色矩陣圖樣102與該閘極線相接觸，所以 其含有一閘極電位。 具體實施你丨2 1〇 第5圖係依據本發明之另一具體實施例所表示之供 LCD用之薄膜電晶體基材的構造及製造過程的剖視圖。 參考第5圖，在一透明絕緣基材2〇〇上，一為防止光 自單位像素間洩漏的黑色矩陣圖樣2〇2被朝單一方向排列 〇 15 一第一乳化膜204被排列於該黑色矩陣202上，該第 一氧化膜204具有一曝露該黑色矩陣2〇2之一預定部分的 第一接觸孔206。 一第一主動多晶石夕層圖樣208及一第二主動多晶石夕層 圖樣210被排列於該第一氧化膜204上。該第一主動多晶 2〇矽層圖樣208位於該主動部位，該第二主動多晶石夕層圖樣 210被排列於该第一接觸孔2 0 6及其鄰近部分而且盘該零 色矩陣圖樣202相接觸。該第一主動多晶石夕層圖樣2丨丨包 括源極部位及汲極部位。 一第二氧化膜212、214被排列於該第一及第二主動多 14 200410416 玫、發明說明 晶石夕層圖樣208、210上。一閘極圖樣216被排列於該第二 氧化膜212、214的-選擇區域上。該閘極圖樣216包括一 沿著草圖的寬度方向被排列的閘極線及_閘極電極；此問 極電極由該閘極線分支且與該第一主動多晶矽圖樣2〇8之 5閘極部位相重疊。任擇地，該閘極線有一島狀構造或一被 該金屬線所跨接的構造。 一第二氧化膜被排列於包括該閘極圖樣2丨6的一所得 基材上。 一資料圖樣226被排列於該第三氧化膜上。該資料圖 10樣226與該閘極圖樣216相垂直，且經由形成於第二氧化 膜212内的該第二接觸孔22〇與該第一主動多晶矽層圖樣 208的源極部位相接觸。該第一資料圖樣226包括一形成 · 於该第一主動多晶矽層圖樣上的源極電極及一與該閘極線 - 垂直的資料線。 15 一第二資料圖樣228也被排列於該第三氧化膜218上 。該第二資料圖樣228經由形成於該第三氧化膜218内的 · 該第三接觸孔222及形成於該第三氧化膜218内的一第四 接觸孔224以電連結該閘極線216及該第二主動多晶石夕層 圖樣210 ;此第三氧化膜218位於該第二主動多晶石夕層圖 20樣210及其下之第二氧化膜214上面。藉由該第二資料圖 - 樣228及該第二主動多晶矽層圖樣210，該黑色矩陣圖樣 202與該閘極圖樣216 (如閘極線）為電接觸。 一平坦化膜（或一鈍化膜）230被排列於包括該第一 及苐一資料圖樣226及228的該第三氧化膜218上。一像 15 200410416 玖、發明說明 素電極被排列於該平坦化膜230上。 其次，吾人將描述具有上述提及之構造的供LCD用之 薄膜電晶體基材的製造方法。 藉由黃光微影過程在一透明絕緣基材200 (如石英（ 5 SlC>2 )或玻璃）上形成一較低黑色矩陣圖樣202，如此該 車乂低黑色矩陣圖樣202在單元像素部位之邊界線上被朝單 一方向排列。 任擇地，該黑色矩陣圖樣202並未被每一單元像素分 · 離而是被繼續地形成。 在包括3黑色矩陣圖樣202之該基材200的全部表面 上形成一尚溫氧化物（HTQ)來當作第一氧化膜204。 然後，藉由黃光微影過程在該第一氧化膜2〇4内形成 — 一第一接觸孔206。 - 在包括該第一接觸孔206的該第一氧化膜204上形成 15第一及第二主動層圖樣208、210，換言之，藉由黃光微影 過程形成重度摻雜的多晶矽圖樣208、210，如此該多晶石夕 · 圖樣與單元像素部位的該黑色矩陣圖樣202有部分地重疊 〇 在每一單元像素部位形成該第一及第二主動多晶矽層. 2〇 圖樣 208、210。 - 非結晶矽可代替前述之重度摻雜的多晶矽用來作為該 第一及第二主動多晶矽層圖樣208、210。該第一主動多曰 矽層圖樣208包括源極部位、汲極部位及閘極部位。這此 源極及汲極部位係藉由三價或五價雜質離子之離子注入過 16 200410416 程或離子摻雜過程而形成。於應用該離子注入過程時，下 述之閘極線可當作一離子注入光罩。 任擇地’ 4第一及第二主動多晶石夕層圖樣2〇8、2 i 〇可 具有一輕度摻雜的汲極（LDD)構造。 5 其次，在該第一及第二主動多晶矽層圖樣208、210上 形成一第二氧化膜212、214 (如氧化矽膜）。該第二氧化 膜212、214僅在該相對應的第一及第二主動多晶矽層圖樣 208、210上形成。 · 然後，在ό亥第二氧化膜212的一預定部分上形成一閘 1〇極圖樣216。藉由沉積一雜質換雜的多晶石夕膜或一金屬膜 及圖樣化該多晶矽膜或該金屬膜來形成閘極圖樣216。因 該閘極圖樣216係藉由-使用該光罩之黃光微影過程為圖 · 樣化，且該光罩亦用於形成該黑色矩陣圖樣2〇2，故圖樣 _ 化的閘極圖樣216與該黑色矩陣圖樣2〇2有相同的形狀。 15 其次，在一包括該閘極圖樣216之所得基材的全部表 面上形成一第三氧化膜218。 · 然後，形成一第二接觸孔，一第三接觸孔及一第四接 觸孔224,此第一接觸孔曝露該第三氧化膜218及/或該第 一氧化膜212或214的一預定部分（如該第一主動多晶矽 2〇層圖樣208的源極部位）；此第三接觸孔曝露該閘極圖樣 216的一預定部分；此第四接觸孔224曝露該第二主動多 晶石夕層圖樣210的一預定部分。 隨後’一用於該資料圖樣的金屬膜被沉積於包括該第 二、第三及第四接觸孔220、222及224之該第三氧化膜 17 200410416 玖、發明說明 230的全部表面上。藉由黃光微影過程而圖樣化用於該資 料線的該金屬膜以形成一第一資料圖樣226及一第二資料 圖樣228。藉由形成該第二資料圖樣228，該閘極圖樣216 與該黑色矩陣圖樣202為電連結。 5 其次，在包括該第一及第二資料圖樣的該第三氧化膜 218上形成一平坦化膜230。藉由黃光微影過程而圖樣化該 平坦化膜230以形成一曝露該第一主動多晶石夕層圖樣2〇8 之汲極部位的第五接觸孔（未有圖式· 此時，藉由該閘極線及該資料線的相互交錯而界定單 10位像素部位。為了在該界定的單位像素部位上形成像素電 極，一透明導電膜（如氧化銦錫（IT〇)膜或氧化銦鋅（ ΙΖΟ)膜）以預定之厚度沉積，然後圖樣化以形成經由該 · 第五接觸孔與該沒極電極相接觸的像素電極。 _ 藉由前述過程形成的該薄膜電晶體基材内，該第一主 15動多晶石夕層圖樣208及該像素電極加具有一經由該資料 線注入的資料電位，且因為與該閘極線相接觸，所以該黑、 φ 色矩陣圖樣202含有一閘極電位。 此外’於該第-具體實施例中，因為黃光微影過程較 該閘極圖樣的沉積更早實施來形成曝露該黑色㈣圖樣《 ♦ -預定部分的該接觸孔’所以在雜質或其相似物存在下， — 可能導致該閘極圖樣與該閘極絕緣膜間的邊緣部分被污染 〇然而’ §亥第二具體實施例可 J J以維持该閘極圖樣與該閘極 絕緣膜間的邊緣部分在良好狀態。 如前所述，依據本發明，因為該黑色矩陣與該問極圖 18 玖、發明說明 樣有相同的圖樣，所以可以降低由於該閘極線開啟所導致 的失效。因為該黑色矩陣與該閘極圖樣係藉由使用相同的 光罩而开> 成，所以也可以增加產量。進一步言，當該閘極 線開啟發生時，該黑色矩陣可以當作該閘極線，如此可以 由與忒黑色矩陣相接觸的該氧化膜在該主動層形成該閘 極部位。 參考該等較佳實施例，吾人於此已經描述及以圖式說 明本發明，因此對熟習此技藝者而言，其將可清楚地明瞭 任何就本發明所為的各種修飾與變化並未脫離本發明的精 :與範圍。因此，吾人傾向認為任何落人該附加中請專利 乾圍及其相當者的本發明之修飾與變化，仍然為本發明所 涵蓋。 【圖式簡單說明】 糟由詳細說明具體實施例及參考附加圖式，本發明的 前述及其他優點將更加清楚。圖式如下： 第1圖至第3圖係依據本發明之一具體實施例所表示 之供LCD用之㈣電晶體基材的製造過程的平視圖。 第4圖係沿著第3圖之4_4,線的剖視圖。 第5圖係依據本發明之另-具體實施例所表示之供 L⑶用之薄膜電晶體基材_造及製造過㈣剖視圖。’、 200410416 玖、發明說叽 【囷式之主要元件代替符號表】 100透明絕緣基材 102較低黑色矩陣圖樣 104第一氧化膜 106主動多晶矽層圖樣 108第二氧化膜 110閘極圖才篆LCD (Liquid Crystal Display) and EPID have been used for video displays (such as TVs or monitors) for a long time. In terms of display quality and economic efficiency, CRTs have S and market share, but they also have shortcomings such as bulkiness, too much space, and high energy consumption. Nowadays, as various electronic components become smaller and lighter as a result of unification, and due to the rapid advancement of semiconductor technology, more power and energy are saved. Therefore, in response to this new territory, there is also a demand for slimmer, thinner, lighter and more energy efficient The call of the flat panel display. Among the various flat panel displays that have been developed, LCDs are thinner, lighter, more power efficient and energy efficient than other displays, and they have similar display quality to CRT, so LCDs are widely used in various electronic components. in. In addition, LCDs can be easily manufactured, so their use will be more widespread. A liquid crystal display is composed of two substrates, electrodes are formed in the substrates and liquid crystals are placed between the two substrates. The liquid crystal display is a member that controls the amount of light passing through the liquid crystal to perform a display operation by rearranging liquid crystal molecules by applying a voltage to the electrodes. In these LCDs, a general structure widely used includes two substrates, an electrode is formed on each substrate and a thin film transistor (TFT) is used to switch the voltage applied to the electrode. Generally, the electrode is formed on one of the two substrates. As the resolution of these LCD panels increases, the redundancy of the gate lines also increases. The increase in the redundancy of these gate lines improves the feasibility and the ability of the invention to explain the opening of the gate lines, which may cause Dead pixels. [Meiji] Summary of the Invention Therefore, the present invention specifically addresses one or more problems caused by the limitations and disadvantages of related technologies with respect to a thin film transistor substrate for a liquid crystal display and a manufacturing method thereof. One of the objectives of the present invention is to prevent the increase in the number of defective pixels caused by the gate line opening by allowing a black matrix to be used as the gate line instead of the opened gate line when the gate line opening occurs. Another object of the present invention is to maintain the boundary between the gate pattern and the gate insulating film in a good condition. Other features and advantages of the present invention will be presented in the following description, some of which will be clearly known from the description or learned by practicing the present invention. The objectives and other advantages of the present invention will be made clear and achieved through the structure specifically indicated in the text description, patent application scope, and additional drawings. In order to achieve these and other advantages and to be consistent with the purpose of the present invention, we have provided a thin film transistor substrate for a liquid crystal display as a specific embodiment and a general description. The thin film transistor substrate includes: a black matrix arranged between adjacent unit pixels on a transparent insulating substrate for preventing light from leaking between adjacent unit pixels; a first oxide formed on the black matrix Film; an active polycrystalline silicon layer pattern formed on an active portion of the first oxide film; a second oxide film formed on a substrate obtained, the obtained substrate including the active polycrystalline silicon layer pattern and an exposed black matrix A first contact hole of a predetermined portion of the gate; a gate line formed on a selected area of the second oxide film 200410416; description of the invention; and an electrical contact with the black matrix through the first contact hole; A second oxide film formed on the obtained substrate of the gate line, a data line formed on the third oxide film and perpendicular to the gate line; one on the third oxide film including the data line 5 The formed planarizing film and a pixel electrode formed on the planarizing film. Preferably, the black matrix has the same pattern shape as the gate line. Preferably, the first oxide film has the same thickness as the hafnium dioxide film formed on the active polycrystalline silicon layer pattern. Optionally, one of the black matrix or the gate line has an island-like structure. In order to further achieve these and other advantages and to be consistent with the purpose of the present invention, we provide a method for manufacturing a thin film transistor substrate for a liquid crystal display. The method includes the following steps: forming a black matrix between adjacent unit pixels on a transparent insulating substrate to prevent light from leaking between the adjacent unit pixels 15; forming a first oxide film on the black matrix; An active polycrystalline silicon layer pattern is formed on an active part on the first oxide film; a second oxide film is formed on a substrate including the main polysilicon layer pattern; and one of the second oxide films is selected A first contact hole exposing a selected portion of the black matrix is formed on a portion; a gate line is formed on a selected area of the second oxide film and the −20 first contact hole; A third oxide film is formed on the obtained base material of the polar wire; a second contact hole is formed in a predetermined portion of the third oxide film to expose a predetermined portion of the active polycrystalline stone layer pattern; A data line is formed on the oxide film and its predetermined portion; a flattening film is formed on the third oxide film including the data line; and a pixel electrode is formed on the flattening film. To the black The array and the gate line are formed by using the same mask. To further achieve these and other advantages and to be consistent with the purpose of the present invention, we have provided a thin film transistor substrate for a liquid crystal display. This thin film transistor The substrate includes a black matrix between adjacent unit pixels on a transparent insulating substrate, which is used to prevent light from leaking between adjacent unit pixels; a black matrix formed on the black matrix with an exposed black matrix; A predetermined portion of the first oxide film of the first contact hole; an active polycrystalline silicon layer pattern including a first and a second active polycrystalline silicon layer pattern, the first active polycrystalline silicon layer pattern being formed on a first oxide film In the active part, the pattern of the second active polycrystalline silicon layer is formed in the first contact hole and is in contact with the black matrix; a second oxide film formed on the pattern of the active polycrystalline silicon layer; and a selection of the second oxide film A gate line formed on the region; a third oxide film formed on a substrate including the gate line obtained; a shape formed on the second oxide film Data line that is perpendicular to the gate line and is in contact with a source portion of the first active polycrystalline silicon layer pattern through the second contact hole formed in the second oxide film; one is on the third oxide film A metal pattern formed thereon and electrically connected to the first active polycrystalline silicon layer pattern via the third contact hole and a fourth contact hole, the third contact hole formed on the gate electrode and the third oxide In the film, the fourth contact hole is formed in the second active polycrystalline silicon layer pattern and the third oxide film on the second oxide film below it, and one is formed on the third oxide film including the data line And a pixel electrode formed on the planarizing film. 200410416 发明, Description of the Invention I 丨 ^ ^ Fortunately, the gate line has an island structure or a structure that is bridged by the metal line. In order to further achieve these and other advantages, and in accordance with the purpose of the present invention, we provide a method for manufacturing a thin film transistor substrate for a liquid crystal display. The method includes the following steps: forming a black matrix between adjacent unit pixels on a transparent insulating substrate to prevent light from leaking between adjacent unit pixels; forming a first oxide film on the black matrix; A predetermined part of an oxide film forms a first contact hole exposing a predetermined part of the black matrix, a first active layer is formed on an active part on the first oxide film, and a first active layer pattern is formed on the first oxide layer. A contact hole forms a second active polycrystalline silicon layer pattern in contact with the black matrix; a second oxide film is formed on the first and second active polycrystalline silicon layer patterns; A gate pattern is partially formed; a third oxide film is formed on the obtained substrate including the gate pattern; and an active polycrystalline silicon layer is formed in the third oxide film and the 15th dioxide film below it A second contact hole in a source portion of one of the patterns, a third contact hole exposing a predetermined portion of the gate pattern, and a fourth contact hole exposing a predetermined portion of the second active polysilicon layer pattern Forming a first data pattern in contact with the source portion through the second contact hole on the third oxide film and a third and fourth contact through the third oxygen-20 film A second data pattern connecting the gate pattern with the second active-poly silicon layer pattern; forming a planarization film on the third oxide film including the first and second data patterns; and forming a planarization film on the third oxide film A pixel electrode is formed thereon. 10 200410416 Simple explanation of the attribute ‘By explaining the specific embodiment in detail and referring to the attached drawings, the present invention will be more clearly described in terms of other advantages. The drawings are as follows: Figures 1 to 3 are plan views of the manufacturing process of a thin film transistor substrate for an LCD according to a specific embodiment of the present invention. Fig. 4 is a sectional view taken along line 4-4, in Fig. 3; FIG. 5 is a cross-sectional view showing the structure and manufacturing process of a thin film transistor substrate for an LCD according to another embodiment of the present invention. [Embodiment Mode 3 10] Detailed description of Wei Jie's specific embodiment Now, I will explain the preferred embodiment of the present invention in detail with reference to the attached drawings. Embodiment 1 FIGS. 1 to 3 are plan views of a manufacturing process of a thin film transistor substrate for an LCD according to 15 of one embodiment of the present invention, and FIG. 4 is a view along FIG. 3 Sectional view of line 4-4. Refer to FIG. 1 'to form a lower black matrix pattern 102 on a transparent insulating substrate 100 (such as quartz (SiO2) or glass) by a yellow light lithography process, so that the lower black matrix pattern 102 is in the cell The boundary 20 of the pixel portion is aligned in a single direction (first mask). Optionally, the black matrix pattern 102 is not separated by each unit pixel but is continuously formed. A high temperature oxide (HTO) is formed on the entire surface of the substrate 100 including the black matrix pattern 102 as a first oxide film. 11 200410416 发明, description of the invention Referring to FIG. 2, an active layer pattern 106 is formed on the first oxide film 104, in other words, a heavily doped polycrystalline silicon pattern 106 is formed by a yellow light lithography process, so that the polycrystalline silicon pattern 106 and The black matrix pattern 102 in a unit pixel portion partially overlaps (the second mask). 5 The active pattern 106 is formed in each unit pixel portion. Amorphous silicon can be used as the active layer pattern 106 instead of the heavily doped polycrystalline silicon described above. The active layer pattern 106 includes a source portion, a drain portion, and a gate portion. These source and drain sites are formed by an ion implantation process or an ion doping process of trivalent or pentavalent impurity ions (third, tenth, and fourth photomasks). When an ion implantation process is used, the gate line described below can be used as an ion implantation mask. Optionally, the active layer pattern 106 may have a lightly doped drain (LDD) structure. Secondly, a second oxide film (such as a silicon oxide film) is formed on a substrate including the active layer pattern 106. Then, as shown in FIG. 3, in order to electrically connect the black matrix pattern 102 and the active layer pattern 106, at least one first contact hole of each single 7L pixel is formed in the second oxide film 孔Photomask), the first contact hole is formed above the black matrix pattern 102. 20 Preferably, the second oxide film 108 formed on the active polycrystalline silicon layer pattern 10 is formed with the same thickness as the first oxide film 104. Next, a pole pattern 11 0 is formed on the second oxide film 108 including the first contact hole (sixth light army). The gate is formed by depositing an impurity-doped polycrystalline silicon film or a metal film and patterning the polycrystalline silicon film or the metal film. 12 200410416 玖, invention description Pole pattern 110. Since the gate pattern 11 is patterned by a yellow light lithography process using the second mask, and the second mask is also used to form the black matrix pattern 102, the patterned gate pattern 11 It has the same shape as the black matrix pattern 102. 5 The gate pattern 110 includes a gate line and a gate electrode aligned in the width direction of the sketch; the gate electrode is branched from the gate line and is at the gate portion of the active layer pattern 106 Mutual overlap. Optionally, one of the gate pattern 110 or the black matrix pattern 102 can be formed with an island structure. 10 Next, a third oxide film 112 is formed on the entire surface of the obtained substrate including the gate pattern 110. Then, a second contact hole (seventh light mask) is formed that exposes a predetermined portion of the third oxide film 2-such as the source portion of the active layer pattern 106. 15 Later, a metal film used as the data line was deposited on the entire surface of the third oxide film 112 including the second contact hole. The metal film used as the data line was patterned by the yellow light lithography process. To form a data line (not shown) (eighth mask). Secondly, a flattening film of 20 and 20 is formed on the third oxide film 112 including the data line, and the flattening film is patterned by a yellow light lithography process to form a first exposed portion of the drain portion of the active layer pattern 106 Three contact holes (not shown) (ninth mask). Here, the unit pixel portion is defined by the gate lines 10 and the data lines 118 interlaced with each other. In order to form 13 200410416 玖 on the defined unit pixel portion, a conductive film (such as an indium tin oxide (IT〇) film or an zinc oxide (IZO) film) having a transparent pixel electrode is formed with a predetermined thickness. It is deposited, and then the pixel electrode in contact with the non-polar electrode is formed by the third contact hole of δH, as shown in FIG. 5 In the thin film transistor substrate formed by the foregoing process, the active layer pattern 106 and the pixel electrode contain a data potential injected through the data line, and because the black matrix pattern 102 is in contact with the gate line , So it contains a gate potential. The specific implementation diagram 2 5 is a cross-sectional view of a structure and a manufacturing process of a thin film transistor substrate for an LCD according to another embodiment of the present invention. Referring to FIG. 5, on a transparent insulating substrate 200, a black matrix pattern 200 for preventing light from leaking between unit pixels is arranged in a single direction. 15 A first emulsion film 204 is arranged on the black On the matrix 202, the first oxide film 204 has a first contact hole 206 that exposes a predetermined portion of the black matrix 202. A first active polycrystalline silicon layer pattern 208 and a second active polycrystalline silicon layer pattern 210 are arranged on the first oxide film 204. The first active polycrystalline silicon layer pattern 208 is located at the active portion, the second active polycrystalline silicon layer pattern 210 is arranged at the first contact hole 206 and its adjacent parts and the zero-color matrix pattern is arranged. 202 is in contact. The first active polycrystalline stone layer pattern 2 includes a source portion and a drain portion. A second oxide film 212, 214 is arranged on the first and second active layers 14 200410416, and the invention description spar pattern 208, 210. A gate pattern 216 is arranged on a selected area of the second oxide films 212, 214. The gate pattern 216 includes a gate line and a gate electrode arranged along the width direction of the sketch; the interrogation electrode is branched from the gate line and is connected to the first active polysilicon pattern 5 gate 5 The parts overlap. Optionally, the gate line has an island-like structure or a structure spanned by the metal wire. A second oxide film is arranged on a resultant substrate including the gate pattern 21-6. A data pattern 226 is arranged on the third oxide film. The data pattern 226 is perpendicular to the gate pattern 216, and is in contact with the source portion of the first active polysilicon layer pattern 208 through the second contact hole 22o formed in the second oxide film 212. The first data pattern 226 includes a source electrode formed on the first active polysilicon layer pattern and a data line perpendicular to the gate line. A second data pattern 228 is also arranged on the third oxide film 218. The second data pattern 228 is electrically connected to the gate lines 216 and the third contact hole 222 formed in the third oxide film 218 and a fourth contact hole 224 formed in the third oxide film 218. The second active polycrystalline silicon layer pattern 210; the third oxide film 218 is located on the second active polycrystalline silicon layer pattern 20 and the second oxide film 214 below it. With the second data pattern-pattern 228 and the second active polysilicon layer pattern 210, the black matrix pattern 202 is in electrical contact with the gate pattern 216 (such as a gate line). A planarizing film (or a passivation film) 230 is arranged on the third oxide film 218 including the first and first data patterns 226 and 228. One is like 15 200410416. Explanation of the invention The element electrodes are arranged on the planarizing film 230. Next, I will describe a method for manufacturing a thin film transistor substrate for an LCD having the above-mentioned configuration. A yellow black lithography process is used to form a lower black matrix pattern 202 on a transparent insulating substrate 200 (such as quartz (5 SlC> 2) or glass), so that the low black matrix pattern 202 is on the boundary line of the unit pixel portion. Arranged in a single direction. Optionally, the black matrix pattern 202 is not separated by each unit pixel but is continuously formed. A high temperature oxide (HTQ) is formed on the entire surface of the substrate 200 including the three black matrix patterns 202 as the first oxide film 204. Then, a first contact hole 206 is formed in the first oxide film 204 through a yellow light lithography process. -Forming 15 first and second active layer patterns 208, 210 on the first oxide film 204 including the first contact hole 206, in other words, heavily doped polycrystalline silicon patterns 208, 210 are formed by a yellow light lithography process, and so on The polycrystalline stone pattern partially overlaps the black matrix pattern 202 of a unit pixel portion. The first and second active polycrystalline silicon layers are formed at each unit pixel portion. 2o patterns 208, 210. -Amorphous silicon can be used as the first and second active polycrystalline silicon layer patterns 208, 210 instead of the heavily doped polycrystalline silicon described above. The first active silicon layer pattern 208 includes a source portion, a drain portion, and a gate portion. The source and drain sites are formed by ion implantation of trivalent or pentavalent impurity ions through the process of 16 200410416 or ion doping. In applying the ion implantation process, the gate line described below can be used as an ion implantation mask. Optionally, the first and second active polycrystalline crystalline layers patterns 208, 2 i 0 may have a lightly doped drain (LDD) structure. 5 Next, a second oxide film 212, 214 (such as a silicon oxide film) is formed on the first and second active polycrystalline silicon layer patterns 208, 210. The second oxide films 212 and 214 are formed only on the corresponding first and second active polycrystalline silicon layer patterns 208 and 210. Then, a gate 10-pole pattern 216 is formed on a predetermined portion of the second oxide film 212. The gate pattern 216 is formed by depositing an impurity-doped polycrystalline silicon film or a metal film and patterning the polycrystalline silicon film or the metal film. The gate pattern 216 is patterned by the yellow light lithography process using the mask, and the mask is also used to form the black matrix pattern 202. Therefore, the pattern gate pattern 216 and The black matrix pattern 202 has the same shape. 15 Next, a third oxide film 218 is formed on the entire surface of the obtained substrate including the gate pattern 216. Then, a second contact hole, a third contact hole, and a fourth contact hole 224 are formed. The first contact hole exposes the third oxide film 218 and / or a predetermined portion of the first oxide film 212 or 214. (Such as the source portion of the first active polycrystalline silicon 20 layer pattern 208); the third contact hole exposes a predetermined portion of the gate pattern 216; the fourth contact hole 224 exposes the second active polycrystalline silicon layer A predetermined portion of the pattern 210. Subsequently, a metal film for the data pattern is deposited on the entire surface of the third oxide film 17 200410416 (the invention film 230) including the second, third, and fourth contact holes 220, 222, and 224. The metal film for the data line is patterned by a yellow light lithography process to form a first data pattern 226 and a second data pattern 228. By forming the second data pattern 228, the gate pattern 216 and the black matrix pattern 202 are electrically connected. 5 Next, a planarization film 230 is formed on the third oxide film 218 including the first and second data patterns. The planarization film 230 is patterned by a yellow light lithography process to form a fifth contact hole that exposes the drain portion of the first active polycrystalline crystalline layer pattern 208 (no pattern. At this time, by The gate line and the data line are mutually staggered to define a single 10-bit pixel portion. In order to form a pixel electrode on the defined unit pixel portion, a transparent conductive film such as an indium tin oxide (IT0) film or indium zinc oxide (IZO) film) is deposited at a predetermined thickness, and then patterned to form a pixel electrode in contact with the electrode electrode via the fifth contact hole. _ In the thin film transistor substrate formed by the foregoing process, the The first main 15 moving polycrystalline stone layer pattern 208 and the pixel electrode have a data potential injected through the data line, and because it is in contact with the gate line, the black and φ color matrix pattern 202 contains a gate. In addition, in the first embodiment, the yellow light lithography process is performed earlier than the deposition of the gate pattern to form the exposure of the black cymbal pattern "♦-the contact hole of a predetermined portion". similar In the presence of objects, — it may cause the edge portion between the gate pattern and the gate insulating film to be contaminated. However, the second embodiment may be JJ to maintain the edge between the gate pattern and the gate insulating film. Some are in good condition. As mentioned earlier, according to the present invention, because the black matrix has the same pattern as that of the question pole figure 18 and the description of the invention, the failure caused by the gate line turning on can be reduced. The black matrix and the gate pattern are formed by using the same mask, so the yield can also be increased. Furthermore, when the gate line is turned on, the black matrix can be used as the gate line. In this way, the gate portion can be formed on the active layer by the oxide film in contact with the osmium black matrix. With reference to the preferred embodiments, I have described and illustrated the invention herein, so for those skilled in the art In terms of it, it will be clear that any modifications and changes made to the present invention do not depart from the essence and scope of the present invention. Therefore, we tend to think that any one that falls into the scope of this addition Modifications and variations of the invention of the patent patent and its equivalents are still covered by the present invention. [Brief Description of the Drawings] The foregoing and other advantages of the present invention will be more detailed by explaining specific embodiments in detail and referring to additional drawings. It is clear. The drawings are as follows: Figures 1 to 3 are plan views of the manufacturing process of the Cryptoelectric crystal substrate for LCD according to a specific embodiment of the present invention. Figure 4 is along Figure 3. Section 4_4, a cross-sectional view of the line. Figure 5 is a cross-sectional view of the thin film transistor substrate for LCU shown in another embodiment of the present invention. The main components of the formula replace the symbol table] 100 transparent insulating substrate 102 lower black matrix pattern 104 first oxide film 106 active polycrystalline silicon layer pattern 108 second oxide film 110 gate pattern
112第三氧化膜 202黑色矩陣圖樣 204第一氧化膜 206第一接觸孔 208第一主動多晶矽層圖樣 210第二主動多晶矽層圖樣 212第二氧化膜 214第二氧化膜112 Third oxide film 202 Black matrix pattern 204 First oxide film 206 First contact hole 208 First active polycrystalline silicon layer pattern 210 Second active polycrystalline silicon layer pattern 212 Second oxide film 214 Second oxide film
216閘極圖樣 218第三氧化膜 220第二接觸孔 222第三接觸孔 224第四接觸孔 226第一資料圖樣 228第二資料圖樣 230平坦化膜 232像素電極 20216 Gate pattern 218 Third oxide film 220 Second contact hole 222 Third contact hole 224 Fourth contact hole 226 First data pattern 228 Second data pattern 230 Flattening film 232 Pixel electrode 20