TW200409222A - Semiconductor texturing process - Google Patents
Semiconductor texturing process Download PDFInfo
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- TW200409222A TW200409222A TW091135225A TW91135225A TW200409222A TW 200409222 A TW200409222 A TW 200409222A TW 091135225 A TW091135225 A TW 091135225A TW 91135225 A TW91135225 A TW 91135225A TW 200409222 A TW200409222 A TW 200409222A
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- 229910052581 Si3N4 Inorganic materials 0.000 claims description 26
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 26
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- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0236—Special surface textures
- H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Photovoltaic Devices (AREA)
- Weting (AREA)
Abstract
Description
200409222 玖、發明說明 (發明說明應敘明：發明所屬之技術領域、先前技術、內容、實施方式及圖式簡單說明） 【發明所屬之技術領域】 本發明係與一種在一半導體之一表面上刻紋之方法有 。 關，以及有關於一種半導體材料，其表面具有紋路，以降 低其反射率，且/或可增加該半導體吸收光線的能力。 5 【先前技術】 為了增加矽太陽能電池、檢測器或是光電二極體的效 率，最重要的是增加吸收於矽中的波長小於llOOnm的光 · 線的總量。一般有兩種方式會造成光吸收的總量降低。光 10 線被矽的表面反射，或者進入矽中並且未被吸收的光線在 一段時間後離開矽。前述之二種方式可以將矽表面粗造化 或刻紋之方式來降低。降低光反射損失是藉由增加光線多 _ 次撞擊矽表面的機率而達成，而降低光吸收損失是藉由限 制光於矽中（亦稱為光捕捉）。 15 一種刻紋技術，其係利用蝕刻（100)方位之單晶體矽， 所使用的溶液為氫氧化鉀（potassium hydroxide, KOH)以及 異丙醇（isopropyl alcohol，IPA)。其結果會造成一表面被複 鲁 數個方形基底的錐體所覆蓋。然而，這種方式不可以應用 於非（100)結晶方位（crystallographic orientation)的石夕表 20 面。其他還有數種發展中的刻紋技術，其不必僅應用於一 — 特定之結晶方位，例如活性離子#刻（reactive ion etching， RIE)。然而，這些技術所需之費用相當昂貴，而且會造成 其他缺點，例如會增加矽表面上的媒介再組合。此外，這 些技術僅可適用於在平面的晶圓上刻紋，而且不能適用 ϋ續次頁（發明說明頁不敷使用時，請註記並使用續頁） -4- 200409222 發明說明$賣;Μ 在固疋於晶圓架的發條之未被暴露的表面上刻200409222 发明, description of the invention (the description of the invention should state: the technical field, prior art, content, embodiments, and drawings of the invention briefly) [Technical field to which the invention belongs] The present invention relates to a surface of a semiconductor There are methods for engraving. And related to a semiconductor material, the surface of which has a texture to reduce its reflectivity, and / or to increase the semiconductor's ability to absorb light. 5 [Previous technology] In order to increase the efficiency of silicon solar cells, detectors, or photodiodes, the most important thing is to increase the total amount of light and light with a wavelength less than 110 nm that is absorbed in silicon. There are generally two ways to reduce the total amount of light absorption. The light 10 lines are reflected by the surface of the silicon, or the light that enters the silicon and is not absorbed leaves the silicon after a period of time. The two methods mentioned above can be reduced by roughening or engraving the silicon surface. Reducing the light reflection loss is achieved by increasing the probability of light hitting the silicon surface multiple times, and reducing the light absorption loss is by limiting the light in the silicon (also known as light capture). 15 An engraving technique that uses single crystal silicon with an etched (100) orientation. The solutions used are potassium hydroxide (KOH) and isopropyl alcohol (IPA). As a result, a surface is covered by a plurality of square-shaped cones. However, this method cannot be applied to non- (100) crystallographic orientation of Shixi surface. There are several other engraving techniques in development, which need not be applied only to a specific crystal orientation, such as reactive ion etching (RIE). However, these technologies are quite expensive and cause other disadvantages, such as increased media recombination on the silicon surface. In addition, these technologies can only be applied to engraving on flat wafers, and cannot be used. (Continued pages are used when the description page of the invention is insufficient. Please note and use the continued page.) Engraving on the unexposed surface of the mainspring which is fixed to the wafer frame
相關的先前技術揭露於世界專利申#荦泸WQ 02/45143中。 牙〜T明案唬WO 5 【發明内容】 本發明之主要目的在於提供一種半導體刻紋方法，其 可降低半導體表面的反射率。 為達成前述之發明目的，本發明第—較佳實施例係提 供一種半導體刻紋方法，其係用以在—半導體材料之一表 10面上刻紋，包含有下列步驟： 設置一保護體層於前述之半導體材料之表面上，其中 該保護體層的厚度相㈣，而且具有複數個微孔，以及 使該保護體層與該半導體材料接觸一蝕刻劑，且該蝕 刻劑鞋刻該半導體材料的速率快於該保護體層，該蝕刻劑 15是至少經由該等微孔而與該半導體材料接觸，經預定的時 間與在預定的條件下，該半導體材料會在鄰近該等微孔的 部位被該蝕刻劑所蝕刻，藉以使該半導體形成一具有刻紋 之表面，但是該保護體層大體上未被蝕刻。 設置該保護體層的步驟可為一單一步驟，或者其可先 20製造一保護體層，其僅具有少數之微孔或無微孔，接著將 該保護體層變薄，直到其上形成複數個微孔。該保護體層 原先並不是呈現光滑的狀態，而後使其某些部分比其他部 分變薄。因此’當保護體層的表面與蝕刻劑接觸後，其上 較薄的部分會比其他部分先被蝕刻掉，而形成前述之微 -5- 200409222 發明說明$賣;1； 孔。 基此，本發明第二較佳實施例提供一種半導體刻紋製 一 程，其係用以在一半導體材料之表面刻紋路，包含有下列 步驟： - 5 設置一保護體層於前述之半導體材料之表面上； 大體均勻地使該保護體層變薄，直到該保護體層形成 複數個微孔，以及 使該保護體層與該半導體材料接觸一能夠蝕刻該半導 · 體材料比餘刻该保護體層還快的姓刻劑，該姓刻劑至少是 10經由該等微孔而與該半導體材料接觸，經預定的時間與在 預定的條件下，該半導體材料會在鄰近該等微孔的部位被 該蝕刻劑所蝕刻，藉以使該半導體形成一具有刻紋之表 面，但是該保護體層大體上並未被蝕刻。 本發明第三較佳實施例是提供一種半導體材料，其至 - 15少具有一表面，而該表面至少有一部分具有複數個凹窩， 其中該等凹窩係呈不規則之狀態分佈於該表面上，而且該 等凹窩各具有一内側面，其至少一部分係呈圓形。 鲁 本發明第四實施例係提供一種半導體材料，其至少具 有一表面，而該表面至少有一部分具有複數個凹窩，其中 k 20該等凹窩係呈不規則之狀態分佈於該表面上，而且該等凹 - 窩見度不超過ΙΟμι^ι。 本發明第五實施例係提供一種半導體，其一表面上之 至少一部分是利用本發明第一或第二實施例所提供的方法 刻上紋路。 -6_ 200409222 發明說明 本發明第六實施例係提供一種半導體，其具有一表 面，該表面上至少有一部分被刻紋，其是利用透過設於該 表面上之一保護體層的多數個微孔而蝕刻該表面者，而該 保護體層之微孔是以將該保護體層變薄之方式形成的。 5 本發明更提供一種半導體材料，其至少一表面之至少 一部分設置有一保護體層，該保護體層具有複數個微孔， 而該微孔是以將該保護體層變薄之方式形成的。 利用本發明所提供之刻紋方法刻上紋路之半導體材 料，可應用於製造太陽能電池。是以，本發明第七實施例. 10 是提供一種太陽能電池，其具有如第三至第六較佳實施例 所述之半導體材料者。 在本發明所提供之製程中，其所謂之”大體上未被蝕 刻（substantially unetched)”是表示餘刻發生於以下之狀 況：該半導體材料（semiconductor material)在鄰近保護體 15 (protective substance)上所具有之微孔（apertures)附近之部 份被蝕刻，然而直至蝕刻完畢，足夠的保護體仍保留在該 半導體材料之表面’以保護該半導體，避免該半導體在非 鄰近該微孔之區域亦被蝕刻者。 ‘‘大體均勻（substantially uniformly)”是表示薄化 20 (thining)發生於以下之狀況：保護體層之所有表面大約以 相同之速率被薄化，以致於，在一預定時間内，保護體層 表面之所有部份均被移除大約相同之厚度。 在本發明所提供之製程中，該保護體可為任何物質其 可抵抗蝕刻中之至少一種可蝕刻半導體材料之蝕刻劑 200409222 發明說明$賣頁 (etchant)，或者是至少可被至少一钱刻劑所姓刻，但是其 被該蝕刻劑蝕刻掉之速率明顯慢於半導體材料被蝕刻掉之 速率，因此，本發明之製程中會出現大體未被蝕刻之現象。 在第一較佳實施例之製程中，保護體所形成之層之厚 5 度大約只有幾個原子，其可以任何既知的技術，例如化學 蒸氣沉積法（chemical vapour deposition)或是低壓化學蒸氣 沉積法（low pressure vapour deposition)，來達成。其他可 能之技術用來應用於該保護體的包括有熱解射出（spray pyrolysis)、蒸發法（evaporati〇n)、賤渡法（sputtering)、熱 10 氧化法（thermal oxidation)或是熱氮化法（thermal nitridation) 等。更有另一種選擇，該保護體所形成之層可為一聚合物 層，卫將其施用於半導體之表面以形成一層，其厚度相當 薄以致於其上具有多數個微孔。在此狀態下之第一較佳實 施例，該钱刻步驟以電漿蝕刻較為適合。而聚合物之設置 15 是以旋轉塗佈（spin coating)較為適合。較為適合之聚合物 有·用於積體電路製程之光阻聚合物（polymeric photoresists)。較為適當之用於蝕刻矽之電漿為六氟化硫 (SF6) ’四氟化碳（CF4)以及四氟化碳（CF4)與氧之混合物。 在本發明第一較佳實施例之製程之一形式中，該保護 20 體層是以低壓蒸氣沉積法所形成，其厚度大約為2 nm， 而且其為一未完整之層（incomplete layer)，因此其具有多 數個微孔，以致於在微孔下方之半導體材料可被蝕刻掉。 在本發明第二較佳實施例中，該保護體層可以第一較 佳實施例中所述之任一方法沉積該半導體材料上。在第二 -8- 200409222 發明說明$賣頁 較佳實施例之製程中，被沉積之該保護體層之厚度大於該 第-較佳實施例所述之厚度，以致於當該保護體層被設置 ^ 於該半導體材料上時是沒有微孔的。然而，一個被設置於 -表面上之保護體層是不可能具有完全均勻的厚度，而當 5如此的保護體層被逐漸薄化的過程中，最終會有複數個微 孔在I虫刻前最薄的位置形成。換言之，當該層被薄化，該 層之厚度大體上會一致地減少，直到某些部位被穿透，如 此该保護體層上即形成複數個微孔。 在本發明第二較佳實施例中，薄化該保護體層之步驟 10基本上係為-典型的钱刻步驟，使用之敍刻劑可為任何可 以均勻地I虫刻該保護體之敍刻劑。該等敍刻劑為熟知本項 技勢者所熟知的，包括有各種酸、酉复混合物以及電裝。如 果該保護體為聚合物，最好是使用電漿餘刻法來薄化該保 護體層，典型的是使用氧電漿。 - 15 基本上，在該保護體層中之微孔大體上是隨機分佈於 該保護體的表面上，因為微孔是由於該保護體層厚度的不 同所產生的。因此，當進行過第一或第二實施例之步驟後， · 該半導體材料會留下蝕刻所形成之凹窩，其為隨機分佈於 該半導體材料之表面。該等蝕刻凹窩的内側面，其可視為 、 2〇該半導體材料表面之中空部分，通常，但不是一定，為至 少一部分是圓形。亦即，雖然該等蝕刻凹窩内側面上具有 許多琢面（faceting)，該内側面上之至少一部分通常未被琢 面而且是平面，而是因蝕刻劑作用在該半導體材料上之、社 果會出現至少一部分的凹形區域。最典型的，該蝕刻凹嵩 -9- 200409222 5 10 15 發明說明, 的内侧面至少-半為圓形的。最好，該餘刻凹寫的内側面 上大體沒有琢面。該等蝕刻凹窩由其上方來看9除非凹窩 交錯，典型上為圓形。然而在某些情況下，該等蝕刻凹窩 尤其上方觀之大體是並不是圓形的，其是與該半導體材料 之結晶方向有關。無論該等蝕刻凹窩的形狀為何，其直徑 最高大約為ΙΟμιη。通常該等蝕刻凹窩的尺寸範圍在低於 Ιμηι到大約5μηι之間。該等蝕刻凹窩間係由若干牆所區 格，該等牆的厚度比凹窩寬度薄。通常，至少有一^分的 牆大體上未被蝕刻的。然而，多數的牆是形成於該等重疊 的蝕刻凹窩之間，因此形成於其上方之一點。 在第一與第二實施例中所使用的蝕刻劑可以為任何可 蝕刻半導體材料速率快於蝕刻該保護體的蝕刻劑。如此之 蝕刻劑為熟知本項技藝者所熟知的。當一種蝕刻劑被利用 於第二實施例之步驟以使保護體層變薄時，其可為相同或 疋不同於餘刻半導體的餘刻劑。如果該保護體層為聚合物 層’電漿是通常被利用於蝕刻半導體者。The related prior art is disclosed in World Patent Application # 荦 泸 WQ 02/45143.牙 ～ T 明 案 WO5 [Summary of the invention] The main object of the present invention is to provide a semiconductor engraving method, which can reduce the reflectance of the semiconductor surface. In order to achieve the foregoing object of the present invention, a first preferred embodiment of the present invention provides a semiconductor engraving method, which is used for engraving on the surface of one of the semiconductor materials, and includes the following steps: a protective layer is disposed on On the surface of the aforementioned semiconductor material, the thickness of the protective layer is relatively large, and the protective layer has a plurality of micropores, and the protective layer is in contact with the semiconductor material with an etchant, and the etchant shoe engraves the semiconductor material quickly In the protective body layer, the etchant 15 is in contact with the semiconductor material at least through the micropores. After a predetermined time and under predetermined conditions, the semiconductor material will be subjected to the etchant in the vicinity of the micropores. It is etched so that the semiconductor forms a textured surface, but the protective body layer is substantially unetched. The step of setting the protective body layer may be a single step, or it may first manufacture a protective body layer with only a few micropores or no micropores, and then thin the protective body layer until a plurality of micropores are formed thereon. . The protective layer did not appear smooth at first, but then made some parts thinner than others. Therefore, when the surface of the protective body layer is in contact with the etchant, the thinner part of the protective body layer is etched away before the other parts, and the aforementioned micro -5- 200409222 invention description is sold; 1; holes. Based on this, the second preferred embodiment of the present invention provides a semiconductor engraving process, which is used for engraving the surface of a semiconductor material, and includes the following steps:-5 setting a protective layer on the aforementioned semiconductor material On the surface, the protective body layer is thinned substantially uniformly until the protective body layer forms a plurality of micropores, and the protective body layer is in contact with the semiconductor material. The semiconductor material can be etched faster than the protective body layer in the rest The last name is an etching agent of at least 10 which comes into contact with the semiconductor material through the micropores. After a predetermined time and under predetermined conditions, the semiconductor material will be etched near the micropores. The protective agent layer is etched, so that the semiconductor forms a textured surface, but the protective body layer is not substantially etched. A third preferred embodiment of the present invention is to provide a semiconductor material having at least -15 at least one surface, and at least a part of the surface has a plurality of dimples, wherein the dimples are distributed on the surface in an irregular state. The dimples each have an inner side surface, at least a part of which is circular. The fourth embodiment of the present invention provides a semiconductor material having at least one surface, and at least a part of the surface has a plurality of dimples, wherein k 20 dimples are distributed on the surface in an irregular state. And the visibility of the pits is not more than 10μ ^^ ι. A fifth embodiment of the present invention provides a semiconductor, and at least a portion of a surface thereof is engraved with a method provided by the first or second embodiment of the present invention. -6_ 200409222 Description of the invention A sixth embodiment of the present invention provides a semiconductor having a surface, at least a portion of which is engraved, which uses a plurality of micropores through a protective layer provided on the surface. Those who etch the surface, and the micropores of the protective body layer are formed by thinning the protective body layer. 5 The present invention further provides a semiconductor material, at least a part of at least one surface of which is provided with a protective body layer, the protective body layer has a plurality of micropores, and the micropores are formed by thinning the protective body layer. The semiconductor material engraved with the engraving method provided by the present invention can be applied to manufacture solar cells. Therefore, the seventh embodiment of the present invention. 10 is to provide a solar cell having the semiconductor material according to the third to sixth preferred embodiments. In the process provided by the present invention, the so-called "substantially unetched" means that the remaining state occurs in the following situation: the semiconductor material is on the protective substance 15 adjacent to it The parts near the micropores are etched, but until the etching is completed, sufficient protective bodies remain on the surface of the semiconductor material 'to protect the semiconductor and avoid the semiconductor in areas not adjacent to the microholes. Etched. “Substantially uniformly” means that thinning 20 occurs when all surfaces of the protective body layer are thinned at approximately the same rate, so that, within a predetermined time, the surface of the protective body layer is thinned. All parts are removed about the same thickness. In the process provided by the present invention, the protective body can be any substance which can resist at least one etchable semiconductor material in etching. etchant), or it can be engraved with at least one money engraving agent, but the rate at which it is etched away by the etchant is significantly slower than the rate at which semiconductor materials are etched out. Therefore, in the process of the present invention, the The phenomenon of etching. In the process of the first preferred embodiment, the layer formed by the protective body has a thickness of about 5 atoms, which can be any known technique, such as chemical vapour deposition or chemical vapour deposition. Low pressure vapour deposition. Other possible techniques are used for the protection body. Including spray pyrolysis, evaporation method, sputtering method, thermal oxidation method or thermal nitridation method, etc. There is another option The layer formed by the protective body may be a polymer layer, which is applied to the surface of the semiconductor to form a layer, and its thickness is so thin that there are many micropores thereon. The first in this state is better In the embodiment, plasma etching is more suitable for the money engraving step. The spin coating is more suitable for the polymer setting 15. The more suitable polymers are: photoresist polymers for integrated circuit manufacturing processes (Polymeric photoresists). A more suitable plasma for etching silicon is sulfur hexafluoride (SF6) 'carbon tetrafluoride (CF4) and a mixture of carbon tetrafluoride (CF4) and oxygen. In the first comparison of the present invention, In one form of the manufacturing process of the preferred embodiment, the protective layer 20 is formed by a low-pressure vapor deposition method, has a thickness of about 2 nm, and is an incomplete layer, so it has a plurality of micropores. To The semiconductor material under the microholes can be etched away. In the second preferred embodiment of the present invention, the protective body layer can be deposited on the semiconductor material by any of the methods described in the first preferred embodiment. On the second -8- 200409222 Description of the Invention In the manufacturing process of the preferred embodiment, the thickness of the protective body layer deposited is greater than the thickness described in the first preferred embodiment, so that when the protective body layer is provided on the semiconductor There is no microporosity in the material. However, it is impossible for a protective body layer provided on the surface to have a completely uniform thickness, and when 5 such a protective body layer is gradually thinned, there will eventually be a plurality of micropores that are the thinnest before the engraving. The location is formed. In other words, when the layer is thinned, the thickness of the layer is reduced substantially uniformly until some parts are penetrated, and thus a plurality of micropores are formed in the protective layer. In the second preferred embodiment of the present invention, the step 10 of thinning the protective body layer is basically a typical money engraving step. The engraving agent used may be any engraving that can evenly engrav the protective body. Agent. Such engravers are well known to those skilled in the art and include various acids, complex compounds, and electrical equipment. If the protective body is a polymer, it is preferable to use a plasma etching method to thin the protective body layer, and an oxygen plasma is typically used. -15 Basically, the micropores in the protective body layer are substantially randomly distributed on the surface of the protective body, because the micropores are caused by the thickness of the protective body layer. Therefore, after performing the steps of the first or second embodiment, the semiconductor material will leave pits formed by etching, which are randomly distributed on the surface of the semiconductor material. The inner side of the etched dimples can be regarded as a hollow part of the surface of the semiconductor material. Usually, but not necessarily, at least a part is circular. That is, although there are many facetings on the inside surface of the etch dimples, at least a part of the inside surface is usually not faceted and is flat, but because the etchant acts on the semiconductor material, the As a result, at least a part of the concave area will appear. Most typically, the etched recess -9-200409222 5 10 15 invention description, the inner side is at least-semi-circular. Preferably, the indentation has substantially no facets on the inside side. The etched dimples are viewed from above 9 unless the dimples are staggered, typically circular. However, in some cases, the etched dimples, especially when viewed from above, are generally not circular, which is related to the crystalline direction of the semiconductor material. Regardless of the shape of the etched dimples, the diameter is up to about 10 μm. The size of such etched dimples generally ranges from less than 1 μm to about 5 μm. The etched dimples are defined by walls that are thinner than the width of the dimples. Usually, at least one minute of the wall is largely unetched. However, most walls are formed between these overlapping etched dimples and are therefore formed at a point above them. The etchant used in the first and second embodiments may be any etchant that can etch the semiconductor material faster than the etchant. Such etchants are well known to those skilled in the art. When an etchant is used in the step of the second embodiment to make the protective layer thin, it may be the same or different from the remaining semiconductor. If the protective layer is a polymer layer, the plasma is usually used for etching semiconductors.
本發明之製程之目的在於減低一半導體材料之表面之 反射性，有別於一拋光表面，以及/或者改進半導體材料 中之光限制（光捕捉）(light confinement (light trapping))。 本發明之製程中，癥結點在於該半導體表面之刻紋之 最佳程度是否已經到達以及何時蝕刻應被停止，其以幾種 方式來決定。其中一種方式為監視被刻紋的表面，例如藉 由目視或是以可量測光在表面的反射性的裝置來達成。第 二種方式為預定一些條件（亦即保護體的本質、厚度、蝕The purpose of the process of the present invention is to reduce the reflectivity of the surface of a semiconductor material, to distinguish it from a polished surface, and / or to improve light confinement (light trapping) in semiconductor materials. In the process of the present invention, the crux of the problem lies in whether the optimal degree of engraving on the semiconductor surface has been reached and when etching should be stopped, which is determined in several ways. One way is to monitor the engraved surface, for example, by visual inspection or by a device that measures the reflectance of light on the surface. The second way is to predetermine some conditions (that is, the nature, thickness,
-10- 20 200409222 刻劑的成分以及溫度）時間以取得最佳的結果。這可由在 適當條件下的蝕刻範例來得到，例如在不同蝕刻時間長度 然後量測反射性以及/或光捕捉行為。這樣的量測結果可 供決定最佳蝕刻時間。然而，可惜的是，如果一種蝕刻劑 5 被用於#刻許多晶圓（wafers)或是許多批次的晶圓時，該 蝕刻劑溶液之成份將隨著時間而改變。如此，蝕刻的時間 需要被調整藉以得到最佳的刻紋效果。 本發明之製程中，使半導體材料接觸蝕刻劑的步驟可 能會造成該保護體在某些部分被蝕刻9這取決於所使用的. 10 蝕刻劑以及蝕刻條件。如果在本步驟中該保護體有某部分 被蝕刻，將造成該保護體會擁有更多的微孔，相較於在進 行本步驟前該保護體所擁有的微孔數。 在使半導體材料接觸蝕刻劑的步驟之前，在該保護體 層中之微孔是很小的，典型的直徑小於100 nm，更典型 15 的直徑小於10 nm。隨著蝕刻步驟進行，微孔的尺寸會加 大且數量會增多。在蝕刻步驟結束，微孔的數量以及半導 體材料上蝕刻凹窩的數量在每ΙΟΟμηι2有10〜1000個。 在第一與第二實施例的製程中與第三、第四、第五以 及第六實施例之半導體材料，該半導體材料均為矽。當該 20 半導體材料為矽，本發明之製程之保護體典型為氮化矽， 餘刻齊】典型為氫氟酸（hydrofluoric acid)以及石肖酸（nitric acid)混合物，例如：比重49%氫化氟（HF)水溶液之體積比 1:50混合物（亦即100g水溶液中有49g HF)以及比重70% 的硝酸。其他化學物可添加入該蝕刻劑溶液中以提供預定 -11- 200409222 的蝕刻性質，例如提高半導體表面的溼度。如此之添加物 為熟知半導體蝕刻技藝者所熟知的。當該半導體材料為 - 矽，其可能為單結晶矽、微結晶矽或是多結晶矽。另一種 可能之用以蝕刻氮化矽的蝕刻劑為四氟化碳（cf4)以及氧 5 電漿。 本發明之製程中更包含一步驟：在蝕刻該半導體材料 以使表面產生複數個蝕刻凹窩之步驟之後，將該保護體移 除。該保護體之移除可以施用一種蝕刻劑，其蝕刻該保護 · 體之速率快於蝕刻該半導體材料。例如··當該半導體材料 10 為矽而且該保護體為氮化矽，該保護體可以活性離子蝕刻 (reactive ion etching)或是在升溫中（大約180°C)接觸填酸 (phosphoric acid)之方式移除之。另一種較佳之方式為在石夕 基板上移除氮化發是在氫氟酸(hydrogen fluoride)水溶液中 (典型的比重為5%)進行蝕刻。 15 更為典型的是，本發明之製程更包含有在蝕刻該半導 體材料以使其表面產生蝕刻凹窩之後，再移除該保護體 層，然後以習知的方法在所有表面上設置一防反射層 · (antireflective layer)之步驟。以此種方式會得到，相較於 僅單獨設置防反射層，大體上很大的反射性降低。 20 典型上，第一或第二實施例之製程可使一表面對於可 見光的反射度，相較於磨光的表面，降低大約50%。如果 在加上設置一抗反射層，可再大幅降低可見光的反射。 如果該半導體材料為矽而該保護體層為2nm厚之氮化 矽，蝕刻該半導體之步驟可由接觸以如前所述之比例1:50 -12- ^υ〇4〇9222-10- 20 200409222 Ingredients and temperature) time for best results. This can be obtained by etching examples under appropriate conditions, such as measuring reflectivity and / or light-trapping behavior at different etch time lengths. Such measurements can be used to determine the optimal etching time. Unfortunately, however, if an etchant 5 is used to engrav many wafers or lots of wafers, the composition of the etchant solution will change over time. In this way, the etching time needs to be adjusted to obtain the best engraving effect. In the process of the present invention, the step of contacting the semiconductor material with an etchant may cause the protective body to be etched in some parts. 9 Depending on the etchants used and the etching conditions. If a part of the protective body is etched in this step, the protective body will have more micropores than the number of micropores that the protective body had before the step. Prior to the step of contacting the semiconductor material with the etchant, the micropores in the protective layer are very small, typically having a diameter of less than 100 nm, and more typically 15 having a diameter of less than 10 nm. As the etching step proceeds, the size and number of micropores will increase. At the end of the etching step, the number of micropores and the number of etched dimples on the semiconductor material are 10 to 1,000 per 100 μm2. In the processes of the first and second embodiments, and the semiconductor materials of the third, fourth, fifth, and sixth embodiments, the semiconductor materials are all silicon. When the 20 semiconductor material is silicon, the protective body of the process of the present invention is typically silicon nitride. The remaining time is typically a mixture of hydrofluoric acid and nitric acid, for example: 49% hydrogenated. The fluorine (HF) aqueous solution has a volume ratio of 1:50 mixture (ie, 49 g of HF in 100 g of aqueous solution) and 70% nitric acid. Other chemicals can be added to the etchant solution to provide predetermined etch properties of -11-200409222, such as increasing the humidity of the semiconductor surface. Such additives are well known to those skilled in semiconductor etching techniques. When the semiconductor material is -silicon, it may be monocrystalline silicon, microcrystalline silicon, or polycrystalline silicon. Another possible etchant for etching silicon nitride is carbon tetrafluoride (cf4) and an oxygen plasma. The process of the present invention further includes a step of removing the protective body after the step of etching the semiconductor material to generate a plurality of etched dimples on the surface. The protective body can be removed by applying an etchant that etches the protective body faster than the semiconductor material. For example, when the semiconductor material 10 is silicon and the protection body is silicon nitride, the protection body can be reactive ion etching or contact with phosphoric acid during heating (about 180 ° C) Way to remove it. Another preferred method is to remove the nitrided hair on the Shi Xi substrate by etching in an aqueous solution of hydrogen fluoride (typical specific gravity is 5%). 15 More typically, the process of the present invention further comprises, after the semiconductor material is etched to cause an etching recess on its surface, the protective layer is removed, and then an anti-reflection is provided on all surfaces by a conventional method. Step (antireflective layer). In this way, it is obtained that, compared with the case where the antireflection layer is provided alone, the reflectance is substantially reduced. 20 Typically, the manufacturing process of the first or second embodiment can reduce the reflectance of a surface to visible light by about 50% compared to a polished surface. If an anti-reflection layer is added, the reflection of visible light can be greatly reduced. If the semiconductor material is silicon and the protective layer is 2 nm thick silicon nitride, the step of etching the semiconductor can be performed by contacting at a ratio of 1:50 -12- ^ υ〇〇〇〇〇2222
之氩氟酸/硝酸混合液，經幾分鐘（典型為2-5分鐘），在一 般室溫下進行蝕刻。 有時候該矽基板上會在氮化矽沉積之前長出一氧化矽 的薄層（例如20-3〇nm)。此種氧化物的生成是本發明之製 程中不需要之物質（經觀察發現，存在於氮切保護體; 方之氧化矽層，除了稍許增加反應時間外並不影響本發明 之製程）。然而，該氧化物層之產生可避免該矽基板之電 子特性之降低，此等現象在氮化石夕保護層下方無氧化層存 在時，有時可以被觀察到。 木發明之製程對於在不易輕射之表面刻紋具有特別的 優點，該等表面例如世界專利申請案號w〇〇2/45i43號專 利案所述固定於-支架上而生產的石夕條表面。因此，本發 明之-較佳形式，該半導體材料為__條，其具有小於 15 ΙΟΟμιη的厚度以及最大寬度為3咖以及其中至少一對相 反之表面以本發明之製程刻紋。亦即，每一個至少一對之 相反表面具有複數個大體上隨機分佈之凹窩，該等凹窩具 有内側面其至少一部分為圓形的，且/或其寬度最大為 ΙΟμηι。 【實施方式】 20 ^ ，了詳細說明本發明之構造及特點所在，茲舉以下之 較佳實施例並配合圖式說明如后，其中·· 第一圖係顯示一矽條之表面被刻紋的示意圖，· =Α圖至第圖係顯示本發明之方法之流程圖； 弟三圖係為一曲線圖，顯示經本發明之方法所製作之 -13- 200409222 矽條可吸收光的總量（部分進入矽條的光量）與一雙面均磨 亮之石夕晶圓之比較，以及 第四圖至第六圖為電子顯微照片，顯示矽的表面經本 發明之方法刻紋路後之型態。 5 圖示之詳細說明： 藉由圖示可使本發明更方便地被了解。第一圖與第二 A圖至第二D圖並未明確表示出尺寸而且僅為示意圖。The argon fluoride acid / nitric acid mixture is etched at room temperature for several minutes (typically 2-5 minutes). Sometimes a thin layer of silicon oxide (for example, 20-30 nm) is grown on the silicon substrate before the silicon nitride is deposited. The formation of such oxides is not required in the process of the present invention (it is observed that it exists in the nitrogen-cut protective body; the square silicon oxide layer does not affect the process of the present invention except for slightly increasing the reaction time). However, the generation of the oxide layer can avoid the degradation of the electronic characteristics of the silicon substrate. Such phenomena can sometimes be observed when there is no oxide layer under the protective layer of the nitride. The process of wood invention has special advantages for engraving on the surface that is not easy to be shot. Such surfaces are, for example, the surface of stone battens produced by fixing on-brackets as described in the world patent application number w002 / 45i43 patent. . Therefore, in a preferred form of the present invention, the semiconductor material is a strip, which has a thickness of less than 15 100 μm and a maximum width of 3 cm, and at least one pair of opposite surfaces is engraved with the process of the present invention. That is, each of the at least one pair of opposite surfaces has a plurality of substantially randomly distributed dimples, the dimples having an inner side surface at least a part of which is circular and / or having a width of at most 10 μηι. [Embodiment] 20 ^, the structure and features of the present invention are described in detail. The following preferred embodiments are illustrated in conjunction with the drawings as follows. Among them, the first picture shows the surface of a silicon strip being engraved. Schematic diagrams, A = A to D are the flowcharts of the method of the present invention; the third figure is a graph showing the total amount of light that can be absorbed by the silicon strip produced by the method of the present invention (13-200409222) The amount of light entering the silicon strip) is compared with a polished Shixi wafer on both sides, and Figures 4 to 6 are electron micrographs showing the surface of the silicon after it has been etched by the method of the present invention. . 5 Detailed description of the diagrams: The present invention can be more easily understood through the diagrams. The first and second drawings A to D do not clearly show the dimensions and are only schematic diagrams.
第一圖表示一矽條1沿著由本發明第一實施例之製程 之刻紋的斷面圖。刻紋的步驟如下：一氮化矽2的薄層以. 10 低壓化學蒸氣沉積法（low pressure chemical vapour deposition，LPCVD)設置於該石夕條基層1上。此技術可在 該基層表面上形成一均勻且保角（conformal)的氮化石夕層 2。重要地，該氮化矽2同樣是以LPCVD法成形在窄通道 或是溝槽以及矽條之側牆上，該矽條以世界專利WO 15 02/45143號專利案中所揭之方法製成。僅有一非常薄之氮The first figure shows a cross-sectional view of a silicon strip 1 along the engraving process of the first embodiment of the present invention. The steps of engraving are as follows: a thin layer of silicon nitride 2 is disposed on the base layer 1 of the stone strip by a low pressure chemical vapour deposition (LPCVD) method. This technique can form a uniform and conformal nitride nitride layer 2 on the surface of the base layer. Importantly, the silicon nitride 2 is also formed on a side wall of a narrow channel or trench and a silicon strip by LPCVD method, and the silicon strip is made by a method disclosed in World Patent No. WO 15 02/45143. . Only a very thin nitrogen
化石夕層2，幾個原子層厚，被沉積。如此相當薄的層會具 有許多孔5，其使該矽基層可經由該等孔5而被暴露。然 後該矽條1被適當的蝕刻劑所蝕刻，例如：氫氟酸與硝酸 以1:5 0的比例之混合溶液。在室溫下，這種姓刻劑#刻 20 氮化矽的速率比蝕刻矽的速率低300倍。一般而言，蝕刻 凹窩6會在該矽條1之孔5的位置形成。在幾分鐘後，大 部分之表面均會覆蓋尺寸最大為幾個微米的蝕刻凹窩6。 而蝕刻步驟在此結束。蝕刻步驟可由改變氮化矽沉積的參 數，其會影響該層2上孔5的密度，與改變蝕刻的時間與 14- 200409222 發明說明 溫度來達成。如果是在一低蝕刻溫度下，即會得到一個蝕 刻氮化矽2比蝕刻矽1為低的速率。例如：在0°C下，蝕 刻劑钱刻氮化石夕2的速率比#刻石夕的速率低6000倍。在 本發明之製程中亦可進行二次前述之刻紋步驟，以得到更 5 進一步之紋路性質。Fossil layer 2, a few atomic layers thick, is deposited. Such a relatively thin layer would have many holes 5 which allow the silicon-based layer to be exposed through the holes 5. The silicon strip 1 is then etched by a suitable etchant, such as a mixed solution of hydrofluoric acid and nitric acid in a ratio of 1:50. At room temperature, the nicking agent #etching 20 silicon nitride is 300 times slower than etching silicon. Generally speaking, the etching recess 6 is formed at the position of the hole 5 of the silicon strip 1. After a few minutes, most of the surface will be covered with etched dimples 6 with a maximum size of a few microns. The etching step ends here. The etching step can be achieved by changing the parameters of the silicon nitride deposition, which will affect the density of the holes 5 in the layer 2, and changing the etching time and temperature. If it is at a low etching temperature, an etched silicon nitride 2 will be obtained at a lower rate than the etched silicon 1. For example, at 0 ° C, the rate of the etchant Qian-Nitride Xi Xi 2 is 6000 times lower than the rate of # lith-Shi Xi. In the process of the present invention, the aforementioned engraving step can also be performed twice to obtain further texture properties.
第二A圖至第二D圖顯示，以輪廓的形式，一矽表 面之斷面圖，分別顯示經本發明第二實施例之製程之不同 階段之示意圖。一氮化矽層2,厚度為2-4nm，被以LPCVD 法沉積於一矽基層1之表面上。第2A圖顯示該矽基層1. 10 被氮化物沉積後之情形。氮化物層2，其被設置於該矽表 面1上，並非均勻平滑之薄膜，其具有厚度之變異。第二 A圖中顯示凹部3, 4。根據氮化物層之厚度，凹部可能會 延伸於該矽基層之表面上，而於該氮化物層產生複數個微 孔，或者凹部僅延伸分佈於該石夕基層表面之一部分，如第 15 二A圖所示。第二A圖亦顯示該等凹部具有不同之深度。Figures A through D show the cross-sectional views of a silicon surface in the form of outlines, which respectively show the schematic diagrams of the different stages of the process through the second embodiment of the present invention. A silicon nitride layer 2 having a thickness of 2-4 nm is deposited on a surface of a silicon base layer 1 by a LPCVD method. FIG. 2A shows the silicon base layer 1. 10 after being deposited by nitride. The nitride layer 2, which is disposed on the silicon surface 1, is not a uniform and smooth film, and has a variation in thickness. Recesses 3, 4 are shown in the second A picture. Depending on the thickness of the nitride layer, the recessed portion may extend on the surface of the silicon-based layer, and a plurality of micropores may be generated in the nitride layer, or the recessed portion may only be distributed on a part of the surface of the stone-based substrate, such as 15A As shown. The second A diagram also shows that the recesses have different depths.
在該等凹部僅延伸於該石夕基層表面之一部分的情形 下，該矽基層被沉浸於一用以蝕刻該氮化矽之溶液中。該 溶液可為比重為49%的硝酸水溶液以10倍的水稀釋，或 者氫氟酸與确酸混合，例如比重49%的氫氟酸水溶液與比 20 重70%的硝酸以體積比1:50的比例混合。該氮化矽層被 逐漸地且均勻地被薄化。最後該氮化物層變的很薄而使該 等最深的凹部3穿透該氮化物層而使下方之石夕基層1表面 被暴露，而使該氮化物層產生複數個微孔5，如第二B圖 所示。較淺之該等凹部4並未在此階段中穿透該氮化物層 -15- 200409222 2 〇 矽基層1現在沉浸於一可蝕刻矽快於蝕刻氮化矽之溶 液中，例如：比重49%的氫氟酸水溶液與比重70%的墙酸 以體積比1:50的比例混合。其結果會造成蝕刻凹窩6會 5 在矽基層1位於該等微孔5之位置，如第二C圖所示。突 出該蝕刻凹窩6上之氮化矽2薄層是非常脆弱的而且容易 破損，可讓新的蝕刻劑進入該等蝕刻凹窩6中。該等蝕刻 凹窩6會隨著蝕刻程序之進行而變得較大。 · 在該蝕刻程序中，該氮化矽層2也會輕微地變薄。或. 10 者會使該氮化矽層2上形成其他的微孔7。這些微孔7也 會使該矽基層上形成蝕刻凹窩8,如第二D圖所示。當得 到最佳之刻紋程度後即可停止蝕刻程序。這種情況會在大 部分的碎1表面均被刻紋，但仍有一小部分未被刻紋。 蝕刻程序亦可在一溫度範圍被使用。特別是較低的溫 15 度通常產生一比蝕刻矽較低之蝕刻氮化矽速率，因此例如 在o°c下進行蝕刻，而不是在室溫下，在某些情況下是可 行的。該氮化矽層亦可被處理以降低其在一範圍内之矽蝕 · 刻劑之蝕刻率。例如：高溫氮化矽（1000〜1100°C)退火後 一般脅造成矽蝕刻劑蝕刻該氮化矽之速率降低。 20 前述之刻紋技術特別適合於薄膜矽電池，因為在刻紋 一 製程中僅會消耗少數之矽（每刻紋表面大約2-3微米）。本 刻紋技術可被應用於矽晶圓（wafers)或多變晶粒尺寸之薄 膜。 範例： 16- 200409222 發明說明/Μ胃 在以下所有範例中，沉積氮化矽均是以低溫化學蒸氣 沉積法，溫度為750°C並以一二氯石夕烧（dichlorosilane)流 速為30標準立方公分/每分鐘（seem)，一氨水（ammonia)流 速為120 seem以及壓力70Pa。典型之沉積時間為75秒。 5 例一：In the case where the recesses extend only a part of the surface of the Shixi substrate, the silicon substrate is immersed in a solution for etching the silicon nitride. The solution can be a 49% nitric acid aqueous solution diluted with 10 times water, or hydrofluoric acid mixed with acid, for example, a 49% hydrofluoric acid aqueous solution and a 20% 70% nitric acid in a volume ratio of 1:50. The proportions are mixed. The silicon nitride layer is gradually and uniformly thinned. Finally, the nitride layer becomes very thin, so that the deepest recessed portions 3 penetrate the nitride layer, and the surface of the underlying stone layer 1 is exposed, so that the nitride layer generates a plurality of micropores 5, as shown in FIG. Figure B shows. The shallower recesses 4 did not penetrate the nitride layer at this stage -15-200409222 2 〇 The silicon-based layer 1 is now immersed in a solution that can etch silicon faster than silicon nitride, for example: a specific gravity of 49% The hydrofluoric acid aqueous solution was mixed with 70% wall acid in a volume ratio of 1:50. As a result, the etched recesses 6 and 5 will be located on the silicon substrate 1 at the positions of the micro holes 5 as shown in the second C diagram. It is highlighted that the thin layer of silicon nitride 2 on the etched recess 6 is very fragile and easily broken, and it is possible to allow new etchant to enter the etched recesses 6. The etch dimples 6 become larger as the etching process progresses. The silicon nitride layer 2 is also slightly thinned during the etching process. Or, 10 will cause other micro holes 7 to be formed in the silicon nitride layer 2. These micro-holes 7 will also form etched dimples 8 on the silicon-based layer, as shown in the second D diagram. The etch process can be stopped when the optimum level of engraving is obtained. In this case, most of the broken surface is etched, but a small part is still not etched. Etching procedures can also be used over a temperature range. In particular, a lower temperature of 15 degrees usually results in a lower etched silicon nitride rate than etched silicon, so that, for example, etching at o ° C rather than room temperature is feasible in some cases. The silicon nitride layer can also be processed to reduce the etching rate of the silicon etch and etchant in a range. For example: After annealing at high temperature silicon nitride (1000 ~ 1100 ° C), the rate of etching of silicon nitride by silicon etchant is generally reduced. 20 The aforementioned engraving technology is particularly suitable for thin-film silicon batteries, as only a small amount of silicon is consumed during the engraving process (about 2-3 microns per etched surface). This engraving technique can be applied to silicon wafers (wafers) or thin films of varying grain sizes. Examples: 16- 200409222 Description of the invention / M stomach In all of the following examples, silicon nitride is deposited using a low-temperature chemical vapor deposition method at a temperature of 750 ° C and a dichlorosilane flow rate of 30 standard cubic meters. Cm / min, the flow rate of ammonia is 120 seem and the pressure is 70Pa. A typical deposition time is 75 seconds. 5 Example 1:
一厚度大約為2 nm之氮化矽層被沉積於一磨亮之（111) 方位之矽晶圓上。一樣本自該晶圓切斷，且以一 1:50之 氫氟酸與硝酸溶液，溫度為〇°C，進行蝕刻。此樣本利用 矽樹脂被包覆於1 mm厚之低金屬玻璃中，而且其反射度. 10 是以一具有一完整球體之分光光度計（spectrophotometer) 測量之。此樣本在一 900 nm波長下具有11%之反射度， 而一磨光被包覆的參考矽晶圓之反射度為24%，而一以 (100)方位矽，其被刻上倒錐形之紋路，在相同波長下具有 8%之反射度。這些結果顯示該刻紋製程對於降低該矽表 15 面反射度相當有效。A silicon nitride layer with a thickness of about 2 nm is deposited on a polished (111) orientation silicon wafer. A sample was cut from the wafer and etched with a 1:50 solution of hydrofluoric acid and nitric acid at a temperature of 0 ° C. This sample was coated with 1 mm thick low-metal glass using silicone resin, and its reflectance was measured with a spectrophotometer with a complete sphere. This sample has a reflectance of 11% at a wavelength of 900 nm, while the reflectance of a polished coated reference silicon wafer is 24%, and a (100) orientation silicon is engraved with an inverted cone The texture has a reflectance of 8% at the same wavelength. These results show that the engraving process is quite effective in reducing the surface reflectance of the silicon surface.
例二：蝕刻薄矽條 一直徑100 mm、厚度1 mm、（ 110)方位之石夕晶圓被使 用。該晶圓上具有複數個薄矽條，間距為105微米，厚度 大約為70微米，係依照世界專利W0 02/45143號專利案 20 中所揭之方法製成。如此獲得之薄矽之側壁上係高度地被 磨亮。在該等側壁上刻紋可當作太陽能電池中面對太陽之 表面" 一氮化矽之薄層被沉積於該晶圓上。該等薄矽條之其 中一者被從該晶圓上打破並且固設於該晶圓之表面上。在 -17- 200409222 發明說明續頁 此方式中，在_過財，其t-料之側壁表面係清楚 可見的。再經過5分鐘㈣刻，溫度為室溫、㈣劑與例 1 相同，該科條被刻紋的狀況最佳，而且結鋒刻。此 日守该專石夕條的居度大約為65微米。 里測被刻紋之秒之来附生丨，止 九限制（先捕捉）的程度。第三圖係 顯示6 5微米厚之已刻纹之々反 , 之矽條，與微米厚之未刻紋之 石夕條之光吸收量比較圖。並、、主枯 一 ，、α邊地顯示本刻紋程序對於波 長為」5G_11GG nm之光捕捉有顯著地改進因&，如果本 刻紋方法被應驗⑪太陽能電池巾將會縣地提升能量轉 10Example 2: Etching a thin silicon strip A Shi Xi wafer with a diameter of 100 mm, a thickness of 1 mm, and a (110) orientation was used. The wafer has a plurality of thin silicon stripes with a pitch of 105 micrometers and a thickness of about 70 micrometers, and is manufactured according to the method disclosed in World Patent WO 02/45143 Patent Case 20. The side walls of the thin silicon thus obtained are highly polished. The engravings on the sidewalls can be used as a thin layer of silicon nitride on the wafer as the surface facing the sun in a solar cell. One of the thin silicon bars is broken from the wafer and fixed on the surface of the wafer. In -17- 200409222 Invention Description Continued In this way, the surface of the side wall of the t-material is clearly visible in Guocai. After 5 minutes of engraving, the temperature was room temperature, and the tincture was the same as in Example 1. The condition of this branch was the best engraving, and the front engraving. The abode of this special stone Yujo is about 65 microns today. The inside is measured by the engraved seconds, and the degree of restriction (captured first). The third figure shows the comparison of the light absorption between a 65-micron-thick, unetched silicon strip and a micron-thick, un-etched stone strip. And, the main one, the α edge shows that this engraving program has a significant improvement factor for light capture with a wavelength of "5G_11GG nm". If this engraving method is fulfilled, the solar cell towel will increase the energy of the county. Turn 10
換率。 例三：表面鈍化 許多（111)方位，>1000 ohm-cm之滲爛浮動區域之石夕 日日圓（boron doped float-zoned silicon wafers)被使用。一大 約為30 nm厚之氧化物熱生長於該等晶圓上。一氮化石夕的 !5 薄層之後被沉積而且該等晶圓被以例二之方法刻紋。在刻 紋之後，該晶圓上設置一鱗擴散層（phosphorus diffusion) 並熱生長一 30 nm厚之氧化物層。然後該等晶圓在5%氫 與95%氮之混合物中，以430°C之溫度下退火30分鐘。 在經過前述之處理後，每一邊的發射體飽和電流強度 20 (emitter saturation current density)為 20-25 fA/cm2。這個低 的數值表示在被刻紋的表面上具有優越之表面鈍化效果。 本發明之製程之優點為： 本發明之製程為一種較為簡單與不昂貴的方法可降低 一半導體材料之一表面之反射度。此外，本發明之製程可 -18- 200409222 發明說明#賣頁 使不暴露於輻射線中之表面，例如不能以活性離子蝕刻刻 紋之表面刻上紋路（致使反射度降低）。更有一點，本發明 · 之製程可施用於（111)晶格方位的表面，其無法以非等方性 一 的钱刻劑（anisotropic etchants)，例如氫氧化鉀，ϋ刻以刻 5 上紋路。 本發明之發明範圍並非僅侷限於說明書中圖示與範例 所敘述之方法，任何以相同之原理之變異之方法而為熟悉 本項技藝可輕易實施者，應仍屬於本發明之範圍。 © -19- 200409222Swap rate. Example 3: Surface passivation Many (111) orientations, > 1000 ohm-cm osmotic floating area of the stone yawn (boron doped float-zoned silicon wafers) are used. A large approximately 30 nm thick oxide is thermally grown on these wafers. A thin layer of! 5 nitride was deposited and the wafers were etched in the same manner as in Example 2. After the engraving, a phosphor diffusion layer is disposed on the wafer and a 30 nm thick oxide layer is thermally grown. The wafers were then annealed in a mixture of 5% hydrogen and 95% nitrogen at 430 ° C for 30 minutes. After the aforementioned treatment, the emitter saturation current density 20 (emitter saturation current density) on each side is 20-25 fA / cm2. This low value indicates superior surface passivation on the engraved surface. The advantages of the process of the present invention are: The process of the present invention is a relatively simple and inexpensive method that can reduce the reflectance of a surface of a semiconductor material. In addition, the manufacturing process of the present invention may be -18- 200409222 Invention Description # Selling page Surfaces that are not exposed to radiation, such as those that cannot be etched with reactive ion etching, can be etched (resulting in reduced reflectance). Furthermore, the process of the present invention can be applied to the surface of the (111) lattice orientation, which cannot be etched with an anisotropic etchants, such as potassium hydroxide, to etch 5 lines. . The scope of the invention of the present invention is not limited to the methods described in the illustrations and examples in the specification. Any method that uses the same principle and is familiar with this technique and can be easily implemented should still belong to the scope of the present invention. © -19- 200409222
【圖式簡單說明】 第一圖係顯示一矽條之表面被刻紋的示意圖； 第二A圖至第二D圖係顯示本發明之方法之流穩劇； 第三圖係為一曲線圖，顯示經本發明之方法所製作之 5矽條可吸收光的總量（部分進入石夕條的光量）與_雙:均磨 亮之矽晶片之比較，以及 ，顯示石夕的表面經本 第四圖至第六圖為電子顯微照片 發明之方法刻紋路後之型態。 10 【圖式符號說明】 3, 4凹部 1矽基層 2氮化矽層 5，7微孔 6，8钱刻凹寓 -20-[Schematic description] The first diagram is a schematic diagram showing the surface of a silicon strip being engraved; the second diagram A to the second D are diagrams showing the stability of the method of the present invention; the third diagram is a graph Shows the total amount of light that can be absorbed by the 5 silicon strips produced by the method of the present invention (the amount of light that enters Shixian strip) and _double: uniformly polished silicon wafers, and shows that the surface of Shi Xi is Figures 6 through 6 show the pattern after the engraving method of the invention of the electron micrograph. 10 [Illustration of Symbols] 3, 4 Concavities 1 Silicon Base Layer 2 Silicon Nitride Layer 5, 7 Micro-holes 6, 8 Coins and Indentations -20-
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