TW200406924A - Thin film lateral SOI device - Google Patents

Thin film lateral SOI device Download PDF

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TW200406924A
TW200406924A TW091132261A TW91132261A TW200406924A TW 200406924 A TW200406924 A TW 200406924A TW 091132261 A TW091132261 A TW 091132261A TW 91132261 A TW91132261 A TW 91132261A TW 200406924 A TW200406924 A TW 200406924A
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thickness
layer
dielectric layer
silicon
dielectric
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TW091132261A
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Rene Paul Zingg
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Koninkl Philips Electronics Nv
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

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  • Engineering & Computer Science (AREA)
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  • Thin Film Transistor (AREA)

Abstract

A thin film lateral SOI device comprises a substrate and a buried oxide layer (4) (BOx) as a dielectric layer on the substrate; a silicon layer (6) on the buried oxide layer, the silicon layer comprising a first thickness silicon region (8), a second thickness silicon region (10) having a thickness smaller than the first thickness silicon region (8) and a third thickness silicon region (12) having a thickness smaller than the second thickness silicon region (10); a dielectric layer (TOx) on top of the silicon layer (6), comprising a gate dielectric layer (18) on top of the first thickness silicon region (8), a field dielectric layer (20) on top of the a second thickness silicon region (10), the field dielectric layer (20) having a thickness larger than the thickness of the gate dielectric layer (18), and a drift dielectric layer (22) on top of the third thickness silicon region (12) the drift dielectric layer (22) having a thickness larger than the thickness of the drift dielectric layer (20); a gate (42) on top of the gate dielectric layer (18) above a channel region (38); a field plate (44) extending across the field dielectric layer (20); a drain (30) laterally spaced to the third thickness silicon region (12) of the silicon layer (6); and a source (32) laterally separated from the gate.

Description

0) 0) 200406924 玟、發明說明 (發明說明應敘明：發明所屬之技術領域、先前技術、内容、實施方式及圖式簡單說明) 發明範疇 本發明相關於一薄獏橫向SOI(覆矽氧化層）裝置。 SOI橫向電力裝置由於來自操作晶圓的載子空乏（漂移 區的擠壓），顯示劣化的高側效能。藉由世界專利號 WOOO/3 1776中所述步進及階梯式s〇COS裝置（事實上它 將矽膜厚度及其中可用的摻雜區極大化），已將此劣化減 至最小 ° 惟步進及階梯式socos裝置在漂移區中具有電子的電 位槽’漂移區由於矽膜厚度及氧化層厚度的變動而在 膜中具有不同高度，這又造成垂直電場與電流方向的部分 對齊，而增加衝擊離子化比率，並藉此限制可接受的縱向 電場。除此缺點外尚有其他缺點，以致必須在靠近垂直電 場小的源極區有過渡步驟，並使裝置渴望得到一定的電壓 等級。 發明背景 買〇00/3 1776中所述步進及階梯式薄膜3〇11^1^〇3裝置 的這些特點將參照圖1加以說明，圖1中示出有關此技藝型 悲的裝置。裝置2包括一埋藏式氧化層（Β〇χ)4在基板（未示） 上，及一矽層6在埋藏式氧化層4上，矽層包括（圖工中從左 至右）一第一厚度區8、一第二厚度區10(厚度小於第一厚度 區8)，及一第二厚度區12(厚度小於第二厚度區1〇)。一第一 過渡14位於第一厚度區8與第二厚度區1〇之間，而一第二過 渡16位於第一厚度區1 〇與第三厚度區12之間。一第二氧化 2004069240) 0) 200406924 玟. Description of the invention (The description of the invention should state: the technical field, prior art, content, embodiments, and drawings of the invention are briefly explained) The scope of the invention The invention relates to a thin SOI (Silicon Overlay Oxide) Layer) device. The SOI lateral power device exhibits degraded high-side performance due to the lack of carriers (squeezing in the drift region) from the operating wafer. With the step and stepped soCOS device described in World Patent No. WOOO / 3 1776 (in fact it maximizes the thickness of the silicon film and the doped regions available in it), this degradation has been minimized. The stepped socos device has a potential cell with electrons in the drift region. The drift region has different heights in the film due to changes in the thickness of the silicon film and the thickness of the oxide layer, which in turn causes the vertical electric field to align with the direction of the current and increases. Impacts the ionization ratio and thereby limits the acceptable longitudinal electric field. In addition to this disadvantage, there are other disadvantages that make it necessary to have a transition step near the source region where the vertical electric field is small and make the device long for a certain voltage level. BACKGROUND OF THE INVENTION These features of the stepped and stepped film 30101 ^ 1 ^ 3 device described in Buy 00/3 1776 will be described with reference to Figure 1, which shows a device of this technical type. The device 2 includes a buried oxide layer (Box) 4 on a substrate (not shown), and a silicon layer 6 on the buried oxide layer 4. The silicon layer includes (from left to right in the drawing) a first A thickness region 8, a second thickness region 10 (thickness smaller than the first thickness region 8), and a second thickness region 12 (thickness less than the second thickness region 10). A first transition 14 is located between the first thickness region 8 and the second thickness region 10, and a second transition 16 is located between the first thickness region 10 and the third thickness region 12. One second oxidation 200406924

(2) 層（介電層）設置在矽層6之上，第二氧化層具有一閘極氧化 層18、一場氧化層20(厚度大於閘極氧化層18厚度）及一漂移 氧化層22(厚度大於場氧化層20厚度），一氧化層過渡24位於 場氧化層20與漂移氧化層22之間。一閘極26位於閘極氧化 層18之上，並在一通道區38、場氧化層2〇及漂移氧化層 之上延伸成一場板28。一汲極30於橫向與石夕層6的第三厚度 區12相隔’ 一源極32於橫向與閘極26分開，閘極26包括一 多晶矽層，並由另一氧化層34所覆蓋，另一氧化層34上面 设置另一金屬場板36，其由源極區32橫跨另一氧化層34延 伸，幾乎延伸到場氧化層2〇的一末端。 t 此一稱為步進及階梯式S0I裝置中，該裝置包括一基板， 一埋藏式氧化層在基板上，一矽層在埋藏式氧化層上（s〇i ，覆矽絕緣層），一層介電層18(最好為長成的氧化層），一 閘極或場板28在此介電層上面，另一介電層34，一金屬層 36，及一鈍化層（未示）。該s〇I層朝汲極3〇逐漸減少厚度， 而氧化層則逐漸增加厚度，亦使用金屬層36再從s〇i層移除 場板36，並藉此減少垂直電場。圖！中的線a表示電子的最 小電位，並說明由於半導體及介電層的厚度改變，此最小 電位在SOI層中高度的變化。 US A 5’362,979 4明一 s〇I電晶體，其尤其對於橋接型電 路具有改良式源極高效能。漂移區中橫向延伸的矽層在漂 移區K度部分之上具有一較薄厚度區，場板係與閘極分開 形成，並在漂移區薄部分上延伸，閘極及場板係藉由一金 屬互連形成短路電，路。此s〇I裝置中存在的問題亦是漂移區 -6 - 200406924 w mmmmmm· 中電子漂移未與埋藏式敦化層保持定距離，而造成漂移區 中電子的垂直錯置’依次藉由衝擊離子化限制崩潰電壓而 導致載子倍增。 發明總結 本發明目的在於，在增加縱向電場並藉此減少裝置長度 的同時藉由減少由衝擊離子化造成的載子倍增而進一步改 良步進及階梯式socos裝置的效能。 為達成此目的，本發明的薄膜橫向S0I裝置包括一基板及 埋藏式氧化層（BOX)在基板上作為一介電層；一矽層位在 埋藏$氧化層上，矽層包括一第一厚度矽區、一第二厚度 矽區（厚度小於第一厚度矽區），及一第三厚度矽區（厚度小 於第二厚度矽區）；一介電層（τ〇χ)位於矽層之上，包括一 問極介電層位於第一厚度矽區之上，一場介電層位於第二 厚度矽區之上，其中場介電層厚度大於閘極介電層厚度， 及/7F移；丨包層位於第二厚度矽區之上，漂移介電層厚度 大於場介電層厚度；一閘極位於一通道區（38)以上閘極介電 層之上，一場板橫跨場介電層而延伸；一汲極於橫向與矽 層之第三厚度矽區相隔；及一源極於橫向與閘極分開，·另 一介電層至少覆蓋閘極及漂移介電層；及另一場板橫跨另 一介電層而延伸。藉此可消除電位井的垂直錯置，或在一 具體範例中以大約5的因數減少已知石夕層及氧化層的厚度 。電場與電流方向間的減小比例產品容許再將s〇I膜的薄部 分轉移至汲極，減少高侧操作中的擠壓效應，因此改良裝 置的電流驅動。， 200406924 (4) _瓣_輯.: 。根據本發明一較佳實例提供一薄膜s〇I裝置，其中介電層 最好為一 L〇C〇S方法所製成的氧化層。 根據本發明一較佳實例提供一薄膜s〇i裝置，其中閘極結 束於智介電層與漂移介電區間的過渡，此待徵形成的優點 2，在電場末端與額外介電層的上方及其間的過渡，可隨 思沈積任何層（在場板上沈積者）及另一介電層。此外，場板 末知的位置經良好界定，以便於極小化漂移區中電子垂直 錯置的方式，設計矽層及第二介電層或上氧化層的厚度尺 寸。 根據本發明一較佳實例提供一薄膜s〇i裝置，包括另一介 電層至少覆蓋閘極及漂移介電層。 根據本發明一較佳實例提供一薄膜s〇i裝置，包括另一場 板秩跨另一介電層（46)而延伸，此實例中，額外的場板補充 閘極的場板延伸，俾便適應場板配置，以控制矽層中完整 的漂移區，或保護漂移區對抗外界的影響。 根據本發明一較佳實例提供一薄膜s〇i裝置，其中另一場 板幾乎延伸至漂移介電層的一末端。 根據本發明一較佳實例提供一薄膜s〇I裝置，其中另一場 板連接至源極，藉此另一場板與利於控制裝置的閘極場板 延伸在相同電位位準上。 根據本發明一較佳實例提供一薄膜s 〇1裝置，其中閘極由 多晶矽所組成，如此藝中所熟知，在裝置製造過程期間有 利於整合製造閘極的步驟。 根據本發明一較佳實例提供一薄膜s〇I裝置，其中另一場 200406924 板由金屬所組成，洪ώ骀 . ^成裝置製造過程期間另一場板的形狀 受到良好界定。 & 明_較佳實例提供一薄膜裝置，其中另一場 一第至屬層及-第二金屬層所組成，其中第二金屬 層與第一金屬層隔離，笼入趄 、隔離弟一金屬層可連接至閘極，而第二 '9可連接至源極或間極，或連接至任何想用以控制漂 移區的分開電位。 根據本么明一較佳實例提供一薄膜SOI裝置，其中藉由一 介電層隔開第二金屬層與第一金屬層。 本么月其他IsU圭f例在其餘的巾請專利範圍附屬項中說 明其特徵。 -薄膜橫向S0I裝置包括—基板…埋藏式氧化層在基板 。層覆矽埋藏式氧化層（s〇I，覆矽絕緣層），一層介電 層(取好為長成氧化層)，-閘極或場板在此介電層上面。一 ^夕至屬層從下方藉由_介電膜與區域接觸孔及—純化層 隔離而元成該裝置，s〇I層係朝没極逐漸減少厚度，而氧化 層則逐漸增加厚度，亦使用金屬層再從SOI層移除場板，並 糟此減少垂直電場。為極小化電子最小電位沿裝置的錯置 ，SOI膜厚度及場板下的介電層係根據一等式相匹配，此減 少衝擊離子化產生的載子倍增’藉此容許較高橫向電場， 二允+較短衣置用於已知電壓等級。減少漂移區、增加可 月b衫雜增加S0I膜厚度及減少面積，上述各項可個別地或 以組合方式有貢獻於減少特定的導通電阻（Qnlstance)， 尤其在高侧操作中/。 200406924(2) a layer (dielectric layer) is disposed on the silicon layer 6; the second oxide layer has a gate oxide layer 18, a field oxide layer 20 (thickness greater than the thickness of the gate oxide layer 18), and a drift oxide layer 22 ( The thickness is greater than the thickness of the field oxide layer 20). An oxide layer transition 24 is located between the field oxide layer 20 and the drift oxide layer 22. A gate 26 is located above the gate oxide layer 18 and extends into a field plate 28 over a channel region 38, field oxide layer 20, and drift oxide layer. A drain electrode 30 is separated from the third thickness region 12 of the stone layer 6 in the lateral direction. A source electrode 32 is separated from the gate electrode 26 in the lateral direction. The gate electrode 26 includes a polycrystalline silicon layer and is covered by another oxide layer 34. An oxide layer 34 is provided with another metal field plate 36, which extends from the source region 32 across the other oxide layer 34 to almost one end of the field oxide layer 20. t This is called a stepping and stepped SOI device. The device includes a substrate, a buried oxide layer on the substrate, a silicon layer on the buried oxide layer (soi, silicon-on-insulator layer), and a layer. A dielectric layer 18 (preferably a grown oxide layer), a gate or field plate 28 on top of the dielectric layer, another dielectric layer 34, a metal layer 36, and a passivation layer (not shown). The SOI layer gradually decreases in thickness toward the drain 30, while the oxide layer gradually increases in thickness. The metal layer 36 is also used to remove the field plate 36 from the SOI layer, thereby reducing the vertical electric field. Figure! The line a in the middle indicates the minimum potential of the electrons, and illustrates the change in the height of this minimum potential in the SOI layer due to changes in the thickness of the semiconductor and the dielectric layer. US A 5'362,979 4 is a so-I transistor, which has an improved source efficiency, especially for bridged circuits. The laterally extending silicon layer in the drift region has a thinner thickness region above the K-degree portion of the drift region. The field plate system is formed separately from the gate and extends over the thin portion of the drift region. The gate and field plate are formed by a Metal interconnections form short circuits. The problem in this so device is also the drift region-6-200406924 w mmmmmm · The middle electron drift does not keep a certain distance from the buried Tuning layer, and the vertical dislocation of the electrons in the drift region is caused by the impact ionization in turn. Limiting the breakdown voltage results in multiplication of carriers. Summary of the Invention The purpose of the present invention is to further improve the performance of stepping and stepped socos devices by reducing the carrier multiplication caused by impact ionization while increasing the longitudinal electric field and thereby reducing the device length. To achieve this, the thin film lateral SOI device of the present invention includes a substrate and a buried oxide layer (BOX) as a dielectric layer on the substrate; a silicon layer is located on the buried oxide layer, and the silicon layer includes a first thickness A silicon region, a second thickness silicon region (thickness less than the first thickness silicon region), and a third thickness silicon region (thickness less than the second thickness silicon region); a dielectric layer (τ〇χ) is located on the silicon layer Including an interlayer dielectric layer on the first thickness silicon region, a field dielectric layer on the second thickness silicon region, where the field dielectric layer thickness is greater than the gate dielectric layer thickness, and / 7F shift; 丨The cladding layer is located on the second thickness silicon region, the thickness of the drift dielectric layer is greater than the thickness of the field dielectric layer; a gate is located above the gate dielectric layer in a channel region (38), and a field plate crosses the field dielectric layer And an extension; a drain electrode is separated from the third thickness silicon region of the silicon layer in the lateral direction; and a source electrode is separated from the gate electrode in the lateral direction; another dielectric layer covers at least the gate electrode and the drift dielectric layer; and another field plate Extending across another dielectric layer. This can eliminate the vertical misalignment of the potential well, or reduce the thickness of the known stone layer and oxide layer by a factor of about 5 in a specific example. The reduced ratio between the direction of the electric field and the current allows the thin portion of the SOI film to be transferred to the drain again, reducing the squeezing effect in high-side operation, thus improving the current drive of the device. , 200406924 (4) _ flap_ series .:. According to a preferred embodiment of the present invention, a thin film SOI device is provided, wherein the dielectric layer is preferably an oxide layer made by a LOCOS method. According to a preferred embodiment of the present invention, a thin-film SOi device is provided, in which the gate ends at the transition between the intelligent dielectric layer and the drift dielectric interval. The advantage of this feature is to be formed at the end of the electric field and above the additional dielectric layer. During the transition, any layer (those deposited on the field plate) and another dielectric layer can be deposited at will. In addition, the unknown position of the field plate is well-defined in order to minimize the vertical offset of electrons in the drift region, and design the thickness of the silicon layer and the second dielectric layer or the upper oxide layer. According to a preferred embodiment of the present invention, a thin film SOI device is provided, which includes another dielectric layer covering at least a gate electrode and a drift dielectric layer. According to a preferred embodiment of the present invention, a thin-film SOi device is provided, which includes another field plate extending across another dielectric layer (46). In this example, an additional field plate supplements the field plate extension of the gate electrode. Adapt to the field plate configuration to control the complete drift region in the silicon layer, or protect the drift region from external influences. According to a preferred embodiment of the present invention, a thin film SOI device is provided, in which another field plate extends almost to one end of the drift dielectric layer. According to a preferred embodiment of the present invention, a thin film SOI device is provided, in which another field plate is connected to a source, whereby the other field plate and a gate field plate which is beneficial to the control device extend at the same potential level. According to a preferred embodiment of the present invention, a thin-film sol device is provided, in which the gate is composed of polycrystalline silicon, as is well known in the art, which facilitates the integration of the steps of manufacturing the gate during the device manufacturing process. According to a preferred embodiment of the present invention, a thin-film SOI device is provided, in which another 200406924 plate is composed of metal, and the shape of the other plate during the manufacturing process of the device is well defined. & Ming_A preferred example provides a thin film device, in which another field is composed of a first metal layer and a second metal layer, where the second metal layer is isolated from the first metal layer, and the first metal layer is caged and isolated. It can be connected to the gate, and the second '9 can be connected to the source or the intermediate electrode, or to any separate potential that is used to control the drift region. According to a preferred embodiment of the present invention, a thin film SOI device is provided in which a second metal layer and a first metal layer are separated by a dielectric layer. The other IsU cases of this month describe their characteristics in the remaining items of the patent scope. -Thin film lateral SOI device includes-substrate ... buried oxide layer on the substrate. A layer of silicon buried oxide (SOI, silicon-on-insulator), a dielectric layer (taken to form an oxide layer), a gate or field plate on top of this dielectric layer. The device layer is formed from below by isolating the dielectric film from the area contact holes and the purification layer. The device is gradually reduced in thickness toward the anode, while the oxide layer is gradually increased in thickness. The use of a metal layer removes the field plate from the SOI layer and reduces the vertical electric field. In order to minimize the misalignment of the minimum potential of the electrons along the device, the thickness of the SOI film and the dielectric layer under the field plate are matched according to an equation. This reduces the carrier multiplication caused by impact ionization, thereby allowing higher lateral electric fields. Two allow + shorter clothes are used for known voltage levels. Decreasing the drift region, increasing the thickness of the S0I film, and reducing the area, the above items can contribute individually or in combination to reduce specific on-resistance (Qnlstance), especially in high-side operation. 200406924

(6)(6)

上述裝置為一步進及階梯S〇I裝置或一步進及階梯 SOCOS(矽-氧化物-通道-氧化物-矽）裝置，形成— ldm〇s 。本發明可應用至任何薄膜S0I裝置，其在上氧化層或電極 (或場板）末端引起的位準過渡中具有步進過渡。藉由根據本 發明教示設計裝置的場板，可策劃額外上氧化層厚度的變 化，以使電子的電位槽平整。本發明的裝置t，可再將埋 藏式氧化層上矽層的薄部分移往集極，以減少高側操作中 的擠壓效應’並因此改良裝置的電流驅動。 附圖簡單說明 茲將參照至附圖說明本發明一實例的此等及其他多種優 點，其中 圖1以示意剖面圖說明此藝的一階梯式薄膜橫向覆矽絕 緣層裝置； 圖2根據本發明一實例，以示意剖面圖說明一薄膜橫向覆 矽絕緣層裝置；及The above device is a step and step SOI device or a step and step SOCOS (silicon-oxide-channel-oxide-silicon) device, forming ldm0s. The invention can be applied to any thin film SOI device, which has a step transition in the level transition caused by the upper oxide layer or the end of the electrode (or field plate). By designing the field plate of the device in accordance with the teachings of the present invention, changes in the thickness of the additional upper oxide layer can be planned to flatten the potential cell of the electron. In the device t of the present invention, a thin portion of the silicon layer on the buried oxide layer can be moved to the collector again to reduce the squeezing effect 'in high-side operation' and therefore improve the device's current drive. Brief description of the drawings: These and other advantages of an example of the present invention will be described with reference to the accompanying drawings, in which FIG. 1 illustrates a stepped thin film lateral silicon insulating layer device of the art in a schematic cross-sectional view; FIG. 2 according to the present invention An example illustrating a thin film lateral silicon-on-insulator device in a schematic cross-sectional view; and

圖3根據本發明另一實例，以示意剖面圖說明一薄膜橫向 覆矽絕緣層裝置。 附圖詳細說明 用 本發明的薄膜橫向SOI裝置40實例以圖2說明，圖中使 相同參考數目說明如圖1中之相同零件。 一本發明的薄膜橫向S0I裝置亦具有一埋藏式氧化層‘ 一基板（未示）上，及一矽層6在埋藏式氧化層4上，矽層 -、有第厚度區8、第一厚度區10，及第三厚度區 在矽層6上面的氧彳匕層包括一閘極氧化層18、一場氧化/ -10- 200406924 ⑺ 20 ’及一漂移氧化層22，它們分別設置在矽層6的厚度區8 、10 、 12 〇 本發明如圖2所示的薄膜橫向s〇I裝置40由一閘極42所 組成，閘極42位於一通道區38之上，並延伸成一場板44 在問極氧化層18及場氧化層20之上。依SOI區1〇及12的厚 度與漂移氧化層22的厚度，閘極場板結束於此過渡24，藉 此使厚度能與將***場板48與SOI膜12間的另一介電層46 匹配。思即多晶矽閘極42正結束於從第一石夕層厚度區8的 場氧化層（F〇x)至第二矽層厚度區1〇的漂移氧化層（D〇x) 的過渡24。 1 至少由另一氧化層46覆蓋閘極42、場板44及漂移氧化層 22 另 场板4 8由源極3 2橫跨另一氧化層4 6延伸，幾乎到 達/示移氧化層22的一末端並覆蓋另一氧化層46。當閘極在 場氧化層20與漂移氧化層22間的過渡24結束時，就如此藝 現況的裝置般，另一氧化層46及另一場板48皆橫跨閘極延 伸與場氧化層而平滑延伸，如同此領域中無步進般。另一 場板48可由源極32的延伸具體化.，並由一金屬層所組成， 藉此可維持一平順的最小電子電位平面B(圖2)。 圖1裝置中，在矽層的電子電位最小極限由上氧化層厚度 (TOx)、埋藏式氧化層厚度（B0x)及矽膜厚度（ts〇i)間的關係 表示如下： Ο) (TOx^BOx)^-^ ts〇I' 200406924 ⑻ 用於第一氧化層厚度區2〇,及 ΤΟχΊ *s — * ε 2 Sl 2 so 1 b〇x (2) (ΓΟχ2 + 50x) * + ε〇χ hoi1 用於漂移氧化層20加上另一氧化層34的厚度，其中： BOx係埋藏式氧化層4的厚度 丁〇xl係場氧化層20的厚度 T0x2係漂移介電層22的厚度加上另一介電層牝的厚度 ts〇n係第二厚度矽區1〇的厚度 tsoi2係第三厚度矽區12的厚度 ssi係矽的介電常數 εοχ係氧化層的介電常數。 作為一範例，圖1所示此藝現狀的裝置具有ts〇n = 10 μηι ，丁0x1 = 775 nm，ΒΟχ=3 μιη，tSOI2=425 nm，及 Τ〇χ2 = 2·0 μηι ，在氧化層過渡埋藏式氧化層之上電位最小極限從233 nm 改變至168 nm，並在從多晶矽至場板28至金屬場板36的過 渡回到195 nm，此由圖1中的線a示出。 圖2的裝置中在矽層的電子電位最小極限係根據下列上 氧化層厚度（TOx)、埋藏式氧化層厚度（B〇x)及矽膜厚度 (tSOI)間的關係選取如下： Τ0χ'Ά、、χ TOx2*a^Lts〇i^s〇x lSOIl (ΓΟχ丨+綠)* i + 心(TOx2^BOx) s hoi. 其中： -12- (3) 200406924 (9) 發明說讎頁 TOxl係場板至過渡（24)左邊以下全部介電層之整體厚度 TOx2係場板至過渡（24)右邊之下全部介電層之厚度， Β Οχ係埋臧式氣化層的厚度 tson係覆矽絕緣層至過渡（24)左邊的厚度 tson係覆矽絕緣層至過渡（24)右邊的厚度 ε Sl係矽之介電常數 e ox係介電層之介電常數。 換吕之’藉由在漂移區的兩區域中選取厚度參數而使等 式的左手項目等於其右手項目，可如圖2的線B所示般整平 SOI層（區域1〇)中電子電位井的垂直錯置。 本發明在圖2所示的裝置造成從233過渡至246 nm ,或藉 由將場板末端併入過渡24 ’及選擇ts〇n = i μπι，ts〇i2=56〇 nm ’ TOxl = 〇,775 μπι，τ〇χ2=2 3 μιηΑΒ〇χ=3 μπι，而成為先 前值的九分之一，根據等式（3)調整埋藏式氧化層及矽層的 厚度造成電位槽深度減少。 本發明另一薄膜橫向S〇l裝置50實例如圖3所示，其中使 用相同參考數字說明如圖1及2中的相同零件。 衣ι50中，另一場板由一第一金屬層52及一第二金屬層 54所具體化，並由一氧化層56隔開第二金屬層與第一金屬 層52，第二金屬層可連接至源極，連接至閘極，或連接至 一分開電位，如圖3所見，場板54以下SOI層厚度中的另一 變化造成一 soi厚度區12及14，其中sons 14相較5〇1區12 的厚度又具有較小的厚度。 對圖3所示本發明的裝置而言，下列等式係成立的·· -13- 2004069243 is a schematic cross-sectional view illustrating a thin film lateral silicon insulating layer device according to another example of the present invention. Detailed description of the drawings An example of a thin film lateral SOI device 40 according to the present invention will be described with reference to Fig. 2, which uses the same reference numerals to describe the same parts as in Fig. 1. A thin film lateral SOI device of the present invention also has a buried oxide layer on a substrate (not shown), and a silicon layer 6 on the buried oxide layer 4. The silicon layer has a first thickness region 8 and a first thickness. The region 10 and the third thickness region above the silicon layer 6 include a gate oxide layer 18, a field oxide / -10-200406924 ⑺ 20 ', and a drift oxide layer 22, which are disposed on the silicon layer 6 respectively. The thickness region 8, 10, 12 of the present invention is shown in Figure 2. The thin film lateral so device 40 is composed of a gate 42 that is located above a channel region 38 and extends into a field plate 44 at Above the interlayer oxide layer 18 and the field oxide layer 20. Depending on the thickness of the SOI regions 10 and 12 and the thickness of the drift oxide layer 22, the gate field plate ends at this transition 24, thereby enabling the thickness to be equal to another dielectric layer 46 that will be inserted between the field plate 48 and the SOI film 12. match. That is, the polysilicon gate 42 is ending at the transition 24 from the field oxide layer (Fox) of the first silicon layer thickness region 8 to the drift oxide layer (Dox) of the second silicon layer thickness region 10. 1 At least the gate electrode 42, the field plate 44 and the drift oxide layer 22 are covered by another oxide layer 46. The other field plate 4 8 extends from the source electrode 3 2 across the other oxide layer 4 6 and almost reaches / shows the oxide layer 22 One end and covers another oxide layer 46. When the transition 24 between the gate oxide layer 20 and the drift oxide layer 22 ends, as in the current device, the other oxide layer 46 and the other field plate 48 extend across the gate and the field oxide layer to be smooth. Extension as if there is no step in this field. The other field plate 48 can be embodied by the extension of the source electrode 32 and is composed of a metal layer, thereby maintaining a smooth minimum electron potential plane B (Fig. 2). In the device of Fig. 1, the minimum limit of the electron potential in the silicon layer is represented by the relationship between the thickness of the upper oxide layer (TOx), the thickness of the buried oxide layer (B0x), and the thickness of the silicon film (ts〇i) as follows: Ο) (TOx ^ BOx) ^-^ ts〇I '200406924 ⑻ Used for the first oxide thickness region 20, and Τχχ * s — * ε 2 Sl 2 so 1 b〇x (2) (ΓΟχ2 + 50x) * + ε〇χ hoi1 is used for the thickness of drift oxide layer 20 plus another oxide layer 34, where: the thickness of BOx buried oxide layer 4 but the thickness of field oxide layer 20 and the thickness of T0x2 drift dielectric layer 22 plus another The thickness tson of a dielectric layer 系 is the thickness of the second thickness silicon region 10 and the thickness tsoi2 is the thickness of the third thickness silicon region 12. The ssi is the dielectric constant of the silicon and the dielectric constant of the oxide layer. As an example, the state-of-the-art device shown in FIG. 1 has tsoon = 10 μηι, but 0x1 = 775 nm, βχ = 3 μιη, tSOI2 = 425 nm, and Τχ2 = 2.0 μηι. The minimum limit of the potential above the transitional buried oxide layer changes from 233 nm to 168 nm, and returns to 195 nm during the transition from polycrystalline silicon to field plate 28 to metal field plate 36, which is shown by line a in FIG. 1. The minimum electronic potential limit of the silicon layer in the device of FIG. 2 is selected according to the following relationships between the thickness of the upper oxide layer (TOx), the thickness of the buried oxide layer (B0x), and the thickness of the silicon film (tSOI): Τ0χ'Ά , Χ TOx2 * a ^ Lts〇i ^ s〇x lSOIl (ΓΟχ 丨 + green) * i + heart (TOx2 ^ BOx) s hoi. Among them: -12- (3) 200406924 (9) Invention page TOxl Total thickness of all dielectric layers below the left of the field plate to the transition (24) TOx2 The thickness of all dielectric layers from the field plate to the right of the transition (24) below, Β χχ is the thickness of the buried gasification layer tson system coating The thickness tson on the left side of the silicon insulating layer to the transition (24) is the thickness on the right side of the silicon insulating layer to the transition (24) ε Sl is the dielectric constant of the silicon e ox is the dielectric constant of the dielectric layer. For Lü Zhi ', by selecting the thickness parameter in the two regions of the drift region, the left-hand term of the equation is equal to its right-hand term, and the electron potential in the SOI layer (area 10) can be leveled as shown by line B in FIG. 2 Vertical misalignment of the well. The device shown in FIG. 2 of the present invention causes the transition from 233 to 246 nm, or by incorporating the end of the field plate into the transition 24 ′ and selecting ts〇n = i μπ, ts〇i2 = 56〇 nm 'TOxl = 〇, 775 μπ2, τ〇χ2 = 2 3 μιηΑΒ〇χ = 3 μπι, which becomes one-ninth of the previous value. Adjusting the thickness of the buried oxide layer and silicon layer according to equation (3) causes the depth of the potential tank to decrease. An example of another thin film lateral sol device 50 of the present invention is shown in Fig. 3, in which the same parts as in Figs. 1 and 2 are explained using the same reference numerals. In the clothes 50, another field plate is embodied by a first metal layer 52 and a second metal layer 54 and an oxide layer 56 separates the second metal layer from the first metal layer 52, and the second metal layer can be connected To the source, to the gate, or to a separate potential, as seen in Figure 3, another change in the thickness of the SOI layer below the field plate 54 results in a soi thickness region 12 and 14, where sons 14 is compared to 501. The thickness of the region 12 again has a smaller thickness. For the device of the present invention shown in FIG. 3, the following equations are established ... 13-200406924

(ίο) TOX''々'h〇i'、x Τ〇'Ά30!ι、χ TOx^esl^tSOI^s〇x (ΤΟχ^ΒΟχ)^^ε〇χ (ΤΟχ2^ΒΟχ)^ + ε〇χ ^^Οχ^ΒΟχ)^~ ° tso 丨' S ts〇h ox 其中： B〇x係埋藏式氧化層4之厚度(ίο) TOX``々'h〇i ', x Τ〇'Ά30! ι, χ TOx ^ esl ^ tSOI ^ s〇x (ΤΟχ ^ ΒΟχ) ^^ ε〇χ (ΤΟχ2 ^ ΒΟχ) ^ + ε〇 χ ^^ Οχ ^ ΒΟχ) ^ ~ ° tso 丨 'S ts〇h ox where: B〇x is the thickness of the buried oxide layer 4

T〇xl係場板至過渡24左邊以下全部介電層的整體厚度 Τ〇X 2係场板至過渡2 4右邊之下全部介電層的厚度，即$ 移介電層22厚度加上另一介電層46的厚度 ΤΟχ3係另一場板54之下全部介電層的厚度，即第三介電 層厚度區的厚度加上另一介電層46的厚度，再加上介電層 56的厚度 ts〇ii係第一石夕層厚度區10的厚度 tS()i2係該第二矽層厚度區12的厚度 ts〇i3係第三矽層厚度區14至第二矽層厚度區12右邊的厚 度The overall thickness of all dielectric layers below the left side of the Toxl series field plate to the transition 24, and the thickness of all the dielectric layers below the right side of the 2x field system to the transition 24, ie, the thickness of the mobile dielectric layer 22 plus another The thickness of one dielectric layer 46 is the thickness of all the dielectric layers under the other field plate 54, that is, the thickness of the third dielectric layer thickness region plus the thickness of the other dielectric layer 46, plus the dielectric layer 56. The thickness ts〇ii is the thickness tS () i2 of the first silicon layer thickness region 10 is the thickness of the second silicon layer thickness region 12 ts〇i3 is the third silicon layer thickness region 14 to the second silicon layer thickness region 12 Right thickness

ε3ί係矽之介電常數 £。<係介電層之介電常數。 圖3所示本發明的裝置中，ts〇I尸i μηι, ts〇i2 = 56〇 nm， TOxl = 0,775 nm，TOx2 = 2.3 μπι，tS0l3 = 425 nm及 Τ〇χ3 = 3·1 •um，及ΒΟχ = 3 μπι，及埋藏式氧化層至矽層介面之上的電 子電位為215 nm，在矽層中心成對稱。此實例中同樣可如 圖3中線C所示，將SOI層（區域12,14)中電子電位井的垂直 錯置整平。 此文件所涵蓋本'發明的新特徵及優點已由前述說明提出 200406924ε3ί is the dielectric constant of silicon. < The dielectric constant of the dielectric layer. In the device of the present invention shown in FIG. 3, ts〇i 尸 i μηι, ts〇i2 = 56〇nm, TOxl = 0,775 nm, TOx2 = 2.3 μπι, tS0l3 = 425 nm and TOX3 = 3.1 · um, And B〇χ = 3 μπι, and the electron potential of the buried oxide layer to the silicon layer interface is 215 nm, which is symmetrical at the center of the silicon layer. In this example, the vertical offset of the electron potential wells in the SOI layer (areas 12, 14) can also be leveled as shown by line C in FIG. 3. The new features and advantages of this invention covered by this document have been proposed by the foregoing description 200406924

〇1) ’惟應了解此揭示在許多方面僅作說明，不逾越本發明範 缚可在細節上變化，尤其在形狀、尺寸及零件配置等事項 上’本發明的範疇當然由後附申請專利範圍所表達的 所界定。‘ 予 圖式代表符號說明 2, 40, 50 裝置 4 埋藏式氧化層 6 石夕層 8 第一厚度矽區 10 弟二厚度砍區 12 第三厚度矽區 14 第一過渡 16 第二過渡 18 閘極介電層 20 場介電層 22 漂移介電層 24 氧化層過渡 26, 42 閘極 28, 44 場板 30 >及極 32 源極 34 另一氧化層 36 另一金屬場板 38 通道區〇1) 'However, it should be understood that this disclosure is only for explanation in many aspects, and it can be changed in details without exceeding the scope of the present invention, especially in matters such as shape, size, and component arrangement. What the scope expresses. '' Pre-Schematic Symbols Description 2, 40, 50 Device 4 Buried oxide layer 6 Shi Xi layer 8 First thickness silicon area 10 Second thickness silicon area 12 Third thickness silicon area 14 First transition 16 Second transition 18 Gate Polar dielectric layer 20 field dielectric layer 22 drift dielectric layer 24 oxide layer transition 26, 42 gate 28, 44 field plate 30 > and pole 32 source 34 another oxide layer 36 another metal field plate 38 channel area

-15- 200406924 (12) 46 另一介電層 48 場板 52 第一金屬層 54 第二金屬層 56 氧化層 發瞬說賴續質-15- 200406924 (12) 46 another dielectric layer 48 field plate 52 first metal layer 54 second metal layer 56 oxide layer

-16--16-

Claims (1)

200406924 拾、申請專利範圍 1. 一種薄膜橫向覆石夕絕緣層（s〇i)裝置，包括： 一基板及一埋藏式氧化層（4)(Β〇χ)於基板上作為介 電層； 一石夕層（6)，位於埋砥式氧化層上，該石夕層包括一第一 厚度矽區（8)，一第二厚度矽區（1〇)，其厚度小於第一厚 度矽區（8)，及一第三厚度矽區（12),其厚度小於第二厚 度矽區（10) ; φ 一介電層（TOx)，位於矽層（6)之上，包括一閘極介電 層（18)位於第一厚度矽區（8)之上、一場介電層（2〇)位於 第二厚度矽區（10)之上，其中場介電層（20)厚度大於閘 極介電層（18)之厚度，及一漂移介電層（22)位於第三厚 - 度矽區（12)之上，漂移介電層（22)厚度大於場介電層（2〇) 之厚度； 一閘極（42)，位於一通道區（38)上方之閘極介電層（1 8) 之上； 一場板（44)，橫跨場介電層（2〇)而延伸； φ 一汲極（30) ’於橫向與矽層（6)之第三厚度矽區（12)相 隔；及 一源極（32)，於橫向與閘極分開。 2·如申請專利範圍第1項之薄膜SOI裝置，其中該介電層最 好係由一 LOCOS方法製成之氧化層。 3.如申請專利範圍第1或2項之薄膜SOI裝置，其中該問 極（42)中止於場介電層（20)與漂移介電層（22)間之過渡 (24)。 4· (24)。 4· 5. 6. 7. 8. 9. 10 11 12 如申請專利範圍第i、2或3項之薄膜s〇I裝置，包括另/ 介電層（46)，至少覆蓋閘極（42)及漂移介電層（22)。 如申請專利範圍先前任一項之薄膜SOI裝置，包括另一 場板（48;52,54)橫跨另一介電層（46)而延伸。 如申請專利範圍第5項之薄膜SOI裝置，其中該另一場板 (48;52,54)幾乎延伸至漂移介電層（22)之末端。 如申請專利範圍第5或6項之薄膜SOI裝置，其中該另/ 場板（48;52,54)連接至源極（32)。 如申請專利範圍第1項之薄膜SOI裝置，其中該另一場板 (42)由多晶硬組成。 i 如申請專利範圍第5項之薄膜SOI裝置，其中該另一場板 (48)由金屬組成。 如申請專利範圍第5項之薄膜SOI裝置，其中該另一場板 由一第一金屬層（52)及一第二金屬層（54)組成，第二金 屬層（54)與第一金屬層（52)隔離。 如申請專利範圍第10項之薄膜SOI裝置，其中該第二金 屬層（54)由一介電層（56)與第一金屬層（52)隔離。 如申請專利範圍先前任一項之薄膜SOI裝置，其中該S〇l 及介電層之厚度係根據以下公式而相關聯·♦ T0xx * esi + - ts〇h ^ εοχ Τ0χ2 * + -* εοχ {T〇xx^B〇xy^-^sox (τ〇χ2 + β〇χ，反十ε〇χ hoi' lS〇l2 其中： 200406924200406924 Patent application scope 1. A thin film lateral stone-covered insulating layer (SO) device, comprising: a substrate and a buried oxide layer (4) (B0χ) on the substrate as a dielectric layer; a stone The layer (6) is located on the buried oxide layer. The layer includes a first-thickness silicon region (8) and a second-thickness silicon region (10), the thickness of which is less than the first-thickness silicon region (8). ), And a third-thickness silicon region (12), the thickness of which is smaller than the second-thickness silicon region (10); φ a dielectric layer (TOx), located on the silicon layer (6), including a gate dielectric layer (18) is located on the first thickness silicon region (8) and the field dielectric layer (20) is located on the second thickness silicon region (10), wherein the field dielectric layer (20) is thicker than the gate dielectric layer (18), and a drift dielectric layer (22) is located on the third thick-degree silicon region (12), and the thickness of the drift dielectric layer (22) is greater than the thickness of the field dielectric layer (20); The gate (42) is located above the gate dielectric layer (18) above a channel region (38); the field plate (44) extends across the field dielectric layer (20); φ a drain (30) 'Yu Heng And the silicon layer (6) of a third thickness of silicon region (12) separated; and a source (32), the lateral and the gate apart. 2. The thin-film SOI device according to item 1 of the patent application range, wherein the dielectric layer is preferably an oxide layer made by a LOCOS method. 3. The thin film SOI device according to item 1 or 2 of the patent application scope, wherein the question (42) is stopped at the transition (24) between the field dielectric layer (20) and the drift dielectric layer (22). 4. · (24). 4 · 5. 6. 7. 8. 9. 10 11 12 If the thin film SOC device of item i, 2 or 3 of the scope of patent application includes an additional / dielectric layer (46), at least the gate (42) And a drift dielectric layer (22). For example, a thin-film SOI device of any of the previous patent application scopes includes another field plate (48; 52, 54) extending across another dielectric layer (46). For example, the thin film SOI device of the scope of application for patent No. 5 wherein the other field plate (48; 52, 54) extends almost to the end of the drift dielectric layer (22). For example, the thin film SOI device with the scope of patent application No. 5 or 6, wherein the other / field plate (48; 52, 54) is connected to the source (32). For example, the thin film SOI device of the scope of application for patent No. 1 wherein the other field plate (42) is composed of polycrystalline hard. i The thin-film SOI device according to item 5 of the patent application, wherein the other field plate (48) is composed of metal. For example, the thin film SOI device with the scope of application for patent No. 5 wherein the other field plate is composed of a first metal layer (52) and a second metal layer (54), and the second metal layer (54) and the first metal layer ( 52) Isolation. For example, the thin-film SOI device of the scope of application for patent No. 10, wherein the second metal layer (54) is isolated from the first metal layer (52) by a dielectric layer (56). For example, the thin film SOI device of any of the previous claims, where the thickness of the S0l and the dielectric layer is related according to the following formula: T0xx * esi +-ts〇h ^ εοχ Τ0χ2 * +-* εοχ { T〇xx ^ B〇xy ^-^ sox (τ〇χ2 + β〇χ, inverse ε〇χ hoi 'lS〇l2 where: 200406924 T〇xl係％板至過渡（24)左邊之下全部介電層之整體厚 度 ^ Τ〇χ2係場板至過渡（24)右邊之下全部介電層之整體厚 度 BOx係埋藏式氧化層之厚度 ts〇ii係覆矽絕緣層至過渡（24)左邊之厚度 ts〇i2係覆矽絕緣層至過渡（24)右邊之厚度 丨係矽之介電常數 8。<係介電層之介電常數。 1 3 .如申請專利範圍第1至11任一項之薄膜s〇I裝置，其中 SOI及介電層之厚度係根據以下公式而相關聯： TOxx ^ ssi + — SOI, T0x2 6si ^ 9 tS〇l2、 TOxz^ssi (ΤΟχχ+ΒΟχ)^^ + εα (Γ0χ2 + 50x)*-£l_ + hoi, (TOx，BOxy 上 ^o/3 0 其中 BOx係埋藏式氧化層（4)之厚度 T〇xl係場板至過渡（24)左邊以下全部介電層之敕體厚 度 Τ〇χ2係場板至過渡（24)右邊之下全部介電層之厚户 漂移介電層（22)厚度加上另一介電層(46)之厚度· 即第三，介 再加上 Τ〇χ3係另一場板（48)之下全部介電層之厚度， 電層厚度區之厚度加上另一介電層（46)之厚戶： 介電層(56)之厚度 tsoil係第一石夕層厚度區（10)之厚度 200406924The overall thickness of all dielectric layers below the left side of Toxl series plate to the transition (24) ^ The overall thickness of all dielectric layers below the left side of the transition plate (24) to the bottom of the transition plate (24) The thickness ts〇ii is the thickness on the left side of the silicon insulation layer to the transition (24). Ts〇i2 is the thickness on the right side of the silicon insulation layer to the transition (24). It is the dielectric constant 8 of silicon. < The dielectric constant of the dielectric layer. 1 3. The thin film SOC device according to any one of claims 1 to 11, wherein the thickness of the SOI and the dielectric layer are related according to the following formula: TOxx ^ ssi + — SOI, T0x2 6si ^ 9 tS. l2, TOxz ^ ssi (ΤΟχχ + ΒΟχ) ^^ + εα (Γ0χ2 + 50x) *-£ l_ + hoi, (TOx, on BOxy ^ o / 3 0 where BOx is the thickness T of the buried oxide layer (4). xl series field plate to transition (24) the thickness of all dielectric layers below the left of the dielectric layer Τχ2 series field plate to the transition (24) the thickness of all the dielectric layers below the right and the thickness of the drift dielectric layer (22) plus The thickness of the other dielectric layer (46), that is, the third, the dielectric plus the thickness of all dielectric layers under the TOX3 series field plate (48), the thickness of the thickness area of the dielectric layer plus another dielectric Thicker layer (46): The thickness of the dielectric layer (56) tsoil is the thickness of the first stone layer thickness region (10) 200406924 tsoi2係該第二矽層厚度區（12)之厚度 tsoi3係第三矽層厚度區（14)至第二矽層厚度區（12)右邊 之厚度 ssi係矽之介電常數 €0?(係介電層之介電常數。tsoi2 is the thickness of the second silicon layer thickness region (12), tsoi3 is the thickness of the third silicon layer thickness region (14) to the second silicon layer thickness region (12), and ssi is the dielectric constant of silicon. The dielectric constant of the dielectric layer.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI584473B (en) * 2016-08-10 2017-05-21 亞洲大學 Half bridge high voltage level shifter and method for manufacturing the same

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7501669B2 (en) 2003-09-09 2009-03-10 Cree, Inc. Wide bandgap transistor devices with field plates
US7573078B2 (en) 2004-05-11 2009-08-11 Cree, Inc. Wide bandgap transistors with multiple field plates
US7550783B2 (en) 2004-05-11 2009-06-23 Cree, Inc. Wide bandgap HEMTs with source connected field plates
US9773877B2 (en) 2004-05-13 2017-09-26 Cree, Inc. Wide bandgap field effect transistors with source connected field plates
US11791385B2 (en) 2005-03-11 2023-10-17 Wolfspeed, Inc. Wide bandgap transistors with gate-source field plates
TW200735361A (en) 2005-12-14 2007-09-16 Koninkl Philips Electronics Nv MOS transistor and a method of manufacturing a MOS transistor
US7592211B2 (en) 2006-01-17 2009-09-22 Cree, Inc. Methods of fabricating transistors including supported gate electrodes
US7709269B2 (en) 2006-01-17 2010-05-04 Cree, Inc. Methods of fabricating transistors including dielectrically-supported gate electrodes
US8823057B2 (en) 2006-11-06 2014-09-02 Cree, Inc. Semiconductor devices including implanted regions for providing low-resistance contact to buried layers and related devices
JP5105160B2 (en) 2006-11-13 2012-12-19 クリー インコーポレイテッド Transistor
US7692263B2 (en) 2006-11-21 2010-04-06 Cree, Inc. High voltage GaN transistors
GB2451122A (en) * 2007-07-20 2009-01-21 X Fab Uk Ltd Low threshold voltage transistor with non-uniform thickness gate dielectric
CN103633136B (en) * 2012-08-20 2016-02-10 上海华虹宏力半导体制造有限公司 LDMOS device and manufacture method thereof
US9679981B2 (en) 2013-06-09 2017-06-13 Cree, Inc. Cascode structures for GaN HEMTs
US9847411B2 (en) 2013-06-09 2017-12-19 Cree, Inc. Recessed field plate transistor structures

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6346451B1 (en) * 1997-12-24 2002-02-12 Philips Electronics North America Corporation Laterial thin-film silicon-on-insulator (SOI) device having a gate electrode and a field plate electrode
WO1999034449A2 (en) * 1997-12-24 1999-07-08 Koninklijke Philips Electronics N.V. A high voltage thin film transistor with improved on-state characteristics and method for making same
DE19800647C1 (en) * 1998-01-09 1999-05-27 Siemens Ag SOI HV switch with FET structure
US6232636B1 (en) * 1998-11-25 2001-05-15 Philips Electronics North America Corporation Lateral thin-film silicon-on-insulator (SOI) device having multiple doping profile slopes in the drift region

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI584473B (en) * 2016-08-10 2017-05-21 亞洲大學 Half bridge high voltage level shifter and method for manufacturing the same

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