200307296 玖、發明說明： t 明所屬領域】 發明領域 本發明係有關一種測試位於積體電路上之記憶體裝置 5 之方法及測試此種裝置之方法。 L先前技術3 發明背景 多種新近積體電路採用先進先出（FIF0)記憶體裝置。 例如切換裝置典型包括此種FIFO記憶體裝置於各輸入埠。 10典型FIFO記憶體裝置係實施為雙埠記憶體，比以暫存器為 主之5己憶體貫作更輕薄短小。類似全部積體電路，此種記 憶體裝置偶爾故障，需要測試，既確保所得之積體電路為 可操作，同時也於積體電路製造過程辨識出故障。 目前測試記憶體之有利方法為BIST(内建自我測試）， 15顯示於第1圖。記憶體裝置1有一位址輸入Addr供接收界定 吕己憶體一個所在位置的位址，一資料輸入D供載明與寫入該 位址之資料以及一控制輸入C ’若該載明的資料欲寫至載明 的位址，則控制輸入C接收「寫」或「讀」指令。積體電路 包括一BIST模組3及開關5、7、9。 20 於積體電路之測試模期間，開關5、7、9傳輪BIST模組 3至記憶體裝置1各別的輸入。因此BIST傳輸預定序列之輸 入給記憶體裝置1，記憶體裝置丨之輸出經監視，俾判定記 憶體裝置1是否經由其輸出端子Η輸出對應預定輸出信 號。BIST模組3確保確知已知信號發送至記憶體裝置之全部 200307296 輪入端，故記憶體裝置可可靠地單獨測試，即使積體電路 之其它所在位置有故障，記憶體裝置仍然可可靠地單獨測 试。 但一旦完成測試操作，則積體電路開始正常操作。於 5此種模，開關5、7、9確保各別信號13、15、17(可由積體 電路的其它模組產生，或另外可由積體電路接收自外側)傳 輪至記憶體裝置之輸入端Addr、D及C。於積體電路之此種 正常操作中，BIST模組3絲毫也未使用，BIST模組3及開關 13、15、17構成積體電路整體效率及面積的額外負擔。 10 當積體電路包含複數個記憶體裝置1時(例如當積體電 路為有多個輸入埠之切換裝置時），對每個記憶體裝置1提 供一個BIST模組3構成重大的額外負擔。但另外，只提供單 一BIST模組3且輪流使用該BIST模組3來測試複數個記憶 體裝置，又造成積體電路邏輯顯著變複雜，因而難以提供 15 對稱電路設計。 t發明内容3 發明概要 本發明尋求解決前述問題，特別提供一種新顆積體電 路以及測試積體電路之新穎方法。 20 ㈣略言之本發明提示—種帶有-或多記憶體裝置之積 體電路，其測試方法係於積體電路内部傳輸(〇一位址信號 其指示-記憶體位址，⑼一資料信號其指示該位址之資 料，以及㈣對各記憶體裝置傳輸_各別指令信?虎，該指令 #號‘不4貝料是否將寫至各別記憶體裝置。監視由各記 200307296 十思體裝置輸出之資料以及至少部分其接收之資料。 因資料係於晶片外部產生，故積體電路無需BIST模組 來產生確切已知信號給記憶體裝置之全部輸入端。確實與 BIST方法相反’如此表示到達記憶體模組之資料於其送至 5 §己憶體裝置途中由於積體電路之其它故障而可能與預定的 輸入説疾。但輸入記憶體裝置之資料以充分準確度監視， 監視其是否因積體電路上記憶體裝置以外之錯誤造成訛 誤’發現該項事實，記憶體裝置將不會被不正確地歸咎產 生該項錯誤。 1〇 換言之與基於額外測試邏輯（該邏輯僅於測試程序期 間使用）之功能測試相反，本發明可對記憶體裝置作功能測 試。如此本發明經由免除需要提供其它晶片上邏輯，而可 顯著節省成本。 發明人進一步提議，監視輸入各記憶體裝置之資料包 15含只監視由位址信號及指令信號形成的監視信號。若監視 #號係藉包括（或邏輯上等於)x〇R操作之操作預先形成且 送至掃描暫存器，則此種監視特別有效，原因在於該種情 況下當位址信號及指令信號恆變時，監視信號也將恆變··換 吕之監視信號有效壓縮完整位址信號及指令信號。 2〇 特別於本發明之第一方面為一種積體電路，其包括一 或多個記憶體裝置，各個記憶體裝置有一位址輸入端，其 係i、接收載明記憶體之一位址之一位址信號，一資料輸入 端其係供接收資料，一指令輸入端其係供接收指令信號， 4 4曰々彳a號‘示該資料是否欲寫入該位址，以及一輸出端， 200307296 該積體電路進一步包括一監視單元，其係供由至少若 干輸入各個記憶體裝置之信號導出一監視信號。 本發明之第二方面為一種測試包括一或多記憶體裝置 之積體電路之方法，各個記憶體裝置有一位址輸入端，其 5 係供接收載明記憶體之一位址之一位址信號，一資料輸入 端其係供接收資料，一指令輸入端其係供接收指令信號， 該指令信號指示該資料是否欲寫入該位址，以及一輸出端， 該方法包含： 傳輸信號至積體電路，讓該一或多記憶體裝置各自接 10 收一位址信號、一資料信號以及對各記憶體裝置接收一對 應指令信號， 監視至少若干輸入各記憶體裝置之信號以及由記憶體 裝置輸出之信號。 圖式簡單說明 15 現在將參照以下各圖說明本發明之具體實施例之細 節，該等說明僅供舉例說明之用，附圖中： 第1圖示意顯示已知BIST記憶體測試方案；以及 第2圖顯示根據本發明，設置於積體電路之記憶體裝置 之組態。 20 【實施方式】 較佳實施例之詳細說明 參照第2圖，顯示一種記憶體裝置21，其具有一位址輸 入端Addr供接收載明記憶體内部位址之位址信號，一資料 輸入端D供接收載明欲寫入該位址之資料之資料信號，以及 200307296 一控制輸入端c，若載明之資料欲寫入該載明的位址，則該 控制輸入端c接收「寫入」指令。比較第1圖所示組態，本 具體實施例有額外XOR閘（監視單元)23,其接收位址信號25 及控制信號27作為輸入信號，以及產生組合信號29。 5 記憶體裝置21典型為設置於一積體電路上的複數個相 等組成之記憶體裝置之一。積體電路接收於積體電路外部 產生的資料，且傳輸給全部記憶體裝置，該等資料包含一 位址信號（串聯位址）、一資料信號以及各個記憶體裝置之一 各別指令信號。資料信號例如可接續為AA/55/FF/00。注意 10雖然各個資料係於晶片外部產生，但於送至記憶體裝置1之 途中可藉電路修改成為晶片上信號，該種電路於積體電路 之正常操作期間，處理輸入積體電路之信號，且傳輸該等 信號給記憶體裝置。 理想上，全部記憶體裝置（例如裝置21)接收位址信號、 15資料化號及其本身之控制信號。但因積體電路可能故障， 故無法確定此項資料是否正確傳輸給各個記憶體裝置。可 藉凰視各別圮憶體裝置之輸出29加以觀察。輸出29送至掃 ^暫存器3卜由該處，輸信號可被監視。來自複數個記 體裝置21之輸出送至同-掃描暫存器。記憶體裝置21之 20其它輪出信號係於正常功能模監視。 目前預計本發明將應用於帶有24快速乙太網路埠及2 十億位元埠之切換裝置。典型地此種裝置之同一區塊實作 次數係與埠數目相等。 雖然前文只說明一個本發明具體實施例，但本發明非 200307296 僅囿限於此，熟諳技藝人士顯然易知於本發明範圍可做出 多項變化。例如裝置可實作為單埠記憶體而非雙埠記憶體。 【圖式簡單說明】 第1圖示意顯示已知BIST記憶體測試方案；以及 5 第2圖顯示根據本發明，設置於積體電路之記憶體裝置 之組態。 【圖式之主要元件代表符號表】 1，21…記憶體裝置 3.. .内建自我測試模組 5，7，9…開關 11.. .輸出端 13，15，17…信號 23.. .XOR 閘 25.. .位址信號 27.. .控制信號 29.. .組合輸出 Addr…位址輸入端 D…資料輸入端 C...控制輸入端200307296 (ii) Description of the invention: Field of invention] Field of the invention The present invention relates to a method for testing a memory device 5 located on an integrated circuit and a method for testing such a device. L Prior Art 3 Background of the Invention Many recent integrative circuits use a first-in-first-out (FIF0) memory device. For example, the switching device typically includes such a FIFO memory device in each input port. The 10 typical FIFO memory device is implemented as a dual-port memory, which is lighter and shorter than the conventional 5-memory memory device, which is mainly a register. Similar to all integrated circuits, this memory device occasionally fails and needs to be tested to ensure that the resulting integrated circuit is operable and to identify the failure during the integrated circuit manufacturing process. The current advantageous method for testing memory is BIST (built-in self-test), 15 is shown in Figure 1. The memory device 1 has an address input Addr for receiving an address that defines a location of Lu Jiyi body, a data input D for specifying and writing data of the address, and a control input C 'if the specified data To write to the specified address, the control input C receives a "write" or "read" command. The integrated circuit includes a BIST module 3 and switches 5, 7, and 9. 20 During the test mode of the integrated circuit, switch 5, 7, and 9 to transfer the respective inputs of the BIST module 3 to the memory device 1. Therefore, the BIST transmits the input of the predetermined sequence to the memory device 1, and the output of the memory device is monitored to determine whether the memory device 1 outputs a corresponding predetermined output signal through its output terminal. The BIST module 3 ensures that the known signals are sent to all the 200,307,296 rounds of the memory device, so the memory device can be tested independently and reliably, even if the other location of the integrated circuit is faulty, the memory device can still be reliably alone. test. But once the test operation is completed, the integrated circuit starts to operate normally. In the mode of 5, the switches 5, 7, and 9 ensure that the respective signals 13, 15, and 17 (can be generated by other modules of the integrated circuit, or can be received by the integrated circuit from the outside) are transmitted to the input of the memory device. Addr, D and C. In such normal operation of the integrated circuit, the BIST module 3 is not used at all, and the BIST module 3 and the switches 13, 15, 17 constitute an additional burden on the overall efficiency and area of the integrated circuit. 10 When the integrated circuit includes a plurality of memory devices 1 (for example, when the integrated circuit is a switching device with multiple input ports), providing a BIST module 3 for each memory device 1 constitutes a significant additional burden. But in addition, only providing a single BIST module 3 and using the BIST module 3 in turn to test multiple memory devices has caused the integrated circuit logic to be significantly complicated, making it difficult to provide a 15-symmetrical circuit design. SUMMARY OF THE INVENTION 3 Summary of the Invention The present invention seeks to solve the aforementioned problems, and particularly provides a new integrated circuit and a novel method for testing the integrated circuit. 20 ㈣ A brief summary of the present invention-a integrated circuit with-or multi-memory devices, the test method is transmitted inside the integrated circuit (0 bit address signal which indicates-memory address, a data signal It indicates the data of the address, and transmits to each memory device _ each command letter? Tiger, whether the command # number is not written to each memory device. Monitoring by each record 200307296 The data output by the device and at least part of the data it receives. Because the data is generated outside the chip, the integrated circuit does not need a BIST module to generate the exact known signal to all inputs of the memory device. It is indeed the opposite of the BIST method ' This means that the data arriving at the memory module is sent to 5 § The memory device may fail to communicate with the predetermined input due to other failures of the integrated circuit on the way. However, the data input to the memory device is monitored with sufficient accuracy. If it is caused by errors other than the memory device on the integrated circuit, if the fact is found, the memory device will not be incorrectly blamed for the error. 10 In other words In contrast to functional tests based on additional test logic (which is only used during the test program), the present invention enables functional testing of memory devices. In this way, the present invention saves significant cost by eliminating the need to provide other on-chip logic. Invention It was further proposed that the data packet 15 for monitoring input to each memory device contains a monitoring signal formed by monitoring only the address signal and the instruction signal. If the monitoring # number is formed in advance by an operation including (or logically equal to) x〇R operation And sent to the scanning register, this kind of monitoring is particularly effective, because in this case, when the address signal and the instruction signal are constantly changing, the monitoring signal will also effectively change the monitoring signal of the constant change. Signals and command signals. 20 Especially in the first aspect of the present invention is an integrated circuit, which includes one or more memory devices, each memory device has a single address input terminal, which is i, receiving the specified memory One address and one address signal, a data input terminal is used to receive data, and a command input terminal is used to receive command signals. A 'indicates whether the data is to be written into the address and an output terminal. 200307296 The integrated circuit further includes a monitoring unit for deriving a monitoring signal from at least several signals input to each memory device. The present invention The second aspect is a method for testing an integrated circuit including one or more memory devices. Each memory device has an address input terminal, and 5 is used to receive an address signal that specifies an address of the memory. A data input terminal is used to receive data, a command input terminal is used to receive a command signal, the command signal indicates whether the data is to be written into the address, and an output terminal. The method includes: transmitting a signal to an integrated circuit To allow the one or more memory devices to receive a 10-bit address signal, a data signal, and a corresponding command signal to each memory device, to monitor at least a number of signals input to each memory device, and to output signals from the memory device. signal. Brief Description of the Drawings 15 Details of specific embodiments of the present invention will now be described with reference to the following drawings, which are for illustration purposes only, in the drawings: Figure 1 schematically shows a known BIST memory test scheme; and FIG. 2 shows a configuration of a memory device provided in an integrated circuit according to the present invention. 20 [Embodiment] A detailed description of the preferred embodiment, referring to FIG. 2, shows a memory device 21, which has a single address input terminal Addr for receiving an address signal that specifies the location of a memory body, a data input terminal D is used to receive a data signal containing the data to be written into the address, and 200307296 a control input c, if the contained data is to be written into the stated address, the control input c receives the "write "instruction. Comparing the configuration shown in Fig. 1, this embodiment has an additional XOR gate (monitoring unit) 23, which receives an address signal 25 and a control signal 27 as input signals, and generates a combined signal 29. 5 The memory device 21 is typically one of a plurality of memory devices of equal composition provided on an integrated circuit. The integrated circuit receives data generated outside the integrated circuit and transmits it to all memory devices. The data includes an address signal (serial address), a data signal, and a separate command signal for each memory device. The data signal can be connected to AA / 55 / FF / 00, for example. Note 10 Although each data is generated outside the chip, it can be modified into a signal on the chip by a circuit on the way to the memory device 1. This type of circuit processes the signal input to the integrated circuit during the normal operation of the integrated circuit. And transmit these signals to the memory device. Ideally, all memory devices (such as device 21) receive the address signal, the 15 data number, and its own control signal. However, because the integrated circuit may be faulty, it is impossible to determine whether this data is correctly transmitted to each memory device. This can be observed by viewing the output 29 of each individual memory device. The output 29 is sent to the scan register 3, where the output signal can be monitored. The outputs from the plurality of memory devices 21 are sent to the on-scan register. The other output signals of the memory device 21-20 are monitored by the normal function mode. The present invention is currently expected to be applied to switching devices with 24 fast Ethernet ports and 2 billion bit ports. Typically, the same block is implemented the same number of times as the number of ports. Although the foregoing only describes a specific embodiment of the present invention, the present invention is not limited to 200307296, and it is obvious to those skilled in the art that various changes can be made in the scope of the present invention. For example, the device can be implemented as port memory instead of dual port memory. [Brief description of the drawings] FIG. 1 schematically shows a known BIST memory test scheme; and 5 FIG. 2 shows a configuration of a memory device provided in an integrated circuit according to the present invention. [Representative symbol table of the main components of the figure] 1, 21 ... Memory device 3 .. Built-in self-test module 5, 7, 9 ... Switch 11 ... Output terminals 13, 15, 17 ... Signal 23 .. .XOR gate 25.. Address signal 27... Control signal 29... Combined output Addr ... address input D ... data input C ... control input