TW200306670A

TW200306670A - Complementary schottky junction transistors and methods of forming the same

Info

Publication number: TW200306670A
Application number: TW092105598A
Authority: TW
Inventors: Trevor Thornton
Original assignee: Univ Arizona State
Priority date: 2002-03-15
Filing date: 2003-03-14
Publication date: 2003-11-16
Also published as: KR20040105216A; JP2005521246A; EP1485952A1; AU2003214190A1; WO2003079445A1

Abstract

Various methods for forming semiconductor devices are provided that include the step of implanting dopants into the devices to achieve doping concentrations that allow complementary n- and p-channel SJT behavior with devices of substantially equal gate length and gate width. Moreover, complementary SJT devices are provided that include n- and p-channel devices that have approximately equal gate lengths and widths. SJT devices may be appropriately doped and configured such that input current and the output current both vary substantially exponentially with a gate-source voltage in the sub-threshold mode, and such that the drain current varies substantially linearly with the gate current through a substantially constant current gain that is given by a ratio of the drain current to the gate current.

Description

200306670 五、發明說明（1) 優先權本申請案係主張美國臨時申請案第6 0 / 3 6 4，5 2 8號的優先權’其名稱為” Complementary N- and P-Channel Schottky Junction Transistors for Micro一Power Integrated Circuits (微功率積體電路之互補式n及p通道肖特基接面電晶體）π ，申請日為2 〇〇 2年3月1 5曰。一、【發明所屬之技術領域】本發明之各項實施例係有關於半導體裝置以及製造半導體I置之技術。更特別是，各項實施例係有關於可作為電流控制電流源的互補式場效應電晶體裝置。先前技術】子裝置，諸許多項目中業及航空應係一種三端換能力。近可執行不同用上是尤其 °在醫療裝 Μ及其他應微功率（m i c 置一般係對電使用於品 ν 工電晶體大或交耗，且池的應換電池裝置、謂的「功率裝如一極體、電晶體及其他類似者等均被，如家庭、辦公室、車輛、個人電子產用、醫療裝置及其他領域。一般而言， 1置’其提供如在類比與數位電路中放來的研發致力於發展具有降低功率消功能之電晶體。降低功率消耗在需要電需要的，當功率耗盡時，就可能需要更置（諸如起搏器（pacemaker))、人造衛星用中，更換電池非常不方便，所以對所 r〇P〇wer)」元件的需要增加。此外，低超大型積體（ULSI)電路為較佳，因其常200306670 V. Description of Invention (1) Priority This application claims the priority of US Provisional Application No. 6 0/3 6 4, 5 2 8 'its name is "Complementary N- and P-Channel Schottky Junction Transistors for Micro-Power Integrated Circuits (Complementary n and p-channel Schottky junction transistors for micro power integrated circuits) π, the application date is March 15, 2002. 1. [Technical Field to which the Invention belongs [Each embodiment of the present invention relates to a semiconductor device and a technique for manufacturing a semiconductor device. More specifically, each embodiment relates to a complementary field effect transistor device that can be used as a current control current source. Prior Technology] Device, many projects in the industry and aviation should be a three-terminal exchange capability. It can be used for different applications, especially in medical equipment and other micropower applications (mic devices are generally used for electricity, products, and industrial crystals). Or power consumption, and the battery of the battery should be replaced, so-called "power devices such as a pole, transistors and other similar devices have been used, such as home, office, vehicles, personal power For sub-products, medical devices, and other fields. Generally speaking, it provides research and development as released in analog and digital circuits, and is committed to developing transistors with reduced power dissipation functions. Reduced power consumption is required when electricity is needed. When the power is exhausted, it may be necessary to install more (such as pacemaker), artificial satellites, and it is very inconvenient to replace the battery, so the need for all components is increased. In addition, a low super large integrated circuit (ULSI) circuit is preferred because it is often

200306670200306670

常需要低功率裝置以降低總功率消耗。第1圖係各類型之電晶，斤此+ 电日日版坆些電晶體一般屬於場效應電晶體（FET)以及雙極接面雷曰ΜΓβττ、*工_ 勿 l 條囬冤日日脰（B J Τ )之兩種類別的苴中一種。一般而言，場效應電晶體係依據施加於一閘極端電壓而動作，而閘極端適當地控制影響一半導體通道中電流流動之空乏區。一般雙極接面電晶體的特性係兩個ρ_Ν 面連接在一起，如第1(C)圖所示。目前，使用於微處理器與其他數位應用中的「電晶體裝置，大多數為互補式金氧半導體場效應電2體」 (CMOS FET)，其於一強反轉區域中操作，其中輸入的^極一源極（gate-source)電壓（Vgs)係大於一臨界電壓ι。於言些電晶體中，半導體通道中的電流（即汲極電流^ 隨（vgs-vth)2而變化。這些裝置之臨界電壓Vth可以在D〇 H = 右，而通道中的電流可以在毫安培範圍内。強反轉之η工舀知Μ 0 S F Ε Τ裝置的貫例之一偏壓結構係說明於第1 (& 中。 ^圃Low power devices are often required to reduce overall power consumption. Figure 1 shows various types of transistors. This + electric Japanese version. These transistors generally belong to field effect transistors (FETs) and bipolar junctions. ΓΓτττ, * 工 _ Do not return to the sun. (BJ T) One of the two types of 苴. Generally speaking, a field effect transistor system operates based on an extreme voltage applied to a gate, and the gate appropriately controls the empty region that affects the current flow in a semiconductor channel. The characteristic of a general bipolar junction transistor is that two ρ_N planes are connected together, as shown in Figure 1 (C). At present, "transistor devices used in microprocessors and other digital applications, most of which are complementary metal-oxide-semiconductor field-effect transistors" (CMOS FETs), operate in a strong inversion region, where the input The gate-source voltage (Vgs) is greater than a threshold voltage. In some transistors, the current in the semiconductor channel (that is, the drain current ^ varies with (vgs-vth) 2. The threshold voltage Vth of these devices can be at DOH = right, and the current in the channel can be Within the range of amps. One of the conventional examples of the strong reversal η device MF 0 SF Ε Τ device is biased structure is described in the first (&

、就需要最小電流之應用而論，CMOS電路可被施加偏周成所謂的「次臨界金氧半導體場效應電晶體」，其於一二反轉區域中操作，其中閘極-源極電壓（Vgs)係小於Vt、。上 (b)圖係說明一弱反轉的η通道M0SFET之實例偏壓條牛^ 這些條件下，M0SFET汲極電流Id —般係由微微安培、。紙 (Picoamp)變化至微安培（microamp)範圍，以及薪由公式獲得：〇TIn terms of applications that require a minimum current, CMOS circuits can be biased into so-called "subcritical metal-oxide-semiconductor field-effect transistors," which operate in a one-two inversion region, where the gate-source voltage ( Vgs) is less than Vt. The above (b) diagram illustrates an example of a weakly inverted n-channel MOSFET bias bias bar. Under these conditions, the MOSFET drain current Id—generally from picoamps. Paper (Picoamp) changes to the microamp range, and the salary is obtained by the formula: 〇T

200306670 五、發明說明（3) 苴 4 ⑴ 夕w其令^ hiT/e在室溫下可大約為25.8 mV，#係載子遷移率/ C°x係氧化電容，以及W/L係電晶體之寬度與長度比。對置於弱反轉區操作時，汲極電流飽和（如^ sat > 3心 ::5二之低汲極電流及小電Μ，產生非常i合於諸如不多里汁异器、呼叫器、醫學植入物、ULSI邏輯率電路應用之次臨界操作。然而，這些裝置; 速度低。於弱反轉區中的截止頻率一般係藉由f主要缺點係 Γ較弱反轉侧5裝置而論，雖然一般200306670 V. Description of the invention (3) 苴 4 夕 xi w hiT / e can be about 25.8 mV at room temperature, #series carrier mobility / C ° x series oxidation capacitor, and W / L series transistor Ratio of width to length. When operating in a weak inversion region, the drain current saturates (such as ^ sat > 3 heart :: 5 2 of the low drain current and the small current M, resulting in a very suitable combination such as Devices, medical implants, and ULSI logic rate circuits are used for critical operation. However, these devices have low speeds. The cut-off frequency in the weak reversal zone is generally based on the main disadvantage of f, which is the weaker reversal side 5 device As for the general

的操作頻率。S Lg_3_之條件下，產生一大約9MH 弱反轉或弱堆積區（與強反轉或的電晶體之間的差異在於，弱反轉隹知區相對）中操作極電流一般是隨閘極—源極電壓愈 ^ 貝桑作區中之汲呈指數變化。因為有方程式麼之間的差異（如的小幅變化-般造成汲極電Μ的大二數特性’因此vth 試藉由縮減閑極長度Lg，以改善微功;因此，嘗法一般而言並不實際，這是因為裝置、直之速度fT。此方臨界電壓vth之困難。基於此項原=，，，確實有精準匹配極長度一般均不適當（如Lg > 1、 m)、午夕彳政功率電路之閘低於1 MHz。 “ 111以及其操作頻率一般均目前已搭配使用各種BJT裝置，、乂輪入偏壓電流控制 200306670 五、發明說明（4) 一電晶體，其中隹榀帝、ώ τ 利用基極-射極電以指數叫（ν^)來表示。這是因為電流（I )二Abe彳I制集極電流Ic 一般為不適當，許多m利用輸又)基：C極t麼(^)的指數相依關係。電流增益/?，即丨=θ丨H而非基極-射極電壓，透過 ΝΡΝ ΜΤ的電流偏壓"冓b二：制集極電流L。透過-實例盾目，丨μ羽&、、Ό構之控制係說明於第1 (C)圖中。原貝J上，高知β j τ裝置可# 流，而使用於微功率區，以二^加-足夠小的基極電培之範圍。然❿，因為BJT 一妒;〜係處於微微安培至微安供巧·雷六f gp τ A 又為〉、數載子裝置’所以輪入擴政電谷（即正向偏壓基極對射極）f 時間是不合乎要求，因此使截面所化的充電因此BJT 一？:不被用來作為高頻率之微功率裝置。也另一白知電晶體結構係金屬半 MESFET。MESFET -般皆被使用A处么 ^ ^ UJ ^ ^ if ^ g 〇 ^ ^ ^ ,b ^ 動通道層通常係相當厚，且有相卷、$ 〇之條件時，閘極下之空乏區小於诵、、之4竑物’以致在_Operating frequency. Under the condition of S Lg_3_, a 9MH weak inversion or weak accumulation region (the difference between a strong inversion or a transistor in that the weak inversion region is opposite) and the operating electrode current generally follows the gate. -The more the source voltage changes exponentially in the Besançon farming area. Because there is a difference between the equations (such as small changes-as a result of the large number of characteristics of the drain electrode M '), vth tries to improve the micropower by reducing the length of the idle electrode Lg; therefore, the general method is Impractical, this is because of the device, the straight speed fT. The critical voltage vth of this side is difficult. Based on this principle, there are indeed accurate matching pole lengths that are generally inappropriate (such as Lg > 1, m), midnight The gate of the government power circuit is lower than 1 MHz. "111 and its operating frequency are generally used with various BJT devices, and the wheel-in bias current control 200306670 V. Description of the invention (4) A transistor, of which The Emperor and Emperor τ use the base-emitter to express it with an index called (ν ^). This is because the current (I) and the collector current Ic made by Abe 彳 I are generally inappropriate, and many m use the power of the base): The exponential dependence of the C pole t? Through the example shields, the control system of μ 羽 &, Ό structure is illustrated in Figure 1 (C). On the original shell J, the Kochi β j τ device can be used in the micropower region, with two ^ plus-a sufficiently small base electric range. However, because BJT is jealous; ~ is in the pico amp to The microampere supply Lei Liu f gp τ A is again>, the number of carrier devices' so the turn into the expansion power valley (that is, forward biased base to emitter) f time is not satisfactory, so the cross section Charging so BJT One ?: Not used as a high-frequency micropower device. Another Shichi transistor structure is a metal semi-MESFET. MESFETs are generally used at A place ^ ^ UJ ^ ^ if ^ g 〇 ^ ^ ^, b ^ The dynamic channel layer is usually quite thick, and when there are conditions of phase volume and $ 〇, the empty area under the gate is smaller than that of chanting, and so on.

之一典型偏壓結構係說明於第丨“；^2^厚度。n通道MESFET 依據弟1 ( d)圖’就一 η通道空多、電壓Vth —般係小於零，而且閘極電^ ^MESFET而言’臨界化，以控制汲極電流，其係隨間^\於>%<〇範圍中變間的不同（即1。而產生之微小的壓與臨界電壓之中，流進閘極之電流係由於一反向卞又化。农此結構 X ^偏壓肖特基接面所導A typical bias structure is described in section ^; ^ 2 ^ thickness. According to Figure 1 (d) of the n-channel MESFET, the n-channel is more empty, the voltage Vth is generally less than zero, and the gate voltage is ^ ^ MESFETs are 'criticalized' to control the drain current, which varies from time to time in the range of ^%>% <0 (that is, 1. The tiny voltage and threshold voltage generated flow into The current in the gate is reduced due to a reverse current. Guided by the X ^ bias Schottky junction of this structure

200306670 五、發明說明（5) 致。在許多裝置中，相較於汲極電流，閘極電流於設計上小到可忽略。閘極電流通常不是用以控制汲極電流，而是用以建立閘極電壓。換句話說，meSFET中的閘極電流僅僅是一般的π漏電流’’，通常係維持至可能最低的範圍。增強模式MESFET也已經產生，以致空乏區延伸至如第2 圖所示之Vgs = 〇處的主動通道層。此電晶體係藉由施加一順向偏壓至閘極而被導通’以致空乏區僅延伸至半導體通道之一部分。然而，被施加至閘極之電壓通常必須維持至一定的低狀態，以致閘極輸入電流係更小於；:及極電流。又，閘極電流一般對於控制汲極電流是沒有作用的，而是用以建立閘極電壓。如此一來，汲極電流Id係經由閘極電壓所控制，且隨（Vgs - vth)產生些微小幅功率而變化。於此結構中，當閘極-源極電壓大於臨界電壓（即vgs > vth)時，一般認為電晶體係導通。當增強模式MESFET被導通時，這些裝置通常係於強堆積（類似於一M0SFET中之強反轉）區内操、作，而且汲極電流一般係處於毫安培範圍内。由於是高功率消耗之關係，此電流範圍在微功率應用上一般是極欲避免的。通常，微功率裝置應具有微安培至微微安培範圍的汲極電流。 M0SFET與MESFET之間的極大不同點係一M0SFET之閑極 (即輸入）電極與導通通道之間具有一絕緣層。沒有閘極絕緣體，就不能將半導體表面反轉，而且M0SFET之汲極電茂是微不足道的。絕緣體必須具有足夠之厚度，如此可使= 極至通道沒有漏電流產生。然而，當Μ 0 S F E T之閘極長产縮200306670 V. Description of Invention (5) Consistent. In many devices, the gate current is designed to be negligible compared to the sink current. Gate current is usually not used to control the drain current, but is used to establish the gate voltage. In other words, the gate current in a meSFET is only a general π leakage current '', which is usually maintained to the lowest possible range. An enhancement mode MESFET has also been created, so that the empty region extends to the active channel layer at Vgs = 0 as shown in FIG. 2. This transistor system is turned on by applying a forward bias to the gate 'so that the empty region extends only to a portion of the semiconductor channel. However, the voltage applied to the gate usually must be maintained to a certain low state, so that the gate input current is smaller than: and the pole current. In addition, the gate current generally has no effect on controlling the drain current, but is used to establish the gate voltage. In this way, the drain current Id is controlled by the gate voltage, and changes with (Vgs-vth) generating some small amplitude power. In this structure, when the gate-source voltage is greater than the threshold voltage (ie, vgs > vth), the transistor system is generally considered to be conducting. When the enhancement mode MESFET is turned on, these devices usually operate and operate in the region of strong accumulation (similar to the strong inversion in a MOSFET), and the drain current is generally in the milliampere range. Due to the high power consumption, this current range is generally avoided in micropower applications. Generally, a micropower device should have a sink current in the microamp to picoamp range. The great difference between the MOSFET and the MESFET is that an insulating layer is provided between the free electrode (that is, the input) electrode and the conduction channel of the MOSFET. Without the gate insulator, the semiconductor surface cannot be reversed, and the drain electrode of the MOSFET is trivial. The insulator must be of sufficient thickness so that there is no leakage current from the pole to the channel. However, when the gate of M 0 S F E T is long and shrinks

III _圓_ Η _ ΛIII _Circle_ Η _ Λ

mi, ilk 200306670 五、發明說明（6) 減至較小的幾縮減。以非常流經絕緣體，極絕緣體之最閘極長度。相 MESFET之比例因此，希通道裝置，來互補裝置以降至一晶片或晶將配合附圖與及申請專利範何結構時，絕溥的閘極絕緣最後流至通道小可容許厚度對的，MESFE丁尺寸應能小於望能利用消耗構成微功率電低成本以及增圓上。再者，上述之技術領圍而趨於明瞭緣間極體而言。此閘 ’依次不需要習知大功率非路。此加裝置本發明域與背氧化物之厚度就成比例，過多電流可能由閘極極漏電流係用以限制閘其將限制M0SFET之最小一閘極絕緣體。因此，部分的M0SFET。常小的互補式η通道與p 外，希望能發明小型的之數量，且裝置能結合之其他較佳特色及特性景’透過下文之詳述以三、【發明内容】肖特基接面電晶體（SJT)提之優點。這些優點之一些夕4於習知半導體裝置切換速度、以及顯著降^的.、:電晶體e配、較快的體特別適合於微功率電路用】二^件，使肖特基接面電晶之獨特性，使得特別小 ^ ，肖特基接面電晶體 /置構成。因此，同時#句等大小之n通 :方法’這些方法包含植 ;广上各種形成半導體裝置 ::以實質相等的閘極長度歲閘二:現-摻雜濃度之步 :允，互補式η通道及p通道之裝置，此摻雜濃卜’提供互補式肖特美垃土接面電晶體性处。屮、月特基接面電晶體裝置，粒性月匕。此 — 具包含具有大約第】〗頁 200306670 五、發明說明mi, ilk 200306670 V. Description of the invention (6) Reduced to a small number. The maximum gate length of the pole insulator is very flowing through the insulator. Proportion of phase MESFET. Therefore, the channel device is used to complement the device to reduce to a chip or crystal. When the structure is matched with the drawings and patent application, the absolute gate insulation finally flows to the channel with a small allowable thickness. MESFE The size of Ding should be smaller than that expected to make use of the power consumption to form a low cost and increase the power of micropower. Furthermore, the above-mentioned technical scope tends to be clear in terms of marginal polarities. This gate 'in turn does not need to be acquainted with high power circuits. This device is proportional to the thickness of the back oxide. Excessive current may be used by the gate leakage current to limit the gate, which will limit the smallest gate insulator of a MOSFET. So part of the MOSFET. Apart from the often small complementary η channel and p, it is hoped that a small number can be invented, and other better features and characteristics that the device can combine. Through the details below, the content of the Schottky interface is The advantages of crystal (SJT). Some of these advantages are based on the known switching speed of semiconductor devices, and the significant reduction in :: transistor e, fast body is particularly suitable for micro power circuits] two parts, so that Schottky interface The uniqueness of the crystal makes it particularly small ^, Schottky interface transistor / set. Therefore, at the same time, the number of n-passes such as the method: these methods include planting; a wide variety of semiconductor devices are formed: with a substantially equal gate length, the second gate: the current-doping concentration step: allowable, complementary η For channel and p-channel devices, this doped dope provides a complementary Schottmeier soil junction transistor.屮, Moon Teji interface transistor device, granular moon dagger. This — with a tool that has approximately

相等的閘極長度與寬度之η通道及p通道裝置。四、【實施方式】下列之詳細說明完全僅作為實例，而且並無要限制本發明或本2明之應用以及用途。此外，也無受限於上述技術領域、背景、概述或下列詳細說明中的任何明示之原理。依據本發明之各方面，產生一增強模式MESFET，藉此，通迢汲極電流係因一流進或流出MESFET之閘極電極的偏電流之應用而受到控制。藉以謹慎選擇通道摻雜％、通道厚度a、及閘極長度Lg，即可使依據下文所述之方法製造的裝置之電流增益大於丨（如召 > 丨）。例如，可使本發明所說明之汲極電流的閘極電流控制與雙極接面電晶體（bjt)中的集，電流之基極電流控制類似。因此，依據本發明而構成之衣置可適當地視為肖特基接面電晶體（s】τ )。然而’因為宵特基接面電晶體係一種多數載子裝置，此其不可能與雙極接面電晶體一樣產生少數載子之問 2。特別是，肖特基接面電晶體之各項實施例通常不會產 2極接面電曰曰曰體巾之少數載子所造成的擴散電容，因為、基接面電晶體的操作一般不倚賴少數載子。么因此，肖特基接面電晶體閘極電極之輸入電容可以數大小，小於一雙極接面電晶體之輸入電容，而使肖特土妾面電晶體操作於微功率區内的較高頻率。在各項貝知例中’肖特基接面電晶體之輸入閘極電流N-channel and p-channel devices with equal gate length and width. 4. [Embodiment] The following detailed descriptions are merely examples, and they are not intended to limit the applications and uses of the present invention or the present invention. Furthermore, it is not limited to the above-mentioned technical fields, backgrounds, overviews, or any of the principles explicitly stated in the following detailed description. According to aspects of the present invention, an enhanced mode MESFET is generated, whereby the through-drain current is controlled by the application of a bias current flowing into or out of the gate electrode of the MESFET. By carefully selecting the channel doping%, the channel thickness a, and the gate length Lg, the current gain of the device manufactured according to the method described below can be greater than 丨 (such as & > 丨). For example, the gate current control of the drain current described in the present invention can be made similar to that of the bipolar junction transistor (bjt), and the base current control of the current is similar. Therefore, a device constructed in accordance with the present invention can be appropriately regarded as a Schottky junction transistor (s) τ. However, because the Schottky junction transistor system is a majority carrier device, it is impossible to generate minority carriers like bipolar junction transistors 2. In particular, the embodiments of the Schottky junction transistor usually do not produce the diffusion capacitance caused by the minority carriers of the body electrode, because the operation of the base junction transistor is generally not Rely on minority carriers. Therefore, the input capacitance of the gate electrode of the Schottky junction transistor can be counted to be smaller than the input capacitance of a bipolar junction transistor, which makes the Schottky junction transistor operate at a higher level in the micropower region. frequency. The input gate current of the Schottky junction transistor in each case

第12頁 200306670 五、發明說明（8) 及輸出汲極電流，可以藉由選擇適當之層厚與摻雜隨施加的閘極偏壓呈指數變化，使汲極雷户 / 1 /又向 %极m閘極雷法（裝置之增益）的比例相對地不受臨界電壓的影響。_ 作用於 >及極電流與閘極電流比之臨界電壓的'效靡 '于、善次臨界區内的電晶體匹配，且可以使裝置間^县$ Ζ ί 更短，因此允許電晶體操作於明顯更高的頻率。=$，貝已發現不同的宵特基接面電晶體裝置更特別適用於 $ 應用之範圍中（即微微安培至微安培）的汲極電流。'再半利用本發明所述之互補式η通道及ρ通道裝置，^杂办電路應用。因λ，由肖特基接面電晶體所構成之ς 比及數位電路能夠於較高頻率操作，此頻率高於利 = 弱反轉M0SFET之習知裝置所構成之電路的頻率。肖特基接面電晶體之各項實施例的一額外優點裝f之互補類盤而構成的電路保有小於習知⑽”打雷路之面積。面積縮減有兩個原因。第一，壯恶 Λ " ^ 衣罝一般·不堂亚古_ 絕緣體設於閘極與通道之間，所有之閑極長度小於習知M〇SFET裝置斤通逼及ρ通道裝置有相同或相似寬度之傳導通道的互^二’可構成含基接面電晶體。在習知的簡式:以= 道裝置之寬度縮減以及(2)將閑極長度縮至:通力，所以由新裝置之互補類型所構# 、月匕的整合程度要高於習知_之整斤電路能夠實現一閘極絕緣體的縮減有關之優點俜π X八他與本發明之 ▲“係（1)降低輸入（閘極）電 200306670 五、發明說明（9) 谷以及（2 )降低製造複雜度。各項示範之實施例的分析依據可藉由下列方程式（2)來概括： βPage 12 200306670 V. Description of the invention (8) and the output drain current can be changed exponentially by selecting the appropriate layer thickness and doping with the applied gate bias voltage, so that the drain thunder / 1 / to% The ratio of pole m gate lightning method (device gain) is relatively unaffected by the threshold voltage. _ The effect of the threshold voltage on the critical voltage ratio between the pole current and the gate current is matched to the transistor in the subcritical region, and the device can be made shorter, so the transistor is allowed. Operates at significantly higher frequencies. = $, Bay has found that different Schottky junction transistor devices are more particularly suitable for the drain current in the $ application range (ie picoamps to microamps). 'Secondly, the complementary n-channel and p-channel devices described in the present invention are used for circuit applications. Due to λ, the ratio and digital circuit composed of Schottky interface transistors can operate at higher frequencies, which is higher than the frequency of the circuit composed of conventional devices with favorable = weakly inverted M0SFET. An additional advantage of each embodiment of the Schottky junction transistor is that the circuit composed of the complementary type disks is smaller than the area of the conventional "thunder road". The area is reduced for two reasons. First, the evil Λ " ^ General Yi Bu Tang Yagu _ insulator is located between the gate and the channel, all the length of the free pole is less than the conventional MOSFET device and the ρ channel device has the same or similar width of the conduction channel Mutual coupling can constitute a base-containing junction transistor. In the conventional short form: the width of the device is reduced and (2) the length of the idler pole is reduced to: KONE, so it is constructed by the complementary type of the new device # The degree of integration of the moon dagger is higher than that of the conventional _ jin circuit can achieve the advantages related to the reduction of a gate insulator 俜 π X 八 He and the ▲ "system of the invention (1) reduce the input (gate) electricity 200306670 5. Description of the invention (9) Valley and (2) Reduce manufacturing complexity. The analysis basis of each exemplary embodiment can be summarized by the following equation (2): β

Id _ sk2 μ I aL2 q2A* Ν -expId _ sk2 μ I aL2 q2A * Ν -exp

Doping^Doping ^

Doping 2slh 其中ε k mNc QNd a -(2) ^dopi] % A* 電容率（permi11ivity ); 波3么哭常數（Boltzman’s constant); n通迢裝置之電子遷移率㈧通道之電洞遷移率）；傳導帶（價電子帶）中的狀態之有效密度；電子電荷； ?=通道内之施體濃度（受體濃度）；通道厚度（η通道及p通道裝置兩者相同）；閘極長度；以及瑞查生常數（Richard si on’ s constant )。在導出的方程式2中，首先考慮一增強模式n型石申化鎵 (GaAs)MESFET，藉由下列方程式得到其閘極電流：Doping 2slh where ε k mNc QNd a-(2) ^ dopi]% A * permittivity (permi11ivity); wave 3 constant (Boltzman's constant); n-device electron mobility ㈧ channel hole mobility) The effective density of the states in the conduction band (valence electron band); electronic charge;? = Donor concentration (acceptor concentration) in the channel; channel thickness (same for both η and p-channel devices); gate length; And Richard si on's constant. In the derived equation 2, first consider an enhancement mode n-type gallium sulfide (GaAs) MESFET. The gate current is obtained by the following equation:

第14頁 200306670 五、發明說明（ίο)= WLgAr2e~^jUT {ev^/UT -1) g (3) 其中，W、Lg係通道寬度及長度，Ob係肖特基阻障層高度以及A*係瑞查生常數。如果MESFET係屬弱堆積或操作於次臨界區内，則可將汲極電流寫為： r N+W NnaL„ ευ\μ exp(^) 一 (4) 其中，：l< α <2 ; Ν+ = 源極與汲極接觸摻雜濃度 ND = 通道摻雜濃度；以及 α = 通道厚度。假設α Ν+ / Nd 以及Vds 則 ν^εμττ2 aL„ UT exp(-Page 14 200306670 V. Description of the invention (ίο) = WLgAr2e ~ ^ jUT {ev ^ / UT -1) g (3) Among them, W and Lg are channel width and length, Ob is Schottky barrier layer height and A * Reichson constant. If the MESFET is a weak stack or operates in a subcritical region, the drain current can be written as: r N + W NnaL „ευ \ μ exp (^) one (4) where: l < α <2; Ν + = source and drain contact doping concentration ND = channel doping concentration; and α = channel thickness. Assuming α Ν + / Nd and Vds then ν ^ εμττ2 aL „UT exp (-

Kh, (5) 以及Kh, (5) and

第15頁 200306670 五、發明說明（11) (6)Page 15 200306670 V. Description of Invention (11) (6)

1 =WLA^e'^/UTeVgs/UT g g 利用方程式（5 )與（6 )之比，即獲得裝置之電流增益1 = WLA ^ e '^ / UTeVgs / UT g g Using the ratio of equations (5) to (6), the current gain of the device is obtained

h _ £k2Mh _ £ k2M

M-vth)iuT aL2a2A^ (7) 第3圖係一實例之金屬對n型半導體肖特基接面的一能帶圖。此圖說明肖特基阻障層高度、内建電壓Vbi、以及空乏區範圍W之間的關係。内建電壓係因肖特基阻障層而產生的電位差（如下所表示），其形成於肖特基閘極與半導體通道之間。由第3圖得知，肖特基阻障層高度以及内建電壓可藉由下列方程式表示： (8)M-vth) iuT aL2a2A ^ (7) Figure 3 is an example of an energy band diagram of a metal to n-type semiconductor Schottky junction. This figure illustrates the relationship between the height of the Schottky barrier layer, the built-in voltage Vbi, and the empty area range W. The built-in voltage is a potential difference due to the Schottky barrier (as shown below), which is formed between the Schottky gate and the semiconductor channel. According to Figure 3, the height of the Schottky barrier layer and the built-in voltage can be expressed by the following equation: (8)

III 國_| 第16頁 (9) 200306670 五、發明說明（12) 由標準内文可得知：以及： (Ec~Ef、二 kT\n(仏Country III_ | Page 16 (9) 200306670 V. Description of the invention (12) From the text of the standard: And: (Ec ~ Ef 、二 kT \ n (仏

NdNd

• · · (10) 由方程式（8 )、（ 9 )及（1 0 )，其能以下列方式表示： • (11 以及將此項代入方程式（7)，得到下列方程式： β = ί±^^μ_Ε 8• · · (10) From equations (8), (9), and (1 0), it can be expressed as follows: • (11 and substituting this term in equation (7), we get the following equation: β = ί ± ^ ^ μ_Ε 8

D qN Da 2εϋ τ …（1 2 ) 方程式1 2可視為一常數項乘以一指數常數項。因此，利用一施加偏壓於次臨界FET之閘極電流，、厂1之表示項 (其導致汲極電流變化）已被刪除；因此，臨界電壓之變動可能實質上不存在於問題中。因此，電晶體匹配則顯得更加容易，而且可構成使用含有較短閘極長之砷路，戶斤以使操作頻率比習知技術次臨界電晶體之^還^D qN Da 2εϋ τ (1 2) Equation 1 2 can be regarded as a constant term multiplied by an exponential constant term. Therefore, with a gate current applied to the sub-critical FET, the indication term of Factory 1 (which causes the change in the drain current) has been deleted; therefore, the variation of the threshold voltage may not substantially exist in the problem. Therefore, transistor matching is easier, and it can constitute the use of a short arsenic circuit with a short gate electrode, so that the operating frequency is lower than that of the conventional subcritical transistor.

200306670 五、發明說明（13) 例如，考慮含有一閘極長度、3 = 8〇_ H及/Γ0.8ν之一實例的GaAs mesfet。利用這此數值 = 剛塵可以被估計為伏特Γ 猎由方私式8獲得一大約29之電流增益上可能低估了。值貝k 圖。ί4播圖夂係Γ/例的肖特基接面電晶體20 0之一橫剖面 ;曰；〇"'二施人例以及參考第4 ®，-實例的肖特基接面 ί二 ί2 置於—基體m上之—選擇性的絕緣 “的美，202 )上通運】Γ係設置於絕緣層2〇4(或其他實施 208係、尚乂“二端210、閘極端214、以及汲極端 z U 8係適當地形成於通道2 〇 6上。肖特基接面電晶體可利用任何技術，諸如砷化二==)、或其他而構成，通常含有直接設 ;k < 6 |方之絕緣層204 ,其可降低基體洩漏效應:SOI也相容於主要的石夕製程技術。基體2〇2可為如第4圖所不之矽基體，或是其他任一基體材料，諸如砷化鎵、气 =」、複Λ石夕、非結晶石夕、、：氧化石夕（玻璃）或其他。絕緣 ^ 可以’儿積、濺鍍、或以其他方法，設置於基體2 〇 2 上，以及形成埋藏於内的二氧化矽（如第4圖所示）或含他任一適當的絕緣材料，諸如氮化矽。一雖然其他厚度亦可利用，但是習知的SOI技術能夠產生含有0.05至0.4微米範圍之厚度的埋入氧化物。例如，諸如晶圓連接（wafer bonding)之其他技術能夠產生大於1〇微米或以上厚度之埋入氧化物。絕緣層2〇4之厚度會隨各項實施 200306670200306670 V. Description of the invention (13) For example, consider a GaAs mesfet that contains an example of a gate length, 3 = 8〇_ H, and /Γ0.8ν. Using this value = Rigid dust can be estimated as volts. Γ Hunting can obtain an approximately 29 current gain from Fangshui 8 which may be underestimated. Value shell k diagram. Figure 4 shows a cross-section of one of the Schottky junction transistors of the case Γ / example 20; said; "two examples" and the reference to the 4th example, the Schottky junction. 2 Placed on the-substrate m-the beauty of selective insulation "202") Γ system is provided on the insulation layer 204 (or other implementation of 208 series, still "two ends 210, gate terminal 214, and drain The extreme z U 8 series is suitably formed on the channel 206. The Schottky junction transistor can be constructed using any technique, such as arsenide ==), or other, and usually contains a direct device; k < 6 | The square insulation layer 204 can reduce the substrate leakage effect: SOI is also compatible with the main Shixi process technology. The substrate 200 may be a silicon substrate as shown in FIG. 4, or any other substrate material, such as gallium arsenide, gas = ”, complex stone, amorphous stone, and: oxide stone (glass )or others. Insulation ^ can be deposited, sputtered, or otherwise, placed on the substrate 200, and formed with buried silicon dioxide (as shown in Figure 4) or any suitable insulating material containing it, Such as silicon nitride. -Although other thicknesses are also available, the conventional SOI technology can produce buried oxides with a thickness in the range of 0.05 to 0.4 microns. For example, other technologies such as wafer bonding can produce buried oxides with thicknesses greater than 10 microns or more. The thickness of the insulating layer 204 will vary with the implementation of 200306670

例而變化，但可以為〇.2_〇 5微米，如約〇·35微米。半導體通道206可以濺鍍、沉積、長晶、或以其他方式狀；當的？成！!絕緣層204上。雖然ρ型石夕可被使用於ρ通 f衣^ ’但疋在弟4圖所示之實施例中，通道206係標示為η ;迢1置之η型石夕。另外，可以使用其他任-半導體材料，諸如砷化叙（GaAs)、氮化鎵（GaN)、複晶矽、非結晶矽等。習知的S 0 I技術能夠產生今右士妁n n j __ 有大約ο.01至ο.2微米範圍的厚 :之夕表面層。目丽其他技術’諸如晶大於u微米或以上之厚度的石夕表面層。4二產生 :：然其他材料、摻雜物、以及摻雜物濃度也許確只實：用於其他實施例巾，但是此實施例所形成之 06且有一 a = 〇.〇5#m厚度的矽層，此層已經 ^ # 摻雜η型層。 υ cm之/辰度ND的在各項貫施例中，閘極端214(亦被稱為「閉極雷 f僅被稱r閘極」）係依據任何一技術，形成於通道;。」6 ，作為一肖特基接面。閘極端可由二矽化鈷、或是其他任一材料沉積於半導體通道2〇6上，、以來、，\ 基阻障層。例如，所示之二矽化鈷幾乎是^ 7 T ^ 'Examples vary, but can be 0.2-5 micrometers, such as about 0.35 micrometers. The semiconductor channel 206 can be sputtered, deposited, grown, or otherwise; when? to make! ! On the insulating layer 204. Although ρ-type stone eve can be used in ρ 通 f 衣 ^ ′, in the embodiment shown in FIG. 4, the channel 206 is labeled as η; In addition, other semiconductor materials can be used, such as arsenide (GaAs), gallium nitride (GaN), polycrystalline silicon, amorphous silicon, and the like. The conventional S 0 I technology is capable of producing a surface layer with a thickness of about ο.01 to ο.2 micrometers. Other technologies of Muli's such as the surface layer of Shi Xi with a crystal thickness greater than u microns or more. 4 Second generation :: Of course, other materials, dopants, and dopant concentrations may only be true: It is used in other embodiments, but the 06 formed in this embodiment has a thickness of a = 〇.〇5 # m Silicon layer, this layer has been ^ # doped n-type layer. υ cm 之 / 辰度 ND In various embodiments, the gate extreme 214 (also known as "closed pole f is only called r gate") is formed on the channel according to any technique; "6, as a Schottky interface. The gate electrode can be deposited on the semiconductor channel 206 by cobalt disilicide or any other material. For example, the two cobalt silicides shown are almost ^ 7 T ^ '

近乎理想的肖特基二極體，並且其相容於^制· ； n型矽：實施例中，雖缺制迕尺寸磕每备二、夕衣程。在各項是目二= : = : = 但 =…諸…。·嶋)。源極端至 :極」）以及没極端2〇8(亦稱為「源極」）：二形成於通道206上，並且可由任何—傳導材料，諸如链方式Nearly ideal Schottky diode, and it is compatible with ^ system; n-type silicon: In the embodiment, although the size of the system is not sufficient, it is necessary to prepare two or more clothes. In each item is item two =: =: = but = ... all ... · 嶋). Source extreme to: pole ") and non extreme 208 (also called" source "): two are formed on the channel 206 and can be made of any conductive material, such as a chain

200306670 五、發明說明（15) 銅孟銀、或其他任一材料或石夕化金之道之歐姆接觸。為了丄= 枯^觸之形纟，接冑區⑵2)以下的帛導體通道可濃宓植入摻雜物原子。η通道石夕裝置之摻雜物可為辰 ;:任—材料，以形成-半導體通伽之η型區。通ίϊ 裝置之摻雜物可為蝴或是其他任一材料，以形成？半通了 f區。源極與汲極之間的距離隨各項實施例變化，前：r…設計規定，此距離可二 + yt 省如在一示範的實施例中，其約為〇. 9微化石夕(si〇2):戈其他任—材料之保護層22。來覆蓋，有-乳度，i ϋ ί:::j内之摻雜物或是摻雜物濃兩工乏區2 1 6形成於閘極2 1 4附近，在施 ρ,υ ^208 ^ 端t n ^ 如果一正偏壓vds施加於汲極與源極；；2Η Λ^ „ ,,,, 電流Ig，即可以不用g广係厂肖特基接面。藉由改變閘極極電流Id，士口上、十、夕「、慮到臨界電壓而適當調整並控制汲空乏區可藉It车t析基礎」部分所示。來形成。空乏區於半導：體通迢上方的肖特基接觸之呈現一垂直距離W。在、夂1§ /通逭内之肖特基接觸的下方延伸料之傳導帶盥價:；員/施例中，空乏區係發生於半導體材觸之材料接觸的其他可造成半導體材料肖特基接月匕τ ’曲的結果。距離W可依據方程式丨2來200306670 V. Description of the invention (15) The ohmic contact of copper, manganese, silver, or any other material or the way of petrified gold. For the purpose of 丄 = contact, 触 conductor channels below 胄 2) can be implanted with dopant atoms. The dopant of the η channel Shixi device may be Chen;: Any-material to form a semiconductor-type n-type region. Can the dopant of the device be a butterfly or any other material to form it? Half-pass the f-zone. The distance between the source and the drain varies with various embodiments. Before: r ... The design stipulates that this distance can be two + yt. As in an exemplary embodiment, it is about 0.9 microfossil evening (si 〇2): Ge other tasks-the protective layer 22 of the material. To cover, there is -milk degree, i ϋ ί ::: j The dopant or dopant-rich doubly-contaminated region 2 1 6 is formed near the gate 2 1 4 at ρ, υ ^ 208 ^ Terminal tn ^ If a positive bias voltage vds is applied to the drain and source; 2Η Λ ^ „,,,, The current Ig can not be connected to the Schottky interface of the Guangxi factory. By changing the gate current Id, Shikou, Shi, and Xi "as shown in the section" Analyzing the critical voltage and properly adjusting and controlling the exhausted area can be analyzed by using it. " To form. The empty area in the semiconducting: the Schottky contact above the body pass presents a vertical distance W. The conduction band price of the extension material under the Schottky contact in 夂 1§ / Tong: in the example / example, the empty area is caused by the contact of the semiconductor material contact with other materials that can cause the Schott semiconductor material. The result of the base-on moon dagger τ 'curve. The distance W can be calculated according to equation 2

第20頁 200306670Page 20 200306670

五、發明說明（16) 決定，其說明如下。如第4圖所示之一例示肖牲作，係利用MED I C I軟體工复（& =面電晶體裝置2 0 〇之操 Fremont Callfornia)模鞑來源為 Ava；；t! TCAD 〇ί 體將結構分割成網絡，其中、，1 一維電腦杈型。MED1 C1軟式。-實例的網絡係說明於第(、73出適當的有關裝置方程 2。〇中之電流。第6圖說明實：5::/其可用以計算裝置 602，其為一施加至閘極之電、甲’極電流604以及汲極電流 0.3中的間極電壓而言，所^的函數。以範圍。〈Vgs<V. Description of Invention (16) The decision is as follows. As shown in Figure 4, one example of Xiao Shao's work is the use of MED ICI software (&Fre; Call for Fremont Callfornia of the surface transistor device 200). The source is Ava; t! TCAD 〇ί The structure is divided into networks, of which, 1 and 1-dimensional computer forks. MED1 C1 soft. -The example network is illustrated in (2, 73) and the appropriate currents in the device equation 2. 0. Figure 6 illustrates the fact: 5 :: / which can be used to calculate the device 602, which is a voltage applied to the gate , A ′ pole current 604, and the drain voltage of 0.3, the function of ^. In the range. <Vgs <

流604，而且閘極與汲極電流；二極電流602係大於閘極電的Idmgt比（即電流增益成f數上升一實例没極電流的函數。由圖中可以p了兄於_第7圖中’其為一传知’所示之實例雷洁J# Μ 隨1d而變…且在幾乎三個十的汲極電流範圍，可維V 在40至100左右的範圍。 # 第8圖針對施加至閘極之不同的輸入偏電流，說明一實例的肖特基接面電晶體2 0 0之汲極電流為汲極電壓之函數，其數據係以每微米之閘極寬度之奈安培（lnA=1〇_9安培）單位來表示。此圖說明理想電流飽和對高電壓4之關係，其係解釋為一可用於許多類比及數位電路應用^輸出阻抗y其說明第8圖中之一閘極電流係用以控制所選擇的Id—Vds描繪' 記錄（trace)。此項與習知技術MESFET對比，習知之閘極電壓係用以選擇Id - Vds描繪記錄。上述之數值模擬說明一習知技術增強模式腿$ F E T與肖特基接面電晶體之間的重要差異。第6圖說明一示範的實施Current 604, and the gate and sink currents; the two-pole current 602 is greater than the Idmgt ratio of the gate electricity (that is, the current gain increases as the number of f is an example of the function of the non-polar current. From the figure, you can see p__7 The example shown in the figure 'It is a knowledge' Lei Jie J # Μ varies with 1d ... and in almost three ten-drain current range, the dimensionable V is in the range of 40 to 100. # 第 8 图为为The different input bias currents applied to the gates illustrate the drain current of a Schottky junction transistor 200 as an example as a function of the drain voltage. The data is in nanoamperes per micrometer of gate width ( lnA = 10_9 amps). This figure illustrates the relationship between ideal current saturation and high voltage 4. It is interpreted as an output impedance that can be used in many analog and digital circuit applications. The gate current is used to control the selected Id-Vds trace. This is compared with the conventional technology MESFET. The conventional gate voltage is used to select the Id-Vds trace. The above numerical simulation description 1 Known technology enhancement mode leg between FET and Schottky junction transistor Important differences. FIG. 6 illustrates a first exemplary embodiment of a

第2〗頁 200306670 五、發明說明（17) 例，其中流進肖特基接面脚 ^ 電流604之整體有效範圍;曰== 及極電細2，於閉極 _，呈指數變化。在』範圍之-實質部分），之傳導通道於正常操作條件下時，肖特基接面電晶體知技術增強模式MESFET成對t卜，1 f弱堆積。此項與習時，MESFET之通道在設計上岸屬強^ ^當習知裝置導通發通道内之厚度與摻雜濃度時二*已經決定半導 Ϊ積利二吏得空乏區於正常操作條件可為弱趙。利用下列之方程式13，可 =至通逼之主體通道之源極末端處的空乏區之；圍。項貫施例中的半導 2ε ί队Page 2 200306670 V. Description of the invention (17) Example, in which the Schottky interface pin ^ the overall effective range of the current 604; said == and the pole voltage 2, at the closed pole _, it changes exponentially. In the "range-substantial part", when the conduction channel is under normal operating conditions, the Schottky junction transistor knows that the enhanced mode of the MESFET is t, and 1 f is weakly stacked. In this case, the design of the MESFET channel is strong ^ ^ When the thickness and doping concentration of the conduction device in the conventional device are known, it has been determined that the semiconducting circuit can be used in empty areas under normal operating conditions. For weak Zhao. Using Equation 13 below, it is possible to reach the empty area at the end of the source of the main channel of the through force; SEMICONDUCTOR 2ε ί Team

WW

D (匕—L) (13) 其中，W係空乏區之寬声，Ν $ J常數’ Vbi係、於間極端2心半;代/通二度’ Τ J屋，以及vgs係施加於閘極端214與建髮。由方程式⑻及（9)得知，上述之干/jL0之間的電電麼Vbl可以計算為大約貫=之内建缘Ψ 士 +炉从〜t 1 3 )传知，用以 ::ΪΓ、η 例之例示通道之源極末端處的空… nm ^ 65 nm、· 55 〇· 2/^· 25、、及〇· 3V之間極電塵分別延伸75 道20fi之为 nm nm、及42 nm之一距離。半導體通心僅明顯小於為5〇 nm之通道厚度。跨過半^體通道2〇6 第22頁 200306670 五、發明說明（18) 之工之區2 1 6的範圍係以圖解方式說明於第9圖中。〜。就上述之示範的實施例來說，肖特基接面電晶體之正笔細作電壓（如次臨界區）可容許閘極電流上升至一最大數直即Ig ’其中此示範之貫施例的數值可以在1 # a /// m左右。南於此數值時，形成於閘極上之電壓可以顯著地超過 • 3 V ’通道之源極末端處的空乏區2 1 6可能非常小於5 〇 =，，及半導體通道2〇6可能不再屬弱堆積。因此，汲極電 4可能不再隨（Vgs — Vth)而呈指數變化，以及 ^上升而快速下降，直到川為止，以至於間;二再用以控制〉及極電流。曰因此，肖特基接面電晶體（SJT)之各實施例在某些方面是類似金屬半導體場效應電晶體（MESFET)。然而，不像習知的MESFET、,，肖特基接面電晶體可以設計，使得輸入閘極，流Ig及通道電流Id於裝置之操作區，皆隨閘極電壓呈指數鰱化，操作區可包含一些或所有的次臨界區。又，肖特基接面電晶體可以適當地設計並且於次臨界區範圍内操作，以使得汲極電流透過汲極電流與閘極電流比所得到的一 ^ 全恆定的電流增益，隨閘極電流呈線性變化。因 ς 基接面電晶體之各項實施例可以使用為電流源，其中一相當广的輪入電流Ig，經由一電流 > 1 ’控制-較大的通道電流1(1。肖特基接 d g 可特別且有利地應用於互補式電路中，其詳述曰-技咖互補式裝置D (Dagger—L) (13) Among them, W is the wide sound in the empty zone, Ν $ J constant 'Vbi is the middle of the extreme, 2 heart and a half; Generation / Tong second degree' T J House, and vgs is applied to the gate Extreme 214 with Jianfa. From equations ⑻ and (9), it can be known that the electric power Vbl between the above-mentioned gan / jL0 can be calculated as approximately = = built-in margin 士士 + 炉 from ~ t 1 3), used to :: ΪΓ, The example of the η example shows that the space at the end of the source electrode of the channel ... nm ^ 65 nm, · 55 〇 2 / ^ · 25, and 0.3 V between 70 and 20V, respectively. One nm distance. The semiconductor via is only significantly smaller than the channel thickness of 50 nm. Crossing the half-body channel 2006 page 22 200306670 V. The scope of the work area 2 1 6 of the invention description (18) is illustrated graphically in Figure 9. ~. According to the above-mentioned exemplary embodiment, the fine voltage (eg, the subcritical region) of the Schottky junction transistor can allow the gate current to rise to a maximum value, that is, Ig. Among the examples of this exemplary embodiment, The value can be around 1 # a /// m. At this value, the voltage formed on the gate electrode can significantly exceed the empty region 2 1 6 at the end of the source of the 3 V 'channel, which may be very less than 5 〇 =, and the semiconductor channel 206 may no longer belong to Weak accumulation. Therefore, the drain current 4 may no longer change exponentially with (Vgs — Vth), and ^ rises and decreases rapidly until it reaches the river, so that it is in between; secondly it is used to control> and the pole current. Therefore, embodiments of the Schottky junction transistor (SJT) are similar in some respects to metal semiconductor field effect transistors (MESFETs). However, unlike the conventional MESFET, Schottky junction transistors can be designed so that the input gate, current Ig, and channel current Id in the operating area of the device are exponentially scaled with the gate voltage. The operating area May contain some or all of the subcritical sections. In addition, the Schottky junction transistor can be appropriately designed and operated in the subcritical region, so that the drain current passes through the ratio of the drain current to the gate current to obtain a fully constant current gain. The current changes linearly. Various embodiments of the ground-based junction transistor can be used as a current source, in which a relatively wide wheel current Ig, via a current > 1 'control-a larger channel current 1 (1. Schottky connection dg can be particularly and advantageously applied to complementary circuits, which are described in detail

第23頁 200306670 五、發明說明（19) 由一電路觀點得知，使用互補式裝置來降低功率消耗及/或來改善設計適應性通常是有利的。一對互補式的裝置一般係由一η通道電晶體及一p通道電晶體所組成。如果施加相等及相對的偏壓至這些電晶體之輸入，會產生相等及相對的輸出電流，則這些Ρ通道與η通道裝置一般稱為、「互 ΐ式」二基本互補對之裝置能以一有效方式利用"，以便在貫際上實現於任何一數位或類比電路。例如，在一習知的互補式金屬氧半導體（CM0S)電路中，通過電路之每一電流，徑了般都通過!！型及p型電晶體。在任何狀態只有一種= 晶體係導通，所以通常很少或沒有靜態功率消耗。當一閘極切換¥ ’通#電流流動僅使一應避免的寄生電容充電。另諸如場效應電晶體（FET)之習知裝置通常係藉由使p型裝置之通道寬度大約大於η通道裝置約兩倍，以補償電子載體之較大遷移率而形成互補式。習知M0SFET及MESFET於臨 Ϊ =上或以下操作通常確實是如此。ρ型裝置增加的尺寸常 $造成尺寸及成本上的缺點。此外，ρ通道裝置增加的電容系產生導致功率消耗，以及降低切換速度。然而，利用肖 =基接面電晶體之能力，有可能製造具有近乎相等之閘極 ^度與閘極長度的互補式〇通道及ρ通道肖特基接面電晶體二置。對照於習知互補式矽裝置，互補式肖特基接面電晶 =的使用產生的一些優點述明在各項實施例中，其可以包二對^定函數而言具有較小的電路區域（因此降低成本）；且特定汲極電流而驗具有較高的操作速度；以及對短閘極長度裝置而言具有較佳的電晶體匹配。Page 23 200306670 V. Description of the invention (19) From a circuit point of view, it is often advantageous to use complementary devices to reduce power consumption and / or improve design adaptability. A pair of complementary devices is generally composed of an n-channel transistor and a p-channel transistor. If equal and relative bias voltages are applied to the inputs of these transistors, an equal and relative output current will be generated. These P-channel and η-channel devices are generally referred to as "mutually complementary" devices with two basically complementary pairs. An effective way to use " in order to implement it in any digital or analog circuit. For example, in a conventional complementary metal-oxide-semiconductor (CM0S) circuit, every current that passes through the circuit passes through in the same way! And p-type transistors. There is only one type of crystal in any state, so there is usually little or no static power consumption. When a gate is switched, the current flow only charges a parasitic capacitor that should be avoided. Another conventional device, such as a field effect transistor (FET), usually forms a complementary type by making the channel width of the p-type device about two times larger than that of the n-channel device to compensate for the larger mobility of the electron carrier. It is known that M0SFET and MESFET are usually the same when operating on or below. The increased size of the p-type device often causes disadvantages in size and cost. In addition, the increased capacitance of the p-channel device results in power consumption and reduced switching speed. However, it is possible to manufacture complementary 0-channel and p-channel Schottky junction transistors with nearly equal gate angle and gate length by using the ability of the Schottky junction transistors. Compared with the conventional complementary silicon device, some advantages resulting from the use of the complementary Schottky junction transistor are described. In various embodiments, it can include two small circuit areas for a given function. (Thus reducing costs); and specific sink currents for higher operating speeds; and better transistor matching for short gate length devices.

第24頁 200306670 五、發明說明（20) 如上所述，當肖_特基接面電晶體於臨界以下（ vth)刼作時’即>可如一同厂電流控制的電流源一樣，適4地μ 計並操作。在這坠貫施例中，主要1士 w A t 田口又 A = ，其中通逼中流動的沒極電流，而I係輪人n 極電流。為要獲付互補式肖特基接面電晶俨 g 1 / ., 1 1J 入依據上述之方程式 2，其可表示為一/特基接面電晶體裴置之電流增益係依下列表示，而取決於通道幾何結構以及摻雜·· ” βPage 24 200306670 V. Description of the invention (20) As mentioned above, when the Shao_Teji junction transistor is operated below the threshold (vth), it can be used as a current source controlled by the same plant. Ground μ meter and operate. In this penetrating example, the main 1 w w A t Taguchi is again A =, in which the non-polar current flows during the forcing, and I is the n-polar current of the wheeler. In order to obtain the complementary Schottky junction transistor 俨 g 1 /., 1 1J into Equation 2 according to the above, which can be expressed as a / Tec junction junction transistor Pei's current gain is as follows, It depends on the channel geometry and doping ... "β

DopingDoping

Doping ‘ 2εϋπ 其中，£代表電容率，k # ^ ^ ^ …（2) 遷移率（如一η通t衣置之電子遷移率或一曾狀、遷移率），Nc係傳導帶中的狀能之有1二 ^衣置之遠洞 λΤ 广1狀悲之有效密度（如價電子帶）， Q係電子電荷，Nd〇ping係通道中之施體度’以及U ^ 4生常# °方程式2中的參數'中有許多^固定，不是因為其均係為物理常數（e、k、Nc、及為就是因為其均藉由製程所固定。例如，針對η通道及p通道來置’通道厚度a通常幾乎都設計一樣地，其目的為簡化製t 程。通道長度Lg之設計通常也盡可能達到細小之要求，並且在η通道及p通道裝置中大約都維持相同長度。因此，方程式2中的唯一剩餘變數皆係載子遷移率#，以及通道摻雜Doping '2εϋπ where £ represents permittivity, k # ^ ^ ^… (2) Mobility (such as electron mobility or uniformity, mobility in a η through t-coating), the state energy in the Nc conduction band There are effective distances (such as valence electron bands) in the long hole λΤ and wide hole 1 in the clothes, Q series electron charge, donor degree in Ndoping system 'and U ^ 4 生常 # ° Equation 2 There are many parameters in the parameter 'fixed, not because they are all physical constants (e, k, Nc, and because they are all fixed by the process. For example, the channel thickness is set for the η channel and the p channel. a is usually designed almost the same, and its purpose is to simplify the process of t. The design of the channel length Lg is usually as small as possible, and the same length is maintained in the η and p channel devices. Therefore, in Equation 2 The only remaining variables are the carrier mobility #, and the channel doping

200306670200306670

NDoping 係作倍大。就互補式之閘極寬度不同的載極電流的雜的方式相同的電益數值，通道摻雜等的閘極以及因較面電晶體他裝置之為剩餘變數。電子遷移率大約為電洞遷移率的大部分的習知裝置（如M0SFET以及MESFET)，每：裝置的最便利且實際方式，就是要使p通道裝\ 大力比η通道裝置之閘極寬度約大兩倍，以利 =遷移率。然而，藉由控制含有一閘極電流之汲員肖特基接面電晶體方法，就有可能以改變通道摻二以使得其補償較低的電洞遷移率，來獲得幾^ 流增益，產生η通道及ρ通道裝置均相等的電流择，不用改變裝置之相對的大小。換句話說，藉^ ，子植入步驟之適當控制，即可實現具有幾^相見度與長度之互補式裝置。由於產生空間的降低小Ρ通道裝置而產生的電容降低，互補式肖特基接電路適當彳占有較小的晶圓面積，並且可於高於其頻率操作。以次臨界CMOS為主的微功率電路，通常係利用標準 CMOS晶圓代工服務來構成。肖特基接面電晶體2〇〇(第2圖）之互補式類型可以藉由任何一技術，諸如第丨〇圖所述之技術來整合於一單一基體2 〇 2上。依據第1 〇圖，一實例的多肖特基接面電晶體電路700可形成於一單一基體2〇2上，其可為一石夕絕緣體（SOI)晶圓、矽藍寶石（sos)晶圓、或其他任一適合的晶圓或基體之一部分。在一示範的實施例中，起始基體2 0 2能呈現一低的摻雜濃度（如約低於1〇15/cm3之Na、 ND)。例如，在一肖特基接面電晶體電路7 〇〇之一實施例中’例如SO I基體以1 015/cm3等級，進行ρ型摻雜。埋入之氧NDoping is doubled. For complementary gate currents with different gate currents in different ways, the same gain value, gate doping, etc., and other devices due to the transistor are the remaining variables. Most of the conventional devices (such as MOSFET and MESFET) whose electron mobility is approximately the hole mobility, the most convenient and practical way of the device is to make the p-channel \ It's twice as big, to benefit = mobility. However, by controlling the drain Schottky junction transistor method that contains a gate current, it is possible to obtain several current gains by changing the channel doping so that it compensates for the lower hole mobility, resulting in The η channel and ρ channel devices have the same current selection without changing the relative size of the device. In other words, by using the proper control of the sub-implantation step, a complementary device with several degrees of visibility and length can be realized. Due to the reduction in space generated by the small P-channel device, the capacitance of the complementary Schottky connection circuit appropriately occupies a small wafer area and can operate at a frequency higher than that. Sub-critical CMOS-based micropower circuits are usually constructed using standard CMOS foundry services. The complementary type of Schottky junction transistor 200 (Fig. 2) can be integrated on a single substrate 200 by any technique, such as the technique described in Fig. According to FIG. 10, an example multi-Schottky junction transistor circuit 700 may be formed on a single substrate 202, which may be a silicon insulator (SOI) wafer, a silicon sapphire (sos) wafer, Or any other suitable part of the wafer or substrate. In an exemplary embodiment, the initial substrate 202 can exhibit a low doping concentration (e.g., Na, ND below about 1015 / cm3). For example, in one embodiment of a Schottky junction transistor circuit 7000, for example, the SO I substrate is doped at a p-type at a level of 1 015 / cm3. Buried oxygen

第26頁 200306670 五、發明說明（22) 化物厚度可為(^之至丨微米（如大約〇 4^m)之大小，以及表面 9H可為士勺0 ."〇5至5微米（如大約0 ·12"m)之厚度大小。基體· 一 /、可一氧化物層或其他絕緣體層，其詳細說明如下所 —不同衣置之通道2〇6(諸如第10圖中之通道2〇6人及2〇6]3) 可藉由平σ蝕刻、離子束引起的損傷、矽局部氧化Page 26, 200306670 V. Description of the invention (22) The thickness of the compound can be (^ to 丨 micron (such as about 0 4 ^ m)), and the surface 9H can be 0 to 5 micrometers (such as The thickness is about 0 · 12 " m). The base body can be an oxide layer or other insulator layer, which is described in detail as follows—channels 206 of different clothes (such as channel 2 in FIG. 10). 6 people and 206] 3) Flat σ etching, damage caused by ion beam, local oxidation of silicon

= = 〇S)、淺溝隔離及/或其他任—技術來隔離。η通道裝置 200Α之η型摻雜物可藉由離子植入或其他任一適當技術來植亡:=同Pji道裝置2_之？型摻雜物（第l〇(d)圖）一樣。在二==的實施例中，n通道2〇6A能藉由植入一約有25 “乂能 2里0』:二Ϊ大約3.5Xl〇1VCm2之一劑量範圍來形成。P通道 B '精由植入一約有10 keV能量的硼，以大約2.8 χ 柏入：之一劑量範圍來形成。當然，此處所指的摻雜物，匕:!库能量大小、以及劑量僅供說明之用，❿且實際的執仃此廣泛地隨各實施例變化。 :選擇性的氧化物或其他絕緣體220能藉由矽之熱氧以及2其他任一適當技術形成☆半導體層2〇6之表面 /及、=層204 (例如第10(〇圖所示）上。如果使用熱氧小^1—/通道2G6可能會被消耗，而且通道206之厚度會 ' SOI層之表面上的原始矽的厚度。用以通逼厚度係氧化後的最終厚度，應為適# / W &作之置2〇ϋΓΛ·裝置之源極與没極接觸7G8，可藉由在些n通道裝 Γ:上絕緣層22°内開些窗孔’並且將-相當多劑量申（或其他任一適當材料）植入於暴露之石夕（第i〇(c)圖）内= = 〇S), shallow trench isolation and / or any other technology-to isolate. The n-type dopant of the n-channel device 200A can be implanted by ion implantation or any other suitable technique: = same as Pji channel device 2_? Type dopants (Figure 10 (d)). In the embodiment of two ==, n channel 206A can be formed by implanting a dose range of about 25 "capacity 2 li 0": the second channel is about 3.5X101VCm2. P channel B 'fine It is formed by implanting a boron with an energy of about 10 keV in a dose range of about 2.8 χ Bo .: Of course, the dopants referred to here, the amount of energy in the bank, and the dose are for illustration purposes only. The actual implementation varies widely with various embodiments .: The selective oxide or other insulator 220 can be formed by the thermal oxygen of silicon and any other appropriate technology. 2 The surface of the semiconductor layer 206 / And, = layer 204 (such as shown in Figure 10 (shown in Figure 0). If you use hot oxygen ^ 1— / channel 2G6 may be consumed, and the thickness of channel 206 will be the thickness of the original silicon on the surface of the SOI layer The final thickness after oxidation is to be suitable for the thickness. It should be set to 20ϋΓΛ. The source and non-electrode contact of the device is 7G8, which can be installed by n-channel insulation. Layer 22 ° with openings and implant a considerable amount of Shen (or any other suitable material) into the exposed Shi Xi (Article i0 (c) Figure)

第27頁 200306670 五、發明說明（23) 來形成。例如，可利用一劑量約2X 1 015 / cm2及約5 0 - 7 5 ke V 之能量將坤植入。同樣地，p通道裝置2 0 0 B之源極與汲極接觸7 0 8，可藉由在p通道裝置上方之絕緣層22 0内開些窗孔，並且將一相當多劑量的石朋植入於暴露之石夕内來形成。一實例的植入為以一劑量約2 X 1 〇15 / c m2且可低於珅植入之能量，例如約2 5 - 5 0 keV植入硼。源極與汲極植入可以藉由一高溫回火（約800至1000度、約1至60分鐘之等級），或透過其他任一適當技術而活化。在一示範的實施例中，植入的通道可適當地於9 5 0 ° C左右回火45分鐘，或者經加工處理至完成為止。源極/汲極形成之後，可於絕緣體220 (第l〇(c)圖）内開啟 ®孔以暴露區域中下方的石夕，於此肖特基閘極2 1 4皆將被形成。一閘極材料（諸如二矽化鈷或其他金屬）隨之可被沉積’以及如有需要，則回火以形成肖特基阻障層及/或任何的阻抗接觸。如果使用金屬矽化物接觸，一適當金屬，諸如鈦或鈷，可以被沉積，隨後則蝕刻以便將金屬層存留於二源極汲極，以及閘極區域之上方。經過一快速熱回如650°C，維持約3〇秒）之後，即適當形成一金屬石夕化物曰。此金屬矽化物形成一歐姆接觸於高摻雜源極/汲極區域 t a开^成宵特基（即整流）接觸於低摻雜之η通道及P 二區之上。如上述，可以設計原始如1或s〇s晶圓之 ί二二便於金屬石夕化物反應消耗-些原始石夕通道-呈指數變化。子度（方私式2中的a)使Id及lg隨閘極電反Page 27 200306670 V. Description of Invention (23). For example, Kun can be implanted with a dose of about 2X 1 015 / cm2 and about 50-75 ke V. Similarly, the source and drain of the p-channel device 2 0 0B contact 7 0 8, by opening a few holes in the insulating layer 22 0 above the p-channel device, and implanting a considerable amount of Shi Peng in The exposed stone came within the evening. An example of implantation is implanting boron at a dose of about 2 × 10 15 / c m2 and which can be lower than the energy of gadolinium implantation, for example about 2 5-50 keV. Source and drain implants can be activated by a high temperature tempering (on the order of 800 to 1000 degrees, about 1 to 60 minutes), or by any other suitable technique. In an exemplary embodiment, the implanted channel may be suitably tempered at about 950 ° C for 45 minutes, or processed to completion. After the source / drain is formed, a hole can be opened in the insulator 220 (Fig. 10 (c)) to expose the lower and middle areas of the area, where Schottky gates 2 1 4 will be formed. A gate material (such as cobalt disilicide or other metal) can then be deposited ' and, if necessary, tempered to form a Schottky barrier layer and / or any impedance contact. If a metal silicide contact is used, a suitable metal, such as titanium or cobalt, can be deposited and then etched to retain the metal layer over the two source drain and gate regions. After a rapid thermal return (e.g., 650 ° C, maintained for about 30 seconds), a metal lithoate is properly formed. The metal silicide forms an ohmic contact with the highly doped source / drain region, and opens a Schottky (ie, rectified) contact with the low-doped n channel and the P second region. As mentioned above, it is possible to design the original two or two wafers, such as 1 or sos wafers, to facilitate the reaction consumption of metal oxides-some of the original stone channels-change exponentially. The sub-degree (a in square private formula 2) makes Id and lg react with the gate voltage

第28頁 200306670 五、發明說明（24) 一單一閘極金屬能用以形成屬於n通道及P通道裝置之肖特基閘極。然而，在各項實施例中’若針對每一種而使用一不同的肖特基材料，則η通道及Ρ通道裝置20 0之特性可做些微差異程度之修改。隨後，吁藉由沉積一高傳導互連層，諸如鋁、銅、金、或其他，將各裝置作配線處理，連接在一起以便形成電路。又，< 以構成窗孔於絕緣層2 2 0 内’以便做各裝置之間的互連處理’作為一適當之方式。例如，第1 0 ( d )圖說明一實例的彡補式肖特基接面電晶體反向器電路。Page 28 200306670 V. Description of the invention (24) A single gate metal can be used to form Schottky gates belonging to n-channel and P-channel devices. However, in each of the embodiments', if a different Schottky material is used for each, the characteristics of the n-channel and p-channel devices 200 can be modified to a slightly different degree. Subsequently, the devices are called for wiring by depositing a highly conductive interconnect layer, such as aluminum, copper, gold, or others, and are connected together to form a circuit. Also, < forming a window hole in the insulating layer 2 2 0 'so as to perform an interconnection process between devices' is an appropriate method. For example, Fig. 10 (d) illustrates an example of a complemented Schottky junction transistor inverter circuit.

雖然第1 0 ( a) - (d )圖說明目的以構成互補式肖特基接面電晶體電路之一實例的步驟，俱是此步驟之其他變化皆係有可能的。例如，二矽化鈷或二矽化鈦可以直接沉積，而不是於鈷或錫之沉積後再進行金屬矽化反應。雖然可以用步驟具有許多變化，可以設計通道之離子植入以及隨後之擴散，以利實現一摻雜濃度，以相等閘極長度及閘極寬度之裝置’其允許互補式^通道與p通道肖特基接面電晶體性能0 本揭示中所示類型的實例之互補式η通道及p通道裝置’已依據上述之步驟來模擬。就本實驗而言，裝置之製缸係利用Avant! TCAD package TSUPREME-4之軟體工具來，行模擬。、經步驟模擬之後，具有例示〇· 5 閘極長度及二0 · 1 2 // m通道厚度之n通道及p通道裝置的電性特性，皆係，由MED I C I來進行模擬。離子劑f㉟f、以及隨後之擴政係經選#，以使得各互補式裝置而產生相同的電流增’、 200306670 五、發明說明（25) 益’以及使得汲極與閘極電流隨閘極電壓呈指數變化，以利實現如上述之肖特基接面電晶體操作模式。就〇 · 1 2 // m通道厚度而言，互補式特性可以藉由以約 25keV之能量，劑量約3· 5xlOn cur2的磷植入，形成η型主動區來實現。隨後能再以約丨0 keV之一能量，劑量約2 · 7 5 xlOncnr2的植入，形成p型主動區。應注意的是，使用於植入之摻雜物，其劑量大約比使用於習知矽MESFET之劑量約低。十倍。完成兩者植入之後，晶圓之回火可設定在 9 5 0、，C ’可持績4 5分鐘，以利活化摻雜物，並且將其擴散於通這内。p通道與n通道裝置之源極與汲極區域分別藉由植 =硼及砷而形成。就此處所述之示範的實施例來說，p通道 I置之源極與汲極區域可藉由植入一含有大約1 〇 keV能量及大約2x1 〇15 cm_2劑量的硼來實現，而η通道裝置之源極與 =極，，Z藉由植入一含有5〇 keV能量及大約hi⑴化…劑置^石申來實ί見。隨後可再藉由約95〇〇c、約一分鐘之快速敎回俨Ϊ是藉由其他任一技術來活化源極與汲極植入物。康Λ述之植入及回火條件，將摻雜物濃度表示為通二：曰曰因内之一距離的函數，例示之摻雜量曲線係說明於 m首:據第13圖，標繪圖1301及13〇8(分別）表示實有二雜、二特基接面電晶體中之摻雜濃度，其含 ΐ:;: Γ ΐ道m?里入氧化物204、以及基體2。2内， ^別声_、入Λ迢之距碓所繪不。描繪記錄點1 3 0 2及1 3 1 0 高劑^ 道物及^通逼裝置中之源極與沒極接觸具有相當 J里的4雜物植入。ρ通道主動區之摻雜物植入係表示於 200306670Although Figures 10 (a)-(d) illustrate the steps for constructing an example of a complementary Schottky junction transistor circuit, other variations of this step are possible. For example, cobalt disilicide or titanium disilicide can be deposited directly instead of metal silicidation after the deposition of cobalt or tin. Although there can be many variations in the steps, channel ion implantation and subsequent diffusion can be designed to facilitate the realization of a doping concentration device with equal gate length and gate width. 'It allows complementary ^ channel and p channel channel Performance of a Teflon Junction Transistor 0 The complementary η-channel and p-channel devices of the examples of the type shown in this disclosure have been simulated according to the steps described above. For the purpose of this experiment, the cylinder system of the device was simulated using the software tool of Avant! TCAD package TSUPREME-4. After the simulation of the steps, the electrical characteristics of the n-channel and p-channel devices with the illustrated 0.5 gate length and 20 0 1 2 m channel thickness are all simulated by MED I C I. The ionizer f㉟f and the subsequent expansion of the system were selected to make the complementary devices produce the same current increase, 200306670 V. Description of the Invention (25) benefits, and the drain and gate currents follow the gate voltage It changes exponentially to facilitate the operation of the Schottky junction transistor as described above. In terms of the channel thickness of 0.12 m, complementary characteristics can be achieved by implanting phosphorus with an energy of approximately 25 keV and a dose of approximately 3.5 xlOn cur2 to form an n-type active region. Subsequently, it can be implanted with an energy of about 0 keV and a dose of about 2.75 xl Oncnr2 to form a p-type active region. It should be noted that the dosage of dopants used for implantation is about lower than that used for conventional silicon MESFETs. ten times. After the implantation of the two is completed, the tempering of the wafer can be set at 950, and C 'can last for 45 minutes to facilitate the activation of the dopant and diffuse it into the pass. The source and drain regions of the p-channel and n-channel devices are formed by implanting boron and arsenic, respectively. For the exemplary embodiment described herein, the source and drain regions of the p-channel I can be achieved by implanting a boron containing about 10 keV energy and a dose of about 2 x 1015 cm_2, while the n-channel The source and the pole of the device, Z was realized by implanting a material containing 50 keV of energy and about hi ... The source and drain implants can then be activated again by a rapid 约 of about 9500c for about one minute. The implantation and tempering conditions described by Kang Λ, expressed the concentration of the dopant as a function of a distance within the reason: the dopant amount curve is exemplified in m head: according to Figure 13, the plot 1301 and 1308 (respectively) indicate the doping concentration in the real two-hetero, two-tertite junction transistor, which contains ΐ:;: Γ ΐ channel m? Into the oxide 204 and the matrix 2.2 , ^ 别声 _, not drawn into the distance of Λ 迢. Describe the recording points 1 3 0 2 and 1 3 1 0 The source and immortal contact in the high-dose ^ channel and 通 through-force device has a considerable 4 里 of implantation. The dopant implantation of the p-channel active region is shown in 200306670

描繪點13G4上，且描緣點13()6表示為基體内 (background d〇ping)。、描繪點 13 叙"隹雜物植入，且描繪點⑶4表示為基體區之： ί=4?Λ,:嫩-共同基體2。2上，'所以㈣似。雖然任何推雜物之類型能被:置用通運肖特基接面電晶體的例示摻雜物包含硼但疋P 基接面電晶體的例示摻雜物包含磷 n、運肖特摻雜物濃度係作為範例t 表不於弟1 3圖之特定例而廣泛變化。用’而摻雜濃度能隨著各項實施依據第1 3圖中的摻雜> 道肖特基接面電晶體之電=。篦n可模擬流進n通道及P通為兩個裝置之輸入閘極電^ 圖係說明因一實例模擬流。第11圖係說明含有一、” 而產生的輸出汲極電例η通道裝置20 0A產生的結也果17,以伏特汲極偏壓（vds)之一實伏特之一實例p通道裝置=生的=二一含有施加的Vds = -1· 0 流與汲極電流皆為正， : n通道裝置之閘極電皆為負。第11圖係說明例雷^置之/閘極電流與汲極電流大範圍的閘極電流偏壓=個狀:，範圍，以及說明於一相等，但符號相反）。裝、置中之汲極電流大小劑量、回火時間等）可以麫、琴i M、、件（如通道植入能量、安培範圍之閘極偏壓大小Ί最高互以利提供約有n-1G至10-8 流範圍之不同互補性，可 ^ '。於較高或較低電了以精由修改製程條件來實現，例The drawing point 13G4 and the drawing edge point 13 () 6 are represented as background doping. 13. Depicting point 13 & Debris is implanted, and the drawing point ⑶4 is expressed as the matrix area: ί = 4? Λ ,: tender-common matrix 2.2, 'So ㈣ is similar. Although any type of dopant can be used: an exemplary dopant of a Schottky junction transistor containing boron is included, but an exemplary dopant of a samarium P-based junction transistor includes phosphorous n, a Schottky dopant Concentrations are widely used as an example. The doping concentration can be changed with each implementation according to the doping in Fig. 13 >篦 n can simulate the flow into the n channel and P pass. The input gate voltage of the two devices ^ The figure illustrates the simulated flow due to an example. FIG. 11 illustrates an example of an output drain voltage generated by a “n” channel device. The result produced by a channel device 20 0A is also 17. One example of a real volt is one of the volt drain bias (vds). == 21 contains the applied Vds = -1 · 0 The current and the drain current are both positive, and the gate current of the n-channel device is all negative. Figure 11 illustrates an example of lightning / gate current and drain A large range of gate current bias voltage of the pole current = shape :, range, and description are equal to each other, but the signs are opposite). The size and dose of the drain current of the device and center, tempering time, etc.) , (Such as channel implantation energy, ampere range gate bias size, maximum mutual benefit to provide different complementarities of about n-1G to 10-8 flow range, can be higher or lower Electricity is realized by modifying the process conditions, for example

200306670 五、發明說明（27) 如藉由改變通道摻雜及/或的增益。以改&方程式（2)所表得，以及跨導二二之V:可止!f由率方本發明所述之裝置的總閘極 / ^(1)表不為A = Id/UT。如圖係說明一間極長⑵利用咖f模擬。入(即閘極)電容之實例描繪圖：此n ^二-輸 0.12 /zm之離子植入通道（植入 /有—厚度仏量為3.5xl0n/cm2。雖然確實里為E = 25keV，及其劑就本特定的示範實施例而·; 其他不同的參數，但時間為45分鐘，閘極長度物'入後回火之溫度為9 5 0。。， 1 0V。Λ楚！ 9回—予係為〇· 5 ，以及汲極偏壓係為壯晉圖可容易看出’此實例的肖特基接面電晶體一等效雙即接面電晶體，這是因為 :曰二/ 7擴散電谷所導致。因此，構成之肖特基接面曰曰=此以較南於一相等雙極接面電晶體之頻率於微功率二”呆作。此外，纟具有較短之閘極長度，因此提供相較知技術弱反轉CM0S電路較增加之操作頻率。又依據第圖，一大約1A/ /zm之汲極偏壓的輸入電容量可約為 3· 5xl〇’F/ ，其可對應於一約i8GHz之截止頻率。此新装置之閘極電容亦可小於一具相同尺寸之習知肋”£7。一習>M0SFET之輸入電容通常係由所謂的氧化物電容 c〇x控制，而且就含有一2nm閘極氧化物及約有〇5#m閘極長度^ 一強反轉的M0SFET而言，氧化物電容量大約為8〇χ 1 ° F /从m。因此’多種的肖特基接面電晶體可具有比相同第32頁 200306670 五、發明說明（28) ^ 了及含有相同電流之習知M0SFET大約快2〇倍的截止頻雖錢示出模擬結果，例如第1](_ 為目的，當知本發明之許多實施例所獲得之明實施例之不同而與此處所呈現士句可Ik *，…寸、摻雜物、摻：：；^以;乏=化*例將適”遺各項實施例產生顯著變化的不同…200306670 V. Description of the invention (27) For example, by changing channel doping and / or gain. Calculated by changing & equation (2), and V of transconductance 22: stop! F is given by the total gate / ^ (1) of the device described in the present invention is not A = Id / UT . As shown in the figure, a very long cymbal is simulated using coffee f. An example drawing of an input (ie, gate) capacitor: this n ^-input 0.12 / zm ion implantation channel (implanted / has-thickness is 3.5xl0n / cm2. Although it is E = 25keV, and The agent is based on this particular exemplary embodiment; other different parameters, but the time is 45 minutes, the temperature of the gate electrode after the tempering is 9 5 0., 10 V. Λ Chu! 9 times- The pre-series is 0.5, and the drain-bias system is the graph. It can be easily seen that the Schottky junction transistor in this example is equivalent to the double-junction transistor, because: Caused by the diffusion of the electric valley. Therefore, the composition of the Schottky junction is equal to the "micropower two" at a frequency south of an equal bipolar junction transistor. In addition, 纟 has a shorter gate Length, so it provides an increased operating frequency compared to the known weakly inverted CM0S circuit. According to the figure, an input capacitance of a drain bias voltage of about 1A // zm can be about 3.5 * 10 × F /, It can correspond to a cut-off frequency of about i8GHz. The gate capacitance of this new device can also be smaller than a conventional rib of the same size "£ 7. A study > M0SFET The input capacitance is usually controlled by the so-called oxide capacitor c0x, and for a M0SFET containing a 2nm gate oxide and a gate length of about 05 # m ^ a strong inversion, the oxide capacitance is approximately Is 80 × 1 ° F / from m. Therefore, 'a variety of Schottky junction transistors can have the same speed as the conventional MOSFET with the same current on page 32, 200306670 V. Description of the invention (28) ^ Although the cutoff frequency of 〇 times shows the simulation results, such as the first one] (_, for the purpose of knowing that the many different embodiments obtained by the present invention are different from the embodiment shown here, Ik *, ... inch , Dopants, doped ::; ^ to; lack = = * will be appropriate "the various examples produced significant changes ...

Ik然前文已詳細說明至少一 — 解到還有許多其他的變化存、广彳不貫施例，但應丁他實施例均只是作為者例、，也應了解例示實施例或其範園、應用對：不；：何：式？限本發明之悉該項技藝者於技術上執行例_ 之洋細δ兄明將提供熟 :宜的說明。故應清楚了解：貫：：或其他實施例之― 文化，凡其它未脫離本創作之工=及配置均可作不同 :有特別說明，否則說之申請專利範圍内。除非复貫踐並不特別 :所述之任何元件對於本發以任1序：執何利範圍方法項内的任犯圍之外之—順序依據，、包含除說明於下列的申請專利第33頁 200306670Ik has already explained at least one in detail in the foregoing-it is understood that there are many other variations and extensive and inconsistent embodiments, but the other embodiments are only examples, and you should also understand the exemplified embodiments or their models, Application pair: No; The present invention is limited to those skilled in the art, and its technical implementation examples will be provided by Yang Xi δ Brother Ming. Therefore, it should be clearly understood that: Guan: or other embodiments-culture, all other works that do not depart from this creation = and configuration can be different: there are special instructions, otherwise it is within the scope of patent application. Unless the repetitive practice is not special: any of the elements mentioned are in the order of the issue: the culprit within the scope of the scope of the method-the basis of order, including Page 200306670

圖式簡單說明本發明將配合下列圖式說明於下文中，其中同一數a 代表同一元件，以及予第1 (a)圖係於強反轉區中操作的一jjOSFET之示意圖· 第1 (b)圖係於弱反轉區中操作的一mosFET之示意圖· 第1 (c)圖係一雙極接面電晶體之示意圖；第1(d)圖係一空乏型MESFET之示意圖；第2圖係一習知增強模式MESFET之示意圖；第3圖係一 n型半導體上所形成之一肖特基接圖；日7不忍第4圖係本發明所揭示之一實例肖特基接面電雕 (SJT)的示意圖； ^ 第5圖係一構成肖特基接面電晶體裝置之電性例電，產生的肖特基接面電晶體網狀結構；、貝第6圖係汲極電流與閘極電流作為閘極電壓實例描繪圖；函數的圖；第7圖係電流增益作為汲極電流之一函數的實例描綠電流之汲極電流對汲極電壓的實第8圖係針對不同閘極例描繪圖；特美m係二明空乏區跨過半導體通道之範圍的-實例肖特基，面電晶體之示意圖；弟1 0圖係用以德> 晶體於相同基於上^ ΐ補式n通道與p通道宵特基接面電第11圖係：例流程的示意圖；宁互補式η通道與ρ通道肖特基接面電晶Brief Description of the Drawings The present invention will be described in the following with the following drawings, where the same number a represents the same component, and the schematic diagram of a jjOSFET operating in the strong inversion region in Figure 1 (a) is shown in Figure 1 (b ) Figure is a schematic diagram of a mosFET operating in a weak inversion region. Figure 1 (c) is a schematic diagram of a bipolar junction transistor; Figure 1 (d) is a schematic diagram of an empty MESFET; Figure 2 It is a schematic diagram of a conventional enhanced mode MESFET. FIG. 3 is a Schottky connection formed on an n-type semiconductor; (SJT); ^ FIG. 5 is an electrical example of a Schottky junction transistor device, and a Schottky junction transistor network structure is generated; FIG. 6 is a drain current and Gate current as an example of gate voltage. Function diagram. Figure 7 is an example of current gain as a function of drain current. Figure 8 shows the actual drain current versus drain voltage of green current. Figure 8 is for different gates. Extreme case drawing; Temei m-type open space across the range of semiconductor channels Schottky, a schematic diagram of a surface transistor; Figure 10 is used to de > crystals are based on the same ^ ΐ complement n-channel and p-channel Schottky interface Figure 11: a schematic diagram of an example process; Ning complementary η-channel and ρ-channel Schottky junction transistor

200306670 圖式簡單說明體之〉及極電流對閘極電流的貫例描繪圖，第1 2圖係一 η通道肖特基接面電晶體的閘極電容為汲極電流之一函數之實例描繪圖；以及第1 3圖係一說明互補式η通道與ρ通道裝置之摻雜植入濃度的實例圖。 2 0 0Β ρ通道裝置 2 04 絕緣層 2 0 6 Β ρ通道 210 源極端 216 空乏區 2 2 0 絕緣層 7 0 8 源極與汲極接觸圖式元件符號說明 2 0 0 肖特基接面電晶體 200Α η通道裝置 2 0 2 基體 2 0 6 半導體通道 2 0 6Α η通道 208 汲極端 214 閘極端 218 汲極電流 70 0 肖特基接面電晶體電路 15· 第35頁200306670 Schematic illustration of the schematic diagram and the example of the pole current versus the gate current. Figure 12 shows an example of the gate capacitance of an n-channel Schottky junction transistor as a function of the drain current. Figures 13 and 13 are diagrams illustrating examples of doping implantation concentrations of the complementary n-channel and p-channel devices. 2 0 0Β ρ channel device 2 04 Insulation layer 2 0 6 Β ρ channel 210 Source terminal 216 Empty region 2 2 0 Insulating layer 7 0 8 Source and drain contact Graphical component symbol description 2 0 0 Schottky interface Crystal 200A η channel device 2 0 2 Base 2 0 6 Semiconductor channel 2 0 6Α η Channel 208 Drain terminal 214 Gate terminal 218 Drain current 70 0 Schottky junction transistor circuit 15 · page 35

Claims

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互補式電路於一基體上之方法，包含之步驟六、申請專利範圍 1. 一種形成一有· 裝置絕緣；該複數個裝置，以構成!！通道裝Method of complementary circuit on a substrate, including the steps 6. Scope of patent application 1. A form of a device insulation; the plurality of devices to constitute !! Aisle loading

將該基體上之複數/[固將摻雜物植入於每— 以及ρ通道裝置；Implant a plurality of dopants on the substrate into each-and p-channel device;

=極與汲極接觸形成於每一該複數個裝置上；以及 =些源極與沒極接觸互連，以構成該互補式電路；了 :该植入步驟包含植入該摻雜物以達到一摻雜濃 f ’以貫質上相等的閘極長度與閘極寬度之裝i，該摻雜濃度允許互補式n通道及p通道肖特基接面電晶體性能。 2.如$申晴專利範圍第1項所述之方法，其中該植入步驟更包含選擇摻雜物劑量、離子能量、以及隨後發生之擴散，以實現互補式肖特基接面電晶體（SJT)性能。 3·如申請專利範圍第1項或第2項所述之方法，其中每一該些裝置包含一半導體通道於該源極端與該汲極端之間，其中該半導體通道包含一對應於該半導體通道上所形成之一肖特基閘極的空乏區。 4 ·如申請專利範圍第3項所述之方法’其中每一该些肖特基閘極用以接收一輸入電流，並且依據該輸入電流而調整該空乏區之大小，其中流矣該源極端與該汲極端之間的該電流因此被調整為該輸入電流之一函數。= Pole-to-drain contacts are formed on each of the plurality of devices; and = source and non-pole contacts are interconnected to form the complementary circuit; the implantation step includes implanting the dopant to achieve A doping concentration f ′ is a device of uniform gate length and gate width i. The doping concentration allows complementary n-channel and p-channel Schottky junction transistor performance. 2. The method as described in item 1 of the patent application scope, wherein the implanting step further includes selecting a dopant dose, ion energy, and subsequent diffusion to achieve a complementary Schottky junction transistor ( SJT) performance. 3. The method as described in claim 1 or 2, wherein each of the devices includes a semiconductor channel between the source terminal and the drain terminal, wherein the semiconductor channel includes a channel corresponding to the semiconductor channel One of the empty regions formed by the Schottky gate. 4 · The method described in item 3 of the scope of patent application 'each of the Schottky gates is used to receive an input current, and the size of the empty region is adjusted according to the input current, wherein the source extreme The current to the drain terminal is therefore adjusted as a function of the input current.

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5牛請專範圍第1項至第4項所述之方法，其*該植入，匕含選擇摻雜物劑量、離子能量、以及隨後發生之 ρ ’ί 1 #，使侍每一該複數個裝置中的汲極與閘極電流皆隨 1 “堊而王拐數變化，以實現宵特基接面電晶體模式的 6· 一種操作具有至少一ρ 電路的方法，其中每一裝及一汲極端形成於一半導含一於該源極端與該汲極含之步驟有：將一偏壓提供至至少允許電流於該半導體通道置之一臨界電壓，以使該及控制由該至少一閘極 =整該至少一空乏區以及立而’作為該閘極電流之一電流於該次臨界模式中皆且其中该沒極電流透獲得之一實質固定電流增化0 通道裝置與η通道裝置之一互補式置包含一源極端、一閘極端、以體通道上，其中該半導體通道包端之間的空乏區，其中該方法包一閘極端，以使得至少一空乏區内流動，其中該偏壓係小於該裝裝置於一次臨界模式中操作；以端流進該通道之一閘極電流，以因此該輸出電流產生於該汲極函數’其中該輸入電流與該輸出隨一閘極-源極電壓實質呈指數變過該汲極電流與該閘極電流比所盈，隨該閘極電流實質呈線性變Please refer to the methods described in items 1 to 4 for the implantation. The implantation method includes selecting the dopant dose, the ion energy, and the subsequent occurrence of ρ 'ί 1 #. The drain and gate currents in each device vary with a 1 "chalk and king number to achieve the Chertky junction transistor mode. 6. A method of operating a circuit with at least one ρ, where each The drain terminal is formed at half of the source terminal and the drain terminal. The steps include: providing a bias voltage to at least a threshold voltage that allows a current to be set in the semiconductor channel, so that the control is controlled by the at least one gate. Pole = the at least one empty region and the current as one of the gate currents in the sub-critical mode and where the non-polar current is obtained through a substantially fixed current increase of 0 channel device and η channel device A complementary device includes a source terminal, a gate terminal, and a body channel, wherein the semiconductor channel has an empty region between the ends. The method includes a gate terminal so that at least one empty region flows. Pressure system is less than this The device operates in a critical mode; a gate current flows into the channel from the end, so that the output current is generated by the drain function, where the input current and the output are substantially exponential with a gate-source voltage The ratio of the drain current to the gate current is changed, and it varies substantially linearly with the gate current.

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1 · 一種互補式電路，包含：、至少一 n通道裝置，該η通道裝置具有之源極、閘極、以及及，電極形成於一 η型半導體通道上；以及 =、至/ Ρ通迢裝置，該Ρ通道裝置具有源極、閘極、以汲=電極形成於一Ρ型半導體通道上；1. A complementary circuit comprising:, at least one n-channel device, the n-channel device having a source, a gate, and and an electrode formed on an n-type semiconductor channel; and =, to / P pass through device The P-channel device has a source, a gate, and a drain electrode formed on a P-type semiconductor channel;

2中忒至少一 η通道裝置與該至少一 ρ通道裝置係用以，付在一次臨界模式中操作時，源極與汲極電流皆隨一 f 源極偏壓壬指數變化，以及使得該汲極電流透過該汲虽“ ^與δ亥閑極電流比所獲得之一實質固定電流增益，隨 4間,電流實質呈線性變化，且其中該至少一 η通道裝置與该至少一 ρ通道裝置之該些電極互連以構成該互補式電路。 8 ·如申請專利範圍第7項所述之電路，其中該至少一 η通道 I置與该至少一ρ通道裝置均包含換雜濃度，且其中該ρ通道裝置與該η通道裝置之該相對摻雜濃度係設計以使得該η 通道與ρ通道裝置之該些間極面積實質相等。 9·如申請專利範圍第8項所述之電路，其中該11通道裝置包含由一25keV能量，3· 5Χ1011 cnr2之劑量的一磷離子植入所形成之磷摻雜物。離子植入所形成之硼摻雜物。2 The at least one n-channel device and the at least one p-channel device are used to operate in a critical mode, and both the source and drain currents change with an f source bias index, and make the sink A substantially fixed current gain obtained by the ratio of the pole current through the drain current and the delta pole current, and the current substantially linearly changes with the four, and wherein the at least one n-channel device and the at least one p-channel device The electrodes are interconnected to form the complementary circuit. 8 The circuit as described in item 7 of the scope of patent application, wherein the at least one n-channel I and the at least one p-channel device both include impurity exchange concentrations, and wherein the The relative doping concentrations of the p-channel device and the n-channel device are designed so that the inter-electrode areas of the n-channel device and the p-channel device are substantially equal. 9. The circuit according to item 8 of the scope of patent application, wherein the The 11-channel device contains a phosphorus dopant formed by implanting a phosphorus ion at a dose of 3 · 5 × 1011 cnr2 at 25 keV. A boron dopant formed by ion implantation.